Plasma treatment device, power supply system, and frequency control method

Abstract

This plasma treatment device comprises a chamber, a substrate support part, first and second power supplies, and a control circuit. The control circuit controls the first power supply and the second power supply such that, in each of a plurality of repeating cycles, a first bias signal and a second bias signal are supplied to the substrate support part in the chamber. The control circuit adjusts a second frequency of the second bias signal in each of a plurality of sub-periods in each of the plurality of repeating cycles, in accordance with the matching degree of the impedance of the load of the second power supply in the same sub-period in the preceding repeating cycle, so as to improve the matching degree.

Description

Plasma Processing Apparatus, Power Supply System, and Frequency Control Method 【0001】 Exemplary embodiments of the present disclosure relate to a plasma processing apparatus, a power supply system, and a frequency control method. 【0002】 The plasma processing apparatus is used in plasma processing of a substrate. In the plasma processing apparatus, bias high-frequency power is used to draw ions from the plasma generated in the chamber to the substrate. Patent Document 1 below discloses such a plasma processing apparatus. 【0003】 Japanese Patent Application Laid-Open No. 2009-246091 【0004】 The present disclosure provides a technique for reducing the degree of reflection of a bias signal having a higher frequency among two bias signals supplied to a substrate support portion. 【0005】 In one exemplary embodiment, a plasma processing apparatus is disclosed. The plasma processing apparatus includes a chamber, a substrate support portion, a first power supply, a second power supply, and a control circuit. The substrate support portion is disposed in the chamber. The first power supply is electrically coupled to the substrate support portion. The first power supply is configured to generate a first bias signal for drawing ions from the plasma in the chamber to the substrate on the substrate support portion. The waveform of the first bias signal has a waveform period having a time length of the reciprocal of the first frequency. The second power supply is electrically coupled to the substrate support portion. The second power supply is configured to generate a second bias signal, which is an RF signal, for drawing ions from the plasma in the chamber to the substrate on the substrate support portion. The control circuit controls the first power supply and the second power supply so as to supply the first bias signal and the second bias signal to the substrate support portion in each of a plurality of repetition periods. The control circuit adjusts the second frequency of the second bias signal in each of a plurality of sub-periods within each of the plurality of repetition periods. The time length of each of the plurality of sub-periods is shorter than the time length of the waveform period. The control circuit adjusts the second frequency of each sub-period according to the impedance matching degree of the load of the second power supply in the same sub-period within the previous repetition period among the plurality of repetition periods so as to improve the matching degree. 【0006】 According to one exemplary embodiment, a technique is provided for reducing the degree of reflection of the bias signal having the higher frequency among two bias signals supplied to a substrate support. 【0007】This is a diagram illustrating an example configuration of a plasma processing system. This is a diagram illustrating an example configuration of a capacitively coupled plasma processing apparatus. This is a diagram showing a plasma processing apparatus according to one exemplary embodiment. This is a diagram showing an example waveform of the first bias signal. This is a diagram showing an example of a plasma processing apparatus according to one exemplary embodiment. This is a diagram showing an example of a plasma processing apparatus according to one exemplary embodiment. This is a diagram showing an example of a plasma processing apparatus according to one exemplary embodiment. This is a diagram showing an example of a plasma processing apparatus according to one exemplary embodiment. This is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. Figures 13(a) and 13(b) are each timing charts related to a plasma processing apparatus according to one exemplary embodiment. This is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. This is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. This is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. This is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. This is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. This is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. This is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. This is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. This is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. This is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. This is a flowchart showing a frequency control method according to one exemplary embodiment. This is a block diagram of a computer (a type of circuit) capable of realizing the various control modes described herein. This is a diagram showing another example of a substrate support that can be used in plasma processing apparatuses according to various exemplary embodiments. 【0008】Various exemplary embodiments will be described in detail below with reference to the drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals. 【0009】 Figure 1 is a diagram illustrating an example configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support unit 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space, and at least one gas outlet for discharging gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20, which will be described later, and the gas outlet is connected to an exhaust system 40, which will be described later. The substrate support unit 11 is located in the plasma processing space and has a substrate support surface for supporting a substrate. 【0010】The plasma generation unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), ECR (Electron Cyclotron Resonance) plasma, helicon wave excited plasma (HWP), or surface wave plasma (SWP), etc. Various types of plasma generation units, including AC (Alternating Current) plasma generation units and DC (Direct Current) plasma generation units, may also be used. In one embodiment, the AC signal (AC power) used in the AC plasma generation unit has a frequency in the range of 100 kHz to 10 GHz. Therefore, the AC signal includes an RF (Radio Frequency) signal and a microwave signal. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz. 【0011】The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various processes described herein. The control unit 2 may be configured to control the elements of the plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 is implemented, for example, by a computer 2a. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The functions realized by the processing unit 2a1 described herein may be implemented in a circuit or processing circuit, including a general-purpose processor, an application-specific processor, integrated circuits, ASICs (Application Specific Integrated Circuits), a CPU (Central Processing Unit), a conventional circuit, and / or a combination thereof, programmed to realize the described functions. The processor is considered to be a circuit or processing circuit, including transistors and other circuits. The processor may be a programmed processor that executes a program stored in the storage unit 2a2. This program may be pre-stored in the storage unit 2a2 or retrieved via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a, or it may be a communication line connected to the communication interface 2a3. The storage unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing device 1 via a communication line such as a LAN (Local Area Network).In this disclosure, circuits, units, and means are hardware programmed to perform or configured to perform the functions described. Such hardware may be any hardware described in this disclosure, or any hardware known to be programmed to perform or execute the functions described. If such hardware is a processor that is considered to be a type of circuit, such circuit, means, or unit is a combination of hardware and software used to constitute such hardware and / or processor. 【0012】 The following describes an example configuration of a capacitively coupled plasma processing apparatus as an example of a plasma processing apparatus 1. Figure 2 is a diagram illustrating an example configuration of a capacitively coupled plasma processing apparatus. 【0013】 The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply system 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support unit 11 and a gas introduction unit. The gas introduction unit is configured to introduce at least one processing gas into the plasma processing chamber 10. The gas introduction unit includes a shower head 13. The substrate support unit 11 is located inside the plasma processing chamber 10. The shower head 13 is located above the substrate support unit 11. In one embodiment, the shower head 13 constitutes at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the shower head 13, the side walls 10a of the plasma processing chamber 10, and the substrate support unit 11. The plasma processing chamber 10 is grounded. The shower head 13 and the substrate support unit 11 are electrically insulated from the housing of the plasma processing chamber 10. 【0014】The substrate support portion 11 includes a main body portion 111 and a ring assembly 112. The main body portion 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body portion 111 surrounds the central region 111a of the main body portion 111 in a plan view. The substrate W is placed on the central region 111a of the main body portion 111, and the ring assembly 112 is placed on the annular region 111b of the main body portion 111 so as to surround the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also called the substrate support surface for supporting the substrate W, and the annular region 111b is also called the ring support surface for supporting the ring assembly 112. 【0015】In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is placed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic chuck electrode 1111b placed within the ceramic member 1111a. The electrostatic chuck electrode 1111b is also called a clamping electrode. In one embodiment, the electrostatic chuck electrode 1111b is electrically connected or coupled to a chuck power supply. The chuck power supply may be a DC power supply or an AC power supply. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Furthermore, other members surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have an annular region 111b. In this case, the ring assembly 112 may be placed on the annular electrostatic chuck or the annular insulating member, or it may be placed on both the electrostatic chuck 1111 and the annular insulating member. In addition, at least one bias electrode, which is electrically connected or coupled to the power supply 31 and / or power supply 32 described later, may be placed inside the ceramic member 1111a. In this case, at least one bias electrode functions as a lower electrode. Also, the conductive member of the base 1110 and the bias electrode inside the ceramic member 1111a may function as multiple lower electrodes. In one embodiment, the first voltage generation unit 32a, which functions as a voltage pulse generation unit described later, is electrically connected or coupled to the bias electrode inside the ceramic member 1111a, and the first RF generation unit 31a, described later, is electrically connected or coupled to the conductive member of the base 1110. Furthermore, the electrostatic chuck electrode 1111b may function as a lower electrode. Therefore, the substrate support portion 11 includes at least one lower electrode. 【0016】 The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one covering ring. The edge rings are formed of a conductive or insulating material, and the covering rings are formed of an insulating material. 【0017】 The substrate support section 11 may also include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid such as brine or gas flows through the flow path 1110a. In one embodiment, the flow path 1110a is formed within the base 1110, and one or more heaters are arranged within the ceramic member 1111a of the electrostatic chuck 1111. The substrate support section 11 may also include a heat transfer gas supply section configured to supply heat transfer gas to the gap between the back surface of the substrate W and the central region 111a. 【0018】 The showerhead 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas inlet ports 13c. The processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s through the plurality of gas inlet ports 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas introduction unit may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the side wall 10a. 【0019】 The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one processing gas to the shower head 13 from a corresponding gas source 21 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of at least one processing gas. 【0020】The power supply system 30 includes a power supply 31 that is electrically connected to or coupled to the plasma processing chamber 10. In one embodiment, the power supply 31 is electrically connected to or coupled to the plasma processing chamber 10 via at least one impedance matcher. The impedance matcher may be a mechanically controlled matcher or an electronically controlled matcher. The power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates plasma from at least one processing gas supplied to the plasma processing space 10s. Therefore, the power supply 31 can function as at least part of the plasma generation unit 12. In addition, by supplying a bias RF signal to at least one lower electrode, a bias potential is generated on the substrate W, and ionic components in the formed plasma can be drawn into the substrate W. 【0021】 The power supply 31 includes a first RF generation unit 31a and a second RF generation unit 31b. The first RF generation unit 31a is electrically connected or coupled to at least one lower electrode and / or at least one upper electrode and is configured to generate a source RF signal (source RF power) to generate plasma in the plasma processing space 10s. In one embodiment, the first RF generation unit 31a is electrically connected or coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matcher. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generation unit 31a may be configured to generate a plurality of source RF signals having different frequencies. One or more generated source RF signals are supplied to at least one lower electrode and / or at least one upper electrode. 【0022】The second RF generation unit 31b is electrically connected to or coupled to at least one lower electrode and is configured to generate a bias RF signal (bias RF power). In one embodiment, the second RF generation unit 31b is electrically connected to or coupled to at least one lower electrode via at least one impedance matcher. If the first RF generation unit 31a is electrically connected to or coupled to a lower electrode, the second RF generation unit 31b may be electrically connected to or coupled to the same lower electrode, or it may be electrically connected to or coupled to a different lower electrode. The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a lower frequency than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 100 MHz. In one embodiment, the second RF generation unit 31b may be configured to generate a plurality of bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed. 【0023】 The power supply system 30 may also include a power supply 32 that is electrically connected to or coupled to the plasma processing chamber 10. The power supply 32 includes a first voltage generation unit 32a and a second voltage generation unit 32b. In one embodiment, the first voltage generation unit 32a is electrically connected to or coupled to at least one lower electrode and is configured to generate a first voltage signal. The generated first voltage signal is applied to at least one lower electrode. In one embodiment, the second voltage generation unit 32b is electrically connected to or coupled to at least one upper electrode and is configured to generate a second voltage signal. The generated second voltage signal is applied to at least one upper electrode. 【0024】In various embodiments, the first and / or second voltage signals may be pulsed. In this case, the first voltage generation unit 32a and / or the second voltage generation unit 32b function as voltage pulse generation units configured to generate a sequence of voltage pulses. Thus, the sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. In one embodiment, the sequence of voltage pulses has a plurality of cycles, each cycle including a burst of voltage pulses in a first period and a constant reference voltage in a second period. That is, in the sequence of voltage pulses, the burst of voltage pulses is repeated. The absolute value of the voltage level of the voltage pulse is greater than the absolute value of the voltage level of the reference voltage. The voltage pulse may have an arbitrary waveform having a rectangle, trapezoid, triangle, or a combination thereof, and the arbitrary waveform may change over time. The voltage pulse may have positive polarity or negative polarity. The sequence of voltage pulses may also include one or more positive voltage pulses and one or more negative voltage pulses within one cycle. The first and second voltage generation units 32a and 32b may be provided in addition to the power supply 31, and the first voltage generation unit 32a may be provided in place of the second RF generation unit 31b. 【0025】 The exhaust system 40 may be connected to, for example, a gas outlet 10e located at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 10s. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof. 【0026】 The following refers to Figure 3. Figure 3 is a diagram showing a plasma processing apparatus according to one exemplary embodiment. As shown in Figure 3, the plasma processing apparatus 1 includes a power supply system 50 used as a power supply system 30. The power supply system 50 includes a power supply 51, a power supply 52, and a control circuit 50c. The power supply system 50 may further include a power supply 53. 【0027】Power supply 51 is a first power supply, as an example. Power supply 51 is electrically coupled to the substrate support portion 11 (for example, the lower electrode). Power supply 51 is configured to generate a first bias signal, i.e., bias signal BS1, for drawing ions from the plasma in the chamber 10 to the substrate W on the substrate support portion 11. 【0028】 Figure 4 shows an example of the waveform of the first bias signal. As shown in Figure 4, the waveform of the bias signal BS1 has a waveform period Cb. The waveform period Cb is the shortest period of the waveform of the bias signal BS1. The waveform period Cb has a time length that is the reciprocal of the first frequency f1. The first frequency f1 can be a frequency between 50 kHz and 4 MHz. 【0029】 The bias signal BS1 may be a bias RF signal having a first frequency f1, as shown in the lower part of Figure 4. In this case, the bias signal BS1 is a high-frequency power (RF power) having a first frequency f1 and has a sinusoidal waveform that is periodically generated with a waveform period Cb. In this case, the power supply 51 is composed of a second RF generation unit 31b or another RF generation unit. In this case, the power supply 51 is electrically coupled to the substrate support unit 11 via a matching unit 51m. The variable impedance of the matching unit 51m is set to reduce the reflection of the bias signal BS1 from the load of the power supply 51. 【0030】Alternatively, the bias signal BS1 may include voltage pulses VP that are generated periodically at time intervals equal to the time length of the waveform period Cb, as shown in the upper part of Figure 4. In this case, the power supply 51 is composed of a first voltage generation unit 32a and supplies a sequence of voltage pulses VP to the substrate support unit 11 as periodically generated voltage pulses VP. The waveform of each voltage pulse VP may be a square wave, a triangular wave, or any other waveform. The polarity of the voltage of the voltage pulse VP is set so that a potential difference is generated between the substrate W and the plasma, thereby attracting ions from the plasma to the substrate W. The voltage pulses VP are supplied to the substrate support unit 11 such that the waveform period Cb includes a period during which the potential of the substrate W is at a negative potential. Each voltage pulse VP may have a negative potential, a positive potential, or a potential that changes between a positive potential and a negative potential. The voltage pulse VP may be a pulse of negative voltage or a pulse of negative DC voltage. Furthermore, if the bias signal BS1 includes a voltage pulse VP, the plasma processing device 1 does not need to include a matching circuit 51m. 【0031】 Returning to Figure 3, power supply 52 is a second power supply in one example. Power supply 52 is electrically coupled to the substrate support 11 (e.g., the lower electrode) and is configured to generate a second bias signal, i.e., bias signal BS2, which is an RF signal. Power supply 52 is a separate power supply from power supply 51 and consists of a second RF generation unit 31b or another RF generation unit. The bias signal BS2 has a second frequency f2. The second frequency f2 is higher than the first frequency f1. The second frequency f2 is adjusted within the range of 4 MHz or more and 200 MHz or less. Power supply 52 is electrically coupled to the substrate support 11 (e.g., the lower electrode) via a matching unit 52m. The variable impedance of the matching unit 52m is set to reduce the reflection of the bias signal BS2 from the load of power supply 52. 【0032】Power supply 53 is a third power supply in one example. Power supply 53 is electrically coupled to the upper conductor 18 and is configured to generate an RF signal, i.e., a source RF signal HF, in order to generate plasma from the gas in the chamber 10. Power supply 53 consists of a first RF generation unit 31a. The upper conductor 18 is the upper electrode (hereinafter referred to as "upper electrode 14") described above when the plasma processing apparatus 1 is a capacitively coupled plasma processing apparatus. The upper conductor 18 is the antenna 16 described later when the plasma processing apparatus 1 is an inductively coupled plasma processing apparatus. The source RF signal HF has a third frequency f3. When the plasma processing apparatus 1 is a capacitively coupled plasma processing apparatus, the third frequency f3 can be adjusted within the range of 4 MHz or more and 250 MHz or less. When the plasma processing apparatus 1 is an inductively coupled plasma processing apparatus, the third frequency f3 can be adjusted within the range of 1 MHz or more and 60 MHz or less. Power supply 53 is electrically coupled to the upper conductor 18 via a matching unit 53m. The variable impedance of the matching circuit 53m is set to reduce reflections of the source RF signal HF from the load. 【0033】 The control circuit 50c is configured to control the power supplies 51 to 53. The control circuit 50c may be part of any of the power supplies 51 to 53. Alternatively, the control circuit 50c may be a separate circuit from the power supplies 51 to 53. Details of the control circuit 50c will be described later. 【0034】 The following refers to Figures 5 to 10. Each of Figures 5 to 10 is a diagram showing an example of a plasma processing apparatus according to one exemplary embodiment. In Figures 5 to 10, the matching unit 51m, sensor 51s, sensor 52s, and sensor 53s are omitted, but the plasma processing apparatus 1 shown in each of Figures 5 to 10 may also include the matching unit 51m, sensor 51s, sensor 52s, and sensor 53s, as shown in Figure 3. 【0035】As shown in Figure 5, the plasma processing apparatus 1 may be a capacitively coupled plasma processing apparatus and may include an upper electrode 14 as the upper conductor 18. Alternatively, as shown in Figure 6, the plasma processing apparatus 1 may be an inductively coupled plasma processing apparatus and may include an antenna 16 as the upper conductor 18. When the plasma processing apparatus 1 is an inductively coupled plasma processing apparatus, the top of the chamber 10 includes a dielectric window 15. The antenna 16 is provided on the dielectric window 15. The antenna 16 includes at least one coil. In the example of Figure 6, the antenna 16 includes coils 161 and 162. Each of coils 161 and 162 extends in a spiral shape. Each of coils 161 and 162 may extend around the central axis of the chamber 10. Coil 161 is located inside coil 162. A source RF signal HF from the power supply 53 is distributed to each of coils 161 and 162. 【0036】 In the example shown in Figure 6, the gas introduction section of the plasma processing apparatus 1 includes a central gas injection section (CGI) 13B. The central gas injection section 13B is positioned above the substrate support section 11 and is attached to a central opening formed in the dielectric window 15. The central gas injection section 13B has at least one gas supply port 13Ba, at least one gas flow path 13Bb, and at least one gas inlet 13Bc. The processing gas supplied from the gas supply section 20 to the gas supply port 13Ba passes through the gas flow path 13Bb and is introduced into the plasma processing space 10s from the gas inlet 13Bc. In addition to or instead of the central gas injection section 13B, the gas introduction section may also include one or more side gas injection sections (SGIs) attached to one or more openings formed in the side wall of the chamber 10. 【0037】As shown in Figures 7 and 8, the plasma processing apparatus 1 may further include a drive mechanism 19. The drive mechanism 19 is configured to change the vertical gap length between the top portion defining the plasma processing space 10s from above the substrate support portion 11 and the substrate support portion 11. The drive mechanism 19 includes an actuator such as a cylinder or motor. In the example of Figure 7, the drive mechanism 19 is capable of moving the substrate support portion 11 up and down. In the example of Figure 8, the drive mechanism 19 is configured to move the upper electrode 14 up and down. 【0038】 As shown in Figure 9, the plasma processing apparatus 1 may further include an auxiliary electrode 23 and a drive mechanism 24. The auxiliary electrode 23 is arranged around the substrate support portion 11. The auxiliary electrode 23 may have a ring shape. The auxiliary electrode 23 may be electrically grounded. The potential of the auxiliary electrode 23 may be set to a potential other than the ground potential. The drive mechanism 24 is configured to move the auxiliary electrode 23 up and down. The drive mechanism 24 includes an actuator such as a cylinder or motor. 【0039】 As shown in Figure 10, the plasma processing apparatus 1 may further include an electromagnet 25 and a power supply 26. The electromagnet 25 includes at least one coil. In the example in Figure 10, the electromagnet 25 includes coil 251 and coil 252. Coils 251 and 252 extend around the central axis of the chamber 10. Coil 251 is located above the chamber 10. Coil 252 is located below coil 251 and is arranged to surround the chamber 10. The number of coils in the electromagnet 25 and the arrangement of one or more coils in the electromagnet 25 are not limited to those shown. The power supply 26 supplies current to the electromagnet 25 (e.g., coils 251 and 252) to generate a magnetic field in the chamber 10 by the electromagnet 25. If the electromagnet 25 includes two or more coils, the power supply 26 is capable of supplying individually tuned currents to each of the two or more coils of the electromagnet 25. 【0040】Hereinafter, Figures 11 to 14 will be referred to together with Figure 3. Each of Figures 11 to 14 is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. In each of Figures 11 to 14, "ON" of the bias signal BS1 indicates that the bias signal BS1 is being supplied to the substrate support 11. "OFF" of the bias signal BS1 indicates that the supply of the bias signal BS1 to the substrate support 11 has been stopped. 【0041】 Furthermore, in each of Figures 11 to 14, "ON" for bias signal BS2 indicates that bias signal BS2 is being supplied to the substrate support 11. "OFF" for bias signal BS2 indicates that the supply of bias signal BS2 to the substrate support 11 has been stopped. "HIGH" for bias signal BS2 indicates that a bias signal BS2 with a signal level greater than that of bias signal BS2 indicated as "LOW" is being supplied. Note that the signal level of bias signal BS2 is the power level of bias signal BS2. 【0042】 Furthermore, in each of Figures 11 to 14, "ON" for the source RF signal HF indicates that the source RF signal HF is being supplied to the upper conductor 18. "OFF" for the source RF signal HF indicates that the supply of the source RF signal HF to the upper conductor 18 has been stopped. "HIGH" for the source RF signal HF indicates that a source RF signal HF with a signal level greater than that of the source RF signal HF indicated as "LOW" is being supplied. Note that the signal level of the source RF signal HF is the power level of the source RF signal HF. 【0043】 As shown in Figure 11, power supplies 51 and 52 may continuously supply bias signals BS1 and BS2 to the substrate support section 11, for example, in accordance with control by the control circuit 50c, from the start to the end of processing on the substrate W in the chamber 10. Power supply 53 may also continuously supply a source RF signal HF in parallel with the supply of bias signal BS2, for example, in accordance with control by the control circuit 50c, from the start to the end of processing on the substrate W in the chamber 10. 【0044】 As shown in FIG. 12, the power supply 51 may periodically supply pulses of the bias signal BS1, for example, in response to control by the control circuit 50c, from the start to the end of the process on the substrate W in the chamber 10. The pulses of the bias signal BS1 are periodically supplied with a pulse period Cp. As shown in FIG. 13(a), the bias signal BS1 is in the ON state during the period PO within the pulse period Cp and is supplied to the substrate support portion 11. Also, the bias signal BS1 is in the OFF state during the periods other than the period PO within the pulse period Cp and is not supplied to the substrate support portion 11. As shown in FIG. 13(b), each pulse of the bias signal BS1 includes a repetition of the waveform period Cb. 【0045】 As shown in FIG. 12, the power supply 52 may periodically supply pulses of the bias signal BS2, for example, in response to control by the control circuit 50c, from the start to the end of the process on the substrate W in the chamber 10. The pulses of the bias signal BS2 are periodically supplied with a pulse period Cp. Each pulse of the bias signal BS2 includes a repetition of the shortest period of the waveform of the bias signal BS2. 【0046】 In one embodiment, the control circuit 50c can supply a pulse signal PS that is periodically generated with a pulse period Cp to the power supply 51 and the power supply 52. The power supply 51 and the power supply 52 can supply the pulses of the bias signal BS1 and the pulses of the bias signal BS2 in synchronization with the pulse signal PS. 【0047】 Also, the power supply 53 may periodically supply pulses of the source RF signal HF with a pulse period Cp, for example, in response to control by the control circuit 50c, from the start to the end of the process on the substrate W in the chamber 10, in parallel with the supply of the pulses of the bias signal BS1 and the pulses of the bias signal BS2. The power supply 53 can supply the pulses of the source RF signal HF in synchronization with the pulse signal PS. Each pulse of the source RF signal HF includes a repetition of the shortest period of the waveform of the source RF signal HF. 【0048】As shown in FIG. 14, the processing of the substrate W in the chamber 10 may include a process that is periodically repeated. In this case, the process is repeated at a cycle Cd, and the process conditions are periodically changed at the cycle Cd. Within the cycle Cd, the process conditions change over time to at least two different states. In the example shown in FIG. 14, the cycle Cd includes a period PCA during which the process conditions are condition CA and a period PCB during which the process conditions are condition CB. Note that within the cycle Cd, the process conditions may change over time to three or more different states. 【0049】 The change in the process conditions as shown in FIG. 14 can be brought about by the control of each part of the plasma processing apparatus 1 by the control unit 2. The change in the process conditions can include one or more of a change in the current supplied from the power source 26 to the electromagnet 25, a change in the gas supplied into the chamber 10 by the gas supply unit 20, a change in the pressure within the chamber 10 adjusted by the exhaust system 40, a change in the gap length described above by the drive mechanism 19, and a change in the vertical position of the auxiliary electrode 23 by the drive mechanism 24. 【0050】 Within the cycle Cd of the example shown in FIG. 14, as in the example of FIG. 12, the pulses of the bias signal BS1 and the pulses of the bias signal BS2 can be periodically supplied at a pulse period Cp. That is, the cycle Cd of the process can include a repetition of the pulse period Cp. Also, within the cycle Cd of the process, the pulses of the source RF signal HF may be periodically supplied at the pulse period Cp. 【0051】 The control circuit 50c controls the power source 51 and the power source 52 so as to supply the bias signal BS1 and the bias signal BS2 to the substrate support unit 11 in each of a plurality of repetition cycles (hereinafter referred to as "a plurality of repetition cycles Cr"). Each of the plurality of repetition cycles Cr is, as will be described later, the waveform period Cb, the pulse period Cp, or the cycle Cd of the process. 【0052】The control circuit 50c adjusts the second frequency f2 in each of the multiple sub-periods Pb within each of the multiple repetition periods Cr to improve the first matching degree, according to the degree of impedance matching of the load impedance of the power supply 52 in the same sub-period within the preceding repetition period Cr (hereinafter sometimes referred to as the "first matching degree"). The load impedance of the power supply 52 is the impedance of the load as seen from the power supply 52. ​​The first matching degree is the degree of matching of the load impedance of the power supply 52 with respect to the output impedance or characteristic impedance of the power supply 52. ​​The control circuit 50c may also adjust the second frequency f2 in each of the multiple sub-periods Pb within each of the multiple repetition periods Cr to improve the first matching degree, according to the second frequency f2 in the same sub-period within the preceding repetition period Cr and the first matching degree. In one embodiment, the control circuit 50c adjusts the second frequency f2 in each of the multiple sub-periods Pb within each of the multiple repetition periods Cr, according to the degree of reflection of the bias signal BS2 from the load of the power supply 52 and the second frequency f2 in the same sub-period within the preceding repetition period Cr, in order to reduce the degree of reflection of the bias signal BS2. The control circuit 50c may adjust the second frequency f2 by a feedback process described later. Note that the closer the first matching degree is to the ideal matching state, that is, the higher the first matching degree, the smaller the degree of reflection of the bias signal BS2. 【0053】 Multiple sub-periods Pb are multiple periods that divide each iterative period Cr. In one embodiment, when a bias RF signal is used as the bias signal BS1, the power supply system 50 or plasma processing apparatus 1 may further include a sensor 51s. The sensor 51s measures the voltage and / or current of the bias signal BS1 in the power supply path for the bias signal BS1 that connects the power supply 51 and the substrate support 11 to each other. The control circuit 50c may determine the multiple sub-periods Pb by identifying the waveform period Cb of the bias signal BS1 from the voltage or current measured by the sensor 51s and dividing the identified waveform period Cb. 【0054】To determine the degree of reflection (or first matching degree) of the bias signal BS2 in each subperiod Pb, the power supply system 50 or plasma processing apparatus 1 may further include a sensor 52s. The sensor 52s measures a signal that reflects the degree of reflection (or first matching degree) of the bias signal BS2 in the power supply path for the bias signal BS2 connecting the power supply 52 and the substrate support 11 to each other. The control circuit 50c uses the measured signal from the sensor 52s in each subperiod Pb to determine the degree of reflection (or first matching degree) of the bias signal BS2 in each subperiod Pb. 【0055】 The sensor 52s may include a directional coupler. In this case, the control circuit 50c may determine the degree of reflection (or first degree of matching) of the bias signal BS2 in each sub-period Pb as the power level of the reflected wave of the bias signal BS2, the power level of the forward wave of the bias signal BS2, or the reflectance of the bias signal BS2. 【0056】 Alternatively, the sensor 52s may include a voltage sensor and a current sensor. In this case, the control circuit 50c may determine the degree of reflection (or first matching degree) of the bias signal BS2 in each sub-period Pb as the phase difference between the voltage and current of the bias signal BS2, determined from the measurement results of the sensor 52s in each sub-period Pb, i.e., the voltage and current of the bias signal BS2, the impedance of the load of the power supply 52, or the reflection coefficient of the bias signal BS2. The first matching degree may also be determined from a measurement of plasma emission in the chamber 10 acquired by another sensor (e.g., light intensity). 【0057】In one embodiment, the control circuit 50c may adjust the third frequency f3 in each of the multiple sub-periods Pb within each of the multiple repetition periods Cr to improve the second matching degree, according to the degree of impedance matching of the load impedance of the power supply 53 in the same sub-period within the preceding repetition period Cr (hereinafter sometimes referred to as the "second matching degree"). The load impedance of the power supply 53 is the impedance of the load as seen from the power supply 53. The second matching degree is the degree of matching of the load impedance of the power supply 53 with respect to the output impedance or characteristic impedance of the power supply 53. The control circuit 50c may adjust the third frequency f3 in each of the multiple sub-periods Pb within each of the multiple repetition periods Cr to improve the second matching degree, according to the third frequency f3 in the same sub-period within the preceding repetition period Cr and the second matching degree. In one embodiment, the control circuit 50c may adjust the third frequency f3 in each of the multiple sub-periods Pb within each of the multiple repetition periods Cr, according to the third frequency f3 in the same sub-period within the preceding repetition period Cr and the degree of reflection of the source RF signal HF from the load of the power supply 53, in order to reduce the degree of reflection of the source RF signal HF. The control circuit 50c may adjust the third frequency f3 by a feedback process described later. Note that the closer the second matching degree is to the ideal matching state, that is, the higher the second matching degree, the smaller the degree of reflection of the source RF signal HF becomes. 【0058】 To determine the degree of reflection (or second degree of matching) of the source RF signal HF in each subperiod Pb, the power supply system 50 or plasma processing apparatus 1 may further include a sensor 53s. The sensor 53s measures a signal that reflects the degree of reflection (or second degree of matching) of the source RF signal HF in the feed path for the source RF signal HF connecting the power supply 53 and the upper conductor 18 to each other. The control circuit 50c may use the measured signal from the sensor 53s in each subperiod Pb to determine the degree of reflection (or second degree of matching) of the source RF signal HF in each subperiod Pb. 【0059】The sensor 53s may include a directional coupler. In this case, the control circuit 50c may determine the degree of reflection (or second degree of matching) of the source RF signal HF in each sub-period Pb as the power level of the reflected wave of the source RF signal HF, the power level of the forward wave of the source RF signal HF, or the reflectance of the source RF signal HF. 【0060】 Alternatively, the sensor 53s may include a voltage sensor and a current sensor. In this case, the control circuit 50c may determine the degree of reflection (or second matching degree) of the source RF signal HF in each sub-period Pb as the phase difference between the voltage and current of the source RF signal HF, determined from the measurement results of the sensor 53s in each sub-period Pb, i.e., the voltage and current of the source RF signal HF, the impedance of the load of the power supply 53, or the reflection coefficient of the source RF signal HF. The second matching degree may be determined from a measurement of plasma emission in the chamber 10 acquired by another sensor (e.g., light intensity). 【0061】 The following describes the feedback process. In one embodiment, the feedback process includes a first feedback process. In the first feedback process, each of the multiple repetition periods Cr is a waveform period Cb. The first feedback process is used when bias signals BS1 and BS2 are supplied continuously, as shown in the example in Figure 11. The first feedback process is also used when a source RF signal HF is supplied continuously along with bias signals BS1 and BS2. 【0062】The second feedback process is used when pulses of bias signal BS1 and bias signal BS2 are supplied periodically, as shown in Figure 12. The second feedback process is also used when pulses of source RF signal HF are supplied periodically along with pulses of bias signal BS1 and bias signal BS2. In the second feedback process, each of the multiple repetition periods Cr is a pulse period Cp. The period PO within the pulse period Cp includes periods PA and PB (see Figure 13(a)). Period PA is the period before period PB and may include the start of period PO. In this case, the second feedback process may be applied during period PA, and the first feedback process may be applied during period PB after period PA. That is, during period PB, each of the multiple repetition periods Cr may be a waveform period Cb. 【0063】 The third feedback process is used when the process is performed periodically, as shown in Figure 14. In the third feedback process, the iteration period Cr is the process period Cd. 【0064】 In one embodiment, the period Cd may include a repetition of the pulse period Cp. In this case, the third feedback process may be applied during period PA within period PO within the pulse period Cp, and the first feedback process may be applied during period PB after period PA within period PO within the pulse period Cp. 【0065】As described above, the first feedback process, the second feedback process, and the third feedback process differ from each other only in that their repetition period Cr is different. Below, the first feedback process, the second feedback process, and the third feedback process will be explained together by describing an example of feedback processing performed on the repetition period Cr in the control circuit 50c. In the following explanation, the nth sub-period Pb within the repetition period Cr will be called sub-period Pb[n], and the mth repetition period Cr in the repetition of the repetition period Cr will be called repetition period Cr[m]. Also, in the following explanation, the second frequency f2 in the sub-period Pb[n] within the repetition period Cr[m] will be called f2[m,n], and the third frequency f3 in the sub-period Pb[n] within the repetition period Cr[m] will be called f3[m,n]. Furthermore, in the following explanation, the degree of reflection of the bias signal BS2 during the subperiod Pb[n] within the repetition period Cr[m] is referred to as R2[m,n], and the degree of reflection of the source RF signal HF during the subperiod Pb[n] within the repetition period Cr[m] is referred to as R3[m,n]. 【0066】 In the feedback process, the control circuit 50c reverses the sign of the shift value Δf2[n] if the degree of reflection of the bias signal BS2 in the same sub-period in the repetition of the preceding repetition period Cr[m] is increasing (or the first matching degree is decreasing). The shift value Δf2[n] has an adjustment amount and a sign. The adjustment amount is a positive value, and the shift value Δf2[n] is obtained by assigning the given sign to the adjustment amount. For example, the control circuit 50c reverses the sign of the shift value Δf2[n] if R2[m-p,n] is increasing relative to R2[m-q,n] (or the first matching degree is decreasing). If R2[m-p,n] is not increasing relative to R2[m-q,n] (or the first matching degree is not decreasing), the control circuit 50c maintains the sign of the shift value Δf2[n]. Here, "p" is an integer greater than or equal to 1, and "q" is an integer greater than p. q may also be 2 × p. 【0067】The control circuit 50c determines f2[m,n] to reduce the degree of reflection of the bias signal BS2 during the subperiod Pb[n] within the repetition period Cr[m] (or to improve the first matching degree) when R2[m-p,n] does not meet the acceptable conditions. For example, when R2[m-p,n] is equal to or greater than a threshold, the control circuit 50c determines f2[m,n] by the following equation (1): f2[m,n] = f2[m-p,n] + Δf2[n] …(1) 【0068】 On the other hand, the control circuit 50c sets f2[m,n] to f2[m-p,n] if R2[m-p,n] satisfies the allowable conditions. 【0069】 Furthermore, in the feedback process, the control circuit 50c reverses the sign of the shift value Δf3[n] if the degree of reflection of the source RF signal HF in the same sub-period in the repetition of the preceding repetition period Cr[m] is increasing (or the second matching degree is decreasing). The shift value Δf3[n] has an adjustment amount and a sign. The adjustment amount is a positive value, and the shift value Δf3[n] is obtained by assigning the given sign to the adjustment amount. For example, the control circuit 50c reverses the sign of the shift value Δf3[n] if R3[m-p,n] is increasing relative to R3[m-q,n] (or the second matching degree is decreasing). If R3[m-p,n] is not increasing relative to R3[m-q,n] (or the second matching degree is not decreasing), the control circuit 50c maintains the sign of the shift value Δf3[n]. 【0070】 The control circuit 50c determines f3[m,n] to reduce the degree of reflection of the source RF signal HF during the subperiod Pb[n] within the repetition period Cr[m] (or to improve the second matching degree) when R3[m-p,n] does not meet the acceptable conditions. For example, when R3[m-p,n] is equal to or greater than a threshold, the control circuit 50c determines f3[m,n] by the following equation (2): f3[m,n] = f3[m-p,n] + Δf3[n] ... (2) 【0071】On the other hand, the control circuit 50c sets f3[m,n] to f3[m-p,n] if R3[m-p,n] satisfies the allowable conditions. 【0072】 According to the plasma processing apparatus 1 described above, regardless of whether the repetition period Cr is the waveform period Cb, the pulse period Cp, or the process period Cd, the degree of reflection of the bias signal BS2 in each sub-period Pb within the repetition period Cr is reduced (or the first matching degree is improved). Furthermore, according to the plasma processing apparatus 1, regardless of whether the repetition period Cr is the waveform period Cb, the pulse period Cp, or the process period Cd, the degree of reflection of the source RF signal HF in each sub-period Pb within the repetition period Cr is reduced (or the second matching degree is improved). 【0073】 Furthermore, in the feedback process, the control circuit 50c may, in addition to adjusting frequencies f2 and f3, modulate the signal levels of the bias signal BS2 and the source RF signal HF within each iteration period Cr. The control circuit 50c may modulate the signal levels of the bias signal BS2 and the source RF signal HF in such a way that the load power levels of the bias signal BS2 and the source RF signal HF approach the target level. 【0074】The following references to Figures 15 and 16. Figures 15 and 16 are timing charts related to a plasma processing apparatus according to one exemplary embodiment. Figures 15 and 16 show the time evolution of the signal levels of bias signal BS1, bias signal BS2, and source RF signal HF. When bias signal BS1 is a bias RF signal, the signal level of bias signal BS1 is the power level of bias signal BS1. When bias signal BS1 includes a voltage pulse VP, the signal level of bias signal BS1 is the absolute value of the difference between the reference potential (e.g., 0V) and the voltage level of the voltage pulse VP. The voltage pulse VP may have a potential in the negative direction with respect to the reference potential. As shown in Figures 15 and 16, when pulses of bias signal BS1, bias signal BS2, and source RF signal HF are supplied, the signal levels of bias signal BS1, bias signal BS2, and source RF signal HF may each change to two or more levels (multilevel) within the pulse period Cp. 【0075】 The following refers to Figures 17 to 20. Each of Figures 17 to 20 is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. In one embodiment, the control circuit 50c may delay the start of supplying one of the bias signal BS2 and the source RF signal HF relative to the start of supplying the other of the bias signal BS2 and the source RF signal HF in at least the first iteration of a plurality of iteration periods Cr. In this case, it is possible to reduce the degree of reflection of the other of the bias signal BS2 and the source RF signal HF more quickly compared to when the start of supplying the bias signal BS2 and the start of supplying the source RF signal HF are simultaneous. 【0076】The examples in Figures 17 to 20 are cases in which pulses of bias signal BS1, pulses of bias signal BS2, and pulses of source RF signal HF are supplied periodically. In each example in Figures 17 to 20, the start timing of the supply of pulses of source RF signal HF and the start timing of the supply of pulses of bias signal BS2 are delayed relative to the pulse signal PS. As shown in Figures 17 to 20, the start of the supply of pulses of bias signal BS1 may coincide with the timing of the leading edge of pulse signal PS, or it may be delayed from the timing of the leading edge of pulse signal PS. Also, the start timing of the supply of the leading pulse of either the pulse of bias signal BS2 or the pulse of source RF signal HF may coincide with the timing of the leading edge of pulse signal PS, or it may be delayed from the timing of the leading edge of pulse signal PS. Furthermore, the stop timing of the supply of pulses of bias signal BS2 and / or pulses of source RF signal HF may coincide with the timing of the trailing edge of pulse signal PS, or it may be delayed from the timing of the trailing edge of pulse signal PS. 【0077】 Refer to Figure 21 below. Figure 21 is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. In one embodiment, the control circuit 50c may delay the start of the feedback adjustment of one of the second frequency f2 and the third frequency f3 relative to the start of the feedback adjustment of the other of the second frequency f2 and the third frequency f3. In this case, compared to the case where the start of the adjustment of the second frequency f2 and the start of the adjustment of the third frequency f3 are simultaneous, it is possible to reduce the degree of reflection of the bias signal BS2 and the source RF signal HF having the other frequency earlier. 【0078】In the example shown in Figure 21, the pulses of bias signal BS1, bias signal BS2, and source RF signal HF are supplied periodically. In the example in Figure 21, the start of the adjustment of the third frequency f3 by feedback processing is delayed from the adjustment of the second frequency f2 by feedback processing in the first pulse period Cp. In addition, in each of two or more or all pulse periods Cp in the repetition of pulse period Cp, the start of the adjustment of one of the second frequency f2 and the third frequency f3 by feedback processing may be delayed from the start of the adjustment of the other of the second frequency f2 and the third frequency f3 by feedback processing. 【0079】 Refer to Figure 22 below. Figure 22 is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. In one embodiment, the control circuit 50c may increase the signal level of one of the bias signal BS2 and the source RF signal HF in proportion to the elapsed time from the start of at least the first iteration period of a plurality of iteration periods Cr. In this case, it is possible to reduce the degree of reflection of the other of the bias signal BS2 and the source RF signal HF more quickly compared to the case in which each of the bias signal BS2 and the source RF signal HF has a constant signal level from the start of supply. 【0080】 In the example shown in Figure 22, the pulses of bias signal BS1, bias signal BS2, and source RF signal HF are supplied periodically. In the example in Figure 22, the signal level of source RF signal HF is increased in proportion to the elapsed time from the start of each pulse period Cp. 【0081】Refer to Figure 23 below. Figure 23 is a timing chart related to a plasma processing apparatus according to one exemplary embodiment. In one embodiment, the control circuit 50c may be configured to increase, in accordance with the elapsed time from the start of at least the first iteration of a plurality of iteration periods Cr, one of the adjustment amounts of the second frequency f2 for reducing the degree of reflection of the bias signal BS2 (or improving the first matching degree) and the adjustment amount of the third frequency f3 for reducing the degree of reflection of the source RF signal HF (or improving the second matching degree). In this case, the control circuit 50c may keep the other adjustment amount of the adjustment amount of the second frequency f2 and the adjustment amount of the third frequency f3 constant in at least the first iteration of a plurality of iteration periods Cr. In this case, it is possible to reduce the degree of reflection of the bias signal BS2 and the source RF signal HF whose frequencies are adjusted by the other adjustment amount more quickly. 【0082】 In one embodiment, the control circuit 50c may, at least in the first iteration cycle, increase the one adjustment amount to its maximum value and then maintain the one adjustment amount at its maximum value. In this case, the degree of reflection of the bias signal BS2 and the source RF signal HF, whose frequencies are adjusted by the one adjustment amount, can be reduced more quickly. 【0083】 In one embodiment, the control circuit 50c may maintain the one adjustment amount at its maximum value for at least the first iteration period, and then decrease the one adjustment amount. In another embodiment, the control circuit 50c may decrease the one adjustment amount to a steady state for at least the first iteration period, and then maintain the one adjustment amount at a steady state. In this case, the amount of change in frequency after the one adjustment amount reaches a steady state becomes small, so that the matching state can be stabilized. 【0084】The example in Figure 23 is one in which pulses of bias signal BS1, pulses of bias signal BS2, and pulses of source RF signal HF are supplied periodically. In the example in Figure 23, at each pulse period Cp, the adjustment amount of the third frequency f3 of the source RF signal HF is increased according to the elapsed time from the start of each pulse period Cp. Also, in the first period following the start of pulse period Cp, the change in plasma density is large, so the adjustment amount of the third frequency f3 is gradually increased from a small value. In the second period following the first period, the adjustment amount of the third frequency f3 is maintained at its maximum value. In the second period, the degree of reflection of the source RF signal HF can be reduced more quickly. In the third period following the second period, the adjustment amount of the third frequency f3 is reduced until it reaches a steady value, and then in the subsequent fourth period, the adjustment amount of the third frequency f3 is maintained at a steady value. In the fourth period, the change in plasma density is small, so the adjustment amount of the third frequency f3 is maintained at a small value. 【0085】 The following describes a frequency control method according to one exemplary embodiment with reference to Figure 24. Figure 24 is a flowchart showing a frequency control method according to one exemplary embodiment. In the frequency control method shown in Figure 24 (hereinafter referred to as "Method MT"), a bias signal BS1 is supplied to the substrate support 11 in step STa. A bias signal BS2 is supplied to the substrate support 11 in step STb. A source RF signal HF is supplied to the upper conductor 18 in step STc. 【0086】 Furthermore, in process STd, the second frequency f2 in each sub-period Pb within each iteration period Cr is adjusted. Also, in process STe, the third frequency f3 in each sub-period Pb within each iteration period Cr is adjusted. For details on the adjustment of the second frequency f2 and the third frequency f3 in each sub-period Pb within each iteration period Cr, please refer to the above explanation regarding the plasma processing apparatus 1. In process STJ, it is determined whether or not the stop condition is met. If it is determined in process STJ that the stop condition is not met, the process proceeds to process STa. On the other hand, if it is determined in process STJ that the stop condition is met, method MT is terminated. 【0087】 The following describes examples of circuits (control circuits) that may constitute the control unit 2 and / or control circuit 50c. 【0088】 Figure 25 illustrates a block diagram of a computer (a type of circuit) capable of implementing the various control modes described herein. Furthermore, the control modes of this disclosure can be implemented as a system, method, and / or computer program product. The computer program product may include a computer-readable storage medium on which computer-readable program instructions causing one or more processing units to execute the modes of this embodiment are recorded. 【0089】 A computer-readable storage medium may be a tangible device capable of storing instructions used by an instruction execution device (processor). A computer-readable storage medium may, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples of computer-readable storage media include, but are not exhaustive, flexible disks, hard disks, solid-state drives (SSDs), random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash), static random-access memory (SRAM), compact disks (CDs or CD-ROMs), digital multipurpose disks (DVDs), memory cards or memory sticks (and suitable combinations thereof). In this disclosure, a computer-readable storage medium should not be interpreted as a transient signal itself, such as, for example, radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses passing through optical fiber cables), or electrical signals transmitted via wires. 【0090】The computer-readable program instructions described in this disclosure can be downloaded from a computer-readable storage medium to a suitable computing device or processing device, or they can be downloaded to an external computer or external storage device via a global network (i.e., the Internet), a local area network, a wide area network, and / or a wireless network. Networks include transmission copper wires, optical fiber, wireless communications, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface of each computing device or processing device can receive computer-readable program instructions from the network, transfer those computer-readable program instructions, and store them in a computer-readable storage medium within the computing device or processing device. 【0091】Computer-readable program instructions for performing the operations of the Disclosure may include machine language instructions and / or microcode. These instructions can be compiled or interpreted from source code written in any combination of one or more programming languages, including assembly language, Basic, Fortran, Java®, Python, R, C, C++, C#, etc. Computer-readable program instructions can be fully executed on a user's personal computer, notebook computer, tablet, or smartphone, or may be fully executed on a remote computer or computer server, or on any combination of these computing devices. The remote computer or computer server may be connected to one or more of the user's devices via a computer network, including a local area network, a wide area network, or a global network (i.e., the Internet). Alternatively, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may be configured or customized to execute computer-readable program instructions using information from the computer-readable program instructions and implement embodiments of the Disclosure. 【0092】 This specification will describe aspects of the present disclosure with reference to flowcharts and block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. Those skilled in the art will understand that each block in the flowcharts and block diagrams, as well as combinations of blocks in the flowcharts and block diagrams, can be implemented by computer-readable program instructions. 【0093】Computer-readable program instructions capable of implementing the systems and methods described in this disclosure may be supplied to one or more processors (and / or one or more cores within a processor) of a general-purpose computer, a dedicated computer, or other programmable device. This makes it possible to generate a machine that constructs a system for implementing the functions specifically shown in the flowcharts and block diagrams of this disclosure, through instructions executed via the processors of the computer or other programmable device. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct the computer, programmable device, and / or other device to function in a particular manner. The computer-readable storage medium storing the instructions is a product containing instructions that implement the embodiments of the functions specifically shown in the flowcharts and block diagrams of this disclosure. 【0094】 Furthermore, computer-readable program instructions can be loaded into a computer, another programmable device, or other device, and a series of operations can be executed on that computer, other programmable device, or other device to realize a computer implementation process. Therefore, the functions specifically shown in the flowcharts and block diagrams of this disclosure can be realized by instructions executed on a computer, another programmable device, or other device. 【0095】 Figure 25 is a functional block diagram showing a network system 800 in which one or more computers and servers are connected to a network. In one embodiment, the hardware and software environments illustrated in Figure 25 may serve as an exemplary platform for implementing the software and / or methods relating to this disclosure. 【0096】 Referring to Figure 25, the network system 800 may include, but is not limited to, a computer 805, a network 810, a remote computer 815, a web server 820, a cloud storage server 825, and a computer server 830. In some embodiments, one or more examples of the functional blocks illustrated in Figure 25 may be used. 【0097】 Further details of computer 805 are shown in Figure 25. The functional blocks illustrated within computer 805 are merely illustrative examples for constructing exemplary functions and do not encompass all of its functions. Details of the remote computer 815, web server 820, cloud storage server 825, and computer server 830 are not shown, but these computers and devices may also include functions similar to those shown for computer 805. 【0098】 Computer 805 may be a personal computer (PC), desktop computer, laptop computer, tablet computer, netbook computer, personal data device (PDA), smartphone, or other programmable electronic device capable of communicating with other devices on the network 810. 【0099】 The computer 805 may include a processing unit 835, a bus 837, a memory 840, a non-volatile storage device 845, a network interface 850, a peripheral device interface 855, and a display device interface 865. In some embodiments, these functions may be implemented as individual electronic subsystems (integrated circuit chips or combinations of chips and associated devices), while in other embodiments, some of the combinations of functions may be implemented on a single chip (also known as a system-on-a-chip or SoC). 【0100】The processing unit 835 may be one or more single-chip or multi-chip microprocessors designed and / or manufactured by Intel Corporation, Advanced Micro Devices, Inc. (AMD), Arm Holdings, Apple Computer, etc. Examples of microprocessors include Intel Corporation's Celeron, Pentium®, Core i3, Core i5, Core i7; AMD's Opteron, Phenom, Athlon, Turion, Ryzen; and Arm's Cortex-A, Cortex-R, Cortex-M, etc. 【0101】 Bus 837 may be a proprietary or industry-standard high-speed parallel or serial peripheral interconnect bus such as ISA, PCI, PCI Express (PCI-e), or AGP. 【0102】 The memory 840 and the non-volatile storage device 845 may be computer-readable storage media. The memory 840 may include any suitable volatile storage device such as dynamic random access memory (DRAM) and static random access memory (SRAM). The non-volatile storage device 845 may include one or more of the following: flexible disk, hard disk, solid-state drive (SSD), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash), compact disc (CD or CD-ROM), digital multipurpose disc (DVD), memory card, or memory stick. 【0103】The program 848 may be a collection of machine-readable instructions and / or machine-readable data stored in at least one memory, such as a non-volatile storage device 845, and used to create, manage, and control specific software functions as described in detail and illustrated in the drawings of this disclosure. In some embodiments, memory 840 may be much faster than the non-volatile storage device 845. In that case, the program 848 may be transferred from the non-volatile storage device 845 to memory 840 and then executed by the processing unit 835. The program 848 includes computer program code. In one implementation, at least one memory storing the computer program code comprises at least one processing unit (such as a processing circuit described later) for carrying out the control process and claimed advanced embodiments of this disclosure. 【0104】 Computer 805 may communicate and interact with other computers via network 810 using network interface 850. Network 810 may be, for example, a local area network (LAN), a wide area network (WAN) such as the Internet, or a combination thereof, and may include wired, wireless, or fiber optic connections. In general, network 810 can be any combination of connections and protocols that support communication between two or more computers and associated devices. 【0105】The peripheral interface 855 may enable data input and output via other devices that can be locally connected to the computer 805. For example, the peripheral interface 855 may enable connection to an external device 860. The external device 860 may include devices such as a keyboard, mouse, keypad, touchscreen, and / or other suitable input devices. The external device 860 may also include portable computer-readable storage media such as a thumb drive, portable optical or magnetic disk, and memory card. Software and data used to implement embodiments of the present disclosure (e.g., program 848) may be stored on such portable computer-readable storage media. In this case, the software may be loaded into the non-volatile storage device 845, or directly into memory 840 via the peripheral interface 855. The peripheral interface 855 may use industry-standard connections such as RS-232 or Universal Serial Bus (USB) to connect to the external device 860. 【0106】 The computer 805 may be connected to the display device 870 via the display device interface 865. In one embodiment, the display device 870 may be used to present a command line or a graphical user interface to the user of the computer 805. The display device interface 865 may be connected to the display device 870 using one or more proprietary or industry standard connections such as VGA, DVI, DisplayPort, HDMI®, etc. 【0107】As described above, the network interface 850 enables communication with other computing systems or storage systems or computing devices or storage devices outside of the computer 805. The software programs and data described herein may be downloaded to the non-volatile storage device 845 via the network interface 850 and network 810 from, for example, a remote computer 815, a web server 820, a cloud storage server 825, or a computer server 830. Furthermore, the systems and methods described herein may be implemented by one or more computers connected to the computer 805 via the network interface 850 and network 810. For example, in one embodiment, the systems and methods described herein may be implemented by a combination of a remote computer 815, a computer server 830, or computers interconnected on network 810. 【0108】 The data, datasets, and / or databases used in the embodiments of the systems and methods described herein may be stored in or downloaded from a remote computer 815, a web server 820, a cloud storage server 825, or a computer server 830. 【0109】The circuits used in this application can be defined as one or more of the following: electronic components (such as semiconductor devices), a plurality of electronic components directly connected to each other or interconnected via electronic communication, a computer, a network of computer devices, a remote computer, a web server, a cloud storage server, or a computer server. For example, each of the one or more of the computer, remote computer, web server, cloud storage server, and computer server may be included as a component of the circuit, or may include the circuit. In some embodiments, one or more examples of these components may be used, and each of the one or more examples of these components may also be included in the circuit, or may include the circuit. In some embodiments, a circuit represented by a network system may include a serverless computing system that corresponds to virtualized hardware resources. A circuit represented by a computer may be a personal computer (PC), a desktop computer, a laptop computer, a tablet computer, a netbook computer, a personal data device (PDA), a smartphone, or other programmable electronic device that can communicate with other devices on a network. The circuit may be a general-purpose computer, a dedicated computer, or other programmable device described herein that includes one or more processing units. Each processing unit may be one or more single-chip microprocessors or multi-chip microprocessors. One or more processing units are considered processing circuits or circuits because they incorporate transistors and other circuits. The circuits can implement the systems and methods described in this disclosure based on computer-readable program instructions. These program instructions are supplied to one or more processing units (and / or one or more cores within processing units) of one or more general-purpose computers, dedicated computers, or other programmable devices described herein. This makes it possible to generate a machine that constructs a system for implementing the functions specifically shown in the flowcharts and block diagrams of this disclosure, through instructions contained within the circuits or executed via one or more processing units of a programmable device containing the circuits.Alternatively, a circuit may be a pre-programmed structure, such as a programmable logic device or an application-specific integrated circuit. A circuit is considered a circuit whether it is used alone or in combination with other programmable circuits or other pre-programmed circuits. 【0110】 In light of the above teachings, it is clear that numerous modifications and variations of the present invention are possible. Therefore, it should be understood that, within the scope of the appended claims, the present invention can be implemented in forms other than those specifically described herein. 【0111】 Although various exemplary embodiments have been described above, the invention is not limited to the exemplary embodiments described above, and various additions, omissions, substitutions, and modifications may be made. Furthermore, it is possible to combine elements from different embodiments to form other embodiments. 【0112】For example, the substrate support portion 11 of the plasma processing apparatus 1 according to various exemplary embodiments may have the configuration shown in Figure 26. Figure 26 is a diagram showing another example of a substrate support portion that can be used in the plasma processing apparatus according to various exemplary embodiments. In the example shown in Figure 26, the substrate support portion 11 further has electrodes 1111c and 1111d within the electrostatic chuck 1111. Electrode 1111c is located within the ceramic member 1111a below the substrate support surface and / or the electrostatic chuck electrode 1111b. Electrode 1111c is a conductive film formed from a metallic material and extends horizontally. Electrode 1111c may have a circular shape. Electrode 1111d is located within the ceramic member 1111a below the ring support surface. Electrode 1111d is a conductive film formed from a metallic material and extends horizontally and circumferentially so as to surround electrode 1111c. Electrode 1111d may have a ring shape. In this example, power supply 51 is electrically connected to base 1110 and is configured to supply a bias signal BS1 to base 1110. Power supply 52 is electrically connected to electrodes 1111c and 1111d and is configured to supply a bias signal BS2 to electrodes 1111c and 1111d. Power supply 52 may also be electrically connected to base 1110 and may be configured to supply a bias signal BS2 to base 1110. 【0113】 Herein, various exemplary embodiments included in this disclosure are described in [E1] to [E20] below. 【0114】[E1] A plasma processing apparatus comprising: a chamber; a substrate support disposed within the chamber; a first power supply electrically coupled to the substrate support and configured to generate a first bias signal for drawing ions from the plasma in the chamber to a substrate on the substrate support, wherein the waveform of the first bias signal has a waveform period having a time length inverse of the first frequency; a second power supply electrically coupled to the substrate support and configured to generate a second bias signal which is an RF signal; and a control circuit, wherein the control circuit controls the first power supply and the second power supply to supply the first bias signal and the second bias signal to the substrate support in each of a plurality of iteration periods, and adjusts the second frequency of the second bias signal in each of a plurality of sub-periods in each of the plurality of iteration periods, which have a time length shorter than the time length of the waveform period, in order to improve the impedance matching of the load of the second power supply in the same sub-period in an earlier iteration period among the plurality of iteration periods. 【0115】 [E2] The plasma apparatus according to E1, wherein the control circuit is configured to adjust the second frequency in each of the plurality of sub-periods in each of the plurality of iteration periods, in accordance with the second frequency in the same sub-period within the preceding iteration period. 【0116】 [E3] The plasma processing apparatus according to E1 or E2, wherein each of the plurality of repetition periods is the waveform period, and each of the plurality of sub-periods is a plurality of periods that divide the waveform period. 【0117】[E4] The plasma apparatus according to E3, wherein the first power supply is configured to generate a bias RF signal as the first bias signal, the plasma apparatus further comprises a matching circuit connected between the first power supply and the substrate support, and a sensor configured to measure the voltage or current of the first bias signal between the matching circuit and the substrate support, and the control circuit is configured to identify the start time of the waveform period from the phase of the voltage or current measured by the sensor, and to determine the plurality of sub-periods within the waveform period in which the start time has been identified. 【0118】 [E5] The plasma processing apparatus according to E1 or E2, wherein each of the plurality of repetition periods is the period of the pulse of the first bias signal supplied periodically from the first power supply to the substrate support. 【0119】 [E6] The plasma processing apparatus according to E1 or E2, wherein each of the plurality of repeating periods is the period of a periodically repeated process. 【0120】 [E7] The plasma processing apparatus according to E6, further comprising: an electromagnet arranged around the chamber; and a control unit configured to periodically change the current supplied to the electromagnet at the period of the process. 【0121】 [E8] The plasma apparatus according to E6, further comprising: a gas supply unit configured to supply gas into the chamber; an exhaust system configured to adjust the pressure in the chamber; and a control unit configured to periodically change the pressure in the chamber, which is adjusted by the gas supplied from the gas supply unit into the chamber and / or the exhaust system, at the cycle of the process. 【0122】[E9] The plasma processing apparatus according to E6, further comprising: a top portion defining the plasma processing space in the chamber from above the substrate support portion, or a drive mechanism configured to drive the substrate support portion to change the vertical gap length between the top portion and the substrate support portion; and a control unit configured to control the drive mechanism to periodically change the gap length at the cycle of the process. 【0123】 [E10] The plasma processing apparatus according to E6, further comprising: an auxiliary electrode arranged around the substrate support; a drive mechanism configured to move the auxiliary electrode up and down; and a control unit configured to control the drive mechanism to periodically change the position of the auxiliary electrode along the vertical direction according to the period of the process. 【0124】 [E11] A plasma processing apparatus according to any one of E1 to E10, further comprising: an upper conductor which is an upper electrode or antenna disposed above the plasma processing space in the chamber and the substrate support; and a third power supply electrically coupled to the upper conductor and configured to generate a source RF signal for generating plasma from the gas in the chamber, wherein the control circuit is configured to adjust the third frequency of the source RF signal in each of the plurality of sub-periods in each of the plurality of iteration cycles to improve the impedance matching of the load of the third power supply in the same sub-period in the preceding iteration cycle. 【0125】 [E12] The plasma processing apparatus according to E11, wherein the control circuit is configured to delay the start of supplying one of the second bias signal and the source RF signal relative to the start of supplying the other of the second bias signal and the source RF signal in at least the first of the plurality of iteration periods. 【0126】[E13] The plasma processing apparatus according to E11, wherein the control circuit is configured to delay the start of adjustment of one of the second frequency and the third frequency relative to the start of adjustment of the other of the second frequency and the third frequency. 【0127】 [E14] The plasma processing apparatus according to E11, wherein the control circuit is configured to increase the signal level of one of the second bias signal and the source RF signal in proportion to the elapsed time from the start of at least the first iteration period among the plurality of iteration periods. 【0128】 [E15] The plasma processing apparatus according to E11, wherein the control circuit is configured to increase, in at least the first of the plurality of iteration periods, one of the adjustment amounts of the second frequency adjustment amount for improving the impedance matching of the load of the second power supply and the adjustment amount of the third frequency adjustment amount for improving the impedance matching of the load of the third power supply, in proportion to the elapsed time from the start of the at least first iteration period. 【0129】 [E16] The plasma apparatus according to E15, wherein the control circuit is configured to increase the one adjustment amount to a maximum value and maintain the one adjustment amount at the maximum value during at least the first iteration period. 【0130】 [E17] The plasma apparatus according to E16, wherein the control circuit is configured to maintain the one adjustment amount at its maximum value in at least the first iteration period, and then decrease the one adjustment amount. 【0131】 [E18] The plasma apparatus according to E16, wherein the control circuit is configured to reduce the one adjustment amount to a steady state in at least the first iteration period and then maintain the one adjustment amount at a steady state. 【0132】[E19] A power supply system comprising: a first power supply electrically coupled to a substrate support in the chamber of a plasma processing apparatus and configured to generate a first bias signal for drawing ions from the plasma in the chamber to a substrate on the substrate support, wherein the waveform of the first bias signal has a waveform period having a time length inverse of the first frequency; a second power supply electrically coupled to the substrate support and configured to generate a second bias signal which is an RF signal; and a control circuit, wherein the control circuit controls the first power supply and the second power supply to supply the first bias signal and the second bias signal to the substrate support in each of a plurality of iteration periods, and adjusts the second frequency of the second bias signal in each of a plurality of sub-periods in each of the plurality of iteration periods, which have a time length shorter than the time length of the waveform period, in order to improve the impedance matching of the load of the second power supply in the same sub-period in an earlier iteration period among the plurality of iteration periods. 【0133】 [E20] A frequency control method comprising: a step of supplying a first bias signal from a first power supply to a substrate support in a chamber of a plasma processing apparatus in each of a plurality of iteration periods, the first bias signal being supplied to the substrate support to draw ions from the plasma in the chamber to a substrate on the substrate support, and the waveform of the first bias signal having a waveform period having a time length of the reciprocal of the first frequency; a step of supplying a second bias signal from a second power supply to the substrate support in each of the plurality of iteration periods; and a step of adjusting a second frequency of the second bias signal in each of a plurality of sub-periods in each of the plurality of iteration periods, each of which sub-periods has a time length shorter than the time length of the waveform period, the second frequency in each of the plurality of sub-periods in each of the plurality of iteration periods being adjusted to improve the impedance matching of the load of the second power supply in the same sub-period in an earlier iteration period among the plurality of iteration periods. 【0134】 From the above description, it will be understood that the various embodiments of this disclosure are described herein for illustrative purposes and can be modified in various ways without departing from the scope and spirit of this disclosure. Accordingly, the various embodiments disclosed herein are not intended to limit the scope and spirit, and the true scope and spirit are shown by the appended claims. 【0135】 1...Plasma processing apparatus, 2...Control unit, 10...Chamber, 11...Substrate support unit, 14...Upper electrode, 16...Antenna, 18...Upper conductor, 50...Power supply system, 50c...Control circuit, 51...Power supply, 52...Power supply, 53...Power supply, BS1...Bias signal, BS2...Bias signal, HF...Source RF signal.

Claims

Chamber and, A substrate support portion arranged within the chamber, A first power supply is electrically coupled to the substrate support and configured to generate a first bias signal for drawing ions from the plasma in the chamber to the substrate on the substrate support, wherein the waveform of the first bias signal has a waveform period having a time length that is the reciprocal of the first frequency. A second power supply is electrically coupled to the substrate support and configured to generate a second bias signal, which is an RF signal. Control circuit and Equipped with, The aforementioned control circuit is The first power supply and the second power supply are controlled to supply the first bias signal and the second bias signal to the substrate support in each of the multiple repetition periods. The second frequency of the second bias signal in each of the multiple sub-periods in each of the multiple repetition periods, each of which has a time length shorter than the time length of the waveform period, is adjusted to improve the impedance matching of the load of the second power supply in the same sub-period within the earlier repetition period among the multiple repetition periods. A plasma processing apparatus configured in such a way. 　 The plasma processing apparatus according to claim 1, wherein the control circuit is configured to adjust the second frequency in each of the plurality of sub-periods within each of the plurality of iteration periods, in accordance with the second frequency in the same sub-period within the preceding iteration period. 　 Each of the plurality of repeating periods is the waveform period, Each of the aforementioned sub-periods is a plurality of periods that divide the waveform period. The plasma processing apparatus according to claim 1. 　 The first power supply is configured to generate a bias RF signal as the first bias signal. The plasma processing apparatus is A matching unit connected between the first power supply and the substrate support, A sensor configured to measure the voltage or current of the first bias signal between the matching unit and the substrate support, Furthermore, The control circuit is configured to identify the start time of the waveform period from the phase of the voltage or current measured by the sensor, and to determine the plurality of sub-periods within the waveform period in which the start time was identified. The plasma processing apparatus according to claim 3. 　 The plasma processing apparatus according to claim 1, wherein each of the plurality of repetition periods is the period of the pulse of the first bias signal supplied periodically from the first power supply to the substrate support. 　 The plasma processing apparatus according to claim 1, wherein each of the plurality of repeating periods is the period of a periodically repeated process. 　 An electromagnet arranged around the chamber, A control unit configured to periodically change the current supplied to the electromagnet according to the period of the process, The plasma processing apparatus according to claim 6, further comprising the following: 　 A gas supply unit configured to supply gas into the chamber, An exhaust system configured to adjust the pressure inside the chamber, A control unit configured to periodically change the pressure inside the chamber, which is adjusted by the gas supplied into the chamber from the gas supply unit and / or the exhaust system, at the cycle of the process, The plasma processing apparatus according to claim 6, further comprising the following: 　 A drive mechanism configured to define the plasma processing space within the chamber from above the substrate support portion, or to drive the substrate support portion to change the vertical gap length between the top portion and the substrate support portion, A control unit configured to control the drive mechanism to periodically change the gap length at the time of the process, The plasma processing apparatus according to claim 6, further comprising the following: 　 Auxiliary electrodes arranged around the substrate support portion, A drive mechanism configured to move the auxiliary electrode up and down, A control unit configured to control the drive mechanism to periodically change the position of the auxiliary electrode along the vertical direction according to the period of the process, The plasma processing apparatus according to claim 6, further comprising the following: 　 The plasma processing space within the chamber and the upper conductor which is an upper electrode or antenna positioned above the substrate support portion, A third power supply is electrically coupled to the upper conductor and configured to generate a source RF signal to generate plasma from the gas in the chamber, Furthermore, The control circuit is configured to adjust the third frequency of the source RF signal in each of the multiple sub-periods in each of the multiple iteration cycles in such a way as to improve the impedance matching of the load of the third power supply in the same sub-period within the preceding iteration cycle. A plasma processing apparatus according to any one of claims 1 to 10. 　 The plasma processing apparatus according to claim 11, wherein the control circuit is configured to delay the start of supplying one of the second bias signal and the source RF signal relative to the start of supplying the other of the second bias signal and the source RF signal in at least the first of the plurality of iteration periods. 　 The plasma processing apparatus according to claim 11, wherein the control circuit is configured to delay the start of adjustment of one of the second frequency and the third frequency relative to the start of adjustment of the other of the second frequency and the third frequency. 　 The plasma processing apparatus according to claim 11, wherein the control circuit is configured to increase the signal level of one of the second bias signal and the source RF signal in proportion to the elapsed time from the start of at least the first iteration period among the plurality of iteration periods. 　 The plasma processing apparatus according to claim 11, wherein the control circuit is configured to increase, in at least the first of the plurality of iteration periods, one of the adjustment amounts of the second frequency adjustment amount for improving the impedance matching of the load of the second power supply and the adjustment amount of the third frequency adjustment amount for improving the impedance matching of the load of the third power supply, in proportion to the elapsed time from the start of the at least first iteration period. 　 The plasma processing apparatus according to claim 15, wherein the control circuit is configured to increase the one adjustment amount to a maximum value and maintain the one adjustment amount at the maximum value during at least the first iteration period. 　 The plasma processing apparatus according to claim 16, wherein the control circuit is configured to maintain the one adjustment amount at its maximum value during at least the first iteration period, and then decrease the one adjustment amount. 　 The plasma processing apparatus according to claim 16, wherein the control circuit is configured to maintain the one adjustment amount at a steady state after decreasing it to a steady state in at least the first iteration period. 　 A first power supply is electrically coupled to a substrate support within the chamber of a plasma processing apparatus and configured to generate a first bias signal for drawing ions from the plasma in the chamber to the substrate on the substrate support, wherein the waveform of the first bias signal has a waveform period having a time length that is the reciprocal of the first frequency. A second power supply is electrically coupled to the substrate support and configured to generate a second bias signal, which is an RF signal. Control circuit and Equipped with, The aforementioned control circuit is The first power supply and the second power supply are controlled to supply the first bias signal and the second bias signal to the substrate support in each of the multiple repetition periods. The second frequency of the second bias signal in each of the multiple sub-periods in each of the multiple repetition periods, each of which has a time length shorter than the time length of the waveform period, is adjusted to improve the impedance matching of the load of the second power supply in the same sub-period within the earlier repetition period among the multiple repetition periods. A power supply system configured in such a way. 　 The process involves supplying a first bias signal from a first power supply to a substrate support in the chamber of a plasma processing apparatus in each of a plurality of repetition periods, wherein the first bias signal is supplied to the substrate support to attract ions from the plasma in the chamber to the substrate on the substrate support, and the waveform of the first bias signal has a waveform period having a time length that is the reciprocal of the first frequency. In each of the plurality of repeating periods, a step of supplying a second bias signal from a second power supply to the substrate support portion, A step of adjusting the second frequency of the second bias signal in each of the multiple sub-periods in each of the multiple repetition periods, each of which has a time length shorter than the time length of the waveform period, wherein the second frequency in each of the multiple sub-periods in each of the multiple repetition periods is adjusted to improve the impedance matching of the load of the second power supply in the same sub-period within the earlier repetition period, A frequency control method including the following.

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