Piezoelectric driver circuit

Abstract

A driver circuit for a piezoelectric element is configured for coupling a negative terminal of a piezoelectric element to a positive terminal of a voltage source for applying a negative stabilization voltage across the piezoelectric element after the driver voltage is applied for reconditioning and counteracting a piezoelectric creep effect on the piezoelectric element. A power converter comprises a first high-side switch, a second high-side switch, a first low-side switch, an inductive device, and is configured to generate a driver voltage from the input voltage and apply the driver voltage across the piezoelectric element. The second driver switch and the third driver switch are configured for blocking parasitic body diodes thereof whenever the second driver switch and the third driver switch are turned off during reconditioning.

Description

Docket No.: 0154-14WOPT PatentPIEZOELECTRIC DRIVER CIRCUITTECHNICAL FIELD

[0001] The present disclosure relates to a piezoelectric driver circuit, and in particular to a piezoelectric driver circuit for both sensing a force application and driving a haptic response.BACKGROUND

[0002] When using a piezoelectric actuator for both generating haptic responses and sensing force applications, a physical property of the piezoelectric element limits, even prevents, sensing within a certain time period after receiving an electrical haptic-activation signal waveform. The physical property is called the creep effect, which is a delayed response of the piezoelectric material displacement. When the voltage applied to the piezoelectric material goes back to 0 V, the piezoelectric material does not return to its original strain level, thereby continuing displacing charges that could be misinterpreted as a signal by the strain sensors front-end circuitry.

[0003] If one cannot wait for the effect to fade in time, the usual practice is to quickly apply a stabilization voltage (often negative) across the piezoelectric element, for reconditioning, and therefore to counteract this creep effect. This results with a final state of zero strain level and 0 V across the piezoelectric element, allowing a subsequent reliable sensing phase. When negative voltage is required, the common way to do this is with a H-Bridge circuit that can simply invert the piezoelectric element connectivity before applying voltage driven by a half-bridge piezoelectric driver.

[0004] Considering the high-voltage required in piezoelectric driving solutions, the chosen H- Bridge circuit should include not only high voltage capability, but level-shifters, bootstrapping, and drivers to be controlled, which are both expensive and area (volume) consuming.

[0005] An object of the present disclosure is to provide a piezoelectric driver circuit without the need for a H-bridge circuit for counteracting the creep effect.Docket No.: 0154-14WOPT PatentSUMMARY

[0006] Accordingly, a first apparatus includes a driver circuit for a piezoelectric element configured for coupling a negative terminal of the piezoelectric element to a positive terminal of a voltage source, the voltage source providing a DC input voltage, the driver circuit comprising:

[0007] a power converter comprising a first high-side switch, a second high-side switch, a first low-side switch, an inductive device, and a switching node between the first high-side switch, the second high-side switch and the inductive device; the power converter configured to generate a driver voltage from the input voltage and apply the driver voltage across the piezoelectric element, the driver voltage comprising an analog voltage waveform having a peak amplitude of at least twice the input voltage; and

[0008] a controller configured to control the first high-side switch, the first low-side switch, and the second high-side switch;

[0009] wherein the negative terminal of the piezoelectric element is coupled to the positive terminal of the voltage source for applying a negative stabilization voltage across the piezoelectric element after the driver voltage is applied for reconditioning and counteracting a piezoelectric creep effect on the piezoelectric element; and

[0010] wherein the second driver switch and the third driver switch are configured for blocking parasitic body diodes thereof whenever the second driver switch and the third driver switch are turned off during reconditioning.

[0011] Accordingly, a second apparatus comprises a circuit comprising:

[0012] a voltage source which provides a DC input voltage at an input;

[0013] a piezoelectric element including a negative terminal coupled to a positive terminal of the voltage source configured for generating a sensing voltage in response to a user’s touch, and configured for generating a haptic response in response to a driver voltage;

[0014] a driver circuit comprising a power converter comprising a first high-side switch, a second high-side switch, a first low-side switch, an inductive device, and a switching node between the first high-side switch, the second high-side switch and the inductive device; the power converterDocket No.: 0154-14WOPT Patent configured to generate the driver voltage from the input voltage and apply the driver voltage across the piezoelectric element, the driver voltage comprising an analog voltage waveform comprising a peak amplitude of at least twice the input voltage; and

[0015] a controller configured to control the first high-side switch, the first low-side switch, and the second high-side switch;

[0016] wherein the negative terminal of the piezoelectric element is coupled to the positive terminal of the voltage source for applying a negative stabilization voltage across the piezoelectric element after the driver voltage is applied for reconditioning and counteracting a piezoelectric creep effect on the piezoelectric element; and

[0017] wherein the second driver switch and the third driver switch are configured for blocking parasitic body diodes thereof whenever the second driver switch and the third driver switch are turned off during reconditioning.

[0018] In any of the above embodiments, the apparatus may a further comprising a current feedback sensor configured to detect inductor current in the inductive device;

[0019] wherein, in response to the current feedback sensor, the controller is configured to:

[0020] turn the first low-side switch on, whereby inductor current ramps up in the inductive device to a threshold current,

[0021] turn the first low-side switch off and turn the first high-side switch and the second high- side switch on when the inductor current reaches the threshold current, thereby charging the capacitive load at the output voltage, thereby depleting the inductor current; and

[0022] turn the first high-side switch and the second high-side switch off, and turn the first low- side switch on when the inductor current reaches a target current.

[0023] In any of the above embodiments, the target current may be substantially zero.

[0024] In any of the above embodiments, the power converter may be configured to generate the analog voltage waveform with the peak amplitude of at least 2x-20x greater than the input voltage.Docket No.: 0154-14WOPT Patent

[0025] In any of the above embodiments, the capacitive load comprises a piezoelectric element configured to generate a sensing voltage based on mechanical stress applied thereto; and wherein the controller is configured to sense the sensing voltage and send an output information signal, based on the sensing voltage, to an external peripheral device.

[0026] In any of the above embodiments, the apparatus may include a reference current configured to generate an offset voltage for limiting and dynamically adapting voltages applied to the first high-side driver switch and the second high-side switch.

[0027] In any of the above embodiments, the apparatus may include a bootstrap voltage generator configured for turning the first high-side driver switch and the second high-side driver switch.BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Some example embodiments will be described in greater detail with reference to the accompanying drawings, wherein:

[0029] FIG. l is a circuit diagram of a conventional piezoelectric driver circuit;

[0030] FIG. 2 is a circuit diagram of an example piezoelectric driver circuit in accordance with the present invention;

[0031] FIG. 3 is a circuit diagram of a driver stage of the piezoelectric driver circuit FIG. 2;

[0032] FIG. 4 is a circuit diagram of a driver stage of the piezoelectric driver circuit FIG. 2; and

[0033] FIG. 5 is a circuit diagram of a driver stage of the piezoelectric driver circuit of FIG. 2.DETAILED DESCRIPTION

[0034] While the present teachings are described in conjunction with various embodiments and examples, it is not intended that the present teachings be limited to such embodiments. On the contrary, the present teachings encompass various alternatives and equivalents, as will be appreciated by those of skill in the art.Docket No.: 0154-14WOPT Patent

[0035] FIG. 1 illustrates a two-transistor driver circuit as described in United States Patent No. 10,199,555, issued February 5, 2019 in the name of Simon Chaput, incorporated herein by reference. The two-transistor driver circuit includes a first driver switch Qi and a second driver stage switch Q2 and an inductor L enabling the sinking and sourcing of current in a capacitive load 15 through the second driver switch Q2. In all figures, the body diode of the first and second driver switches Qi and Q2 are represented by a diode symbol to show explicitly the parasitic path. For all transistors, if a conducting terminal to conducting terminal, e.g. Drain-Source (VDS), voltage becomes negative enough, e.g. above the turn-on voltage of the body diode of the second driver switch Q2 connected to the load 15, the current will start to flow from the first conducting terminal, e.g. source, to the second conducting terminal, e.g. drain, via the body diode. The conducting voltage at which the current will start to flow in the diode may be between 0.2 V and 0.7 V typically depending on the exact device and semiconductor technology used.

[0036] The use of an H-Bridge circuit is usually required to drive negative voltage from a halfbridge driver: however, the technique of driving the node HV with an absolute voltage lower than VIN cannot be applied, since it would forward bias the parasitic body diode of the second driver switch Q2 and the node HV will be pulled up by VIN (through the inductor L).

[0037] With reference to FIG. 2, a piezoelectric transducer system 1, includes a piezoelectric driver circuit 2 comprising an input stage 3, a driver stage 4, an amplifier bias / switch control 5, and the output stage 6. The piezoelectric driver circuit 2 includes a power converter, such as a bidirectional synchronous power converter, comprising a first driver switch Qi, (a low-side driver switch), a second driver stage switch Q2 (a first high-side driver switch) and an inductor L enabling the sinking and sourcing of current in a capacitive load 15 through the second driver switch Q2. A third driver switch Q2L (or a second high-side driver switch) is disposed after the inductor L providing two back-to-back high-side driver switches Q2 and Q2L, i.e. transistors, instead of one, with their source terminals connected at node SS. Accordingly, the parasitic body diodes of the second and third driver switches Q2 and Q2L are blocked by each other whenever the transistor channels, i.e. the second and third driver switches Q2 and Q2L, are turned off, regardless of the voltage polarity. Since the second and third driver switches Q2 and Q2L can only conduct current in one direction, having them back-to-back (in series) makes sure the current cannot flow in any direction when they are turned off (high impedance). Both transistor gates GQ2 and GQ2L of theDocket No.: 0154-14WOPT Patent second and third driver switches Q2 and Q2L may be connected making sure the footprint of the driver (or the IC embedding the driver) keeps the same pinout, allowing the third driver switch Q2L to be optional in applications not requiring negative polarity across the load, e.g. no sensing mode. To ease the explanation, N-type MOS transistors are used; however, a skilled person in the art will recognize that a similar situation happens with other transistors, e.g. P-type devices. The first, second and third driver switches Qi, Q2 and Q2L may be of the same type, which may be the most practical choice for an integrated circuit (IC) implementation, although embodiments with mixed switches may be used. The first, second and third driver switches Qi, Q2 and Q2L may comprise, for example, Gallium Nitride (GaN), Silicon Carbide (SiC) or other suitable bipolar junction transistor (BJT) material among other possible suitable switches.

[0038] The piezoelectric transducer system 1 may be implemented in a single chip or using discrete parts due to the high power to process. The input stage 3 may be connected to the voltage source VIN, such as a battery, typically with an input voltage Vinof between 6 V and 26 V, preferably 9 V to 26V. The driver stage 4 may be comprised of the power converter circuit including a forward-boost / reverse-buck converter that generates a clean sine waveform. The driver stage 4 may include the inductor L connected to the voltage source VIN, and the driver stage switches, e.g. driver stage switches comprising or consisting of the first low side switch Qi connected between the inductor Li and ground, and the second and third (high-side) driver stage switches Q2 and Q2L connected between the inductor Li and the output stage 6, i.e. the load 15, such as a piezoelectric element. The control terminal, e.g. gate GQI, of the transistor in the first driver stage switch Qi may be connected to a first (low-side) gate driver 11 in the amplifier bias / switch control 5, and the control terminals, e.g. gates GQ2 and GQ2L, of the transistor in the second and third switches Q2 and Q2L may be connected to a second (high-side) gate driver 12 in the amplifier bias / switch control 5. Both the first gate driver 11 and the second (high-side) gate driver 12 may be connected to a controller 50 in the amplifier bias / switch control 5, which sends control signals to the first and second gate drivers 11 and 12 to control operation of the first, second and third driver stage switches Qi, Q2 and Q2L, respectively. The controller 50 may comprise suitable hardware and suitable software saved in non-transitory memory and executable on the suitable hardware.Docket No.: 0154-14WOPT Patent

[0039] While the aforementioned embodiment is described being used for sine waveforms, persons having ordinary skill in the art will appreciate the embodiments described herein may operate upon arbitrary and complex analogue waveforms, for example, square, triangular, AM modulated, FM modulated, and are not limited to operating upon sine waveforms.

[0040] The second driver stage switch Q2 may be N-type transistor including a first conducting terminal, e.g. source, connected to the first conducting terminal, e.g. source, of the third driver stage switch Q2L, at a node SS; a second conducting terminal, e.g. drain DQ2, connected to the load 15, and a third control terminal, e.g. gate GQ2, connected to the controller 50 of the amplifier bias / switch control 5. The third (second high-side) driver stage switch Q2L may be N-type transistor including a first conducting terminal, e.g. source, connected to the first conducting terminal, e.g. source, of the second (first high-side) driver stage switch Q2; a second conducting terminal, e.g. drain DQL2, connected to the first (first low-side) driver stage switch Qi and the inductor L via a switching node SW and referenced to the switching node voltage Vsw; and a third control terminal, e.g. gate GQL2, connected to the controller 50 of the amplifier bias / switch control 5 via the second (high-side) gate driver 12. While FIG. 2 illustrates an N-type transistor for the first, second and third driver stage switches Qi, Q2 and Q2L, in an alternative embodiment, a different type of switch, e.g. a P-type transistor, may be used for the upper side switches (Q2 and Q2L). However, the third driver stage switch Q2L should be of the same type as the second driver stage switch Q2.

[0041] The inductor L, may be about a 10 pH inductor, although other inductor values are possible. The inductor L value may be selected and configured in order to: (1) achieve a target distortion, e.g. lower inductance increases switching frequency and decreases distortion / THD+N, and / or (2) minimize the switching frequency, e.g. in general, a lower switching frequency corresponds to lower power consumption.

[0042] The output stage 6 may be referenced to the input voltage Vinor some other suitable voltage. The output stage 6 may include a filter, e.g. a filter capacitor and the load 15, for example one or more of the piezoelectric transducers P. Therefore, to obtain 0 V differential across the piezoelectric transducer element P, e.g. in a resting state, the driver voltage signal VoR from the driver stage 4, e.g. the half-bridge voltage VHV, and the reference voltage, which is equal to theDocket No.: 0154-14WOPT Patent input voltage Vin, may be equal. Increasing the driver voltage signal VDR across the load 15 above the input voltage Vinfrom the input voltage source VIN, e.g. in an active state, may be provided by the driver stage 4.

[0043] In the piezoelectric transducer system 1, the conversion ratio, e.g. voltage amplification, of the power converter, i.e. the driver stage 4, may be up to 20x for a driver voltage (haptic activation) signal VDR, e.g. up to 180 VAC or more, from an input voltage VIN, e.g. of about 9-26 VDC.

[0044] A current feedback sensor 25 may be provided to detect an inductor current II in the inductor L, which sends an inductor current signal Sic to the controller 50. Initially, in response to the inductor current II reaching a target current value, e.g. 0 A, measured by the current feedback sensor 25, the controller 50 turns the first (low-side) driver stage switch Qi on and the current in the inductor Li, which is connected to the reference node 20, e.g. VIN, ramps up linearly to a threshold current value. When the inductor current II reaches the threshold current value the controller 50 turns the first driver stage switch Qi off, the switching node voltage Vsw at the switching node SW increases the driver voltage signal VDR to the desired output voltage Vout for the haptic activation signal and current flows from the inductor Li through the second and third driver switches Q2 and Q2L to increment the output voltage Vout. Here, the second and third driver switches Q2 and Q2L turn on connecting the switching node SW to the load 15 and charges the load 15, e.g. the piezoelectric transducer element P. When the inductor current II reaches about 0 A, the second and third driver switches Q2 and Q2L are turned off by the controller 50, and the switching node voltage Vsw at the switching node SW goes back to the input voltage Vin. The controller 50 alternates the state of the first driver switch Qi and the second (and third) driver switches Q2 (and Q2L) to control the amount of energy sent or extracted from the load 15. In the driver stage 4, since the boost converter voltage gain is most of the time larger than 2, the switching node voltage Vsw may decrease to a little bit less than 0 V and turns on the body diode of the first driver switch Qi. Thereupon, the first driver switch Qi may be turned on again under zero voltage switching condition (ZVS), thus reducing the switching losses associated to the parasitic capacitance at the switching node SW.

[0045] Connecting the negative terminal of the load 15 to the input voltage source VIN enables the load polarity to alternate from positive to negative by simply applying a lower voltage on theDocket No.: 0154-14WOPT Patent positive terminal of the load 15. Doing so, a negative voltage as low as -VIN with Vout or VDR=0 at node HV can be reached.

[0046] As depicted in the simplified schematics, the controller 50 via the second (high-side) gate driver 12 turns “on” the second driver stage (first high-side) switch Q2 and the third (second high- side) driver stage switch Q2L with a positive “boot strap” voltage VBST on their gates GQ2 and GQ2L. A positive bootstrap voltage VBST relative to the switching node SW may be generated by a bootstrap capacitor CB and a bootstrap diode DB from a voltage source 41. The second and third driver stage switches Q2 and Q2L are turned “off’ by the second (high-side) gate driver 12 with a 0 V relative to the switching node SW (VGS=0).

[0047] The bootstrapping voltage VBST is generated whenever the switching node SW=0 V, i.e. when the first driver stage switch Qi is «on», the voltage source 41, which can be a desired voltage either the same as the input voltage VIN or any other intermediate voltage source, such as 10 V, charges the bootstrap capacitor CB through the bootstrap diode DB up to the desired voltage creating a floating supply domain bootstrapping voltage VBST referenced to the switching node SW.

[0048] In upper conversion (boost conversion) driving (haptic activation) operation of the conventional half-bridge driver stage 4 (FIG. 2) goes as the following:

[0049] Step 1 : The first driver switch Qi is turned “on” by the controller 50 via the first (low side) driver 11, and charges a positive current II in the inductor L.

[0050] Step 2 : The first driver switch Qi is turned “off’ by the controller 50 via the first (low side) driver 11 when the inductor current II reaches a threshold current value measured by the current feedback sensor 25.

[0051] Step 3 : The positive inductor current II in the inductor L increases the voltage on node SW until it reaches Vsw=VHv+VdiodeQ2+VGSQ2L@iL, where VGSQ2L@IL is the gate-source voltage of the “diode-connected” to the third driver stage switch Q2L for which its drain current equals the inductor current II then flowing through the forward biased body diode of the second22 driver switch Q2 toward node HV and the load 15, e.g. piezoelectric transducer P, for generating a haptic response signal VDR thereon. “Diode-connected” is a term used to described a transistor for whichDocket No.: 0154-14WOPT Patent its gate is connected to its drain, which makes the transistor behave as a diode. In other words, it’s like having two forward biased diodes in series with one of them being the “diode-connected” third driver switch Q2L.

[0052] Step 4 : The second and third driver stage switches Q2 and Q2L are turned “on” by the controller 50 via the second (high-side) gate driver 12 to reduce conduction losses across their parasitic body diodes enabling the output voltage Vout, i.e. the driver voltage VDR, to reach a maximum to provide the haptic activation signal, i.e. voltage, across the the piezoelectric transducer element P in the load 15. The second and third driver switches Q2 and Q2L could stay “off’ or replaced by a diode if the system in only used as an asynchronous converter.

[0053] Step 5 : The inductor current II in the inductor L decreases down to a target value (valley current), e.g. 0 A.

[0054] Step 6 : The second and third driver switches Q2 and Q2L are turned “off’ by the controller 50 via the second (high-side) gate driver 12.

[0055] Step 7: Depending on operating mode, the first driver stage switch Qi is turned “on” right away or eventually turned “on” by the controller 50 via the first (low-side) gate driver 11,

[0056] In the driving mode, i.e. with a positive voltage across the load 15, in step number 1 described above, the switching node voltage Vsw=0V and the half bridge node voltage HV can be as high as VHVMAX. The control terminals, e.g. gates, of the second and third driver stage switches Q2 and Q2L are also at 0V (connected to the switching node SW). Hence, the second driver stage switch Q2 should be chosen to support V(HV)MAX on its drain (VDS and VDG). On the other hand, the third driver stage switch Q2L is protected from high voltage on its drain thanks to its body diode. In that case, the third driver stage switch Q2L should only tolerate a gate-source voltage VGS of VBST (VGS when “on”).

[0057] Hence the constraints in driving are:

[0058] VDSQ2MAX=DGQ2MAX=V HVMAX

[0059] VGSQ2MAX=BSTDocket No.: 0154-14WOPT Patent

[0060] VDSQ2LMAX — DGQ2LMAX — VGSQ LMAX — VBST

[0061] In a sensing mode wherein the capacitive load comprises a piezoelectric transducer element P configured to generate a sensing voltage based on mechanical stress applied thereto, the controller 50 is configured to sense the sensing voltage and send an output information signal, based on the sensing voltage, to an external peripheral device, e.g. phone controller or computer CPU.

[0062] Before entering in sensing mode, while reconditioning the piezoelectric transducer element P, there is a negative voltage across the load 15 generated by the input voltage Vinconnected to the negative terminal of the piezoelectric transducer element P. However, when driving the half bridge node HV below the input voltage Vin, the constraints on the second and third driver stage switches Q2 and Q2L are not the same. The high-side, i.e. the second and third driver stage switches Q2 and Q2L, should now have a high impedance, and knowing the DC impedance of the inductor L is 0 Ohm, the switching node voltage Vsw equals the input voltage Vin and the high side is represented as in FIG. 3, which illustrates a high impedance state on the high side with the half bridge node voltage VHV under the switching node voltage Vsw which equals the input voltage Vin.

[0063] Accordingly, the third driver stage switch Q2L will need to tolerate voltages on its drain (VDS and VDG) as high as the input voltage Vinif the gate voltage Vg= 0 V, where VssMAx=Vuv+VdiodeQ2. On the other hand, when the half bridge node voltage VHV is still close to the input voltage Vin (before driven down), the gate source voltage VGS of the third driver stage switch Q2L sees a gate voltage Vg-Vss ~ Vg-Vuv ~ Vg- VIN. It then imposes the third driver stage switch Q2L to also tolerate a gate source voltage VGS of in the input voltage Vin. Hence the constraints in high impedance with the gate voltage Vgto ground are:

[0064] VDSQ2LMAX=DGQ2LMAX=VGSQ2LMAX=IN

[0065] With the same kind of analysis, we can also find

[0066] VDSQ2MAX=VDGQ2MAX=V QZMAX=inDocket No.: 0154-14WOPT Patent

[0067] It is important to note here that the input voltage Vincan be quite large. For instance, depending on the load-dump protection circuit in automotive systems, the input voltage Vincan potentially reach voltages such as 60V in 24V systems. The piezoelectric driver circuit 2 is configured is such a way that the input voltage Vin maximum voltage is not the limiting part of the system.

[0068] With reference to FIGS. 3-5, in some embodiments, a reference current source 31 may be configured to generate first and / or second offset voltages Voirset and Voffset _s. In FIGS. 3 and 5, the first offset voltage Voffset is relative to the half bridge voltage VHV at node HV. In FIGS. 4 and 5, the second offset voltage Voffset s is relative to the switching node voltage Vsw at the switch node SW. With reference to FIG. 5, application of the first offset voltage Voffset can be controlled by the controller 50 and selected via a first offset switch 43 through a first offset diode 46. Similarly, application of the second offset voltage Voffset s can be controlled by the controller 50 and selected via a second offset switch 44 through a second offset diode 47.

[0069] The first and second offset voltages Voffset or Voffset s are configured for limiting and / or dynamically adjusting the gate voltage Vg applied to the second (high-side) gate driver 12 driven by an amplifier 32 for the second and third driver stage switches Q2 and Q2L. The amplifier 32 has an output that may be connected and / or disconnected by the controller 50 via an amplifier switch SA when the controller 50 is in the driving mode. Similarly, when the driver stage 4 is set for high impedance, i.e. the situation of Fig 3., Fig 4. or Fig 5, the second (high-side) gate driver 12 is disconnected from the second and third driver stage switches Q2 and Q2L (actually put in a high impedance (HiZ) output state) via a driver switch SD. The current source 31 is configured to generate offset voltages Voffset or Voffset s that generate a biasing voltage, e.g. on the positive (+) input of the amplifier 32, to drive the gate voltage Vg through the amplifier 32. Accordingly, the adaptative control of the gate voltage Vg, enables the use of less expensive high-side driver stage switches, i.e. the second and third driver stage switches Q2 and Q2L.

[0070] Indeed, in this example, the gate voltage Vgis controlled in a way that it follows V(HV)- Voffset as in FIG. 3. Hence, the gate-source voltage VGS of the third driver stage switch Q2L only sees V(HV)- Voffset- V(HV) = -Voffset. With Voffset between 0 V and VBST, we make sure the VGSDocket No.: 0154-14WOPT Patent limitations on the second and third driver stage switches Q2 and Q2L are given in driving mode only, as described above.

[0071] Hence the overall constraints with this invention are:

[0072] VDSQ2MAX=DGQ2MAX=V(.HV~)MAX

[0073] VGSQ2MAX=BST

[0074] VDSQ2LMAX=DGQ2LMAX=IN

[0075] VGSQ2LMAX=BST

[0076] Thus, giving a larger number of options and potentially lower cost when it comes to choosing the second driver stage switch Q2 and the third driver stage switch Q2L.

[0077] When the piezoelectric transducer element P is in the sensing mode, the impedance of the half-stage driver stage 4 should be maximized in a broad temperature range to prevent adding error (leakage) in the sensing frontend. Indeed, the sensing frontend makes sure the half-bridge voltage VHV stays within a few hundred millivolts from the input voltage Vinto make sure the body diodes have only minimal leakage currents below a critical level to prevent inaccuracy.

[0078] Beyond that however, in order to ensure that the channel of the third driver stage switch Q2L, i.e. the second high-side switch, with its body diode in reverse, according to the polarity across the load 15 between the half-bridge node HV and the input voltage VIN, is strongly turned “off’, i.e. enhanced depletion of the channel, with a negative gate-to-source voltage VGS= V ) — V(SS) ~V(VJN). To do so, the gate voltage Vg is biased with an offset voltage Voffset relative to the input voltage Vin (the fix reference node, since HV can slightly move) as in FIG. 4.

[0079] The foregoing description of one or more example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the disclosure be limited not by this detailed description.

Claims

Docket No.: 0154-14WOPT PatentWE CLAIM:

1. A driver circuit for a piezoelectric element configured for coupling a negative terminal of the piezoelectric element to a positive terminal of a voltage source, the voltage source providing a DC input voltage, the driver circuit comprising: a power converter comprising: a first high-side driver switch, a second high-side driver switch, a first low-side driver switch, an inductive device, and a switching node between the first low-side driver switch, the first high-side driver switch and the inductive device, wherein the power converter is configured to generate a driver voltage from the input voltage and apply the driver voltage across the piezoelectric element, the driver voltage comprising an analog voltage waveform having a peak amplitude of at least twice the input voltage; and a controller configured to control the first high-side driver switch, the first low-side driver switch, and the second high-side driver switch; wherein the negative terminal of the piezoelectric element is coupled to the positive terminal of the voltage source for applying a negative stabilization voltage across the piezoelectric element after the driver voltage is applied for reconditioning and counteracting a piezoelectric creep effect on the piezoelectric element; and wherein the first high-side driver switch and the second high-side driver switch are configured for blocking parasitic body diodes thereof whenever the first high-side driver switch and the second high-side driver switch are turned off during reconditioning.Docket No.: 0154-14WOPT Patent2. The driver circuit according to claim 1, further comprising a current feedback sensor configured to detect an inductor current in the inductive device; wherein, in response to the current feedback sensor, the controller is configured to: turn the first low-side driver switch on, whereby inductor current ramps up in the inductive device to a threshold current, turn the first low-side driver switch off and turn the first high-side driver switch and the second high-side driver switch on when the inductor current reaches the threshold current, thereby charging the piezoelectric element at the driver voltage, thereby depleting the inductor current; and turn the first high-side driver switch and the second high-side driver switch off, and turn the first low-side driver switch on when the inductor current reaches a target current.

3. The driver circuit according to claim 2, wherein the target current is substantially zero.

4. The driver circuit according to claim 1, wherein the power converter is configured to generate the analog voltage waveform with the peak amplitude of at least 2x-20x greater than the input voltage.

5. The driver circuit according to claim 1, wherein the piezoelectric element is configured to generate a sensing voltage based on mechanical stress applied thereto; and wherein the controller is configured to sense the sensing voltage and send an output information signal, based on the sensing voltage, to an external peripheral device.

6. The driver circuit according to claim 1, further comprising a reference current configured to generate an offset voltage for limiting and dynamically adapting voltages applied to the first high-side driver switch and the second high-side driver switch.

7. The driver circuit according to claim 1, further comprising a bootstrap voltage generator configured for activating the first high-side driver switch and the second high-side driver switch.Docket No.: 0154-14WOPT Patent8. A circuit comprising: a voltage source which provides a DC input voltage at an input; a piezoelectric element including a negative terminal coupled to a positive terminal of the voltage source configured for generating a sensing voltage in response to a user’ s touch, and configured for generating a haptic response in response to a driver voltage; a driver circuit comprising a power converter comprising a first high-side driver switch, a second high-side driver switch, a first low-side driver switch, an inductive device, and a switching node between the first low-side driver switch, the first high-side driver switch and the inductive device; the power converter configured to generate the driver voltage from the input voltage and apply the driver voltage across the piezoelectric element, the driver voltage comprising an analog voltage waveform comprising a peak amplitude of at least twice the input voltage; and a controller configured to control the first high-side driver switch, the first low-side driver switch, and the second high-side driver switch; wherein the negative terminal of the piezoelectric element is coupled to the positive terminal of the voltage source for applying a negative stabilization voltage across the piezoelectric element after the driver voltage is applied for reconditioning and counteracting a piezoelectric creep effect on the piezoelectric element; and wherein the first high-side driver switch and the second high-side driver switch are configured for blocking parasitic body diodes thereof whenever the first high-side driver switch and the second high-side driver switch are turned off during reconditioning.

9. The circuit according to claim 8, further comprising a current feedback sensor configured to detect an inductor current in the inductive device; wherein, in response to the current feedback sensor, the controller is configured to: turn the first low-side driver switch on, whereby inductor current ramps up in the inductive device to a threshold current,Docket No.: 0154-14WOPT Patent turn the first low-side driver switch off and turn the first high-side driver switch and the second high-side driver switch on when the inductor current reaches the threshold current, thereby charging the piezoelectric element at the driver voltage, thereby depleting the inductor current; and turn the first high-side driver switch and the second high-side driver switch off, and turn the first low-side driver switch on when the inductor current reaches a target current.

10. The circuit according to claim 9, wherein the target current is substantially zero.

11. The circuit according to claim 8, wherein the power converter is configured to generate the analog voltage waveform with the peak amplitude of at least 2x-20x greater than the input voltage.

12. The circuit according to claim 8, wherein the controller is configured to sense the sensing voltage and send an output information signal, based on the sensing voltage, to an external peripheral device.

13. The circuit according to claim 8, further comprising a reference current configured to generate an offset voltage for limiting and dynamically adapting voltages applied to the first high- side driver switch and the second high-side driver switch.

14. The circuit according to claim 8, further comprising a bootstrap voltage generator configured for activating the first high-side driver switch and the second high-side driver switch.

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