Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises a plurality of pixel driving circuits, each pixel driving circuit comprising a driving transistor (T3), a fifth transistor (T5) and an eighth transistor (T8), wherein a first electrode of the fifth transistor (T5) is connected to a first power line, a second electrode of the fifth transistor (T5) is connected to a first electrode of the driving transistor (T3), a first electrode of the eighth transistor (T8) is connected to a third initial signal line (Vinit3), and a second electrode of the eighth transistor (T8) is connected to the first electrode of the driving transistor (T3). The display panel further comprises a base substrate and a first active layer. The first active layer is located on a side of the base substrate, and comprises a third active portion (73), a fifth active portion (75), an eighth active portion (78), a ninth active portion (79) and a tenth active portion (710), wherein the third active portion (73) is used for forming a channel region of the driving transistor (T3), the fifth active portion (75) is used for forming a channel region of the fifth transistor (T5), the eighth active portion (78) is used for forming a channel region of the eighth transistor (T8), the ninth active portion (79) is connected between the fifth active portion (75) and the eighth active portion (78), and the tenth active portion (710) is connected between the ninth active portion (79) and the third active portion (73). The display panel has a relatively high degree of integration.

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] The display panel includes a pixel driving circuit. In related technologies, the pixel driving circuit has a complex structure and low integration.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes a plurality of pixel driving circuits, each pixel driving circuit including a driving transistor, a fifth transistor, and an eighth transistor, wherein a first terminal of the fifth transistor is connected to a first power supply line, a second terminal of the fifth transistor is connected to a first terminal of the driving transistor, a first terminal of the eighth transistor is connected to a third initial signal line, and a second terminal of the eighth transistor is connected to a first terminal of the driving transistor, the display panel further comprising:

[0005] Substrate;

[0006] A first active layer is located on one side of the substrate. The first active layer includes a third active portion, a fifth active portion, an eighth active portion, a ninth active portion, and a tenth active portion. The third active portion is used to form the channel region of the driving transistor, the fifth active portion is used to form the channel region of the fifth transistor, and the eighth active portion is used to form the channel region of the eighth transistor.

[0007] The ninth active part is connected between the fifth active part and the eighth active part, and the tenth active part is connected between the ninth active part and the third active part.

[0008] In an exemplary embodiment of this disclosure, a plurality of pixel driving circuits form a plurality of pixel driving circuit groups, and the plurality of pixel driving circuit groups are arrayed along a first direction and a second direction. The pixel driving circuit group includes two pixel driving circuits that are adjacent in the first direction.

[0009] In the same pixel driving circuit group, the orthographic projections of the structures of the two pixel driving circuits located on the first active layer on the substrate are at least partially mirror-symmetrical with respect to the axis of symmetry extending along the second direction.

[0010] In one exemplary embodiment of this disclosure, the first active layer further includes:

[0011] The eleventh active part is connected to the end of the fifth active part away from the eighth active part, and the eleventh active part is connected between the two fifth active parts in the same pixel driving circuit group.

[0012] In one exemplary embodiment of this disclosure, the first active layer further includes:

[0013] The twelfth active part is connected to the end of the eighth active part away from the fifth active part, and the twelfth active part is connected between the two eighth active parts in the same pixel driving circuit group.

[0014] In one exemplary embodiment of this disclosure, the first active layer further includes:

[0015] The twelfth active part is connected to the end of the eighth active part away from the fifth active part. In the same pixel driving circuit group, the orthographic projection of the twelfth active part on the substrate is at least partially located on the side of the orthographic projection of the eighth active part connected to it on the substrate away from the orthographic projection of the other eighth active part on the substrate.

[0016] The eighth transistor includes two channel regions spaced apart, and a portion of the structure of the twelfth active part is used to form another channel region of the eighth transistor.

[0017] In one exemplary embodiment of this disclosure, the two fifth active portions in the same pixel driving circuit group are located between the two tenth active portions.

[0018] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit further includes a sixth transistor, wherein the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit;

[0019] The first active layer further includes a sixth active portion, the sixth active portion being used to form the channel region of the sixth transistor, and the display panel further includes:

[0020] An enable signal line, comprising a first enable signal line segment and a second enable signal line segment, wherein the first enable signal line segment and the second enable signal line segment in the same enable signal line have their orthogonal projections on the substrate extending along the first direction and are spaced apart along the first direction.

[0021] Wherein, the orthographic projection of the first enable signal line segment on the substrate covers the orthographic projection of the two fifth active parts in the same pixel driving circuit group on the substrate, and a portion of the structure of the first enable signal line segment is used to form the gate of the fifth transistor.

[0022] The orthographic projection of the second enable signal segment on the substrate covers the orthographic projection of the sixth active part on the substrate, and a portion of the structure of the second enable signal segment is used to form the gate of the sixth transistor.

[0023] In one exemplary embodiment of this disclosure, the display panel further includes:

[0024] The second source / drain layer includes multiple first power lines and multiple second data fan-out lines. The orthographic projections of the multiple first power lines on the substrate extend along a second direction and are spaced apart along a first direction. The orthographic projections of the multiple second data fan-out lines on the substrate extend along a second direction and are spaced apart along the first direction. The first direction and the second direction intersect. The first power lines are used to provide a high-level power signal to the pixel driving circuit.

[0025] Multiple data lines, whose orthogonal projection on the substrate extends along the second direction, are used to provide data signals to the pixel driving circuit.

[0026] Multiple first data fan-out lines, whose orthographic projection on the substrate extends along the first direction, wherein at least a portion of the multiple first data fan-out lines are used to connect the data line and the second data fan-out line;

[0027] Wherein, the first power line includes a first extension section, and the first extension sections of some of the first power lines form a widened first extension section, and the first extension sections of at least some of the first power lines form a narrowed first extension section, wherein the size of the orthographic projection of the widened first extension section on the substrate in the first direction is greater than the size of the orthographic projection of the narrowed first extension section on the substrate in the first direction.

[0028] In one exemplary embodiment of this disclosure, the first power line further includes a second extension, the size of the orthographic projection of the second extension onto the substrate in the first direction being larger than the size of the orthographic projection of the first extension onto the substrate in the first direction.

[0029] Multiple first power lines form multiple first power line groups. Each first power line group includes two first power lines that are adjacent in the first direction. The two first power lines in the same first power line group are connected in the same layer through the second extension section.

[0030] In the two first power lines connected on the same layer, the first extension segment of one first power line forms a widened first extension segment, and the first extension segment of the other first power line forms a narrowed first extension segment. The widened first extension segment is connected to the pixel driving circuit through a via.

[0031] In an exemplary embodiment of this disclosure, a plurality of pixel driving circuits form a plurality of pixel driving circuit groups, and the plurality of pixel driving circuit groups are arrayed along a first direction and a second direction. The pixel driving circuit group includes two pixel driving circuits that are adjacent in the first direction.

[0032] In two adjacent pixel driving circuits located in a first direction, the two first power lines form the first power line group.

[0033] In one exemplary embodiment of this disclosure, the display panel further includes:

[0034] A first source / drain layer is located between the substrate and the second source / drain layer. The first source / drain layer includes a plurality of first power connection lines. The orthographic projection of the plurality of first power connection lines on the substrate extends along the first direction and is spaced apart along the second direction. The first power connection lines are connected to the pixel driving circuit through vias, and the first power lines are connected to the first power connection lines intersecting with them through the widened first extension via.

[0035] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the second source / drain layer further includes:

[0036] The seventh bridging part is connected to the pixel driving circuit and the first electrode of the light-emitting unit through vias;

[0037] In two adjacent pixel driving circuits located in adjacent pixel driving circuit groups in a first direction, the orthographic projections of the two seventh bridging portions on the substrate are located between the orthographic projections of the two first extensions on the substrate.

[0038] In an exemplary embodiment of this disclosure, the orthographic projections of the narrowed first extension segment, the widened first extension segment, the widened first extension segment, and the narrowed first extension segment on the substrate are alternately and repeatedly distributed along the first direction.

[0039] In one exemplary embodiment of this disclosure, the data line is located in the second source / drain layer. In the data line and the first power line corresponding to the same pixel driving circuit, the orthographic projection of the data line on the substrate is located on the side of the orthographic projection of the second data fan-out line on the substrate that is away from the orthographic projection of the first power line on the substrate.

[0040] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a second transistor, wherein a first terminal of the second transistor is connected to the gate of the driving transistor, and a second terminal is connected to the second terminal of the driving transistor; the display panel further includes:

[0041] A third gate layer is located on one side of the substrate. The third gate layer includes a second bridging portion, which is connected to the gate of the driving transistor through a via.

[0042] The first source / drain layer is located on the side of the third gate layer opposite to the substrate. The first source / drain layer includes a third bridging portion, which is connected to the second bridging portion and the first electrode of the second transistor through vias.

[0043] In an exemplary embodiment of this disclosure, the first power connection line includes a third extension and a fourth extension, wherein the size of the orthographic projection of the third extension on the substrate in the second direction is greater than the size of the orthographic projection of the fourth extension on the substrate in the second direction.

[0044] The display panel further includes a light-emitting unit, and the pixel driving circuit further includes a seventh transistor, the first electrode of the seventh transistor being connected to a second initial signal line, and the second electrode being connected to the first electrode of the light-emitting unit;

[0045] The second initial signal line is located in the first source / drain layer. The orthographic projection of the second initial signal line on the substrate extends along the first direction. A groove is formed on the side of the second initial signal line on the substrate facing the orthographic projection of the first power connection line on the substrate. The groove and the orthographic projection of the third extension on the substrate are arranged opposite to each other in the second direction.

[0046] The pixel driving circuit further includes a second transistor, the first terminal of which is connected to the gate of the driving transistor, and the second terminal of which is connected to the second terminal of the driving transistor. The first source-drain layer includes a third bridging portion, which is connected to the gate of the driving transistor and the first terminal of the second transistor through vias.

[0047] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a second transistor, wherein a first terminal of the second transistor is connected to the gate of the driving transistor, and a second terminal is connected to the second terminal of the driving transistor; the display panel further includes:

[0048] A third gate layer is located on one side of the substrate. A portion of the structure of the third gate layer is used to form the top gate of the second transistor. The third gate layer also includes the third initial signal line.

[0049] The first active layer further includes a twelfth active portion, which is connected between the two eighth active portions in the same pixel driving circuit group;

[0050] The third initial signal line is connected to the first terminal of the eighth transistor through one or more vias.

[0051] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a second transistor, wherein a first terminal of the second transistor is connected to the gate of the driving transistor, and a second terminal is connected to the second terminal of the driving transistor; the display panel further includes:

[0052] A third gate layer is located on one side of the substrate. A portion of the structure of the third gate layer is used to form the top gate of the second transistor. The third gate layer also includes the third initial signal line.

[0053] The first source / drain layer is located on the side of the third gate layer opposite to the substrate. The first source / drain layer includes a fourth bridging portion, which is connected to the third initial signal line and the first electrode of the eighth transistor through vias.

[0054] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a second transistor, wherein a first terminal of the second transistor is connected to the gate of the driving transistor, and a second terminal is connected to the second terminal of the driving transistor; the display panel further includes:

[0055] A first source / drain layer is located on the side of the third gate layer opposite to the substrate. The first source / drain layer includes a fourth bridging portion, which is connected to the third initial signal line through one or more vias.

[0056] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor and a second transistor. The first terminal of the first transistor is connected to a first initial signal line, the second terminal of the first transistor is connected to the gate of the driving transistor, the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor.

[0057] The display panel also includes:

[0058] A first reset signal line extends along the first direction in the orthogonal projection on the substrate, and a portion of the structure of the first reset signal line is used to form the top gate of the first transistor;

[0059] A first gate line extends along the first direction in its orthogonal projection on the substrate, and a portion of the structure of the first gate line is used to form the top gate of the second transistor.

[0060] A data line, whose orthogonal projection on the substrate extends along the second direction, is used to provide data signals to the pixel driving circuit.

[0061] In the two data lines corresponding to the same pixel driving circuit group, a first recessed area is formed on the side of the orthogonal projection of one data line on the substrate facing the orthogonal projection of the other data line on the substrate, and the first recessed area is at least partially located between the orthogonal projection of the first reset signal line on the substrate and the orthogonal projection of the first gate line on the substrate.

[0062] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor, wherein a first terminal of the first transistor is connected to a first initial signal line and a second terminal is connected to the gate of the driving transistor;

[0063] The display panel also includes:

[0064] A second gate layer is located on one side of the substrate. The second gate layer includes the first initial signal line, and the orthographic projection of the first initial signal line on the substrate extends along a first direction.

[0065] A third gate layer is located on the side of the second gate layer away from the substrate. The third gate layer includes a first initial bridging segment. The orthographic projection of the first initial bridging segment on the substrate extends along a first direction. The first initial bridging segment is connected to the first initial signal line through a plurality of vias.

[0066] In one exemplary embodiment of this disclosure, the display panel further includes:

[0067] The first source / drain layer is located on the side of the third gate layer away from the substrate. The first source / drain layer includes multiple first data fan-out lines. The orthographic projection of the multiple first data fan-out lines on the substrate extends along a first direction and is spaced apart along a second direction. The second direction intersects the first direction.

[0068] The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes multiple data lines and multiple second data fan-out lines. The orthographic projections of the multiple data lines on the substrate extend along a second direction and are spaced apart along the first direction. The orthographic projections of the multiple second data fan-out lines on the substrate extend along a second direction and are spaced apart along the first direction.

[0069] The data line is used to provide data signals to the pixel driving circuit, and at least a portion of the first data fan-out lines are used to connect the data line and the second data fan-out line.

[0070] The first data fan-out line includes a first via connection portion. The first data fan-out line is connected to the second data fan-out line via through the first via connection portion. The orthographic projection of the via between the first initial bridging segment and the first initial signal line on the substrate and the orthographic projection of the first via connection portion on the substrate at least partially overlap.

[0071] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a fourth transistor, the first terminal of the fourth transistor being connected to a data line, and the second terminal being connected to the first terminal of the driving transistor. The display panel further includes:

[0072] A first gate layer is located on one side of the substrate. The first gate layer includes a second gate line. The orthographic projection of the second gate line on the substrate extends along the first direction. A portion of the structure of the second gate line is used to form the gate of the fourth transistor.

[0073] The first source / drain layer is located on the side of the first gate layer opposite to the substrate. The first source / drain layer includes a first power connection line. The orthographic projection of the first power connection line on the substrate extends along the first direction. The first power connection line is used to provide a high-level power signal to the pixel driving circuit.

[0074] The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes multiple second data fan-out lines. The orthographic projection of the multiple second data fan-out lines on the substrate extends along a second direction and is distributed along a first direction. The first direction and the second direction intersect.

[0075] A data line, whose orthogonal projection on the substrate extends along the second direction, is used to provide data signals to the pixel driving circuit, and at least a portion of the second data fan-out lines are connected to the data line.

[0076] The first power connection line includes a main body and a first protrusion. The orthographic projection of the main body on the substrate extends along the first direction, and the orthographic projection of the first protrusion on the substrate is located on the side where the orthographic projection of the main body on the substrate is in the second direction.

[0077] The overlapping area of ​​the orthographic projection of the second data fan-out line on the substrate and the orthographic projection of the second gate line on the substrate at least partially overlaps with the orthographic projection of the first protrusion on the substrate.

[0078] In one exemplary embodiment of this disclosure, the gate of the fifth transistor is connected to an enable signal connection line, the orthographic projection of the enable signal connection line on the substrate extends along a first direction, and the display panel further includes:

[0079] A first source / drain layer is located on the side of the first active layer opposite to the substrate. The first source / drain layer includes a first power connection line. The orthographic projection of the first power connection line on the substrate extends along the first direction. The first power connection line is used to provide a high-level power signal to the pixel driving circuit.

[0080] The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes multiple second data fan-out lines. The orthographic projection of the multiple second data fan-out lines on the substrate extends along a second direction and is distributed along a first direction. The first direction and the second direction intersect.

[0081] A data line, whose orthogonal projection on the substrate extends along the second direction, is used to provide data signals to the pixel driving circuit, and at least a portion of the second data fan-out lines are connected to the data line.

[0082] The first power connection line includes a main body and a second protrusion. The orthographic projection of the main body on the substrate extends along the first direction, and the orthographic projection of the second protrusion on the substrate is located on the side where the orthographic projection of the main body on the substrate is in the second direction.

[0083] The overlapping area of ​​the orthographic projection of the second data fan-out line on the substrate and the orthographic projection of the enable signal connection line on the substrate at least partially overlaps with the orthographic projection of the second protrusion on the substrate.

[0084] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, the pixel driving circuit further includes a seventh transistor, the first electrode of the seventh transistor is connected to a second initial signal line, the second electrode is connected to a first electrode of the light-emitting unit, the gate of the fifth transistor is connected to an enable signal connection line, and the orthographic projection of the enable signal connection line on the substrate extends along a first direction.

[0085] The display panel also includes:

[0086] A first source / drain layer is located on the side of the first active layer away from the substrate, and the first source / drain layer includes the second initial signal line;

[0087] The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes multiple second data fan-out lines. The orthographic projection of the multiple second data fan-out lines on the substrate extends along a second direction and is distributed along a first direction. The first direction and the second direction intersect.

[0088] A data line, whose orthogonal projection on the substrate extends along the second direction, is used to provide data signals to the pixel driving circuit, and at least a portion of the second data fan-out lines are connected to the data line.

[0089] The overlapping area of ​​the orthographic projection of the second data fan-out line on the substrate and the orthographic projection of the enable signal connection line on the substrate at least partially overlaps with the orthographic projection of the second initial signal line on the substrate.

[0090] In one exemplary embodiment of this disclosure, the display panel further includes:

[0091] A constant voltage signal line is used to provide a constant voltage signal to the pixel driving circuit, and the orthogonal projection of the constant voltage signal line on the substrate extends along a first direction.

[0092] A constant voltage connection line extends along a second direction on the substrate, the second direction intersecting the first direction, and the constant voltage connection line is connected to the constant voltage signal line intersecting it through a via.

[0093] The display panel also includes:

[0094] The second source / drain layer is located on the side of the first active layer away from the substrate. The second source / drain layer includes a data line, a first power line, and a constant voltage connection line. The orthographic projection of the data line and the first power line on the substrate extends along the second direction. The data line is used to provide data signals to the pixel driving circuit, and the first power line is used to provide high-level power signals to the pixel driving circuit.

[0095] In the same pixel driving circuit, the orthographic projection of the constant voltage connection line on the substrate is located on the side where the orthographic projection of the data line on the substrate is far from the orthographic projection of the first power line on the substrate.

[0096] In one exemplary embodiment of this disclosure, the display panel further includes:

[0097] The second source / drain layer is located on the side of the first active layer away from the substrate. The second source / drain layer includes a data line, a first power line, and a constant voltage connection line. The orthographic projection of the data line and the first power line on the substrate extends along the second direction. The data line is used to provide data signals to the pixel driving circuit, and the first power line is used to provide high-level power signals to the pixel driving circuit.

[0098] In the same pixel driving circuit, the orthographic projection of the constant voltage connection line on the substrate is located on the side where the orthographic projection of the first power line on the substrate is far from the orthographic projection of the data line on the substrate.

[0099] In one exemplary embodiment of this disclosure, the display panel further includes:

[0100] A data line, the data line being used to provide data signals to the pixel driving circuit, the data line extending along the second direction in its orthogonal projection on the substrate.

[0101] Multiple second data fan-out lines, the orthographic projection of the second data fan-out lines on the substrate extends along a second direction, and a portion of the multiple second data fan-out lines are used to connect the data lines;

[0102] Among them, some of the second data fan-out lines are reused as the constant voltage connection lines.

[0103] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit further includes: a first transistor, a second transistor, a fourth transistor, a sixth transistor, a seventh transistor, and a capacitor;

[0104] The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor;

[0105] The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor;

[0106] The first terminal of the fourth transistor is connected to the data line, and the second terminal of the fourth transistor is connected to the first terminal of the driving transistor;

[0107] The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit;

[0108] The first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit;

[0109] The first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the first power supply line.

[0110] Among them, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the first transistor and the second transistor are N-type transistors.

[0111] In one exemplary embodiment of this disclosure, the pixel driving circuit includes P-type transistors and N-type transistors, and the display panel further includes:

[0112] A first active layer is located on one side of the substrate, and a portion of the structure of the first active layer is used to form the channel region of the P-type transistor in the pixel driving circuit.

[0113] A first gate layer is located on the side of the first active layer away from the substrate, and a portion of the structure of the first gate layer is used to form the gate of the P-type transistor in the pixel driving circuit.

[0114] The second gate layer is located on the side of the first gate layer away from the substrate, and a portion of the structure of the second gate layer is used to form the bottom gate of at least a portion of the N-type transistors in the pixel driving circuit.

[0115] The second active layer is located on the side of the second gate layer away from the substrate, and a portion of the structure of the second active layer is used to form the channel region of the N-type transistor in the pixel driving circuit.

[0116] A third gate layer is located on the side of the second active layer away from the substrate, and a portion of the structure of the third gate layer is used to form the top gate of at least a portion of the N-type transistors in the pixel driving circuit.

[0117] The first source / drain layer is located on the side of the third gate layer opposite to the substrate, and a portion of the structure of the first source / drain layer is used to form a bridging portion connecting different transistors.

[0118] According to one aspect of this disclosure, a display device is provided, wherein the display panel described above is included.

[0119] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0120] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0121] Figure 1 is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure;

[0122] Figure 2 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0123] Figure 3 shows the structural layout of the first active layer in Figure 2;

[0124] Figure 4 is a structural layout of the first gate layer in Figure 2;

[0125] Figure 5 shows the structural layout of the second gate layer in Figure 2;

[0126] Figure 6 shows the structural layout of the second active layer in Figure 2;

[0127] Figure 7 shows the structural layout of the third gate layer in Figure 2;

[0128] Figure 8 shows the structural layout of the first source / drain layer in Figure 2;

[0129] Figure 9 shows the structural layout of the second source / drain layer in Figure 2;

[0130] Figure 10 is a structural layout of the first active layer and the first gate layer in Figure 2;

[0131] Figure 11 is a structural layout of the first active layer, the first gate layer, and the second gate layer in Figure 2;

[0132] Figure 12 is a structural layout of the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 2;

[0133] Figure 13 is a structural layout of the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 2;

[0134] Figure 14 is a structural layout of the first active layer, first gate layer, second gate layer, second active layer, third gate layer, and first source / drain layer in Figure 2;

[0135] Figure 15 is a partial cross-sectional view of the display panel shown in Figure 2, cut along the dashed line CC.

[0136] Figure 16 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0137] Figure 17 is a structural layout of the first active layer in the display panel shown in Figure 16;

[0138] Figure 18 is a structural layout of the first active layer and the first gate layer in the display panel shown in Figure 16;

[0139] Figure 19 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0140] Figure 20 is a structural layout of the third gate layer in the display panel shown in Figure 19;

[0141] Figure 21 is a structural layout of the first source / drain layer in the display panel shown in Figure 19;

[0142] Figure 22 is a structural layout of another exemplary embodiment of the display panel of this disclosure;

[0143] Figure 23 is a structural layout of the first active layer in the display panel shown in Figure 22;

[0144] Figure 24 is a structural layout of the third gate layer in the display panel shown in Figure 22;

[0145] Figure 25 is a structural layout of the second source / drain layer in the display panel shown in Figure 22;

[0146] Figure 26 is a structural layout of the first source / drain layer, the first gate layer, the second active layer, and the third gate layer in the display panel shown in Figure 22.

[0147] Figure 27 is a structural layout of another exemplary embodiment of the display panel of this disclosure;

[0148] Figure 28 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0149] Figure 29 is a structural layout of another exemplary embodiment of the display panel of this disclosure;

[0150] Figure 30 is a structural layout of another exemplary embodiment of the display panel of this disclosure;

[0151] Figure 31 is a structural layout of the first source / drain layer in the display panel shown in Figure 30;

[0152] Figure 32 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0153] Figure 33 is a structural layout of the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in the display panel shown in Figure 31.

[0154] Figure 34 is a structural layout of the first active layer, first gate layer, second gate layer, second active layer, third gate layer, and first source / drain layer in the display panel shown in Figure 31.

[0155] Figure 35 is a structural layout of another exemplary embodiment of the display panel of this disclosure;

[0156] Figure 36 is a structural layout of the first source / drain layer in the display panel shown in Figure 34;

[0157] Figure 37 is a structural layout of the first active layer, first gate layer, second gate layer, second active layer, third gate layer, and first source / drain layer in the display panel shown in Figure 34.

[0158] Figure 38 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0159] Figure 39 is a structural layout of the second source / drain layer in another exemplary embodiment of the display panel of this disclosure;

[0160] Figure 40 is a structural layout of the second source / drain layer in another exemplary embodiment of the display panel of this disclosure;

[0161] Figure 41 is a structural layout of the second source / drain layer in another exemplary embodiment of the display panel of this disclosure;

[0162] Figure 42 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0163] Figure 43 is a structural layout of the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in the display panel shown in Figure 42.

[0164] Figure 44 is a cross-sectional view of the display panel shown in Figure 42 along the dashed line DD;

[0165] Figure 45 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0166] Figure 46 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0167] Figure 47 is a cross-sectional view of the display panel shown in Figure 46 along the dashed line EE;

[0168] Figure 48 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0169] Figure 49 is a structural layout of the first active layer in the display panel shown in Figure 48;

[0170] Figure 50 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0171] Figure 51 is a cross-sectional view of the display panel shown in Figure 50 along the dashed line FF;

[0172] Figure 52 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0173] Figure 53 is a structural layout of the first active layer, first gate layer, second gate layer, second active layer, and third gate layer in the display panel shown in Figure 52.

[0174] Figure 54 is a cross-sectional view of the display panel shown in Figure 52 along the dashed line GG;

[0175] Figure 55 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0176] Figure 56 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0177] Figure 57 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0178] Figure 58 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0179] Figure 59 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0180] Figure 60 is a schematic diagram of the structure of the second active layer in the display panel shown in Figure 59;

[0181] Figure 61 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0182] Figure 62 is a schematic diagram of the structure of the second active layer in the display panel shown in Figure 61;

[0183] Figure 63 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0184] Figure 64 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0185] Figure 65 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0186] Figure 66 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0187] Figure 67 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0188] Figure 68 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0189] Figure 69 is a structural layout of the shielding layer in the display panel shown in Figure 68;

[0190] Figure 70 is a structural layout of another exemplary embodiment of the display panel of this disclosure;

[0191] Figure 71 is a structural layout of the first active layer to the first source / drain layer in the display panel shown in Figure 70. Detailed Implementation

[0192] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0193] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0194] Figure 1 shows a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. In this configuration, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the second gate drive signal terminal G2; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to node N; the first electrode of the second transistor T2 is connected to node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate drive signal terminal G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, and the gate is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to node N, the first electrode is connected to the first initial signal terminal Vinit1, and the gate is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to node N, and the second electrode is connected to the first power supply terminal VDD; the first electrode of the eighth transistor T8 is connected to the third initial signal line Vinit3, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the second reset signal terminal Re2. This pixel driving circuit can be connected to an OLED (OLED Light Emitting Unit) to drive the OLED to emit light. The OLED can be connected between the second terminal of the sixth transistor T6 and the second power supply terminal VSS. The first transistor T1 and the second transistor T2 can be N-type transistors; the driving transistors T3, T4, T5, T6, T7, and T8 can be P-type transistors.

[0195] The pixel driving circuit driving method can include a reset stage, a data writing stage, and a light-emitting stage. In the reset stage, the first reset signal terminal Re1 outputs a high-level signal, the second reset signal terminal Re2 outputs a low-level signal, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs a first initial signal to node N, the second initial signal terminal inputs a second initial signal to the first electrode of the light-emitting unit, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3. In the data writing stage, the first gate driving signal terminal G1 outputs a high-level signal, the second gate driving signal terminal G2 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and simultaneously the data signal terminal Da outputs a data signal to write a compensation voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. In the light-emitting stage: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in capacitor C. In this pixel driving circuit, the output current of the driving transistor is I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth). 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Where I is the driving transistor output current; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the driving transistor threshold voltage.

[0196] It should be noted that in other exemplary embodiments, the pixel driving circuit may have other driving methods. For example, the second initial signal terminal may also input a second initial signal to the first electrode of the light-emitting unit during the data writing stage.

[0197] This exemplary embodiment also provides a display panel, which may include a substrate, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source / drain layer, and a second source / drain layer stacked sequentially, wherein an insulating layer may be disposed between adjacent layers. As shown in Figures 2-14, Figure 2 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure, Figure 3 is a structural layout diagram of the first active layer in Figure 2, Figure 4 is a structural layout diagram of the first gate layer in Figure 2, Figure 5 is a structural layout diagram of the second gate layer in Figure 2, Figure 6 is a structural layout diagram of the second active layer in Figure 2, Figure 7 is a structural layout diagram of the third gate layer in Figure 2, Figure 8 is a structural layout diagram of the first source / drain layer in Figure 2, Figure 9 is a structural layout diagram of the second source / drain layer in Figure 2, and Figure 10 is a structural layout diagram of the first active layer in Figure 2, ... The structural layout of the first gate layer is shown in Figure 11, which is a structural layout of the first active layer, first gate layer, and second gate layer in Figure 2; Figure 12 is a structural layout of the first active layer, first gate layer, second gate layer, and second active layer in Figure 2; Figure 13 is a structural layout of the first active layer, first gate layer, second gate layer, second active layer, and third gate layer in Figure 2; and Figure 14 is a structural layout of the first active layer, first gate layer, second gate layer, second active layer, third gate layer, and first source / drain layer in Figure 2. This display panel may include multiple pixel driving circuits as shown in Figure 1. Multiple pixel driving circuits form multiple pixel driving circuit groups Pz, which are arrayed along a first direction X and a second direction Y. Each pixel driving circuit group Pz includes two adjacent pixel driving circuits Pix in the first direction X. In the same pixel driving circuit group Pz, the orthographic projections of the two pixel driving circuits Pix on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the second direction Y. For example, the orthographic projections of the structures of the two at least partially mirror-symmetrical pixel driving circuits Pix located in the first active layer on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the second direction Y.

[0198] In this exemplary embodiment, as shown in Figures 2, 3, and 10, the first active layer may include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, and an eighth active portion 78. The third active portion 73 can be used to form the channel region of a driving transistor T3; the fourth active portion 74 can be used to form the channel region of a fourth transistor T4; the fifth active portion 75 can be used to form the channel region of a fifth transistor T5; the sixth active portion 76 can be used to form the channel region of a sixth transistor T6; the seventh active portion 77 can be used to form the channel region of a seventh transistor T7; and the eighth active portion 78 is used to form the channel region of an eighth transistor T8. The first active layer also includes a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, and a sixteenth active portion 716. The ninth active portion 79 is connected between the fifth active portion 75 and the eighth active portion 78, and the tenth active portion 710 is connected between the ninth active portion 79 and the third active portion 73. This arrangement can improve the integration of the pixel driving circuit. The two fifth active portions 75 in the same pixel driving circuit group are located between the two tenth active portions 710. The eleventh active part 711 is connected to the end of the fifth active part 75 away from the eighth active part 78, and the eleventh active part 711 is connected between the two fifth active parts 75 in the same pixel driving circuit group; the twelfth active part 712 is connected to the end of the eighth active part 78 away from the fifth active part 75, and the twelfth active part 712 is connected between the two eighth active parts 78 in the same pixel driving circuit group; the thirteenth active part 713 is connected between the third active part 73 and the sixth active part 76; the fourteenth active part 714 is connected to the end of the seventh active part 77 away from the sixth active part 76; the fifteenth active part 715 is connected to the end of the fourth active part 74 away from the third active part 73; and the sixteenth active part 716 is connected between the sixth active part 76 and the seventh active part 77. The first active layer can be formed of polycrystalline silicon material, and correspondingly, the driving transistors T3, T4, T5, T6, T7, and T8 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0199] As shown in Figures 2, 4, and 10, the first gate layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthogonal projections of the second gate line G2, the enable signal line EM, and the second reset signal line Re2 onto the substrate can all extend along the first direction X. The orthogonal projection of the second gate line G2 onto the substrate covers the orthogonal projection of the fourth active portion 74 onto the substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor T4. The enable signal line EM includes a first enable signal segment EM1 and a second enable signal segment EM2. The orthographic projections of the first enable signal segment EM1 and the second enable signal segment EM2 on the substrate extend along the first direction X and are spaced apart. The orthographic projection of the first enable signal segment EM1 on the substrate covers the orthographic projections of the two fifth active parts 75 in the same pixel driving circuit group Pz on the substrate. A portion of the structure of the first enable signal segment EM1 is used to form the gate of the fifth transistor T5. The orthographic projection of the second enable signal segment EM2 on the substrate covers the orthographic projection of the sixth active part 76 on the substrate. A portion of the structure of the second enable signal segment EM2 is used to form the gate of the sixth transistor T6. The orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projections of the seventh active portion 77 and the eighth active portion 78 on the substrate. A portion of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7, and a portion of the structure of the second reset signal line Re2 can be used to form the gate of the eighth transistor T8. The orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. Furthermore, this display panel can utilize the first gate layer as a mask to perform a conductor treatment on the first active layer; that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductive structure.

[0200] As shown in Figures 2, 5, and 11, the second gate layer may include: a third reset signal line 2Re1, a third gate line 2G1, a second conductive portion 22, and a first connection portion 21. The third reset signal line 2Re1 can be used to provide the first reset signal terminal in Figure 1, and the third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 1. The third reset signal line 2Re1 may include multiple third reset signal line segments 2Re11, and the orthographic projections of the multiple third reset signal line segments 2Re11 on the same third reset signal line 2Re1 are spaced apart along the first direction X and extend along the first direction X. The third gate line 2G1 may include multiple third gate line segments 2G11, and the orthographic projections of the multiple third gate line segments 2G11 on the same third gate line 2G1 are spaced apart along the first direction X and extend along the first direction X. The orthographic projection of the second conductive portion 22 on the substrate and the orthographic projection of the first conductive portion 11 on the substrate at least partially overlap. The second conductive portion 22 is used to form the second electrode of the capacitor C. The first connecting portion 21 is connected between two adjacent second conductive portions 22 in the first direction X.

[0201] As shown in Figures 2, 6, and 12, the second active layer may include a first active portion 91, a second active portion 92, a seventeenth active portion 917, an eighteenth active portion 918, and a nineteenth active portion 919. The first active portion 91 is used to form the channel region of the first transistor T1, and the second active portion 92 is used to form the channel region of the second transistor T2. The seventeenth active portion 917 is connected to the end of the first active portion 91 away from the second active portion 92, the eighteenth active portion 918 is connected between the first active portion 91 and the second active portion 92, and the nineteenth active portion 919 is connected to the end of the second active portion 92 away from the first active portion 91. The orthogonal projection of the third reset signal segment 2Re11 on the substrate can cover the orthogonal projection of the first active portion 91 on the substrate, and a portion of the structure of the third reset signal segment 2Re11 can be used to form the bottom gate of the first transistor T1. The orthogonal projection of the third gate segment 2G11 on the substrate can cover the orthogonal projection of the second active portion 92 on the substrate, and part of the structure of the third gate segment 2G11 can be used to form the bottom gate of the second transistor T2. The second active layer can be formed of indium gallium zinc oxide, and correspondingly, the first transistor T1 and the second transistor T2 can be N-type metal oxide thin film transistors.

[0202] As shown in Figures 2, 7, and 13, the third gate layer may include: a first initial signal line Vinit1, a third initial signal line Vinit3, a first reset signal line Re1, a first gate line 3G1, an enable signal connection line 3EM, and a second bridging portion 32. The orthogonal projections of the first initial signal line Vinit1, the third initial signal line Vinit3, the first reset signal line Re1, the first gate line 3G1, and the enable signal connection line 3EM on the substrate can all extend along the first direction X. The first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 1, the third initial signal line Vinit3 is used to provide the third initial signal terminal in Figure 1, the first gate line 3G1 is used to provide the first gate drive signal terminal in Figure 1, and the first reset signal line Re1 is used to provide the first reset signal terminal in Figure 1. The first reset signal line 3Re1 can be connected via a via to the third reset signal line segment 2Re11 within the same third reset signal line. The orthographic projection of the first reset signal line 3Re1 onto the substrate can cover the orthographic projection of the first active part 91 onto the substrate. A portion of the structure of the first reset signal line 3Re1 is used to form the top gate of the first transistor T1. The first gate line 3G1 can be connected via a via to the third gate line segment 2G11 within the same third gate line. The orthographic projection of the first gate line 3G1 onto the substrate can cover the orthographic projection of the second active part 92 onto the substrate. A portion of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. The enable signal connection line 3EM can be connected via a via to the first enable signal line segment EM1 and the second enable signal line segment EM2 within the same enable signal line EM. The second bridging portion 32 can be connected to the first conductive portion 11 via a via. An opening 221 can be formed on the second conductive portion 22. The orthogonal projection of the via connecting the first conductive portion 11 and the second bridging portion 32 on the substrate can be located within the orthogonal projection of the opening 221 on the substrate. This display panel can use the third gate layer as a mask to perform conductor processing on the second active layer. That is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0203] As shown in Figures 2, 8, and 14, the first source / drain layer may include a first bridging section 41, a third bridging section 43, a fourth bridging section 44, a fifth bridging section 45, a sixth bridging section 46, an eighth bridging section 48, a first data fan-out line FIPH, a first power connection line 4VDD, and a second initial signal line Vinit2. Specifically, the first bridging section 41 is connected to the sixteenth active section 716 via a via, thereby connecting to the second terminal of the sixth transistor. The third bridging section 43 is connected to the second bridging section 32 and the eighteenth active section 918 via vias, respectively, to connect the gate of the driving transistor and the second terminal of the first transistor, and the first terminal of the second transistor. The fourth bridging section 44 can be connected to the third initial signal line Vinit3 and the twelfth active section 712 via vias, respectively, to connect the first terminal of the eighth transistor and the third initial signal line Vinit3. The fifth bridging section 45 can be connected to the fifteenth active section 715 via a via, thereby connecting to the first terminal of the fourth transistor T4. The sixth bridging section 46 connects to the thirteenth active section 713 and the nineteenth active section 919 via vias to connect the second electrode of the second transistor T2 and the second electrode of the driving transistor T3. The first power connection line 4VDD can connect to the eleventh active section 711 and the first connection section 21 via vias to connect the first electrode of the fifth transistor T5 and the second electrode of the capacitor C. The eighth bridging section 48 connects to the first initial signal line Vinit1 and the seventeenth active section 917 via vias to connect the first electrode of the first transistor T1 and the first initial signal terminal. The orthogonal projection of the first data fan-out line FIPH on the substrate can extend along the first direction X. The first data fan-out line FIPH can be used as a row direction fan-out line connecting data lines in the FIP (Fanout In Pixel). The first data fan-out line can also be set in the area outside the fan-out area of ​​the display area. The first data fan-out line outside the fan-out area can improve the uniformity of the fan-out area and other display areas.

[0204] As shown in Figures 2 and 9, the second source / drain layer may include a first power line 5VDD, a data line Da, a second data fan-out line FIPV, and a seventh bridge portion 57. The orthogonal projections of the first power line 5VDD, data line Da, and second data fan-out line FIPV onto the substrate can extend along the second direction Y. The first power line 5VDD provides the first power supply terminal in Figure 1, and the data line Da provides the data signal terminal in Figure 1. The first power line 5VDD can be connected to the first power connection line 4VDD via a via to connect the first power supply terminal to the first electrode of the fifth transistor and the second electrode of the capacitor. The data line Da can be connected to the fifth bridge portion 45 via a via to connect the data signal terminal to the first electrode of the fourth transistor. The second data fan-out line FIPV can be a column-direction fan-out line connecting the data line in the FIP (Fanout In Pixel). The second data fan-out line can also be provided in the area outside the fan-out area of ​​the display area, which can improve the uniformity of the fan-out area and other display areas. The first data fan-out line FIPH can be connected between the data line Da and the second data fan-out line FIPV. The seventh bridge section 57 can be connected to the first bridge section 41 via a via to connect to the second electrode of the sixth transistor. The seventh bridge section 57 can also be used to connect the first electrode of the light-emitting unit via a via. Two adjacent and connected first power lines 5VDD in the first direction X form a first power line group 5VDDZ.

[0205] In this exemplary embodiment, as shown in Figures 2 and 9, the first power line 5VDD includes a first extension 5VDD1. A portion of the first extensions 5VDD1 of the plurality of first power lines 5VDD form a widened first extension KVDD1. At least a portion of the first extensions 5VDD1 of the plurality of first power lines 5VDD form a narrowed first extension ZVDD1. The orthographic projection of the widened first extension KVDD1 onto the substrate in the first direction X is larger than the orthographic projection of the narrowed first extension ZVDD1 onto the substrate in the first direction X. The redundant space created by the narrowed first extension ZVDD1 facilitates the integration of the second data fan-out line FIPV into the second source / drain layer.

[0206] In this exemplary embodiment, as shown in FIG2 and 9, the first power line 5VDD further includes a second extension 5VDD2. The size of the orthographic projection of the second extension 5VDD2 on the substrate in the first direction X is greater than the size of the orthographic projection of the first extension 5VDD1 on the substrate in the first direction. In two adjacent pixel driving circuits located in adjacent pixel driving circuit groups in the first direction, the two first power lines 5VDD are connected in the same layer through the second extension 5VDD2. In the two first power lines connected in the same layer, the first extension of one first power line 5VDD forms a widened first extension KVDD1, and the first extension of the other first power line 5VDD forms a narrowed first extension ZVDD1. The widened first extension KVDD1 is connected to the pixel driving circuit through a via.

[0207] In this exemplary embodiment, as shown in Figures 2 and 9, in two adjacent pixel driving circuits located in adjacent pixel driving circuit groups Pz in the first direction X, the orthographic projections of the two seventh bridging portions 57 (only one is shown in Figure 2) on the substrate lie between the orthographic projections of the two first extension segments 5VDD1 on the substrate. Narrowing the first extension segment ZVDD1 can avoid the seventh bridging portion 57.

[0208] In this exemplary embodiment, as shown in Figures 2 and 9, the narrowed first extension segment ZVDD1, the widened first extension segment KVDD1, the widened first extension segment KVDD1, and the narrowed first extension segment ZVDD1 can be alternately and repeatedly distributed along the first direction X. That is, the orthographic projections of the narrowed first extension segment, the widened first extension segment, the widened first extension segment, and the narrowed first extension segment on the substrate are distributed sequentially along the first direction, and the orthographic projections of the narrowed first extension segment, the widened first extension segment, the widened first extension segment, and the narrowed first extension segment on the substrate form repeating units.

[0209] It should be noted that the second source / drain layer shown in Figure 9 can also be applied to pixel driving circuits with other arbitrary layout structures.

[0210] In this exemplary embodiment, the display panel further includes an electrode layer located on the side of the second source / drain layer facing away from the substrate, and a pixel definition layer located on the side of the electrode layer facing away from the substrate. The electrode layer includes a plurality of electrode portions: a first electrode portion, a second electrode portion, and a third electrode portion. A plurality of pixel openings corresponding to the electrode portions are formed on the pixel definition layer. The orthographic projection of the electrode portion on the substrate coincides with the orthographic projection of its corresponding pixel opening on the substrate. The first electrode portion is used to form the first electrode of a red light-emitting unit, the second electrode portion is used to form the first electrode of a blue light-emitting unit, and the third electrode portion is used to form the first electrode of a green light-emitting unit. The orthographic projections of the first electrode portion and / or the second electrode portion on the substrate may overlap with the orthographic projection of the second extension 5VDD2 on the substrate, and the orthographic projection of the third electrode portion on the substrate may not overlap with the orthographic projection of the second extension 5VDD2 on the substrate.

[0211] Figure 15 shows a partial cross-sectional view of the display panel shown in Figure 2, taken along the dashed line CC. The display panel may further include a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a first dielectric layer 105, a passivation layer 106, and a first planarization layer 107. The substrate 100, the first active layer, the first insulating layer 101, the first gate layer, the second insulating layer 102, the second gate layer, the third insulating layer 103, the second active layer, the fourth insulating layer 104, the third gate layer, the first dielectric layer 105, the first source / drain layer, the passivation layer 106, the first planarization layer 107, and the second source / drain layer are sequentially stacked. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 can be single-layer or multi-layer structures, and the materials of the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 105 can be a silicon nitride layer; the material of the first planarization layer 107 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 106 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first, second, and third source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of any one of the first and second source / drain layers can be less than the sheet resistance of any one of the first, second, and third gate layers.

[0212] In this exemplary embodiment, as shown in Figures 16-18, Figure 16 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, Figure 17 is a structural layout diagram of the first active layer in the display panel shown in Figure 16, and Figure 18 is a structural layout diagram of the first active layer and the first gate layer in the display panel shown in Figure 16.

[0213] Compared to the display panel shown in FIG. 2, in the display panel shown in FIG. 16, in the same pixel driving circuit group, the orthographic projection of the twelfth active portion 712 on the substrate is at least partially located on the side where the orthographic projection of the eighth active portion 78 connected to it on the substrate is away from the orthographic projection of the other eighth active portion 78 on the substrate; wherein, the eighth transistor T8 includes two channel regions spaced apart, and a portion of the structure of the twelfth active portion 712 is used to form another channel region of the eighth transistor T8. As shown in FIG. 17, the twelfth active portion 712 may include a first sub-active portion 7121 and a second sub-active portion 7122. The first sub-active portion 7121 is used to form another channel region of the eighth transistor, and the second sub-active portion 7122 is connected to the end of the first sub-active portion 7121 away from the eighth active portion 78. The second sub-active portion 7122 is used for via connection to the third initial signal line Vinit3.

[0214] As shown in Figures 16-18, the third gate layer may include a third initial signal line Vinit3, which provides the third initial signal terminal in Figure 1. The third initial signal terminal can be connected to the second sub-active part 7122 via a via. Other structures of the display panel shown in Figure 16 may be the same as those of the display panel shown in Figure 2.

[0215] It should be noted that the technical features in the display panel shown in Figure 16 can also be applied to other embodiments.

[0216] In this exemplary embodiment, as shown in Figures 19-21, Figure 19 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, Figure 20 is a structural layout diagram of the third gate layer in the display panel shown in Figure 19, and Figure 21 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 19.

[0217] Compared to the display panel shown in FIG. 2, in the display panel shown in FIG. 19, in the two data lines Da corresponding to the same pixel driving circuit group Pz, a first recessed region Da1 is formed on the side where the orthogonal projection of one data line Da on the substrate faces the orthogonal projection of the other data line Da on the substrate. The first recessed region Da1 is at least partially located between the orthogonal projection of the first reset signal line 3Re1 on the substrate and the orthogonal projection of the first gate line 3G1 on the substrate. Furthermore, in the display panel shown in FIG. 19, in the same pixel driving circuit, a second recessed region 3Re11 is formed on the side where the orthogonal projection of the first gate line 3G1 on the substrate faces the orthogonal projection of the first reset signal line 3Re1 on the substrate, and a third recessed region 3G11 is formed on the side where the orthogonal projection of the first reset signal line 3Re1 on the substrate faces the orthogonal projection of the first gate line 3G1 on the substrate. The first recessed region Da1 and the second recessed region 3Re11 at least partially overlap, and the first recessed region Da1 and the third recessed region 3G11 at least partially overlap.

[0218] The display panel can transmit light in the overlapping area AA of the first recessed area Da1, the second recessed area 3Re11, and the third recessed area 3G11, thereby improving the light transmittance of the display panel and facilitating the placement of devices such as under-display fingerprint sensors. The other structures of the display panel shown in Figure 19 can be the same as those of the display panel shown in Figure 2.

[0219] It should be noted that the technical features in the display panel shown in Figure 19 can also be applied to other embodiments.

[0220] In this exemplary embodiment, as shown in Figures 22-26, Figure 22 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, Figure 23 is a structural layout diagram of the first active layer in the display panel shown in Figure 22, Figure 24 is a structural layout diagram of the third gate layer in the display panel shown in Figure 22, Figure 25 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 22, and Figure 26 is a structural layout diagram of the first source / drain layer, the first gate layer, the second active layer, and the third gate layer in the display panel shown in Figure 22.

[0221] Compared to the display panel shown in Figure 2, in the display panel shown in Figure 22, within the same pixel driving circuit group, the orthographic projection of the twelfth active portion 712 on the substrate is at least partially located on the side where the orthographic projection of the eighth active portion 78 connected to it on the substrate is away from the orthographic projection of the other eighth active portion 78 on the substrate; wherein, the eighth transistor T8 includes two channel regions spaced apart, and a portion of the structure of the twelfth active portion 712 is used to form another channel region of the eighth transistor T8. As shown in Figures 22-25, the twelfth active portion 712 may include a first sub-active portion 7121 and a second sub-active portion 7122. The first sub-active portion 7121 is used to form another channel region of the eighth transistor, and the second sub-active portion 7122 is connected to the end of the first sub-active portion 7121 away from the eighth active portion 78. The third initial signal line Vinit3 can be directly connected to the second sub-active portion 7122 through a via. In the second direction Y, the orthographic projection of the second sub-active portion 7122 on the substrate lies between the orthographic projection of the first sub-active portion 7121 on the substrate and the orthographic projection of the enable signal connection line 3EM on the substrate. The third gate layer includes an outward protrusion VT, which is connected to the third initial signal line Vinit3. The orthographic projection of the outward protrusion VT on the substrate lies between the orthographic projection of the third initial signal line Vinit3 on the substrate and the orthographic projection of the enable signal connection line 3EM on the substrate. The third initial signal line Vinit3 can be connected to the second sub-active portion 7122 through a via of the outward protrusion VT to connect the third initial signal terminal and the first electrode of the eighth transistor. As shown in Figure 22, compared to the display panel shown in Figure 2, the third initial signal line Vinit3 does not need to be connected to the first electrode of the eighth transistor through a via in the local area BB. This setting can improve the light transmittance of the display panel in the local area BB, thereby facilitating the installation of devices such as fingerprint sensors.

[0222] Furthermore, as shown in Figures 22-26, compared to the display panel shown in Figure 2, in the display panel shown in Figure 22, for each of the two data lines Da corresponding to the same pixel driving circuit group Pz, a first recessed area Da1 is formed on the side where the orthogonal projection of one data line Da onto the substrate faces the orthogonal projection of the other data line Da onto the substrate. The first recessed area Da1 is at least partially located between the orthogonal projection of the first reset signal line 3Re1 onto the substrate and the orthogonal projection of the first gate line 3G1 onto the substrate. The display panel can have high light transmittance in the area BB where the first recessed area Da1 is located. This configuration also facilitates the installation of devices such as fingerprint sensors. Other structures of the display panel shown in Figure 22 can be the same as those of the display panel shown in Figure 2.

[0223] It should be noted that the technical features in the display panel shown in Figure 22 can also be applied to other embodiments.

[0224] Figure 27 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Compared to the display panel shown in Figure 2, the display panel shown in Figure 27 does not have a fourth bridging portion. The third initial signal line Vinit3 in the display panel shown in Figure 27 is directly connected to the twelfth active portion through a via. Other structures of the display panel shown in Figure 27 can be the same as those of the display panel shown in Figure 2. It should be noted that the technical features in the display panel shown in Figure 27 can also be applied to other embodiments.

[0225] Figure 28 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Compared to the display panel shown in Figure 27, the third initial signal line Vinit3 in the display panel shown in Figure 28 is directly connected to the twelfth active unit through a via. This arrangement can reduce the space occupied by the via. Other structures of the display panel shown in Figure 28 can be the same as those of the display panel shown in Figure 27. It should be noted that the technical features in the display panel shown in Figure 28 can also be applied to other embodiments.

[0226] Figure 29 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Compared to the display panel shown in Figure 27, the display panel shown in Figure 29 adds a fourth bridging portion 44. The fourth bridging portion 44 can be connected to the third initial signal line Vinit3 through one or more vias. The fourth bridging portion 44 connected in parallel to the third initial signal line Vinit3 can reduce the self-resistance of the third initial signal line Vinit3. Other structures of the display panel shown in Figure 29 can be the same as those of the display panel shown in Figure 27. It should be noted that the technical features in the display panel shown in Figure 29 can also be applied to other embodiments.

[0227] As shown in Figures 30 and 31, Figure 30 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 31 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 30.

[0228] Compared to the display panel shown in Figure 2, the third initial signal line Vinit3 in the display panel shown in Figure 30 is directly connected to the twelfth active unit through a via.

[0229] Furthermore, as shown in Figures 30 and 31, the first power connection line 4VDD includes a third extension 4VDD3 and a fourth extension 4VDD4. The size of the orthographic projection of the third extension 4VDD3 onto the substrate in the second direction Y is larger than the size of the orthographic projection of the fourth extension 4VDD4 onto the substrate in the second direction Y. The orthographic projection of the second initial signal line Vinit2 onto the substrate extends along the first direction X. A groove VC is formed on the side of the orthographic projection of the second initial signal line Vinit2 onto the substrate facing the orthographic projection of the first power connection line 4VDD onto the substrate. The groove VC and the orthographic projection of the third extension 4VDD3 onto the substrate are disposed opposite to each other in the second direction Y. The third bridging portion 43 connects the gate of the driving transistor and the first electrode of the second transistor through vias, respectively. In this exemplary embodiment, the groove VC is formed on the second initial signal line Vinit2, thereby allowing the first power connection line 4VDD to be moved downwards. The third bridging portion 43 has sufficient space to directly connect to the first conductive portion 11 through vias to connect to the gate of the driving transistor. The other structures of the display panel shown in Figure 30 can be the same as those of the display panel shown in Figure 2.

[0230] The orthographic projections of the groove VC and the third extension 4VDD3 on the substrate are arranged opposite each other in the second direction Y. It can be understood that the area covered by the movement of the groove VC in the second direction and the area covered by the orthographic projection of the third extension 4VDD3 on the substrate in the second direction at least partially overlap.

[0231] It should be noted that the technical features in the display panel shown in Figure 30 can also be applied to other embodiments.

[0232] As shown in Figures 32-34, Figure 32 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure, Figure 33 is a structural layout diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in the display panel shown in Figure 32, and Figure 34 is a structural layout diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 32.

[0233] Unlike the display panel shown in Figure 2, the first initial signal line Vinit1 in the display panel shown in Figure 32 is located in the second gate layer. Simultaneously, the third gate layer in the display panel shown in Figure 32 adds a first initial bridging segment 3Vinit1. The orthographic projection of the first initial bridging segment 3Vinit1 on the substrate extends along the first direction X. The first initial bridging segment 3Vinit1 is connected to the first initial signal line Vinit1 through multiple vias. This arrangement can reduce the resistance of the first initial signal line Vinit1.

[0234] As shown in Figures 32-34, the first data fan-out line FIPH includes a first via connection portion FL. The first data fan-out line FIPH can be connected to the second data fan-out line FIPV via through the first via connection portion FL. The orthographic projection of the via between the first initial bridging segment 3Vinit1 and the first initial signal line Vinit1 on the substrate and the orthographic projection of the first via connection portion FL on the substrate at least partially overlap.

[0235] In this exemplary embodiment, some of the second data fan-out lines FIPV and some of the first data fan-out lines FIPH in the display panel are connected by vias, while some of the second data fan-out lines FIPV and some of the first data fan-out lines FIPH are not connected. This exemplary embodiment places the via between the first initial bridging segment 3Vinit1 and the first initial signal line Vinit1 in the region where the first via connection portion FL is located. This arrangement ensures that the region where the first via connection portion FL is located has a depression created by the via, thereby allowing different locations on the display panel to have similar film layer morphologies, thus improving the uniformity of the display panel. Other structures of the display panel shown in FIG32 can be the same as those of the display panel shown in FIG2.

[0236] It should be noted that the technical features in the display panel shown in Figure 32 can also be applied to other embodiments.

[0237] As shown in Figures 35-37, Figure 35 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, Figure 36 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 35, and Figure 37 is a structural layout diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 35.

[0238] As shown in Figures 35-37, the first power connection line 4VDD includes a main body VZ and a first protrusion VT1. The orthographic projection of the main body VZ on the substrate extends along the first direction X, and the orthographic projection of the first protrusion VT1 on the substrate is located on the side where the orthographic projection of the main body VZ on the substrate is in the second direction Y. The overlapping area of ​​the orthographic projections of the second data fan-out line FIPV and the second gate line G2 on the substrate at least partially overlaps with the orthographic projection of the first protrusion VT1 on the substrate. The first protrusion VT1 can shield the signal interference between the second data fan-out line FIPV and the second gate line G2.

[0239] As shown in Figures 35-37, the first power connection line 4VDD includes a main body VZ and a second protrusion VT2. The orthographic projection of the main body VZ on the substrate extends along the first direction X, and the orthographic projection of the second protrusion VT2 on the substrate is located on the side where the orthographic projection of the main body VZ on the substrate is in the second direction Y. The orthographic projection of the main body VZ on the substrate may be located between the orthographic projections of the first protrusion VT1 and the second protrusion VT2 on the substrate. The overlapping area of ​​the orthographic projections of the second data fan-out line FIPV and the enable signal connection line 3EM on the substrate at least partially overlaps with the orthographic projection of the second protrusion VT2 on the substrate. The second protrusion VT2 can shield the signal interference between the enable signal connection line 3EM and the second data fan-out line FIPV. Other structures of the display panel shown in Figure 35 can be the same as those of the display panel shown in Figure 2.

[0240] It should be noted that the technical features in the display panel shown in Figure 35 can also be applied to other embodiments.

[0241] Figure 38 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Compared with the display panel shown in Figure 2, in the display panel shown in Figure 38, the overlapping area of ​​the orthographic projection of the second data fan-out line FIPV on the substrate and the orthographic projection of the enable signal connection line 3EM on the substrate at least partially overlaps with the orthographic projection of the second initial signal line Vinit2 on the substrate. The second initial signal line Vinit2 can shield the signal interference between the enable signal connection line 3EM and the second data fan-out line FIPV. This exemplary embodiment can achieve at least partial overlap of the overlapping area of ​​the orthographic projection of the second data fan-out line FIPV on the substrate and the orthographic projection of the enable signal connection line 3EM on the substrate with the orthographic projection of the second initial signal line Vinit2 on the substrate by moving the second initial signal line Vinit2 upward in the display panel shown in Figure 2 or by providing a protrusion on the second initial signal line Vinit2. It should be noted that the technical features in the display panel shown in Figure 38 can also be applied to other embodiments.

[0242] Figure 39 shows a structural layout of the second source / drain layer in another exemplary embodiment of the display panel of this disclosure. The second source / drain layer may include multiple constant voltage connection lines 5Vx. The orthographic projection of the multiple constant voltage connection lines 5Vx on the substrate may extend along the second direction Y and be spaced apart along the first direction X. The constant voltage connection lines 5Vx may be connected to corresponding and intersecting constant voltage signal lines via vias. The constant voltage signal lines may include one or more of the aforementioned first initial signal line Vinit1, second initial signal line Vinit2, and third initial signal line Vinit3. Correspondingly, the multiple constant voltage connection lines 5Vx may also include one or more of the first constant voltage connection line 5Vinit1, second constant voltage connection line 5Vinit2, and third constant voltage connection line 5Vinit3. The first constant voltage connection line 5Vinit1 may be connected to the intersecting first initial signal line Vinit1 via vias; the second constant voltage connection line 5Vinit2 may be connected to the intersecting second initial signal line Vinit2 via vias; and the third constant voltage connection line 5Vinit3 may be connected to the intersecting third initial signal line Vinit3 via vias. It should be understood that, in other exemplary embodiments, the constant voltage connection lines 5Vx at various locations can be any type of constant voltage connection line. Furthermore, in other exemplary embodiments, some of the constant voltage connection lines 5Vx can also form a second power line, which can connect to the second electrode of the light-emitting unit. For example, the second power line can be connected via a via to the common cathode in the display panel.

[0243] As shown in Figure 39, in the data line Da and the first power line 5VDD corresponding to the same pixel driving circuit, the orthogonal projection of the constant voltage connection line 5Vx on the substrate can be located on the side where the orthogonal projection of the data line Da on the substrate is far from the orthogonal projection of the first power line 5VDD on the substrate. It should be noted that the technical features in the display panel shown in Figure 39 can also be applied to other embodiments.

[0244] Figure 40 shows a structural layout of the second source / drain layer in another exemplary embodiment of the display panel of this disclosure. The second source / drain layer may also include multiple constant voltage connection lines 5Vx, whose orthogonal projections on the substrate extend along the second direction Y and are spaced apart along the first direction X. Since some of the second data fan-out lines FIPV in the display panel are not connected to data lines, compared to the display panel shown in Figure 2, the display panel shown in Figure 39 can multiplex at least some of the second data fan-out lines FIPV that are not connected to data lines into constant voltage connection lines 5Vx. The orthogonal projections of the second data fan-out lines FIPV, constant voltage connection lines 5Vx, and constant voltage connection lines 5Vx on the substrate are alternately and repeatedly distributed along the first direction. Similarly, the constant voltage connection lines 5Vx can be connected to corresponding and intersecting constant voltage signal lines via vias. The constant voltage signal line may include one or more of the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 mentioned above. Correspondingly, the multiple constant voltage connection lines 5Vx may also include one or more of the first constant voltage connection line 5Vinit1, the second constant voltage connection line 5Vinit2, and the third constant voltage connection line 5Vinit3. The first constant voltage connection line 5Vinit1 can be connected to the intersecting first initial signal line Vinit1 via a via, the second constant voltage connection line 5Vinit2 can be connected to the intersecting second initial signal line Vinit2 via a via, and the third constant voltage connection line 5Vinit3 can be connected to the intersecting third initial signal line Vinit3 via a via. It should be understood that in other exemplary embodiments, the constant voltage connection lines 5Vx at each location can be any type of constant voltage connection line. Furthermore, in other exemplary embodiments, some of the constant voltage connection lines 5Vx may also form a second power line, which can be connected to the second electrode of the light-emitting unit. For example, the second power line can be connected to the common cathode in the display panel via a via. It should be noted that the technical features in the display panel shown in FIG40 can also be applied to other embodiments.

[0245] Figure 41 shows a structural layout of the second source / drain layer in another exemplary embodiment of the display panel of this disclosure. The second source / drain layer may include multiple constant voltage connection lines 5Vx. The orthogonal projection of the multiple constant voltage connection lines 5Vx onto the substrate may extend along the second direction Y and be spaced apart along the first direction X. The constant voltage connection lines 5Vx may be connected to corresponding and intersecting constant voltage signal lines via vias. The constant voltage signal lines may include one or more of the aforementioned first initial signal line Vinit1, second initial signal line Vinit2, and third initial signal line Vinit3. Correspondingly, the multiple constant voltage connection lines 5Vx may also include one or more of the first constant voltage connection line 5Vinit1, second constant voltage connection line 5Vinit2, and third constant voltage connection line 5Vinit3. The first constant voltage connection line 5Vinit1 may be connected to the intersecting first initial signal line Vinit1 via via, the second constant voltage connection line 5Vinit2 may be connected to the intersecting second initial signal line Vinit2 via via via, and the third constant voltage connection line 5Vinit3 may be connected to the intersecting third initial signal line Vinit3 via via via. It should be understood that, in other exemplary embodiments, the constant voltage connection lines 5Vx at various locations can be any type of constant voltage connection line. Furthermore, in other exemplary embodiments, some of the constant voltage connection lines 5Vx can also form a second power line, which can connect to the second electrode of the light-emitting unit. For example, the second power line can be connected via a via to the common cathode in the display panel.

[0246] As shown in Figure 41, in the data line Da and the first power line 5VDD corresponding to the same pixel driving circuit, the orthogonal projection of the constant voltage connection line 5Vx on the substrate can be located on the side where the orthogonal projection of the first power line VDD on the substrate is far away from the orthogonal projection of the data line Da on the substrate.

[0247] As shown in Figure 41, since the first power lines 5VDD are spaced apart, each first power line 5VDD needs to be connected via a via to at least a portion of the first power connection line 4VDD that intersects with it. It should be noted that the technical features in the display panel shown in Figure 41 can also be applied to other embodiments.

[0248] Furthermore, the pixel driving circuit in the display panel can also have other structures. This exemplary embodiment does not limit the structure of the pixel driving circuit. For example, the pixel driving circuit can also be a 9T1C structure.

[0249] As shown in Figures 42 and 43, Figure 42 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 43 is a structural layout diagram of the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in the display panel shown in Figure 42.

[0250] In this exemplary embodiment, as shown in Figures 42 and 43, compared to the display panel shown in Figure 2, the first initial signal line Vinit1 in the display panel shown in Figure 42 is connected to the seventeenth active unit 917 via a via, and the eighth bridging unit 48 can connect the first initial signal line Vinit1 and the seventeenth active unit 917 via vias respectively. That is, in this exemplary embodiment, the first initial signal line Vinit1 is directly connected to the seventeenth active unit 917 via a via, and at the same time, the first initial signal line Vinit1 is also connected to the seventeenth active unit 917 via the eighth bridging unit 48. This arrangement makes the connection between the first initial signal line Vinit1 and the seventeenth active unit 917 more stable.

[0251] Figure 44 shows a cross-sectional view of the display panel shown in Figure 42 along the dashed line DD. This display panel may also include a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a first dielectric layer 105, a passivation layer 106, and a first planarization layer 107. The substrate 100, the first active layer, the first insulating layer 101, the first gate layer, the second insulating layer 102, the second gate layer, the third insulating layer 103, the second active layer, the fourth insulating layer 104, the third gate layer, the first dielectric layer 105, the first source / drain layer, the passivation layer 106, the first planarization layer 107, and the second source / drain layer are sequentially stacked. The first initial signal line Vinit1 can be connected to the seventeenth active part 917 through the first via V1, the eighth bridging part 48 can be connected to the first initial signal line Vinit1 through the second via V2, and the eighth bridging part 48 can be connected to the seventeenth active part 917 through the third via V3.

[0252] The other structures of the display panel shown in Figure 42 can be the same as those of the display panel shown in Figure 2. The technical features in the display panel shown in Figure 42 can also be applied to other embodiments.

[0253] Figure 45 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Compared to the display panel shown in Figure 2, the display panel shown in Figure 45 has the third initial signal line Vinit3 disposed on the first source / drain layer. Correspondingly, the third initial signal line Vinit3 can be directly connected to the eighth transistor through a via. Simultaneously, the display panel shown in Figure 45 can have the second initial signal line Vinit2 disposed on the third gate layer and the first initial signal line Vinit1 disposed on the second gate layer. As shown in Figure 45, in order to improve the light transmittance of the display panel, in the same pixel driving circuit, the orthographic projection of the second initial signal line Vinit2 on the substrate can protrude to the side opposite to the orthographic projection of the third initial signal line Vinit3 on the substrate. The orthographic projection of the second initial signal line Vinit2 on the substrate can at least partially overlap with the orthographic projection of the first initial signal line Vinit1 on the substrate in the adjacent next row of pixel driving circuits.

[0254] In this exemplary embodiment, the third initial signal line Vinit3 typically provides a high-level signal, for example, the potential on the third initial signal line Vinit3 is typically 3V-8V, and the second initial signal line Vinit2 typically provides a low-level signal, for example, the potential on the second initial signal line Vinit2 is typically -2.5V. Because the voltage difference between the second initial signal line Vinit2 and the third initial signal line Vinit3 is large, the voltage between them can easily break down the insulation layer between the two signal lines, resulting in a short circuit between the two signal lines. As shown in FIG45, in this exemplary embodiment, the orthographic projection of the second initial signal line Vinit2 on the substrate and the orthographic projection of the third initial signal line Vinit3 on the substrate do not overlap. This arrangement can reduce the risk of a short circuit between the second initial signal line Vinit2 and the third initial signal line Vinit3.

[0255] It should be understood that, in other exemplary embodiments, the orthographic projections of the second initial signal line Vinit2 and the third initial signal line Vinit3 on the substrate may at least partially overlap. This exemplary embodiment can reduce the risk of short circuits between the second initial signal line Vinit2 and the third initial signal line Vinit3 by increasing the thickness of the first dielectric layer 105 between the first source / drain layer and the third gate layer. For example, the thickness of the first dielectric layer 105 may be greater than the thickness of the fourth insulating layer 104, and / or, the thickness of the first dielectric layer 105 may be greater than the thickness of the third insulating layer 103.

[0256] The other structures of the display panel shown in Figure 45 can be the same as those of the display panel shown in Figure 2. The technical features in the display panel shown in Figure 45 can also be applied to other embodiments.

[0257] Figure 46 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. Compared to the display panel shown in Figure 2, the display panel shown in Figure 46 may include a shielding layer located between the substrate and the first active layer. The shielding layer is a conductive layer, and as shown in Figure 46, the third initial signal line Vinit3 may be located in the shielding layer. The third gate layer may include a ninth bridging portion 39, which may connect the third initial signal line Vinit3 and the twelfth active portion 712 through vias, respectively, to connect the first electrode and the third initial signal terminal of the eighth transistor T8. It should be understood that in other exemplary embodiments, the third initial signal line Vinit3 and the twelfth active portion 712 may also be bridged by a bridging portion located in the first source / drain layer. It should be noted that the technical features in the display panel shown in Figure 46 may also be applied to other embodiments.

[0258] Figure 47 shows a cross-sectional view of the display panel shown in Figure 46 along the dashed line EE. The display panel may further include a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a buffer layer 108, a first dielectric layer 105, a passivation layer 106, and a first planarization layer 107. The substrate 100, shielding layer, buffer layer 108, first active layer, first insulating layer 101, first gate layer, second insulating layer 102, second gate layer, third insulating layer 103, second active layer, fourth insulating layer 104, third gate layer, first dielectric layer 105, first source / drain layer, passivation layer 106, first planarization layer 107, and second source / drain layer are sequentially stacked. The ninth bridging portion 39 can be connected to the twelfth active portion 712 located in the first active layer through vias that pass through the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in sequence. The ninth bridging portion 39 can also be connected to the third initial signal line located in the shielding layer through vias that pass through the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, the first insulating layer 101, and the buffer layer 108 in sequence.

[0259] In this exemplary embodiment, the third initial signal line Vinit3 is located in the shielding layer, and the second initial signal line Vinit2 is located in the first source / drain layer. There is a thickened insulating layer between the shielding layer and the first source / drain layer. This arrangement can reduce the risk of the voltage difference between the third initial signal line Vinit3 and the second initial signal line Vinit2 breaking down the insulating layer between the two signal lines and causing a short circuit.

[0260] As shown in Figures 48 and 49, Figure 48 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 49 is a structural layout diagram of the first active layer in the display panel shown in Figure 48. Compared with the display panel shown in Figure 46, the first active layer includes a twentieth active portion 720 connected to the fourteenth active portion 714. Furthermore, the second initial signal line Vinit2 in the display panel shown in Figure 48 is located in the second gate layer, and the third gate layer may include a tenth bridge portion 310. The tenth bridge portion 310 can connect the second initial signal line Vinit2 and the twentieth active portion 720 respectively through vias to connect the second initial signal terminal and the first electrode of the seventh transistor.

[0261] It should be understood that, in other exemplary embodiments, the second initial signal line Vinit2 can also be connected to the first terminal of the seventh transistor through a bridging portion located in the first source-drain layer; that is, the bridging portion located in the first source-drain layer connects the second initial signal line Vinit2 and the first terminal of the seventh transistor respectively through vias. Furthermore, in other exemplary embodiments, the second initial signal line Vinit2 can also be located in the third gate layer. When the second initial signal line Vinit2 is located in the third gate layer, the second initial signal line Vinit2 can be directly connected to the first terminal of the seventh transistor through vias.

[0262] It should be understood that, in other exemplary embodiments, the second initial signal line Vinit2 may also be located in one or more of the second gate layer, the third gate layer, and the first source / drain layer. The technical features in the display panel shown in FIG48 may also be applied to other embodiments.

[0263] Figure 50 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Compared to the display panel shown in Figure 48, the first source / drain layer of the display panel shown in Figure 50 may further include a second initial parallel line 4Vinit2. The orthogonal projection of the second initial parallel line 4Vinit2 on the substrate may extend along the first direction X. The second initial parallel line 4Vinit2 may be connected to the tenth bridging portion 310 through a via, thereby forming a parallel structure between the second initial parallel line 4Vinit2 and the second initial signal line Vinit2, i.e., the second initial parallel line 4Vinit2 and the second initial signal line Vinit2 are connected by a via. This arrangement can reduce the self-resistance of the second initial signal line Vinit2, thereby reducing the voltage drop of the signal on the second initial signal line Vinit2, and thus improving the uniformity of the display panel. It should be noted that the technical features in the display panel shown in Figure 50 may also be applied to other embodiments.

[0264] Figure 51 shows a cross-sectional view of the display panel shown in Figure 50 along the dashed line FF. The display panel may further include a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a buffer layer 108, a first dielectric layer 105, a passivation layer 106, and a first planarization layer 107. The substrate 100, shielding layer, buffer layer 108, first active layer, first insulating layer 101, first gate layer, second insulating layer 102, second gate layer, third insulating layer 103, second active layer, fourth insulating layer 104, third gate layer, first dielectric layer 105, first source / drain layer, passivation layer 106, first planarization layer 107, and second source / drain layer are sequentially stacked. The second initial parallel line 4Vinit2 can be connected to the tenth bridge section 310 through the third via V3, and the tenth bridge section 310 can be connected to the second initial signal line Vinit2 through the fourth via V4. As shown in Figure 51, the orthogonal projection of the third via V3 on the substrate can at least partially overlap with the orthogonal projection of the fourth via V4 on the substrate. For example, the orthogonal projection of the third via V3 on the substrate can be located within the orthogonal projection of the fourth via V4 on the substrate, or vice versa. This arrangement can reduce the space occupied by the vias, thereby increasing the pixel density of the display panel. It should be understood that in other exemplary embodiments, the orthogonal projection of the third via V3 on the substrate may not overlap with the orthogonal projection of the fourth via V4 on the substrate. This arrangement can make the metal layer at the bottom of the third via V3 flat, thereby improving the contact performance of the third via V3 and the second initial signal line Vinit2.

[0265] As shown in Figures 52 and 53, Figure 52 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 53 is a structural layout diagram of the first active layer, first gate layer, second gate layer, second active layer, and third gate layer in the display panel shown in Figure 52. Compared with the display panel shown in Figure 50, the display panel shown in Figure 52 does not have a twentieth active portion in the first active layer. Meanwhile, the display panel shown in Figure 52 places the second initial signal line Vinit2 in the third gate layer, and the second initial signal line Vinit2 is directly connected to the fourteenth active portion 714 through a via to connect the second initial signal terminal and the first electrode of the seventh transistor.

[0266] Figure 54 shows a cross-sectional view of the display panel shown in Figure 52 along the dashed line GG. The display panel may further include a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a buffer layer 108, a first dielectric layer 105, a passivation layer 106, and a first planarization layer 107. The substrate 100, the shielding layer, the buffer layer 108, the first active layer, the first insulating layer 101, the first gate layer, the second insulating layer 102, the second gate layer, the third insulating layer 103, the second active layer, the fourth insulating layer 104, the third gate layer, the first dielectric layer 105, the first source / drain layer, the passivation layer 106, the first planarization layer 107, and the second source / drain layer are sequentially stacked. Specifically, the second initial parallel line 4Vinit2 can be connected to the second initial signal line Vinit2 through the fifth via V5, and the second initial signal line Vinit2 can be directly connected to the fourteenth active part 714 through the sixth via V6. This arrangement can reduce the number of vias, which is beneficial for the design of high pixel density display panels. The orthographic projections of the fifth via V5 and the sixth via V6 on the substrate can overlap or not overlap.

[0267] In this exemplary embodiment, as shown in Figures 50 and 52, the orthographic projections of the second initial parallel line 4Vinit2 and the second initial signal line Vinit2 on the substrate may partially overlap and partially not overlap. The partial overlap of the orthographic projections of the second initial parallel line 4Vinit2 and the second initial signal line Vinit2 on the substrate improves the light transmittance of the display panel. The partial non-overlap of the orthographic projections of the second initial parallel line 4Vinit2 and the second initial signal line Vinit2 on the substrate avoids the risk of breakage due to excessive segment difference in the upper metal line caused by complete overlap of the second initial parallel line 4Vinit2 and the second initial signal line Vinit2. It should be noted that the technical features in the display panel shown in Figure 52 can also be applied to other embodiments.

[0268] Figure 55 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Compared to Figure 52, the orthographic projection of the third initial signal line Vinit3 on the substrate and the orthographic projection of the second initial signal line Vinit2 on the substrate in the display panel shown in Figure 55 at least partially overlap, and / or, the orthographic projection of the third initial signal line Vinit3 on the substrate and the orthographic projection of the second reset signal line Re2 on the substrate at least partially overlap. This arrangement can further improve the light transmittance of the display panel. This feature can also be applied to any other embodiment. In addition, the display panel shown in Figure 55 only has the second initial signal line Vinit2 in the first source / drain layer. It should be noted that the technical features in the display panel shown in Figure 55 can also be applied to other embodiments.

[0269] Figure 56 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Compared to the display panel shown in Figure 55, the orthographic projection of the third initial signal line Vinit3 on the substrate and the orthographic projection of the first initial signal line Vinit1 in the adjacent next row pixel driving circuit on the substrate at least partially overlap, and / or, the orthographic projection of the third initial signal line Vinit3 on the substrate and the orthographic projection of the first data fan-out line FIPH on the substrate at least partially overlap. This arrangement can also improve the light transmittance of the display panel. This feature can also be applied to any other embodiment. It should be noted that the technical features in the display panel shown in Figure 56 can also be applied to other embodiments.

[0270] Figure 57 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Compared to the display panel shown in Figure 2, the display panel shown in Figure 57 may include a shielding layer located between the substrate and the first active layer. The shielding layer is a conductive layer, and as shown in Figure 57, the second initial signal line Vinit2 may be located in the shielding layer. Specifically, in the same pixel driving circuit, the orthographic projection of the second initial signal line Vinit2 onto the substrate is located on the side where the orthographic projection of the third initial signal line Vinit3 onto the substrate is away from the orthographic projection of the first initial signal line Vinit1 onto the substrate. The third gate layer may include an eleventh bridging portion 311, which may connect the second initial signal line Vinit2 and the fourteenth active portion 714 respectively through vias to connect the second initial signal terminal and the first electrode of the seventh transistor.

[0271] In this exemplary embodiment, as shown in FIG57, the third initial signal line Vinit3 may be located in the first source / drain layer. The orthographic projection of the third initial signal line Vinit3 on the substrate and the orthographic projection of the second initial signal line Vinit2 on the substrate may not overlap. This arrangement can reduce the risk of short circuit between the second initial signal line Vinit2 and the third initial signal line Vinit3.

[0272] It should be noted that the technical features of the display panel shown in Figure 57 can also be applied to any other embodiment.

[0273] It should be understood that since the shielding layer and the first source / drain layer are far apart, the risk of short-circuiting the third initial signal line Vinit3 and the second initial signal line Vinit2 is not high. To improve the light transmittance of the display panel, the orthographic projection of the third initial signal line Vinit3 onto the substrate and the orthographic projection of the second initial signal line Vinit2 onto the substrate can also partially overlap. For example, as shown in FIG58, which is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, the orthographic projection of the third initial signal line Vinit3 onto the substrate and the orthographic projection of the second initial signal line Vinit2 onto the substrate can also partially overlap in the display panel shown in FIG58.

[0274] It should be noted that the technical features of the display panel shown in Figure 58 can also be applied to any other embodiment.

[0275] It should be understood that in other exemplary embodiments, the third initial signal line Vinit3 may also be located in one or more of the second gate layer, the third gate layer, and the first source / drain layer. For example, when the third initial signal line Vinit3 is located in the second gate layer, the third initial signal line Vinit3 can be connected to the twelfth active portion 712 via a bridging portion located in the third gate layer or the first source / drain layer, that is, the bridging portion located in the third gate layer or the first source / drain layer connects the third initial signal line Vinit3 and the twelfth active portion 712 respectively via a via. When the third initial signal line Vinit3 is located in the third gate layer, the third initial signal line Vinit3 can be directly connected to the twelfth active portion 712 via a via, and / or, the third initial signal line Vinit3 can be connected to the twelfth active portion 712 via a bridging portion located in the first source / drain layer. Furthermore, the third initial signal line Vinit3 can be formed by parallel connection of signal lines located in at least two of the second gate layer, the third gate layer, and the first source / drain layer. This arrangement can reduce the resistance of the third initial signal line, thereby improving the uniformity of the display panel. For example, the third initial signal line Vinit3 can be formed by connecting two initial signal lines in parallel, located in the third gate layer and the first source / drain layer.

[0276] In this exemplary embodiment, the first initial signal line Vinit1 may also be located in other conductive layers. For example, the conductive layer containing the first initial signal line Vinit1 may be located between the second active layer and the substrate. Optionally, the first initial signal line Vinit1 may be located in the second gate layer. When the display panel includes a shielding layer located between the substrate and the first active layer, the first initial signal line Vinit1 may also be located in the shielding layer.

[0277] As shown in Figures 59 and 60, Figure 59 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 60 is a structural schematic diagram of the second active layer in the display panel shown in Figure 59. The first initial signal line Vinit1 can be located in the second gate layer, and the first initial signal line Vinit1 can be connected to the first electrode of the first transistor through the twelfth bridge portion 312 located in the third gate layer. As shown in Figures 59 and 60, in this exemplary embodiment, the seventeenth active portion 917 located in adjacent pixel driving circuit groups in the first direction is independently arranged, and the twelfth bridge portion 312 can connect the seventeenth active portion 917 and the first initial signal line Vinit1 respectively through vias. In addition, the twelfth bridge portion 312 can also be located in the first source / drain layer, and the first initial signal line Vinit1 can also include one or more layers located in the shielding layer, the second gate layer, the third gate layer, and the first source / drain layer. It should be noted that the technical features in the display panel shown in Figure 59 can also be applied to other embodiments.

[0278] As shown in Figures 61 and 62, Figure 61 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 62 is a structural schematic diagram of the second active layer in the display panel shown in Figure 61. Compared with the display panel shown in Figure 59, in the display panel shown in Figure 61, the first active portions 91 located in adjacent pixel driving circuit groups in the first direction are connected by a seventeenth active portion 917. An opening 9H is formed on the seventeenth active portion 917, and the orthographic projection of the opening 9H on the substrate overlaps with the orthographic projection of the first initial signal line Vinit1 on the substrate. Correspondingly, the twelfth bridging portion 312 can be connected to the first initial signal line Vinit1 exposed outside the opening 9H through a via. In this exemplary embodiment, the twelfth bridging portion 312 may be located in the third gate layer or the first source / drain layer. The first initial signal line Vinit1 may also include one or more layers located in the shielding layer, the second gate layer, the third gate layer, and the first source / drain layer. It should be noted that the technical features in the display panel shown in Figure 62 can also be applied to other embodiments.

[0279] Figure 63 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Based on the display panel shown in Figure 16, the display panel shown in Figure 63 adds a first source / drain layer. The second initial signal line Vinit2 is located in the first source / drain layer, and the orthographic projections of the second initial signal line Vinit2 and the third initial signal line Vinit3 on the substrate do not overlap. This arrangement reduces the risk of short circuits caused by the voltage difference between the second initial signal line Vinit2 and the third initial signal line Vinit3 breaking down the insulating layer between the two initial signal lines. The display panel shown in Figure 63 bends the twelfth active portion 712 upwards, and the via between the third initial signal line Vinit3 and the twelfth active portion 712 is moved upwards, thereby reserving sufficient space below for the second initial signal line Vinit2.

[0280] As shown in Figures 17 and 63, the first active layer includes a twenty-first active portion 721 connected between the two channel regions of the eighth transistor. The orthographic projection of the second initial signal line Vinit2 on the substrate and the orthographic projection of the second active portion 721 on the substrate at least partially overlap. The second initial signal line Vinit2 can regulate the voltage of the second active portion 721 to improve the problem of leakage current from the second active portion 721 to the source and drain of the eighth transistor. It should be noted that the technical features in the display panel shown in Figure 63 can also be applied to other embodiments.

[0281] Figure 64 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. In the display panel shown in Figure 64, compared to the display panel shown in Figure 63, the second initial signal line Vinit2 can be located in the third gate layer, and the third initial signal line Vinit3 can be located in the first source / drain layer.

[0282] It should be understood that, in other exemplary embodiments, in order to improve the light transmittance of the display panel, the orthographic projections of the second initial signal line Vinit2 and the third initial signal line Vinit3 on the substrate may at least partially overlap. Furthermore, the second initial signal line Vinit2 and the third initial signal line Vinit3 may also be located in other conductive layers. It should be noted that the technical features in the display panel shown in FIG. 64 can also be applied to other embodiments.

[0283] Figure 65 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Compared to the display panel shown in Figure 64, in the display panel shown in Figure 65, the orthographic projection of the third initial signal line Vinit3 on the substrate and the orthographic projection of the second eleventh active part 721 on the substrate at least partially overlap. The third initial signal line Vinit3 can regulate the voltage of the second eleventh active part 721 to improve the problem of leakage current from the second eleventh active part 721 to the source and drain of the eighth transistor. The orthographic projection of the second initial signal line Vinit2 on the substrate protrudes downward so that the orthographic projection of the second initial signal line Vinit2 on the substrate and the orthographic projection of the first initial signal line Vinit1 in the adjacent next row pixel driving circuit at least partially overlap. This arrangement can improve the light transmittance of the display panel. In addition, the orthographic projection of the second initial signal line Vinit2 on the substrate can also at least partially overlap with the orthographic projection of the first data fan-out line FIPH on the substrate. It should be noted that the technical features in the display panel shown in Figure 65 can also be applied to other embodiments.

[0284] Figure 66 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. The display panel may further include a shielding layer located between the substrate and the first active layer, and the shielding layer may be a conductive layer. Compared to the display panel shown in Figure 64, in the display panel shown in Figure 66, the second initial signal line Vinit2 may be located in the shielding layer. The second initial signal line Vinit2 can be connected to the first electrode of the seventh transistor through the thirteenth bridge portion 313 located in the third gate layer or the first active layer, that is, the thirteenth bridge portion 313 is connected to the fourteenth active portion 714 and the second initial signal line Vinit2 respectively through vias. In this exemplary embodiment, the orthographic projection of the second initial signal line Vinit2 on the substrate and the orthographic projection of the third initial signal line Vinit3 on the substrate at least partially overlap or do not overlap completely. As shown in Figure 66, the third initial signal line Vinit3 may be located in the first source / drain layer, which can further increase the distance between the third initial signal line Vinit3 and the second initial signal line Vinit2 in the display panel film layer stacking direction. It should be noted that the technical features in the display panel shown in Figure 66 can also be applied to other embodiments.

[0285] Figure 67 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Compared to the display panel shown in Figure 66, in the display panel shown in Figure 67, the third initial signal line can also be located in the third gate layer.

[0286] It should be understood that in other exemplary embodiments, the third initial signal line Vinit3 may be located in a shielding layer, and the second initial signal line Vinit2 may be located in any one or more of the third gate layer and the first source / drain layer. Furthermore, the third initial signal line Vinit3 may also be located in any one or more of the third gate layer and the first source / drain layer. It should be noted that the technical features in the display panel shown in FIG. 67 can also be applied to other embodiments.

[0287] As shown in Figures 68 and 69, Figure 68 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 69 is a structural layout diagram of the shielding layer in the display panel shown in Figure 68. Compared with the display panel shown in Figure 2, the display panel shown in Figure 69 includes a shielding layer located between the substrate and the first active layer. Since the driving transistor T3 adopts a top-gate design, its channel region is easily affected by ions diffused from the PI substrate or other film layers, thereby affecting the performance of the driving transistor. In this exemplary embodiment, the shielding layer may include a first shielding portion 81, the orthographic projection of the first shielding portion 81 on the substrate covers the orthographic projection of the third active portion 73 on the substrate, and the first shielding portion 81 can block the influence of ions on the performance of the driving transistor. As shown in Figure 69, the shielding layer may include a plurality of arrayed first shielding portions 81, adjacent first shielding portions 81 in the first direction X are connected by a connecting portion 82, and adjacent first shielding portions 81 in the second direction Y are also connected by a connecting portion, thereby forming a grid structure in the shielding layer. When the constant voltage signal lines such as the first initial signal line, the second initial signal line, and the third initial signal line are located in the shielding layer, the first shielding portion 81 distributed in the second direction can also be disconnected to avoid signal short circuits. The first shielding portion 81 can connect to the first power line 5VDD, the first initial signal line, the second initial signal line, the third initial signal line, and the second power line providing the second power terminal VSS, etc., which are constant voltage signal lines. It should be noted that the technical features in the display panel shown in Figure 68 can also be applied to other embodiments.

[0288] As shown in Figures 70 and 71, Figure 70 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 71 is a structural layout diagram of the first active layer to the first source / drain layer in the display panel shown in Figure 70.

[0289] As shown in Figures 70 and 71, the display panel may further include an electrode layer located on the side of the second source / drain layer facing away from the substrate. The electrode layer includes multiple electrode portions for forming the first electrode of a light-emitting unit. The multiple electrode portions include: a first electrode portion R, a second electrode portion B, and a third electrode portion G. The first electrode portion R forms the first electrode of a red light-emitting unit, the second electrode portion B forms the first electrode of a blue light-emitting unit, and the third electrode portion G forms the first electrode of a green light-emitting unit. The electrode portions are connected to a seventh bridge portion 57 via vias. In the multiple electrode portions connected to the same row of pixel driving circuits, the first electrode portion R, the third electrode portion G, the second electrode portion B, and the third electrode portion G are alternately distributed in the row direction. In two adjacent columns of pixel driving circuits, multiple first electrode portions R and multiple second electrode portions B are connected to the same column of pixel driving circuits, and the first electrode portions R and second electrode portions B connected to the same column of pixel driving circuits are alternately distributed in the column direction, while multiple third electrode portions G are connected to another column of pixel driving circuits.

[0290] It should be noted that the electrode layer structure of the display panel shown in Figure 70 can be applied to other embodiments.

[0291] In this exemplary embodiment, as shown in Figures 70 and 71, the first initial signal line, second initial signal line, third initial signal line, and first power line can be designed with different voltages for different colors. For example, the green light-emitting unit can be connected to a separate second initial signal line. In this exemplary embodiment, the green light-emitting unit has a higher turn-on voltage than the red and blue light-emitting units. When resetting the green light-emitting unit via the second initial signal line, the voltage on the second initial signal line connected to the green light-emitting unit can be greater than the voltage on the second initial signal lines connected to the red and blue light-emitting units. This setting can reduce the power consumption of the display panel. It should be understood that in other exemplary embodiments, the turn-on voltage of other color light-emitting units can also be higher. For example, the turn-on voltage of the red light-emitting unit is higher than that of the green and blue light-emitting units, and correspondingly, the voltage on the second initial signal line connected to the red light-emitting unit can be greater than the voltage on the second initial signal lines connected to the green and blue light-emitting units.

[0292] In this exemplary embodiment, as shown in Figures 70 and 71, the first source / drain layer is provided with an auxiliary second initial signal line Vinit2f. The second initial signal line Vinit2f can provide initial signals to the red and blue light-emitting units connected to the pixel driving circuit in the same row, and the auxiliary second initial signal line Vinit2f can provide initial signals to the green light-emitting unit alone.

[0293] In this exemplary embodiment, as shown in Figures 70 and 71, the second initial signal line Vinit2 is located in the second gate layer. It should be understood that in other exemplary embodiments, the second initial signal line Vinit2 and the auxiliary second initial signal line Vinit2f may also be located in other different conductive layers. For example, the second initial signal line Vinit2 may be located in any one or more of the shielding layer, the second gate layer, the third gate layer, and the first source / drain layer, and the auxiliary second initial signal line Vinit2f may be located in any one or more of the shielding layer, the second gate layer, the third gate layer, and the first source / drain layer.

[0294] In this exemplary embodiment, in the display panel shown in FIG2-71, the initial signal lines such as the first initial signal line, the second initial signal line, and the third initial signal line can also be located in other conductive layers. For example, the first initial signal line, the second initial signal line, and the third initial signal line can also be any one of the second gate layer, the third gate layer, and the first source / drain layer. For example, the second initial signal line Vinit2 in FIG14 can be located in the third gate layer, and the third initial signal line Vinit3 in FIG14 can be located in the first source / drain layer. The initial signal lines located in the third gate layer or the first source / drain layer can be directly connected to the corresponding structure through vias or connected to the corresponding structure through adapters.

[0295] In this exemplary embodiment, the technical features of the various display panel embodiments shown in FIG2-71 can be combined with each other to form a new display panel. For example, the structure of the second source / drain layer of the display panel shown in FIG39 can be applied to any of the display panels in FIG2-71; the structure of the second source / drain layer of the display panel shown in FIG40 can be applied to any of the display panels in FIG2-71; the structure of the second source / drain layer of the display panel shown in FIG41 can be applied to any of the display panels in FIG2-71; the structure of the first protrusion and the second protrusion in the display panel shown in FIG35 can be applied to any of the display panels in FIG2-71; and the structure of the display panel shown in FIG38 that shields the second data fan-out line and the enable signal connection line through the second initial signal line can be applied to any of the display panels in FIG2-71.

[0296] It should be noted that, as shown in Figure 2-71, the black squares drawn on the side of the third gate layer away from the substrate represent vias connecting the third gate layer to other layers facing the substrate; the black circles drawn on the side of the first source / drain layer away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black rectangles drawn on the side of the second source / drain layer away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer away from the substrate represent vias connecting the electrode layer to other layers facing the substrate.

[0297] It should be noted that the scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of subpixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only schematic diagrams of the structure. Furthermore, the qualifiers such as "first" and "second" are only used to specify different structural names and do not have a specific order meaning. In this disclosure, the same structural layer can be formed in a single patterning process.

[0298] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0299] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0300] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes multiple pixel driving circuits, each including a driving transistor, a fifth transistor, and an eighth transistor. The first terminal of the fifth transistor is connected to a first power supply line, and the second terminal of the fifth transistor is connected to the first terminal of the driving transistor. The first terminal of the eighth transistor is connected to a third initial signal line, and the second terminal of the eighth transistor is connected to the first terminal of the driving transistor. The display panel also includes: Substrate; A first active layer is located on one side of the substrate. The first active layer includes a third active portion, a fifth active portion, an eighth active portion, a ninth active portion, and a tenth active portion. The third active portion is used to form the channel region of the driving transistor, the fifth active portion is used to form the channel region of the fifth transistor, and the eighth active portion is used to form the channel region of the eighth transistor. The ninth active part is connected between the fifth active part and the eighth active part, and the tenth active part is connected between the ninth active part and the third active part.

2. The display panel according to claim 1, wherein, The plurality of pixel driving circuits form a plurality of pixel driving circuit groups, and the plurality of pixel driving circuit groups are arrayed along a first direction and a second direction, wherein the pixel driving circuit group includes two pixel driving circuits that are adjacent in the first direction. In the same pixel driving circuit group, the orthographic projections of the structures of the two pixel driving circuits located on the first active layer on the substrate are at least partially mirror-symmetrical with respect to the axis of symmetry extending along the second direction.

3. The display panel according to claim 2, wherein, The first active layer further includes: The eleventh active part is connected to the end of the fifth active part away from the eighth active part, and the eleventh active part is connected between the two fifth active parts in the same pixel driving circuit group.

4. The display panel according to claim 2, wherein, The first active layer further includes: The twelfth active part is connected to the end of the eighth active part away from the fifth active part, and the twelfth active part is connected between the two eighth active parts in the same pixel driving circuit group.

5. The display panel according to claim 2, wherein, The first active layer further includes: The twelfth active part is connected to the end of the eighth active part away from the fifth active part. In the same pixel driving circuit group, the orthographic projection of the twelfth active part on the substrate is at least partially located on the side of the orthographic projection of the eighth active part connected to it on the substrate away from the orthographic projection of the other eighth active part on the substrate. The eighth transistor includes two channel regions spaced apart, and a portion of the structure of the twelfth active part is used to form another channel region of the eighth transistor.

6. The display panel according to claim 2, wherein, The two fifth active units in the same pixel driving circuit group are located between the two tenth active units.

7. The display panel according to claim 2, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit further includes a sixth transistor, the first electrode of the sixth transistor being connected to the second electrode of the driving transistor, and the second electrode being connected to the first electrode of the light-emitting unit; The first active layer further includes a sixth active portion, the sixth active portion being used to form the channel region of the sixth transistor, and the display panel further includes: An enable signal line, comprising a first enable signal line segment and a second enable signal line segment, wherein the first enable signal line segment and the second enable signal line segment in the same enable signal line have their orthogonal projections on the substrate extending along the first direction and are spaced apart along the first direction. Wherein, the orthographic projection of the first enable signal line segment on the substrate covers the orthographic projection of the two fifth active parts in the same pixel driving circuit group on the substrate, and a portion of the structure of the first enable signal line segment is used to form the gate of the fifth transistor. The orthographic projection of the second enable signal segment on the substrate covers the orthographic projection of the sixth active part on the substrate, and a portion of the structure of the second enable signal segment is used to form the gate of the sixth transistor.

8. The display panel according to claim 1, wherein, The display panel also includes: The second source / drain layer includes multiple first power lines and multiple second data fan-out lines. The orthographic projections of the multiple first power lines on the substrate extend along a second direction and are spaced apart along a first direction. The orthographic projections of the multiple second data fan-out lines on the substrate extend along a second direction and are spaced apart along the first direction. The first direction and the second direction intersect. The first power lines are used to provide a high-level power signal to the pixel driving circuit. Multiple data lines, whose orthogonal projection on the substrate extends along the second direction, are used to provide data signals to the pixel driving circuit. Multiple first data fan-out lines, whose orthographic projection on the substrate extends along the first direction, wherein at least a portion of the multiple first data fan-out lines are used to connect the data line and the second data fan-out line; Wherein, the first power line includes a first extension section, and the first extension sections of some of the first power lines form a widened first extension section, and the first extension sections of at least some of the first power lines form a narrowed first extension section, wherein the size of the orthographic projection of the widened first extension section on the substrate in the first direction is greater than the size of the orthographic projection of the narrowed first extension section on the substrate in the first direction.

9. The display panel according to claim 8, wherein, The first power line further includes a second extension, the size of which is greater than ... Multiple first power lines form multiple first power line groups. Each first power line group includes two first power lines that are adjacent in the first direction. The two first power lines in the same first power line group are connected in the same layer through the second extension section. In the two first power lines connected on the same layer, the first extension segment of one first power line forms a widened first extension segment, and the first extension segment of the other first power line forms a narrowed first extension segment. The widened first extension segment is connected to the pixel driving circuit through a via.

10. The display panel according to claim 9, wherein, The plurality of pixel driving circuits form a plurality of pixel driving circuit groups, and the plurality of pixel driving circuit groups are arrayed along a first direction and a second direction, wherein the pixel driving circuit group includes two pixel driving circuits that are adjacent in the first direction. In two adjacent pixel driving circuits located in a first direction, the two first power lines form the first power line group.

11. The display panel according to claim 9, wherein, The display panel also includes: A first source / drain layer is located between the substrate and the second source / drain layer. The first source / drain layer includes a plurality of first power connection lines. The orthographic projection of the plurality of first power connection lines on the substrate extends along the first direction and is spaced apart along the second direction. The first power connection lines are connected to the pixel driving circuit through vias, and the first power lines are connected to the first power connection lines intersecting with them through the widened first extension via.

12. The display panel according to claim 9, wherein, The display panel further includes a light-emitting unit, and the second source / drain layer further includes: The seventh bridging part is connected to the pixel driving circuit and the first electrode of the light-emitting unit through vias; In two adjacent pixel driving circuits located in adjacent pixel driving circuit groups in a first direction, the orthographic projections of the two seventh bridging portions on the substrate are located between the orthographic projections of the two first extensions on the substrate.

13. The display panel according to claim 9, wherein, The orthographic projections of the narrowed first extension segment, the widened first extension segment, the widened first extension segment, and the narrowed first extension segment on the substrate are alternately and repeatedly distributed along the first direction.

14. The display panel according to claim 8, wherein, The data line is located in the second source / drain layer. In the same pixel driving circuit, the data line and the first power line are located on the side of the second data fan-out line on the substrate away from the first power line on the substrate.

15. The display panel according to claim 1, wherein, The pixel driving circuit further includes a second transistor, wherein a first terminal of the second transistor is connected to the gate of the driving transistor, and a second terminal is connected to the second terminal of the driving transistor. The display panel further includes: A third gate layer is located on one side of the substrate. The third gate layer includes a second bridging portion, which is connected to the gate of the driving transistor through a via. The first source / drain layer is located on the side of the third gate layer opposite to the substrate. The first source / drain layer includes a third bridging portion, which is connected to the second bridging portion and the first electrode of the second transistor through vias.

16. The display panel according to claim 11, wherein, The first power connection line includes a third extension and a fourth extension, wherein the size of the orthographic projection of the third extension on the substrate in the second direction is greater than the size of the orthographic projection of the fourth extension on the substrate in the second direction. The display panel further includes a light-emitting unit, and the pixel driving circuit further includes a seventh transistor, the first electrode of the seventh transistor being connected to a second initial signal line, and the second electrode being connected to the first electrode of the light-emitting unit; The second initial signal line is located in the first source / drain layer. The orthographic projection of the second initial signal line on the substrate extends along the first direction. A groove is formed on the side of the second initial signal line on the substrate facing the orthographic projection of the first power connection line on the substrate. The groove and the orthographic projection of the third extension on the substrate are arranged opposite to each other in the second direction. The pixel driving circuit further includes a second transistor, the first terminal of which is connected to the gate of the driving transistor, and the second terminal of which is connected to the second terminal of the driving transistor. The first source-drain layer includes a third bridging portion, which is connected to the gate of the driving transistor and the first terminal of the second transistor through vias.

17. The display panel according to claim 2, wherein, The pixel driving circuit further includes a second transistor, wherein a first terminal of the second transistor is connected to the gate of the driving transistor, and a second terminal is connected to the second terminal of the driving transistor. The display panel further includes: A third gate layer is located on one side of the substrate. A portion of the structure of the third gate layer is used to form the top gate of the second transistor. The third gate layer also includes the third initial signal line. The first active layer further includes a twelfth active portion, which is connected between the two eighth active portions in the same pixel driving circuit group; The third initial signal line is connected to the first terminal of the eighth transistor through one or more vias.

18. The display panel according to claim 1, wherein, The pixel driving circuit further includes a second transistor, wherein a first terminal of the second transistor is connected to the gate of the driving transistor, and a second terminal is connected to the second terminal of the driving transistor. The display panel further includes: A third gate layer is located on one side of the substrate. A portion of the structure of the third gate layer is used to form the top gate of the second transistor. The third gate layer also includes the third initial signal line. The first source / drain layer is located on the side of the third gate layer opposite to the substrate. The first source / drain layer includes a fourth bridging portion, which is connected to the third initial signal line and the first electrode of the eighth transistor through vias.

19. The display panel according to claim 17, wherein, The pixel driving circuit further includes a second transistor, wherein a first terminal of the second transistor is connected to the gate of the driving transistor, and a second terminal is connected to the second terminal of the driving transistor. The display panel further includes: A first source / drain layer is located on the side of the third gate layer opposite to the substrate. The first source / drain layer includes a fourth bridging portion, which is connected to the third initial signal line through one or more vias.

20. The display panel according to claim 2, wherein, The pixel driving circuit further includes a first transistor and a second transistor. The first terminal of the first transistor is connected to a first initial signal line, the second terminal of the first transistor is connected to the gate of the driving transistor, the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor. The display panel also includes: A first reset signal line extends along the first direction in the orthogonal projection on the substrate, and a portion of the structure of the first reset signal line is used to form the top gate of the first transistor; A first gate line extends along the first direction in its orthogonal projection on the substrate, and a portion of the structure of the first gate line is used to form the top gate of the second transistor. A data line, whose orthogonal projection on the substrate extends along the second direction, is used to provide data signals to the pixel driving circuit. In the two data lines corresponding to the same pixel driving circuit group, a first recessed area is formed on the side of the orthogonal projection of one data line on the substrate facing the orthogonal projection of the other data line on the substrate, and the first recessed area is at least partially located between the orthogonal projection of the first reset signal line on the substrate and the orthogonal projection of the first gate line on the substrate.

21. The display panel according to claim 1, wherein, The pixel driving circuit further includes a first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line and the second terminal is connected to the gate of the driving transistor; The display panel also includes: A second gate layer is located on one side of the substrate. The second gate layer includes the first initial signal line, and the orthographic projection of the first initial signal line on the substrate extends along a first direction. A third gate layer is located on the side of the second gate layer away from the substrate. The third gate layer includes a first initial bridging segment. The orthographic projection of the first initial bridging segment on the substrate extends along a first direction. The first initial bridging segment is connected to the first initial signal line through a plurality of vias.

22. The display panel according to claim 21, wherein, The display panel also includes: The first source / drain layer is located on the side of the third gate layer away from the substrate. The first source / drain layer includes multiple first data fan-out lines. The orthographic projection of the multiple first data fan-out lines on the substrate extends along a first direction and is spaced apart along a second direction. The second direction intersects the first direction. The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes multiple data lines and multiple second data fan-out lines. The orthographic projections of the multiple data lines on the substrate extend along a second direction and are spaced apart along the first direction. The orthographic projections of the multiple second data fan-out lines on the substrate extend along a second direction and are spaced apart along the first direction. The data line is used to provide data signals to the pixel driving circuit, and at least a portion of the first data fan-out lines are used to connect the data line and the second data fan-out line. The first data fan-out line includes a first via connection portion. The first data fan-out line is connected to the second data fan-out line via through the first via connection portion. The orthographic projection of the via between the first initial bridging segment and the first initial signal line on the substrate and the orthographic projection of the first via connection portion on the substrate at least partially overlap.

23. The display panel according to claim 1, wherein, The pixel driving circuit further includes a fourth transistor, the first terminal of which is connected to a data line, and the second terminal of which is connected to the first terminal of the driving transistor. The display panel further includes: A first gate layer is located on one side of the substrate. The first gate layer includes a second gate line. The orthographic projection of the second gate line on the substrate extends along a first direction. A portion of the structure of the second gate line is used to form the gate of the fourth transistor. The first source / drain layer is located on the side of the first gate layer opposite to the substrate. The first source / drain layer includes a first power connection line. The orthographic projection of the first power connection line on the substrate extends along the first direction. The first power connection line is used to provide a high-level power signal to the pixel driving circuit. The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes multiple second data fan-out lines. The orthographic projection of the multiple second data fan-out lines on the substrate extends along a second direction and is distributed along a first direction. The first direction and the second direction intersect. A data line, whose orthogonal projection on the substrate extends along the second direction, is used to provide data signals to the pixel driving circuit, and at least a portion of the second data fan-out lines are connected to the data line. The first power connection line includes a main body and a first protrusion. The orthographic projection of the main body on the substrate extends along the first direction, and the orthographic projection of the first protrusion on the substrate is located on the side where the orthographic projection of the main body on the substrate is in the second direction. The overlapping area of ​​the orthographic projection of the second data fan-out line on the substrate and the orthographic projection of the second gate line on the substrate at least partially overlaps with the orthographic projection of the first protrusion on the substrate.

24. The display panel according to claim 1, wherein, The gate of the fifth transistor is connected to an enable signal connection line, the orthographic projection of the enable signal connection line on the substrate extends along a first direction, and the display panel further includes: A first source / drain layer is located on the side of the first active layer opposite to the substrate. The first source / drain layer includes a first power connection line. The orthographic projection of the first power connection line on the substrate extends along the first direction. The first power connection line is used to provide a high-level power signal to the pixel driving circuit. The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes multiple second data fan-out lines. The orthographic projection of the multiple second data fan-out lines on the substrate extends along a second direction and is distributed along a first direction. The first direction and the second direction intersect. A data line, whose orthogonal projection on the substrate extends along the second direction, is used to provide data signals to the pixel driving circuit, and at least a portion of the second data fan-out lines are connected to the data line. The first power connection line includes a main body and a second protrusion. The orthographic projection of the main body on the substrate extends along the first direction, and the orthographic projection of the second protrusion on the substrate is located on the side where the orthographic projection of the main body on the substrate is in the second direction. The overlapping area of ​​the orthographic projection of the second data fan-out line on the substrate and the orthographic projection of the enable signal connection line on the substrate at least partially overlaps with the orthographic projection of the second protrusion on the substrate.

25. The display panel according to claim 1, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit further includes a seventh transistor. The first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit. The gate of the fifth transistor is connected to an enable signal connection line, and the orthographic projection of the enable signal connection line on the substrate extends along a first direction. The display panel also includes: A first source / drain layer is located on the side of the first active layer away from the substrate, and the first source / drain layer includes the second initial signal line; The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes multiple second data fan-out lines. The orthographic projection of the multiple second data fan-out lines on the substrate extends along a second direction and is distributed along a first direction. The first direction and the second direction intersect. A data line, whose orthogonal projection on the substrate extends along the second direction, is used to provide data signals to the pixel driving circuit, and at least a portion of the second data fan-out lines are connected to the data line. The overlapping area of ​​the orthographic projection of the second data fan-out line on the substrate and the orthographic projection of the enable signal connection line on the substrate at least partially overlaps with the orthographic projection of the second initial signal line on the substrate.

26. The display panel according to claim 1, wherein, The display panel also includes: A constant voltage signal line is used to provide a constant voltage signal to the pixel driving circuit, and the orthogonal projection of the constant voltage signal line on the substrate extends along a first direction. A constant voltage connection line extends along a second direction on the substrate, the second direction intersecting the first direction, and the constant voltage connection line is connected to the constant voltage signal line intersecting it through a via.

27. The display panel according to claim 26, wherein, The display panel also includes: The second source / drain layer is located on the side of the first active layer away from the substrate. The second source / drain layer includes a data line, a first power line, and a constant voltage connection line. The orthographic projection of the data line and the first power line on the substrate extends along the second direction. The data line is used to provide data signals to the pixel driving circuit, and the first power line is used to provide high-level power signals to the pixel driving circuit. In the same pixel driving circuit, the orthographic projection of the constant voltage connection line on the substrate is located on the side where the orthographic projection of the data line on the substrate is far from the orthographic projection of the first power line on the substrate.

28. The display panel according to claim 26, wherein, The display panel also includes: The second source / drain layer is located on the side of the first active layer away from the substrate. The second source / drain layer includes a data line, a first power line, and a constant voltage connection line. The orthographic projection of the data line and the first power line on the substrate extends along the second direction. The data line is used to provide data signals to the pixel driving circuit, and the first power line is used to provide high-level power signals to the pixel driving circuit. In the same pixel driving circuit, the orthographic projection of the constant voltage connection line on the substrate is located on the side where the orthographic projection of the first power line on the substrate is far from the orthographic projection of the data line on the substrate.

29. The display panel according to claim 26, wherein, The display panel also includes: A data line, the data line being used to provide data signals to the pixel driving circuit, the data line extending along the second direction in its orthogonal projection on the substrate. Multiple second data fan-out lines, the orthographic projection of the second data fan-out lines on the substrate extends along a second direction, and a portion of the multiple second data fan-out lines are used to connect the data lines; Among them, some of the second data fan-out lines are reused as the constant voltage connection lines.

30. The display panel according to claim 1, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit further includes: a first transistor, a second transistor, a fourth transistor, a sixth transistor, a seventh transistor, and a capacitor; The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor; The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor; The first terminal of the fourth transistor is connected to the data line, and the second terminal of the fourth transistor is connected to the first terminal of the driving transistor; The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit; The first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit; The first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the first power supply line. Among them, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the first transistor and the second transistor are N-type transistors.

31. The display panel according to claim 1, wherein, The pixel driving circuit includes P-type transistors and N-type transistors, and the display panel further includes: A first active layer is located on one side of the substrate, and a portion of the structure of the first active layer is used to form the channel region of the P-type transistor in the pixel driving circuit. A first gate layer is located on the side of the first active layer away from the substrate, and a portion of the structure of the first gate layer is used to form the gate of the P-type transistor in the pixel driving circuit. The second gate layer is located on the side of the first gate layer away from the substrate, and a portion of the structure of the second gate layer is used to form the bottom gate of at least a portion of the N-type transistors in the pixel driving circuit. The second active layer is located on the side of the second gate layer away from the substrate, and a portion of the structure of the second active layer is used to form the channel region of the N-type transistor in the pixel driving circuit. A third gate layer is located on the side of the second active layer away from the substrate, and a portion of the structure of the third gate layer is used to form the top gate of at least a portion of the N-type transistors in the pixel driving circuit. The first source / drain layer is located on the side of the third gate layer opposite to the substrate, and a portion of the structure of the first source / drain layer is used to form a bridging portion connecting different transistors.

32. A display device, wherein, Includes the display panel as described in any one of claims 1-31.

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