Display substrate, driving method, and display apparatus

Abstract

The present disclosure provides a display substrate, a driving method, and a display apparatus. The display substrate comprises: a base substrate and a driver circuit provided on the base substrate; the driver circuit comprises a scan signal generation circuit and a reset circuit; the scan signal generation circuit is configured for providing at least one scan signal; the reset circuit is electrically connected to a reset control terminal and the scan signal generation circuit, respectively, and is configured for controlling, under the control of the reset control terminal, the scan signal generation circuit to output an inactive scan signal. The present disclosure can reduce power consumption.

Description

Display substrate, driving method and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, driving method, and display device. Background Technology

[0002] To reduce power consumption when driving static images, low-frequency driving methods are commonly used in related technologies. However, a more common scenario is that only a local area of ​​the image requires a higher refresh rate, such as when the upper half of the screen plays video and the lower half displays text. In this case, only the upper half of the screen needs a higher refresh rate, while the lower half uses a lower refresh rate, thereby reducing power consumption. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a display substrate, including: a substrate and a driving circuit disposed on the substrate;

[0004] The driving circuit includes a scan signal generation circuit and a reset circuit;

[0005] The scan signal generation circuit is used to provide at least one scan signal;

[0006] The reset circuit is electrically connected to both the reset control terminal and the scan signal generation circuit, and is used to control the scan signal generation circuit to output an invalid scan signal under the control of the reset control terminal.

[0007] Optionally, the display substrate further includes a pixel circuit disposed on the substrate; the scan signal generation circuit is electrically connected to the control clock signal terminal and is used to provide a scan signal under the control of the control clock signal provided by the control clock signal terminal;

[0008] The display substrate includes a display area and a peripheral area; the driving circuit is disposed in the peripheral area; the pixel circuit is disposed in the display area;

[0009] When the display substrate is in the first display state, the display area includes multiple areas along the scanning direction. When the last area of ​​the display area is displayed, the pixel circuits in the last area do not perform display refresh during at least one hold frame. The display refresh frequencies of two adjacent areas are different.

[0010] The reset circuit is used to control the scan signal generation circuit to output an invalid scan signal when the display substrate is in the first display state, after the pixel circuit in the region adjacent to the last region in the at least one holding frame has completed the display refresh.

[0011] Optionally, the display substrate further includes a clock control circuit disposed on the substrate;

[0012] The clock control circuit is used to reduce the frequency of the control clock signal after the pixel circuit in the region adjacent to the last region completes the display refresh in the holding frame.

[0013] Optionally, the driving circuit further includes a startup circuit; the scanning signal generation circuit includes a first output control node;

[0014] The startup circuit is electrically connected to the input control clock signal terminal, and is used to connect or disconnect the control signal input terminal and the first output control node under the control of the input control clock signal provided by the input control clock signal terminal.

[0015] The startup circuit is electrically connected to the signal input terminal, and the startup circuit is electrically connected to the first output control node through the reset circuit; or...

[0016] The reset circuit is electrically connected to the signal input terminal, and the reset circuit is electrically connected to the first output control node through the startup circuit.

[0017] Optionally, the driving circuit further includes a startup circuit; the scanning signal generation circuit includes a first output control node; the reset circuit includes a first reset sub-circuit and a second reset sub-circuit; the reset control terminal includes a reset signal terminal and / or a reset input node;

[0018] The startup circuit is electrically connected to the input control clock signal terminal, the signal input terminal, and the reset input node, respectively, and is used to control the connection or disconnection between the signal input terminal and the reset input node under the control of the input control clock signal provided by the input control clock signal terminal;

[0019] The first reset sub-circuit is electrically connected to the reset voltage terminal and the first output control node, respectively. The first reset sub-circuit is also electrically connected to the reset signal terminal or the reset input node, and is used to write the reset voltage provided by the reset voltage terminal into the first output control node under the control of the reset signal or the potential of the reset input node.

[0020] The second reset sub-circuit is electrically connected to the reset signal terminal, the reset input node, and the first output control node, respectively, and is used to control the connection or disconnection between the reset input node and the first output control node under the control of the reset signal.

[0021] Optionally, the driving circuit further includes a startup circuit; the scanning signal generation circuit includes a first output control node; the reset circuit includes a first reset sub-circuit and a second reset sub-circuit; the reset control terminal includes a reset signal terminal and / or a signal input terminal.

[0022] The first reset sub-circuit is electrically connected to the reset output node and the reset voltage terminal respectively. The first reset sub-circuit is also electrically connected to the reset signal terminal or the signal input terminal, and is used to write the reset voltage provided by the reset voltage terminal into the reset output node under the control of the reset signal or the input signal provided by the signal input terminal.

[0023] The second reset sub-circuit is electrically connected to the signal input terminal, the reset signal terminal, and the reset output node, respectively, and is used to control the connection or disconnection between the signal input terminal and the reset output node under the control of the reset signal;

[0024] The startup circuit is electrically connected to the input control clock signal terminal, the reset output node, and the first output control node, respectively, and is used to control the connection or disconnection between the reset output node and the first output control node under the control of the input control clock signal provided by the input control clock signal terminal.

[0025] Optionally, the scanning signal generation circuit includes a first on / off control circuit and a second output circuit;

[0026] The first on / off control circuit is electrically connected to the second voltage signal terminal, the first output control node, and the second output node, respectively, and is used to control the connection or disconnection between the first output control node and the second output node under the control of the second voltage signal provided by the second voltage signal terminal.

[0027] The second output circuit is electrically connected to the second output node, the first scan signal output terminal, and the second voltage signal terminal, respectively, and is used to control the connection or disconnection between the first scan signal output terminal and the second voltage signal terminal under the control of the potential of the second output node.

[0028] Optionally, the driving circuit further includes a control signal generation circuit and a control circuit; the scanning signal includes a first scanning signal and a second scanning signal;

[0029] The scanning signal generation circuit is electrically connected to the first scanning signal output terminal and the second scanning signal output terminal respectively, and is used to provide a first scanning signal through the first scanning signal output terminal and a second scanning signal through the second scanning signal output terminal.

[0030] The control signal generation circuit is electrically connected to the enable signal terminal and the first control node, respectively. The control signal generation circuit is also electrically connected to the first scan signal output terminal, the second scan signal output terminal, the first control terminal, and the second control terminal, respectively. It is used to control the connection or disconnection between the enable signal terminal and the first control node under the control of the first scan signal, the second scan signal, the first control signal provided by the first control terminal, and the second control signal provided by the second control terminal. The first control terminal is electrically connected to the output terminal of the first scan signal of the adjacent i-th stage, and the second control terminal is electrically connected to the output terminal of the second scan signal of the adjacent i-th stage; i is a positive integer.

[0031] The control circuit is connected to the first control node, the drive control terminal, and the drive signal output terminal respectively, and is used to provide a drive signal to the drive signal output terminal under the control of the potential of the first control node and the drive control signal provided by the drive control terminal.

[0032] The drive control terminal is either the first scan signal output terminal or the second scan signal output terminal.

[0033] Optionally, the control circuit includes a first control sub-circuit, a second control sub-circuit, and a first inverting circuit;

[0034] The first control sub-circuit is electrically connected to the first control node, the second control node, the first voltage signal terminal, and the second voltage signal terminal, respectively, and is used to control the second control node to connect with the first voltage signal terminal or the second voltage signal terminal under the control of the potential of the first control node, and to control the first control node to connect with the first voltage signal terminal or the second voltage signal terminal under the control of the potential of the second control node.

[0035] The second control sub-circuit is electrically connected to the drive control terminal, the third control node, the first voltage signal terminal, and the second voltage signal terminal, respectively, and is used to control the third control node to connect with the first voltage signal terminal or the second voltage signal terminal under the control of the drive control signal;

[0036] The first inverting circuit is electrically connected to the third control node and the drive signal output terminal, respectively, and is used to invert the potential of the third control node to obtain the drive signal.

[0037] Optionally, when the display area is in a normal refresh state, the enable signal provided by the enable signal terminal is a valid enable signal;

[0038] When the display area is in the first display state, after the pixel circuit in the area adjacent to the last area completes the display refresh in the at least one holding frame, the enable signal is an invalid enable signal.

[0039] Optionally, the scanning signal generation circuit further includes a first node control circuit, a second on / off control circuit, a first output node control circuit, a second output node control circuit, a first output circuit, a first energy storage circuit, and a second inverting circuit; the control clock signal terminal includes a first control clock signal terminal, a second control clock signal terminal, and a third control clock signal terminal; the input control clock signal terminal is the first control clock signal terminal;

[0040] The first node control circuit is electrically connected to the first control clock signal terminal, the second voltage signal terminal, the first node, and the first output control node, respectively. It is used to write the second voltage signal provided by the second voltage signal terminal into the first node under the control of the first control clock signal provided by the first control clock signal terminal, and to write the first control clock signal into the first node under the control of the potential of the first output control node.

[0041] The second on / off control circuit is electrically connected to the second voltage signal terminal, the first node, and the second output control node, respectively, and is used to control the connection or disconnection between the first node and the second output control node under the control of the second voltage signal.

[0042] The first output node control circuit is electrically connected to the first output node, the second control clock signal terminal, the second output control node, the first output control node, and the first voltage signal terminal, respectively. It is used to control the potential of the first output node under the control of the potential of the second output control node and the second control clock signal provided by the second control clock signal terminal, and to write the first voltage signal provided by the first voltage signal terminal into the first output node under the control of the potential of the first output control node.

[0043] The second output node control circuit is electrically connected to the second output node, the first output node, the first voltage signal terminal, and the third control clock signal terminal, respectively, and is used to control the potential of the second output node under the control of the potential of the first output node and under the control of the third control clock signal provided by the third control clock signal terminal.

[0044] The first output circuit is electrically connected to the first output node, the first voltage signal terminal and the first scan signal output terminal respectively, and is used to write the first voltage signal to the first scan signal output terminal under the control of the potential of the first output node;

[0045] The first energy storage circuit is electrically connected to the first output node and is used to maintain the potential of the first output node;

[0046] The second inverting circuit is electrically connected to the first scan signal output terminal and the second scan signal output terminal respectively, and is used to invert the first scan signal to obtain and output the second scan signal through the second scan signal output terminal.

[0047] Optionally, the third control clock signal terminal and the first control clock signal terminal are the same control clock signal terminal.

[0048] Optionally, the scanning signal generation circuit further includes a first node control circuit, a second on / off control circuit, a first output node control circuit, a second output node control circuit, a first output circuit, a first energy storage circuit, and a second inverting circuit; the control clock signal terminal includes a first control clock signal terminal, a second control clock signal terminal, and a third control clock signal terminal; the input control clock signal terminal is the first control clock signal terminal;

[0049] The first node control circuit is electrically connected to the second control clock signal terminal, the second voltage signal terminal, the first node, and the first output control node, respectively. It is used to write the second voltage signal provided by the second voltage signal terminal into the first node under the control of the second control clock signal provided by the second control clock signal terminal, and to write the second control clock signal into the first node under the control of the potential of the first output control node.

[0050] The second on / off control circuit is electrically connected to the second voltage signal terminal, the first node, and the second output control node, respectively, and is used to control the connection or disconnection between the first node and the second output control node under the control of the second voltage signal.

[0051] The first output node control circuit is electrically connected to the first output node, the third control clock signal terminal, the second output control node, the first output control node, and the first voltage signal terminal, respectively. It is used to control the potential of the first output node under the control of the potential of the second output control node and the third control clock signal provided by the third control clock signal terminal, and to write the first voltage signal provided by the first voltage signal terminal into the first output node under the control of the potential of the first output control node.

[0052] The second output node control circuit is electrically connected to the second output node, the first output node, the first voltage signal terminal, and the first control clock signal terminal, respectively, and is used to control the potential of the second output node under the control of the potential of the first output node and under the control of the first control clock signal provided by the first control clock signal terminal;

[0053] The first output circuit is electrically connected to the first output node, the first voltage signal terminal and the first scan signal output terminal respectively, and is used to write the first voltage signal to the first scan signal output terminal under the control of the potential of the first output node;

[0054] The first energy storage circuit is electrically connected to the first output node and is used to maintain the potential of the first output node;

[0055] The second inverting circuit is electrically connected to the first scan signal output terminal and the second scan signal output terminal respectively, and is used to invert the first scan signal to obtain and output the second scan signal through the second scan signal output terminal.

[0056] Optionally, the first reset sub-circuit includes a first reset transistor, and the second reset sub-circuit includes a second reset transistor;

[0057] The control terminal of the first reset transistor is electrically connected to the reset signal terminal, the first terminal of the first reset transistor is electrically connected to the reset voltage terminal, and the second terminal of the first reset transistor is electrically connected to the first output control node.

[0058] The control terminal of the second reset transistor is electrically connected to the reset signal terminal, the first terminal of the second reset transistor is electrically connected to the reset input node, and the second terminal of the second reset transistor is electrically connected to the first output control node.

[0059] The first reset transistor is an n-type transistor, and the second reset transistor is a p-type transistor; or, the first reset transistor is a p-type transistor, and the second reset transistor is an n-type transistor.

[0060] The startup circuit includes an input transistor;

[0061] The control electrode of the input transistor is electrically connected to the input control clock signal terminal, the first electrode of the input transistor is electrically connected to the signal input terminal, and the second electrode of the input transistor is electrically connected to the reset input node.

[0062] Optionally, the first reset sub-circuit includes a first reset transistor, and the second reset sub-circuit includes a second reset transistor;

[0063] The control terminal of the first reset transistor is electrically connected to the reset input node, the first terminal of the first reset transistor is electrically connected to the reset voltage terminal, and the second terminal of the first reset transistor is electrically connected to the first output control node.

[0064] The control terminal of the second reset transistor is electrically connected to the reset signal terminal, the first terminal of the second reset transistor is electrically connected to the reset input node, and the second terminal of the second reset transistor is electrically connected to the first output control node.

[0065] The startup circuit includes an input transistor;

[0066] The control electrode of the input transistor is electrically connected to the input control clock signal terminal, the first electrode of the input transistor is electrically connected to the signal input terminal, and the second electrode of the input transistor is electrically connected to the reset input node.

[0067] Optionally, the first reset sub-circuit includes a first reset transistor and a second reset transistor;

[0068] The control terminal of the first reset transistor is electrically connected to the reset signal terminal, the first terminal of the first reset transistor is electrically connected to the reset voltage terminal, and the second terminal of the first reset transistor is electrically connected to the reset output node.

[0069] The control electrode of the second reset transistor is electrically connected to the reset signal terminal, the first electrode of the second reset transistor is electrically connected to the signal input terminal, and the second electrode of the second reset transistor is electrically connected to the reset output node.

[0070] The first reset transistor is an n-type transistor, and the second reset transistor is a p-type transistor; or, the first reset transistor is a p-type transistor, and the second reset transistor is an n-type transistor.

[0071] The startup circuit includes an input transistor;

[0072] The control terminal of the input transistor is electrically connected to the input control clock signal terminal, the first terminal of the input transistor is electrically connected to the reset output node, and the second terminal of the input transistor is electrically connected to the first output control node.

[0073] Optionally, the first reset sub-circuit includes a first reset transistor and a second reset transistor;

[0074] The control terminal of the first reset transistor is electrically connected to the signal input terminal, the first terminal of the first reset transistor is electrically connected to the reset voltage terminal, and the second terminal of the first reset transistor is electrically connected to the reset output node.

[0075] The control electrode of the second reset transistor is electrically connected to the reset signal terminal, the first electrode of the second reset transistor is electrically connected to the signal input terminal, and the second electrode of the second reset transistor is electrically connected to the reset output node.

[0076] The startup circuit includes an input transistor;

[0077] The control terminal of the input transistor is electrically connected to the input control clock signal terminal, the first terminal of the input transistor is electrically connected to the reset output node, and the second terminal of the input transistor is electrically connected to the first output control node.

[0078] The display substrate described in at least one embodiment of this disclosure includes a driving module; the driving module includes multiple cascaded driving circuits;

[0079] In at least one stage of the driving circuit, the signal input terminal is electrically connected to the start signal line, and the control signal generation circuit is electrically connected to the start signal line and the inverted start signal line respectively.

[0080] Optionally, the first scan signal output terminal of the nth stage driving circuit is electrically connected to the signal input terminal of the (n+1)th stage driving circuit;

[0081] The first scan signal output terminal of the nth stage driving circuit and the second scan signal output terminal of the nth stage driving circuit are electrically connected to the control signal generation circuit of the (n+1)th stage driving circuit, where n is a positive integer.

[0082] In the 2a-level drive circuit, the first control clock signal terminal is electrically connected to the first clock signal line, the second control clock signal terminal is electrically connected to the second clock signal line, and the third control clock signal terminal is electrically connected to the third clock signal line.

[0083] In the 2a+1 stage drive circuit, the first control clock signal terminal is electrically connected to the third clock signal line, the second control clock signal terminal is electrically connected to the fourth clock signal line, and the third control clock signal terminal is electrically connected to the first clock signal line.

[0084] 'a' is a natural number.

[0085] Optionally, the first scan signal output terminal of the nth stage driving circuit is electrically connected to the signal input terminal of the (n+1)th stage driving circuit;

[0086] The first scan signal output terminal of the nth stage driving circuit and the second scan signal output terminal of the nth stage driving circuit are electrically connected to the control signal generation circuit of the (n+1)th stage driving circuit, where n is a positive integer.

[0087] In the 4a-level driving circuit, the first control clock signal terminal is connected to the first clock signal line, and the second control clock signal terminal is connected to the second clock signal line; in the 4a+1-level driving circuit, the first control clock signal terminal is connected to the second clock signal line, and the second control clock signal terminal is connected to the third clock signal line; in the 4a+2-level driving circuit, the first control clock signal terminal is connected to the third clock signal line, and the second control clock signal terminal is connected to the fourth clock signal line; in the 4a+3-level driving circuit, the first control clock signal terminal is connected to the fourth clock signal line, and the second control clock signal terminal is connected to the first clock signal line; where 'a' is a natural number.

[0088] Optionally, the first scan signal output terminal of the nth stage driving circuit is electrically connected to the signal input terminal of the (n+1)th stage driving circuit;

[0089] The first scan signal output terminal of the nth stage driving circuit and the second scan signal output terminal of the nth stage driving circuit are electrically connected to the control signal generation circuit of the (n+1)th stage driving circuit, where n is a positive integer.

[0090] In the 4a-level driving circuit, the first control clock signal terminal is connected to the first clock signal line, the second control clock signal terminal is connected to the second clock signal line, and the third control clock signal terminal is connected to the third clock signal line; in the 4a+1-level driving circuit, the first control clock signal terminal is connected to the second clock signal line, the second control clock signal terminal is connected to the third clock signal line, and the third control clock signal terminal is connected to the fourth clock signal line; in the 4a+2-level driving circuit, the first control clock signal terminal is connected to the third clock signal line, the second control clock signal terminal is connected to the fourth clock signal line, and the third control clock signal terminal is connected to the first clock signal line; in the 4a+3-level driving circuit, the first control clock signal terminal is connected to the fourth clock signal line, the second control clock signal terminal is connected to the first clock signal line, and the third control clock signal terminal is connected to the second clock signal line; where 'a' is a natural number.

[0091] In a second aspect, embodiments of this disclosure provide a display substrate, including: a substrate and a driving circuit disposed on the substrate;

[0092] The driving circuit includes a scan signal generation circuit, which is used to provide at least one scan signal;

[0093] The driving circuit also includes a reset circuit, which is electrically connected to the reset control terminal and the scan signal generation circuit, respectively. During non-refreshing periods, under the control of the reset control terminal, the reset circuit controls the scan signal generation circuit to output an invalid scan signal.

[0094] Optionally, the display substrate further includes pixel circuitry disposed on the substrate;

[0095] The display substrate includes a display area and a peripheral area; the driving circuit is disposed in the peripheral area; the pixel circuit is disposed in the display area;

[0096] When the display substrate is in the first display state, the display area includes multiple areas along the scanning direction. When the last area of ​​the display area is displayed, the pixel circuits in the last area do not perform display refresh during at least one hold frame. The display refresh frequencies of two adjacent areas are different.

[0097] The display substrate further includes a clock control circuit disposed on the substrate; the scan signal generation circuit is electrically connected to the control clock signal terminal and is used to provide a scan signal under the control of the control clock signal provided by the control clock signal terminal;

[0098] The clock control circuit is used to control the reduction of the frequency of the control clock signal after the pixel circuit in the region adjacent to the last region completes the display refresh in the holding frame.

[0099] Optionally, the driving circuit further includes a startup circuit; the scanning signal generation circuit includes a first output control node;

[0100] The startup circuit is electrically connected to the input control clock signal terminal, and is used to connect or disconnect the control signal input terminal and the first output control node under the control of the input control clock signal provided by the input control clock signal terminal.

[0101] The startup circuit is electrically connected to the signal input terminal, and the startup circuit is electrically connected to the first output control node through the reset circuit; or...

[0102] The reset circuit is electrically connected to the signal input terminal, and the reset circuit is electrically connected to the first output control node through the startup circuit.

[0103] Optionally, the driving circuit further includes a startup circuit; the reset circuit includes a first reset sub-circuit and a second reset sub-circuit; the reset control terminal includes a reset signal terminal and / or a reset input node;

[0104] The startup circuit is electrically connected to the input control clock signal terminal, the signal input terminal, and the reset input node, respectively, and is used to control the connection or disconnection between the signal input terminal and the reset input node under the control of the input control clock signal provided by the input control clock signal terminal;

[0105] The first reset sub-circuit is electrically connected to the reset voltage terminal and the first output control node, respectively. The first reset sub-circuit is also electrically connected to the reset signal terminal or the reset input node, and is used to write the reset voltage provided by the reset voltage terminal into the first output control node under the control of the reset signal or the potential of the reset input node.

[0106] The second reset sub-circuit is electrically connected to the reset signal terminal, the reset input node, and the first output control node, respectively, and is used to control the connection or disconnection between the reset input node and the first output control node under the control of the reset signal.

[0107] Optionally, the driving circuit further includes a startup circuit; the reset circuit includes a first reset sub-circuit and a second reset sub-circuit; the reset control terminal includes a reset signal terminal and / or a signal input terminal.

[0108] The first reset sub-circuit is electrically connected to the reset output node and the reset voltage terminal respectively. The first reset sub-circuit is also electrically connected to the reset signal terminal or the signal input terminal, and is used to write the reset voltage provided by the reset voltage terminal into the reset output node under the control of the reset signal or the input signal provided by the signal input terminal.

[0109] The second reset sub-circuit is electrically connected to the signal input terminal, the reset signal terminal, and the reset output node, respectively, and is used to control the connection or disconnection between the signal input terminal and the reset output node under the control of the reset signal;

[0110] The startup circuit is electrically connected to the input control clock signal terminal, the reset output node, and the first output control node, respectively, and is used to control the connection or disconnection between the reset output node and the first output control node under the control of the input control clock signal provided by the input control clock signal terminal.

[0111] Optionally, the scanning signal generation circuit includes a first on / off control circuit and a second output circuit;

[0112] The first on / off control circuit is electrically connected to the second voltage signal terminal, the first output control node, and the second output node, respectively, and is used to control the connection or disconnection between the first output control node and the second output node under the control of the second voltage signal provided by the second voltage signal terminal.

[0113] The second output circuit is electrically connected to the second output node, the first scan signal output terminal, and the second voltage signal terminal, respectively, and is used to control the connection or disconnection between the first scan signal output terminal and the second voltage signal terminal under the control of the potential of the second output node.

[0114] Optionally, the driving circuit further includes a control signal generation circuit and a control circuit; the scanning signal includes a first scanning signal and a second scanning signal;

[0115] The scanning signal generation circuit is electrically connected to the first scanning signal output terminal and the second scanning signal output terminal respectively, and is used to provide a first scanning signal through the first scanning signal output terminal and a second scanning signal through the second scanning signal output terminal.

[0116] The control signal generation circuit is electrically connected to the enable signal terminal and the first control node, respectively. The control signal generation circuit is also electrically connected to the first scan signal output terminal, the second scan signal output terminal, the first control terminal, and the second control terminal, respectively. It is used to control the connection or disconnection between the enable signal terminal and the first control node under the control of the first scan signal, the second scan signal, the first control signal provided by the first control terminal, and the second control signal provided by the second control terminal. The first control terminal is electrically connected to the output terminal of the first scan signal of the adjacent i-th stage, and the second control terminal is electrically connected to the output terminal of the second scan signal of the adjacent i-th stage, where i is a positive integer.

[0117] The control circuit is connected to the first control node, the drive control terminal, and the drive signal output terminal respectively, and is used to provide a drive signal to the drive signal output terminal under the control of the potential of the first control node and the drive control signal provided by the drive control terminal.

[0118] The drive control terminal is either the first scan signal output terminal or the second scan signal output terminal.

[0119] Optionally, the control circuit includes a first control sub-circuit, a second control sub-circuit, and a first inverting circuit;

[0120] The first control sub-circuit is electrically connected to the first control node, the second control node, the first voltage signal terminal, and the second voltage signal terminal, respectively, and is used to control the second control node to connect with the first voltage signal terminal or the second voltage signal terminal under the control of the potential of the first control node, and to control the first control node to connect with the first voltage signal terminal or the second voltage signal terminal under the control of the potential of the second control node.

[0121] The second control sub-circuit is electrically connected to the drive control terminal, the third control node, the first voltage signal terminal, and the second voltage signal terminal, respectively, and is used to control the third control node to connect with the first voltage signal terminal or the second voltage signal terminal under the control of the drive control signal;

[0122] The first inverting circuit is electrically connected to the third control node and the drive signal output terminal, respectively, and is used to invert the potential of the third control node to obtain the drive signal.

[0123] Optionally, when the display area is in a normal refresh state, the enable signal provided by the enable signal terminal is a valid enable signal;

[0124] When the display area is in the first display state, after the pixel circuit in the area adjacent to the last area completes the display refresh in the at least one holding frame, the enable signal is an invalid enable signal.

[0125] Optionally, the scanning signal generation circuit further includes a first node control circuit, a second on / off control circuit, a first output node control circuit, a second output node control circuit, a first output circuit, a first energy storage circuit, and a second inverting circuit; the control clock signal terminal includes a first control clock signal terminal, a second control clock signal terminal, and a third control clock signal terminal; the input control clock signal terminal is the first control clock signal terminal;

[0126] The first node control circuit is electrically connected to the first control clock signal terminal, the second voltage signal terminal, the first node, and the first output control node, respectively. It is used to write the second voltage signal provided by the second voltage signal terminal into the first node under the control of the first control clock signal provided by the first control clock signal terminal, and to write the first control clock signal into the first node under the control of the potential of the first output control node.

[0127] The second on / off control circuit is electrically connected to the second voltage signal terminal, the first node, and the second output control node, respectively, and is used to control the connection or disconnection between the first node and the second output control node under the control of the second voltage signal.

[0128] The first output node control circuit is electrically connected to the first output node, the second control clock signal terminal, the second output control node, the first output control node, and the first voltage signal terminal, respectively. It is used to control the potential of the first output node under the control of the potential of the second output control node and the second control clock signal provided by the second control clock signal terminal, and to write the first voltage signal provided by the first voltage signal terminal into the first output node under the control of the potential of the first output control node.

[0129] The second output node control circuit is electrically connected to the second output node, the first output node, the first voltage signal terminal, and the third control clock signal terminal, respectively, and is used to control the potential of the second output node under the control of the potential of the first output node and under the control of the third control clock signal provided by the third control clock signal terminal.

[0130] The first output circuit is electrically connected to the first output node, the first voltage signal terminal and the first scan signal output terminal respectively, and is used to write the first voltage signal to the first scan signal output terminal under the control of the potential of the first output node;

[0131] The first energy storage circuit is electrically connected to the first output node and is used to maintain the potential of the first output node;

[0132] The second inverting circuit is electrically connected to the first scan signal output terminal and the second scan signal output terminal respectively, and is used to invert the first scan signal to obtain and output the second scan signal through the second scan signal output terminal.

[0133] Optionally, the third control clock signal terminal and the first control clock signal terminal are the same control clock signal terminal.

[0134] Optionally, the scanning signal generation circuit further includes a first node control circuit, a second on / off control circuit, a first output node control circuit, a second output node control circuit, a first output circuit, a first energy storage circuit, and a second inverting circuit; the control clock signal terminal includes a first control clock signal terminal, a second control clock signal terminal, and a third control clock signal terminal; the input control clock signal terminal is the first control clock signal terminal;

[0135] The first node control circuit is electrically connected to the second control clock signal terminal, the second voltage signal terminal, the first node, and the first output control node, respectively. It is used to write the second voltage signal provided by the second voltage signal terminal into the first node under the control of the second control clock signal provided by the second control clock signal terminal, and to write the second control clock signal into the first node under the control of the potential of the first output control node.

[0136] The second on / off control circuit is electrically connected to the second voltage signal terminal, the first node, and the second output control node, respectively, and is used to control the connection or disconnection between the first node and the second output control node under the control of the second voltage signal.

[0137] The first output node control circuit is electrically connected to the first output node, the third control clock signal terminal, the second output control node, the first output control node, and the first voltage signal terminal, respectively. It is used to control the potential of the first output node under the control of the potential of the second output control node and the third control clock signal provided by the third control clock signal terminal, and to write the first voltage signal provided by the first voltage signal terminal into the first output node under the control of the potential of the first output control node.

[0138] The second output node control circuit is electrically connected to the second output node, the first output node, the first voltage signal terminal, and the first control clock signal terminal, respectively, and is used to control the potential of the second output node under the control of the potential of the first output node and under the control of the first control clock signal provided by the first control clock signal terminal;

[0139] The first output circuit is electrically connected to the first output node, the first voltage signal terminal and the first scan signal output terminal respectively, and is used to write the first voltage signal to the first scan signal output terminal under the control of the potential of the first output node;

[0140] The first energy storage circuit is electrically connected to the first output node and is used to maintain the potential of the first output node;

[0141] The second inverting circuit is electrically connected to the first scan signal output terminal and the second scan signal output terminal respectively, and is used to invert the first scan signal to obtain and output the second scan signal through the second scan signal output terminal.

[0142] In a third aspect, embodiments of this disclosure provide a driving method applied to the aforementioned display substrate, the driving method comprising:

[0143] When the display substrate is in the first display state, after the pixel circuit in the area adjacent to the last area completes the display refresh in the holding frame, the frequency of the control clock signal is reduced.

[0144] After the pixel circuit in the region adjacent to the last region completes the display refresh, the control scan signal generation circuit outputs an invalid scan signal.

[0145] Optionally, the step of reducing the frequency of the control clock signal includes: reducing the frequency of the control clock signal to half of its original frequency. k , where k is a positive integer.

[0146] In a fourth aspect, embodiments of this disclosure provide a driving method applied to the above-described display substrate, the driving method comprising:

[0147] When the display substrate is in the first display state, after the pixel circuit in the area adjacent to the last area completes the display refresh in the holding frame, the frequency of the control clock signal is reduced.

[0148] During non-refresh periods, the control scan signal generation circuit outputs an invalid scan signal.

[0149] Optionally, the step of reducing the frequency of the control clock signal includes: reducing the frequency of the control clock signal to half of its original frequency. k , where k is a positive integer.

[0150] In a fifth aspect, embodiments of the present disclosure provide a display device including the display substrate described above. Attached Figure Description

[0151] Figure 1 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0152] Figure 2 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0153] Figure 3 is a circuit diagram of at least one embodiment of the pixel circuit;

[0154] Figure 4 is a schematic diagram of the driving timing corresponding to the display substrate according to at least one embodiment of the present disclosure;

[0155] Figure 5A is a structural diagram of at least one embodiment of the driving circuit;

[0156] Figure 5B is a structural diagram of at least one embodiment of the driving circuit;

[0157] Figure 5C is a structural diagram of at least one embodiment of the driving circuit;

[0158] Figure 5D is a structural diagram of at least one embodiment of the driving circuit;

[0159] Figure 6 is a structural diagram of at least one embodiment of the driving circuit;

[0160] Figure 7 is a schematic diagram of the driving timing corresponding to the display substrate according to at least one embodiment of the present disclosure;

[0161] Figure 8 is a structural diagram of at least one embodiment of the driving circuit;

[0162] Figure 9 is a structural diagram of at least one embodiment of the driving circuit;

[0163] Figure 10 is a structural diagram of at least one embodiment of the driving circuit;

[0164] Figure 11 is a structural diagram of at least one embodiment of the driving circuit;

[0165] Figure 12A is a circuit diagram of at least one embodiment of the reset circuit in the drive circuit;

[0166] Figure 12B is a circuit diagram of at least one embodiment of the reset circuit in the drive circuit;

[0167] Figure 12C is a circuit diagram of at least one embodiment of the reset circuit in the drive circuit;

[0168] Figure 12D is a circuit diagram of at least one embodiment of the reset circuit in the drive circuit;

[0169] Figure 12E is a circuit diagram of at least one embodiment of the reset circuit in the drive circuit;

[0170] Figure 12F is a circuit diagram of at least one embodiment of the reset circuit in the drive circuit;

[0171] Figure 13A is a structural diagram of at least one embodiment of the driving circuit;

[0172] Figure 13B is a structural diagram of at least one embodiment of the driving circuit;

[0173] Figure 13C is a structural diagram of at least one embodiment of the driving circuit;

[0174] Figure 13D is a structural diagram of at least one embodiment of the driving circuit;

[0175] Figure 14 is a structural diagram of at least one embodiment of the driving circuit;

[0176] Figure 15 is a structural diagram of at least one embodiment of the driving circuit;

[0177] Figure 16 is a structural diagram of at least one embodiment of the driving circuit;

[0178] Figure 17 is a circuit diagram of at least one embodiment of the scan signal generation circuit, reset circuit and start-up circuit in the drive circuit;

[0179] Figure 18 is a circuit diagram of at least one embodiment of the scan signal generation circuit, reset circuit and start-up circuit in the drive circuit;

[0180] Figure 19 is a circuit diagram of at least one embodiment of the scan signal generation circuit, reset circuit and start-up circuit in the drive circuit;

[0181] Figure 20 is a schematic diagram of the driving timing corresponding to the display substrate according to at least one embodiment of the present disclosure;

[0182] Figure 21 is a schematic diagram of the driving timing corresponding to the display substrate according to at least one embodiment of the present disclosure;

[0183] Figure 22 is a schematic diagram of the driving timing corresponding to the display substrate according to at least one embodiment of the present disclosure;

[0184] Figure 23A is a circuit diagram of at least one embodiment of the driving circuit;

[0185] Figure 23B is a circuit diagram of the scan signal generation circuit, reset circuit and start-up circuit in Figure 23A;

[0186] Figure 23C is a circuit diagram of the control signal generation circuit and control circuit in Figure 23A;

[0187] Figure 24A is a timing diagram of at least one embodiment of the driving circuit shown in Figure 23A when it is operating in the high refresh region;

[0188] Figure 24B is a timing diagram of at least one embodiment of the drive circuit shown in Figure 23A when it is operating in the low refresh region;

[0189] Figure 25A is a circuit diagram of at least one embodiment of the driving circuit;

[0190] Figure 25B is a circuit diagram of the scan signal generation circuit, reset circuit and start-up circuit in Figure 25A;

[0191] Figure 25C is a circuit diagram of the control signal generation circuit and control circuit in Figure 25A;

[0192] Figure 26 is a structural diagram of at least one embodiment of the drive module;

[0193] Figure 27A is a timing diagram of at least one embodiment of the driving circuit shown in Figure 25A when it is operating in the high refresh region;

[0194] Figure 27B is a timing diagram of at least one embodiment of the drive circuit shown in Figure 25A when it is operating in the low refresh region;

[0195] Figure 28A is a circuit diagram of at least one embodiment of the driving circuit;

[0196] Figure 28B is a circuit diagram of the scan signal generation circuit, reset circuit and start-up circuit in Figure 28A;

[0197] Figure 28C is a circuit diagram of the control signal generation circuit and control circuit in Figure 28A;

[0198] Figure 29 is a structural diagram of at least one embodiment of the drive module;

[0199] Figure 30 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 28A;

[0200] Figure 31A is a circuit diagram of at least one embodiment of the driving circuit;

[0201] Figure 31B is a circuit diagram of the scan signal generation circuit, reset circuit and start-up circuit in Figure 31A;

[0202] Figure 31C is a circuit diagram of the control signal generation circuit and control circuit in Figure 31A;

[0203] Figure 32 is a structural diagram of at least one embodiment of the drive module;

[0204] Figure 33 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 31A;

[0205] Figure 34A is a circuit diagram of at least one embodiment of the driving circuit;

[0206] Figure 34B is a circuit diagram of the scan signal generation circuit, reset circuit and start-up circuit in Figure 34A;

[0207] Figure 34C is a circuit diagram of the control signal generation circuit and control circuit in Figure 34A;

[0208] Figure 35 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 34A;

[0209] Figure 36A is a circuit diagram of at least one embodiment of the driving circuit;

[0210] Figure 36B is a circuit diagram of the scan signal generation circuit, reset circuit and start-up circuit in Figure 36A;

[0211] Figure 36C is a circuit diagram of the control signal generation circuit and control circuit in Figure 36A;

[0212] Figure 37 is a structural diagram of at least one embodiment of the drive module;

[0213] Figure 38 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 36A. Detailed Implementation

[0214] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0215] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0216] In this specification, "electrical connection" includes the case where constituent elements are connected together by a component having some electrical effect.

[0217] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.

[0218] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0219] Figure 1 illustrates a display substrate according to an embodiment of this disclosure. The display substrate includes a substrate, and a multi-row driving circuit and a multi-row pixel circuit disposed on the substrate. The display substrate includes a display area 100 and a peripheral area 200. The driving circuit is disposed in the peripheral area 200, and the pixel circuit is disposed in the display area 100.

[0220] The multiple driving circuits are cascaded together; at least one driving circuit is electrically connected to the corresponding pixel circuit. During one frame of display time, along the scanning direction, the cascaded driving circuits provide driving signals to the pixel circuits in sequence. The display area includes multiple areas, and the corresponding areas are refreshed in sequence.

[0221] The scanning direction may include, but is not limited to: forward scanning, i.e., scanning from top to bottom, from the first row of pixel circuits to the last row of pixel circuits; reverse scanning, scanning from bottom to top, i.e., scanning from the last row of pixel circuits to the first row of pixel circuits; scanning from both ends to the middle, i.e., the first row of pixel circuits and the last row of pixel circuits simultaneously scan towards the middle of the display area; and scanning from the middle to both ends, i.e., one or more rows of pixel circuits in the middle of the display area scan towards the first or last row of pixel circuits.

[0222] The display substrate can be in different display states. When the display substrate is in the first display state, along the scanning direction, when the last area of ​​the display area is displayed, the pixel circuits in the last area do not perform display refresh during at least one hold frame, and the display refresh rates of two adjacent areas are different. When the display substrate is in the second display state, or during a refresh frame of the first display state, all areas in the display area are refreshed.

[0223] Figure 2 exemplarily illustrates a first display state of a display substrate: the scanning direction of the display area 100 is forward scanning, the display area includes a first area 101, a second area 102, and a third area 103, and the refresh frequency of the second area 102 is higher than the refresh frequency of the first area 101 and the refresh frequency of the third area 103; in at least one hold frame, the pixel circuit in the second area 102 is refreshed, while the pixel circuit in the third area 103 is not refreshed. As shown in Figure 3, at least one embodiment of the pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an eighth display control transistor M8, a storage capacitor Cst, and an organic light-emitting diode O1;

[0224] The gate of M1 is electrically connected to the first reset terminal PR, the source of M1 is electrically connected to the first start voltage terminal I1, and the second terminal of M1 is electrically connected to the drain of M3. The first start voltage terminal I1 is used to provide the first start voltage Vinit1.

[0225] The gate of M2 is electrically connected to the first display control terminal NT, the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3.

[0226] The gate of M4 is electrically connected to the second display control terminal PT, the source of M4 is electrically connected to the data line DL, and the drain of M4 is electrically connected to the source of M3.

[0227] The gate of M5 is electrically connected to the light-emitting control terminal E1, the source of M5 is electrically connected to the high-level terminal VDD, and the drain of M5 is electrically connected to the source of M3.

[0228] The gate of M6 is electrically connected to the light-emitting control terminal E1, the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low-level terminal VSS.

[0229] The gate of M7 is electrically connected to the second reset terminal HR, the source of M7 is electrically connected to the second initial voltage terminal I2, and the drain of M7 is electrically connected to the anode of O1.

[0230] The gate of M8 is electrically connected to the second reset terminal HR, the source of M8 is electrically connected to the third initial voltage terminal I3, and the drain of M8 is electrically connected to the source of M3.

[0231] The first plate of Cst is electrically connected to the gate of M3, and the second plate of Cst is electrically connected to the high-level terminal VDD.

[0232] M1, M3, M4, M5, M6, M7, and M8 are all p-type transistors, while M2 is an n-type transistor.

[0233] In at least one embodiment of this disclosure, the drive signal output terminal of the drive circuit can be a first display control terminal, a second display control terminal, or a second reset terminal of the pixel circuit, but is not limited thereto.

[0234] In at least one embodiment of this disclosure, the driving module may include multiple levels of driving circuits; the first-level driving circuit and the second-level driving circuit may be used to provide scanning signals and / or driving signals to the pixel circuits in the first region 101 of FIG2; the m-th level driving circuit and the (m+1)-th level driving circuit may be used to provide scanning signals and / or driving signals to the pixel circuits in the second region 102 of FIG2; and the n-th level driving circuit may be used to provide scanning signals and / or driving signals to the pixel circuits in the third region 103 of FIG2. Wherein, n and m are positive integers;

[0235] The first region 101 corresponds to the first stage driving circuit to the (m-1)th stage driving circuit, the second region 102 corresponds to the m-th stage driving circuit to the (n-1)th stage driving circuit, and the third region 103 corresponds to the n-th stage driving circuit to the last stage driving circuit.

[0236] For example, as shown in FIG4, in the first refresh frame F1 and the second refresh frame F2, the enable signal provided by the enable signal terminal EN is at a high level. In the first region 101, the second region 102 and the third region 103, the potential of the first scan signal and the potential of the drive signal rise from low level to effective level line by line (in at least one embodiment shown in FIG4, the effective level is high level), and the display refresh is performed on the first region 101, the second region 102 and the third region 103.

[0237] In hold frame S1, in the driving circuits of the pixel circuits corresponding to the first region 101, the second region 102, and the third region 103, the potential of the first scan signal rises sequentially from low level to high level line by line.

[0238] The holding frame S1 includes a first holding time period S11, a second holding time period S12, and a third holding time period S13;

[0239] During the first holding time period S11, in the driving circuit corresponding to the first region 101, the potential of the first scan signal rises from low level to high level line by line.

[0240] During the second holding period S12, in the driving circuit corresponding to the second region 102, the potential of the first scan signal rises from low level to high level line by line.

[0241] During the third holding time period S13, in the driving circuit corresponding to the third region 103, the potential of the first scan signal rises from low level to high level line by line.

[0242] During the first holding time period S11 and the third holding time period S13, the enable signal provided by the enable signal terminal EN is a low voltage signal, which makes the drive signals corresponding to the first region 101 and the third region 103 low voltage signals, and the display refresh is not performed on the first region 101 and the third region 103.

[0243] During the second hold period S12, the enable signal provided by the enable signal terminal EN is a high voltage signal, and the potential of the drive signal corresponding to the second region 102 rises from low level to high level in sequence, thus refreshing the display of the second region 102.

[0244] In Figure 4, CK1 is the first control clock signal terminal, CK2 is the second control clock signal terminal, STV is the start signal line, GT1 is the drive signal output terminal of the first stage drive circuit, GT2 is the drive signal output terminal of the second stage drive circuit, GTm is the drive signal output terminal of the m-th stage drive circuit, GTm+1 is the drive signal output terminal of the (m+1)-th stage drive circuit, and GTn is the drive signal output terminal of the n-th stage drive circuit.

[0245] ST1 is the first scan signal output terminal of the first-stage driving circuit, ST2 is the first scan signal output terminal of the second-stage driving circuit, STm is the first scan signal output terminal of the m-th stage driving circuit, STm+1 is the first scan signal output terminal of the (m+1)-th stage driving circuit, and STn is the first scan signal output terminal of the n-th stage driving circuit.

[0246] The display substrate described in at least one embodiment of this disclosure may include a substrate and a driving circuit disposed on the substrate;

[0247] The driving circuit includes a scan signal generation circuit and a reset circuit;

[0248] The scan signal generation circuit is used to provide at least one scan signal;

[0249] The reset circuit is electrically connected to both the reset control terminal and the scan signal generation circuit, and is used to control the scan signal generation circuit to output an invalid scan signal under the control of the reset control terminal.

[0250] In at least one embodiment of the display substrate described in this disclosure, the reset circuit, under the control of the reset control terminal, controls the scan signal generation circuit to output an invalid scan signal;

[0251] When the scan signal generation circuit directly provides a scan signal to the gate of the transistor in the pixel circuit, the invalid scan signal is a low voltage signal when the transistor in the pixel circuit is an n-type transistor, and the invalid scan signal is a high voltage signal when the transistor in the pixel circuit is a p-type transistor.

[0252] In at least one embodiment of this disclosure, the driving circuit may further include a driving signal output terminal, a control signal generation circuit, and a control circuit. The control signal generation circuit controls the potential of the first control node under the control of the scanning signal, and the control circuit controls the driving signal provided through the driving signal output terminal under the control of the first control node and the driving control terminal.

[0253] When the driving circuit provides the driving signal to the gate of the transistor in the pixel circuit through the driving signal output terminal, when the scan signal generation circuit outputs an invalid scan signal, the driving circuit provides an invalid driving signal, causing the transistor in the pixel circuit to turn off.

[0254] At this time, when the transistor in the pixel circuit is an n-type transistor, when the scan signal generation circuit outputs an invalid scan signal, the scan signal generation circuit controls the drive signal provided by the drive circuit to be a low voltage signal; when the transistor in the pixel circuit is a p-type transistor, when the scan signal generation circuit outputs an invalid scan signal, the scan signal generation circuit controls the drive signal provided by the drive circuit to be a high voltage signal.

[0255] In at least one embodiment of this disclosure, the scanning signal may include a first scanning signal and a second scanning signal.

[0256] The display substrate described in at least one embodiment of this disclosure may include a substrate and a driving circuit disposed on the substrate;

[0257] As shown in Figure 5A, the driving circuit includes a scan signal generation circuit 50 and a reset circuit 51;

[0258] The scan signal generation circuit 50 is electrically connected to the first scan signal output terminal ST and the second scan signal output terminal FT, respectively, and is used to provide a first scan signal through the first scan signal output terminal ST and a second scan signal through the second scan signal output terminal FT.

[0259] The reset circuit 51 is electrically connected to the reset control terminal SC and the scan signal generation circuit 50, respectively, and is used to control the scan signal generation circuit 50 to output an invalid first scan signal and an invalid second scan signal under the control of the reset control terminal SC.

[0260] In at least one embodiment of this disclosure, the reset control terminal may include a reset signal terminal; or, the reset control terminal may include a reset signal terminal and a reset input node; or, the reset control terminal may include a reset signal terminal and a signal input terminal.

[0261] As shown in Figure 5B, the driving circuit includes a scan signal generation circuit 50 and a reset circuit 51;

[0262] The scan signal generation circuit 50 is electrically connected to the first scan signal output terminal ST and the second scan signal output terminal FT, respectively, and is used to provide a first scan signal through the first scan signal output terminal ST and a second scan signal through the second scan signal output terminal FT.

[0263] The reset circuit 51 is electrically connected to the reset signal terminal Trst and the scan signal generation circuit 50, respectively, and is used to control the scan signal generation circuit 50 to output an invalid first scan signal and an invalid second scan signal under the control of the reset signal provided by the reset signal terminal Trst.

[0264] In at least one embodiment shown in Figure 5B, the reset control terminal includes a reset signal terminal Trst.

[0265] As shown in Figure 5C, the driving circuit includes a scan signal generation circuit 50 and a reset circuit 51;

[0266] The scan signal generation circuit 50 is electrically connected to the first scan signal output terminal ST and the second scan signal output terminal FT, respectively, and is used to provide a first scan signal through the first scan signal output terminal ST and a second scan signal through the second scan signal output terminal FT.

[0267] The reset circuit 51 is electrically connected to the reset signal terminal Trst, the reset input node Ri, and the scan signal generation circuit 50, respectively. It is used to control the scan signal generation circuit 50 to output an invalid first scan signal and an invalid second scan signal under the control of the reset signal provided by the reset signal terminal Trst and the potential of the reset input node Ri.

[0268] In at least one embodiment shown in Figure 5C, the reset control terminal includes a reset signal terminal Trst and a reset input node Ri.

[0269] As shown in Figure 5D, the driving circuit includes a scan signal generation circuit 50 and a reset circuit 51;

[0270] The scan signal generation circuit 50 is electrically connected to the first scan signal output terminal ST and the second scan signal output terminal FT, respectively, and is used to provide a first scan signal through the first scan signal output terminal ST and a second scan signal through the second scan signal output terminal FT.

[0271] The reset circuit 51 is electrically connected to the reset signal terminal Trst, the signal input terminal SR, and the scan signal generation circuit 50, respectively. Under the control of the reset signal provided by the reset signal terminal Trst and the input signal provided by the signal input terminal SR, the reset circuit 50 controls the scan signal generation circuit 50 to output an invalid first scan signal and an invalid second scan signal.

[0272] In at least one embodiment shown in Figure 5D, the reset control terminal includes a reset signal terminal Trst and a signal input terminal SR.

[0273] In at least one embodiment of this disclosure, the display substrate further includes a pixel circuit disposed on the substrate; the scan signal generation circuit is electrically connected to a control clock signal terminal and is used to provide a scan signal under the control of a control clock signal provided by the control clock signal terminal;

[0274] The display substrate includes a display area and a peripheral area; the driving circuit is disposed in the peripheral area; the pixel circuit is disposed in the display area;

[0275] When the display substrate is in the first display state, the display area includes multiple areas along the scanning direction. When the last area of ​​the display area is displayed, the pixel circuits in the last area do not perform display refresh during at least one hold frame. The display refresh frequencies of two adjacent areas are different.

[0276] The reset circuit is used to control the scan signal generation circuit to output an invalid scan signal when the display substrate is in the first display state, after the pixel circuit in the region adjacent to the last region in the at least one holding frame has completed the display refresh.

[0277] In at least one embodiment of this disclosure, the reset circuit can also be used to control the scan signal generation circuit to output an invalid first scan signal and an invalid second scan signal during non-refresh periods. The non-refresh periods include, but are not limited to, the frame blanking period between two adjacent frames, and the power-on / power-off period of the display substrate.

[0278] As shown in Figure 6, based on at least one embodiment shown in Figure 5A, the scan signal generation circuit 50 is electrically connected to the control clock signal terminal CLKC, and is used to provide a first scan signal and a second scan signal under the control of the control clock signal provided by the control clock signal terminal CLKC.

[0279] The display substrate also includes a clock control circuit 60 disposed on the substrate; the clock control circuit 60 is electrically connected to the control clock signal terminal CLKC, and is used to reduce the frequency of the control clock signal after the pixel circuit in the region adjacent to the last region in the holding frame has completed the display refresh. Reducing the frequency of the control clock signal can save power consumption.

[0280] In at least one embodiment shown in Figure 2, the third region 103 is the last region included in the display area, and the second region 102 is the region adjacent to the last region. After the display refresh is completed for the pixel circuit in the second region 102, the frequency of the control clock signal can be reduced to reduce power consumption.

[0281] For example, as shown in FIG7, during the third hold time period S13, the display refresh of the second region 102 is completed. The frequency of the first control clock signal provided by the first control clock signal terminal CK1 and the frequency of the second control clock signal provided by the second control clock signal terminal CK2 are reduced, which can achieve the technical effect of saving power consumption. However, due to the clock frequency reduction, the shift speed will also decrease. For example, at the end of the first hold time period S1, the first scan signal and drive signal provided by the nth stage drive circuit corresponding to the second region 102 have not yet completed the shift. In the next refresh frame, the output pulse will continue to shift, and the enable signal provided by the enable signal terminal EN is a high voltage signal. This causes multiple drive signals to be output simultaneously by the drive circuit corresponding to the first region 101 and the drive circuit corresponding to the third region 103 in the next refresh frame, resulting in display abnormality. Based on the above problems, in at least one embodiment of this disclosure, the drive circuit adopts a reset circuit. Before the next refresh frame, the reset circuit controls the scan signal generation circuit to output an invalid scan signal, so as to solve the display abnormality problem while saving power consumption.

[0282] In at least one embodiment of this disclosure, the driving circuit further includes a startup circuit; the scanning signal generation circuit includes a first output control node;

[0283] The startup circuit is electrically connected to the input control clock signal terminal, and is used to connect or disconnect the control signal input terminal and the first output control node under the control of the input control clock signal provided by the input control clock signal terminal.

[0284] The startup circuit is electrically connected to the signal input terminal, and the startup circuit is electrically connected to the first output control node through the reset circuit; or...

[0285] The reset circuit is electrically connected to the signal input terminal, and the reset circuit is electrically connected to the first output control node through the startup circuit.

[0286] In at least one embodiment of this disclosure, the driving circuit further includes a startup circuit; the scanning signal generation circuit includes a first output control node; the reset circuit includes a first reset sub-circuit and a second reset sub-circuit; and the reset control terminal includes a reset signal terminal and / or a reset input node.

[0287] The startup circuit is electrically connected to the input control clock signal terminal, the signal input terminal, and the reset input node, respectively, and is used to control the connection or disconnection between the signal input terminal and the reset input node under the control of the input control clock signal provided by the input control clock signal terminal;

[0288] The first reset sub-circuit is electrically connected to the reset voltage terminal and the first output control node, respectively. The first reset sub-circuit is also electrically connected to the reset signal terminal or the reset input node, and is used to write the reset voltage provided by the reset voltage terminal into the first output control node under the control of the reset signal or the potential of the reset input node.

[0289] The second reset sub-circuit is electrically connected to the reset signal terminal, the reset input node, and the first output control node, respectively, and is used to control the connection or disconnection between the reset input node and the first output control node under the control of the reset signal.

[0290] Optionally, the reset voltage terminal can be a first high voltage terminal or a first low voltage terminal.

[0291] As shown in Figure 8, based on at least one embodiment of the driving circuit shown in Figure 5B, the driving circuit further includes a startup circuit 80; the reset circuit includes a first reset sub-circuit 81 and a second reset sub-circuit 82; the scan signal generation circuit 50 includes a first output control node PD1; the scan signal generation circuit 50 is electrically connected to the control clock signal terminal CLKC.

[0292] The startup circuit 80 is electrically connected to the input control clock signal terminal CLKS, the signal input terminal SR, and the reset input node Ri, respectively, and is used to control the connection or disconnection between the signal input terminal SR and the reset input node Ri under the control of the input control clock signal provided by the input control clock signal terminal CLKS.

[0293] The first reset sub-circuit 81 is electrically connected to the reset voltage terminal VR and the first output control node PD1 respectively. The first reset sub-circuit 81 is also electrically connected to the reset signal terminal Trst, and is used to write the reset voltage provided by the reset voltage terminal VR into the first output control node PD1 under the control of the reset signal.

[0294] The second reset sub-circuit 82 is electrically connected to the reset signal terminal Trst, the reset input node Ri, and the first output control node PD1, respectively, and is used to control the connection or disconnection between the reset input node Ri and the first output control node PD1 under the control of the reset signal.

[0295] In at least one embodiment shown in Figure 8, the first output control node PD1 can be a reset output node.

[0296] As shown in Figure 9, based on at least one embodiment of the driving circuit shown in Figure 5C, the driving circuit further includes a startup circuit 80; the reset circuit includes a first reset sub-circuit 81 and a second reset sub-circuit 82; the scan signal generation circuit 50 includes a first output control node PD1; the scan signal generation circuit 50 is electrically connected to the control clock signal terminal CLKC.

[0297] The startup circuit 80 is electrically connected to the input control clock signal terminal CLKS, the signal input terminal SR, and the reset input node Ri, respectively, and is used to control the connection or disconnection between the signal input terminal SR and the reset input node Ri under the control of the input control clock signal provided by the input control clock signal terminal CLKS.

[0298] The first reset sub-circuit 81 is electrically connected to the reset voltage terminal VR and the first output control node PD1 respectively. The first reset sub-circuit 81 is also electrically connected to the reset input node Ri, and is used to write the reset voltage provided by the reset voltage terminal VR into the first output control node PD1 under the control of the potential of the reset input node Ri.

[0299] The second reset sub-circuit 82 is electrically connected to the reset signal terminal Trst, the reset input node Ri, and the first output control node PD1, respectively, and is used to control the connection or disconnection between the reset input node Ri and the first output control node PD1 under the control of the reset signal.

[0300] In at least one embodiment shown in Figure 9, the first output control node PD1 can be a reset output node.

[0301] In at least one embodiment of this disclosure, the driving circuit further includes a startup circuit; the scanning signal generation circuit includes a first output control node; the reset circuit includes a first reset sub-circuit and a second reset sub-circuit; and the reset control terminal includes a reset signal terminal and / or a signal input terminal.

[0302] The first reset sub-circuit is electrically connected to the reset output node and the reset voltage terminal respectively. The first reset sub-circuit is also electrically connected to the reset signal terminal or the signal input terminal, and is used to write the reset voltage provided by the reset voltage terminal into the reset output node under the control of the reset signal or the input signal provided by the signal input terminal.

[0303] The second reset sub-circuit is electrically connected to the signal input terminal, the reset signal terminal, and the reset output node, respectively, and is used to control the connection or disconnection between the signal input terminal and the reset output node under the control of the reset signal;

[0304] The startup circuit is electrically connected to the input control clock signal terminal, the reset output node, and the first output control node, respectively, and is used to control the connection or disconnection between the reset output node and the first output control node under the control of the input control clock signal provided by the input control clock signal terminal.

[0305] Optionally, the reset voltage terminal can be a first high voltage terminal or a first low voltage terminal.

[0306] As shown in Figure 10, based on at least one embodiment of the driving circuit shown in Figure 5B, the driving circuit further includes a startup circuit 80; the reset circuit includes a first reset sub-circuit 81 and a second reset sub-circuit 82; the scan signal generation circuit includes a first output control node PD1; the scan signal generation circuit 50 includes a first output control node PD1; the scan signal generation circuit 50 is electrically connected to the control clock signal terminal CLKC.

[0307] The first reset sub-circuit 81 is electrically connected to the reset output node Ro and the reset voltage terminal VR respectively. The first reset sub-circuit 81 is also electrically connected to the reset signal terminal Trst, and is used to write the reset voltage provided by the reset voltage terminal VR into the reset output node Ro under the control of the reset signal.

[0308] The second reset sub-circuit 82 is electrically connected to the signal input terminal SR, the reset signal terminal Trst, and the reset output node Ro, respectively, and is used to control the connection or disconnection between the signal input terminal SR and the reset output node Ro under the control of the reset signal;

[0309] The startup circuit 80 is electrically connected to the input control clock signal terminal CLKS, the reset output node Ro, and the first output control node PD1, respectively, and is used to control the connection or disconnection between the reset output node Ro and the first output control node PD1 under the control of the input control clock signal provided by the input control clock signal terminal CLKS.

[0310] In at least one embodiment shown in Figure 10, the signal input terminal SR can be a reset input node.

[0311] As shown in Figure 11, based on at least one embodiment of the driving circuit shown in Figure 5D, the driving circuit further includes a startup circuit 80; the reset circuit includes a first reset sub-circuit 81 and a second reset sub-circuit 82; the scan signal generation circuit 50 includes a first output control node PD1; the scan signal generation circuit 50 is electrically connected to the control clock signal terminal CLKC.

[0312] The first reset sub-circuit 81 is electrically connected to the reset output node Ro and the reset voltage terminal VR respectively. The first reset sub-circuit 81 is also electrically connected to the signal input terminal SR, and is used to write the reset voltage provided by the reset voltage terminal VR into the reset output node Ro under the control of the input signal provided by the signal input terminal SR.

[0313] The second reset sub-circuit 82 is electrically connected to the signal input terminal SR, the reset signal terminal Trst, and the reset output node Ro, respectively, and is used to control the connection or disconnection between the signal input terminal SR and the reset output node Ro under the control of the reset signal;

[0314] The startup circuit 80 is electrically connected to the input control clock signal terminal CLKS, the reset output node Ro, and the first output control node PD1, respectively, and is used to control the connection or disconnection between the reset output node Ro and the first output control node PD1 under the control of the input control clock signal provided by the input control clock signal terminal CLKS.

[0315] In at least one embodiment shown in Figure 11, the signal input terminal SR can be a reset input node.

[0316] Optionally, the first reset sub-circuit includes a first reset transistor, and the second reset sub-circuit includes a second reset transistor;

[0317] The control terminal of the first reset transistor is electrically connected to the reset signal terminal, the first terminal of the first reset transistor is electrically connected to the reset voltage terminal, and the second terminal of the first reset transistor is electrically connected to the first output control node.

[0318] The control terminal of the second reset transistor is electrically connected to the reset signal terminal, the first terminal of the second reset transistor is electrically connected to the reset input node, and the second terminal of the second reset transistor is electrically connected to the first output control node.

[0319] The first reset transistor is an n-type transistor, and the second reset transistor is a p-type transistor; or, the first reset transistor is a p-type transistor, and the second reset transistor is an n-type transistor.

[0320] The startup circuit includes an input transistor;

[0321] The control electrode of the input transistor is electrically connected to the input control clock signal terminal, the first electrode of the input transistor is electrically connected to the signal input terminal, and the second electrode of the input transistor is electrically connected to the reset input node.

[0322] Optionally, the first reset sub-circuit includes a first reset transistor, and the second reset sub-circuit includes a second reset transistor;

[0323] The control terminal of the first reset transistor is electrically connected to the reset input node, the first terminal of the first reset transistor is electrically connected to the reset voltage terminal, and the second terminal of the first reset transistor is electrically connected to the first output control node.

[0324] The control terminal of the second reset transistor is electrically connected to the reset signal terminal, the first terminal of the second reset transistor is electrically connected to the reset input node, and the second terminal of the second reset transistor is electrically connected to the first output control node.

[0325] The startup circuit includes an input transistor;

[0326] The control electrode of the input transistor is electrically connected to the input control clock signal terminal, the first electrode of the input transistor is electrically connected to the signal input terminal, and the second electrode of the input transistor is electrically connected to the reset input node.

[0327] Optionally, the first reset sub-circuit includes a first reset transistor and a second reset transistor;

[0328] The control terminal of the first reset transistor is electrically connected to the reset signal terminal, the first terminal of the first reset transistor is electrically connected to the reset voltage terminal, and the second terminal of the first reset transistor is electrically connected to the reset output node.

[0329] The control electrode of the second reset transistor is electrically connected to the reset signal terminal, the first electrode of the second reset transistor is electrically connected to the signal input terminal, and the second electrode of the second reset transistor is electrically connected to the reset output node.

[0330] The first reset transistor is an n-type transistor, and the second reset transistor is a p-type transistor; or, the first reset transistor is a p-type transistor, and the second reset transistor is an n-type transistor.

[0331] The startup circuit includes an input transistor;

[0332] The control terminal of the input transistor is electrically connected to the input control clock signal terminal, the first terminal of the input transistor is electrically connected to the reset output node, and the second terminal of the input transistor is electrically connected to the first output control node.

[0333] Optionally, the first reset sub-circuit includes a first reset transistor and a second reset transistor;

[0334] The control terminal of the first reset transistor is electrically connected to the signal input terminal, the first terminal of the first reset transistor is electrically connected to the reset voltage terminal, and the second terminal of the first reset transistor is electrically connected to the reset output node.

[0335] The control electrode of the second reset transistor is electrically connected to the reset signal terminal, the first electrode of the second reset transistor is electrically connected to the signal input terminal, and the second electrode of the second reset transistor is electrically connected to the reset output node.

[0336] The startup circuit includes an input transistor;

[0337] The control terminal of the input transistor is electrically connected to the input control clock signal terminal, the first terminal of the input transistor is electrically connected to the reset output node, and the second terminal of the input transistor is electrically connected to the first output control node.

[0338] As shown in Figure 12A, the reset circuit may include a first reset sub-circuit 81 and a second reset circuit 82;

[0339] The first reset sub-circuit 81 may include a first reset transistor RT1, and the second reset sub-circuit 82 may include a second reset transistor RT2.

[0340] The gate of RT1 is electrically connected to the reset signal terminal Trst, the source of RT1 is electrically connected to the first high voltage terminal VGH1 or the first low voltage terminal VGL1, and the drain of RT1 is electrically connected to the reset output node Ro.

[0341] The gate of RT2 is electrically connected to the reset signal terminal Trst, the source of RT2 is electrically connected to the reset input node Ri, and the drain of RT2 is electrically connected to the reset output node Ro.

[0342] In at least one embodiment shown in Figure 12A, the reset voltage terminal is a first high voltage terminal VGH1 or a first low voltage terminal VGL1; RT2 is an n-type transistor and RT1 is a p-type transistor.

[0343] As shown in Figure 12B, the reset circuit may include a first reset sub-circuit 81 and a second reset circuit 82.

[0344] The first reset sub-circuit may include a first reset transistor RT1, and the second reset sub-circuit may include a second reset transistor RT2;

[0345] The gate of RT1 is electrically connected to the reset input node Ri, the source of RT1 is electrically connected to the first high voltage terminal VGH1, and the drain of RT1 is electrically connected to the reset output node Ro.

[0346] The gate of RT2 is electrically connected to the reset signal terminal Trst, the source of RT2 is electrically connected to the reset input node Ri, and the drain of RT2 is electrically connected to the reset output node Ro.

[0347] In at least one embodiment shown in Figure 12B, the reset voltage terminal is a first high voltage terminal VGH1; RT2 is a p-type transistor and RT1 is an n-type transistor.

[0348] As shown in Figure 12C, the reset circuit may include a first reset sub-circuit 81 and a second reset circuit 82;

[0349] The first reset sub-circuit 81 may include a first reset transistor RT1, and the second reset sub-circuit 82 may include a second reset transistor RT2.

[0350] The gate of RT1 is electrically connected to the reset input node Ri, the source of RT1 is electrically connected to the first low voltage terminal VGL1, and the drain of RT1 is electrically connected to the reset output node Ro.

[0351] The gate of RT2 is electrically connected to the reset signal terminal Trst, the source of RT2 is electrically connected to the reset input node Ri, and the drain of RT2 is electrically connected to the reset output node Ro.

[0352] In at least one embodiment shown in Figure 12C, the reset voltage terminal is a first low voltage terminal VGL1; RT2 is an n-type transistor, and RT1 is an n-type transistor.

[0353] As shown in Figure 12D, the reset circuit may include a first reset sub-circuit 81 and a second reset circuit 82.

[0354] The first reset sub-circuit 81 may include a first reset transistor RT1, and the second reset sub-circuit 82 may include a second reset transistor RT2.

[0355] The gate of RT1 is electrically connected to the reset signal terminal Trst, the source of RT1 is electrically connected to the first high voltage terminal VGH1 or the first low voltage terminal VGL1, and the drain of RT1 is electrically connected to the reset output node Ro.

[0356] The gate of RT2 is electrically connected to the reset signal terminal Trst, the source of RT2 is electrically connected to the reset input node Ri, and the drain of RT2 is electrically connected to the reset output node Ro.

[0357] In at least one embodiment shown in Figure 12D, the reset voltage terminal is a first high voltage terminal VGH1 or a first low voltage terminal VGL1; RT2 is a p-type transistor and RT1 is an n-type transistor.

[0358] As shown in Figure 12E, the reset circuit may include a first reset sub-circuit 81 and a second reset circuit 82.

[0359] The first reset sub-circuit 81 may include a first reset transistor RT1, and the second reset sub-circuit 82 may include a second reset transistor RT2.

[0360] The gate of RT1 is electrically connected to the reset input node Ri, the source of RT1 is electrically connected to the first high voltage terminal VGH1, and the drain of RT1 is electrically connected to the reset output node Ro.

[0361] The gate of RT2 is electrically connected to the reset signal terminal Trst, the source of RT2 is electrically connected to the reset input node Ri, and the drain of RT2 is electrically connected to the reset output node Ro.

[0362] In at least one embodiment shown in Figure 12E, the reset voltage terminal is a first high voltage terminal VGH1; RT2 is a p-type transistor, and RT1 is a p-type transistor.

[0363] As shown in Figure 12F, the reset circuit may include a first reset sub-circuit 81 and a second reset circuit 82;

[0364] The first reset sub-circuit may include a first reset transistor RT1, and the second reset sub-circuit may include a second reset transistor RT2;

[0365] The gate of RT1 is electrically connected to the reset input node Ri, the source of RT1 is electrically connected to the first low voltage terminal VGL1, and the drain of RT1 is electrically connected to the reset output node Ro.

[0366] The gate of RT2 is electrically connected to the reset signal terminal Trst, the source of RT2 is electrically connected to the reset input node Ri, and the drain of RT2 is electrically connected to the reset output node Ro.

[0367] In at least one embodiment shown in Figure 12F, the reset voltage terminal is a first low voltage terminal VGL1; RT2 is a p-type transistor, and RT1 is an n-type transistor. Exemplarily, as shown in Figures 12A-12F, the reset circuit includes a first reset sub-circuit and a second reset sub-circuit; wherein,

[0368] When the reset circuits shown in Figures 12A-12C are in operation, the reset circuit begins to reset when the reset signal provided at the reset signal terminal Trst is a low-level signal.

[0369] When the reset circuit shown in Figures 12D-12F is working, the reset circuit starts to reset when the reset signal provided by the reset signal terminal Trst is a high-level signal.

[0370] When the source of the first reset transistor RT1 is electrically connected to the first high-voltage terminal VGH1, the reset circuit can set the electrical position of the reset output node Ro to high voltage; when the source of the first reset transistor RT1 is electrically connected to the first low-voltage terminal VGL1, the reset circuit can set the electrical position of the reset output node Ro to low voltage. The type of the first reset transistor RT1 can be designed as needed. When the signal connected to the gate of the first reset transistor RT1 is high, causing the first reset transistor RT1 to conduct, the first reset transistor RT1 is an n-type transistor; conversely, when the signal connected to the gate of the first reset transistor RT1 is low, causing the first reset transistor RT1 to conduct, the first reset transistor RT1 is a p-type transistor.

[0371] In at least one embodiment of this disclosure, the scanning signal generation circuit may include a first on / off control circuit and a second output circuit;

[0372] The first on / off control circuit is electrically connected to the second voltage signal terminal, the first output control node, and the second output node, respectively, and is used to control the connection or disconnection between the first output control node and the second output node under the control of the second voltage signal provided by the second voltage signal terminal.

[0373] The second output circuit is electrically connected to the second output node, the first scan signal output terminal, and the second voltage signal terminal, respectively, and is used to control the connection or disconnection between the first scan signal output terminal and the second voltage signal terminal under the control of the potential of the second output node.

[0374] In at least one embodiment of this disclosure, the driving circuit further includes a control signal generation circuit and a control circuit; the scanning signal includes a first scanning signal and a second scanning signal;

[0375] The scanning signal generation circuit is electrically connected to the first scanning signal output terminal and the second scanning signal output terminal respectively, and is used to provide a first scanning signal through the first scanning signal output terminal and a second scanning signal through the second scanning signal output terminal.

[0376] The control signal generation circuit is electrically connected to the enable signal terminal and the first control node, respectively. The control signal generation circuit is also electrically connected to the first scan signal output terminal, the second scan signal output terminal, the first control terminal, and the second control terminal, respectively. It is used to control the connection or disconnection between the enable signal terminal and the first control node under the control of the first scan signal, the second scan signal, the first control signal provided by the first control terminal, and the second control signal provided by the second control terminal. The first control terminal is electrically connected to the output terminal of the first scan signal of the adjacent i-th stage, and the second control terminal is electrically connected to the output terminal of the second scan signal of the adjacent i-th stage; i is a positive integer.

[0377] The control circuit is connected to the first control node, the drive control terminal, and the drive signal output terminal respectively, and is used to provide a drive signal to the drive signal output terminal under the control of the potential of the first control node and the drive control signal provided by the drive control terminal.

[0378] The drive control terminal is either the first scan signal output terminal or the second scan signal output terminal.

[0379] Optionally, i can be equal to 1, but is not limited to this.

[0380] In at least one embodiment of this disclosure, when the first scan signal output terminal is the nth level first scan signal output terminal and the second scan signal output terminal is the nth level second scan signal output terminal, the adjacent i-th level first scan signal output terminal is the ni-th level first scan signal output terminal and the adjacent i-th level second scan signal output terminal is the ni-th level second scan signal output terminal; n is a positive integer.

[0381] In at least one embodiment of this disclosure, when the enable signal terminal provides a valid enable signal, the drive circuit operates in the high refresh region and the drive circuit outputs drive signals normally.

[0382] When an invalid enable signal is provided at the enable signal terminal, the drive circuit operates in the low refresh rate region and outputs an invalid drive signal.

[0383] As shown in Figure 13A, based on at least one embodiment of the driving circuit shown in Figure 8, the at least one embodiment of the driving circuit further includes a control signal generation circuit 131 and a control circuit 132; the scanning signal includes a first scanning signal and a second scanning signal;

[0384] The control signal generation circuit 131 is electrically connected to the enable signal terminal EN and the first control node CS1, respectively. The control signal generation circuit 131 is also electrically connected to the first scan signal output terminal ST, the second scan signal output terminal FT, the first control terminal TC1, and the second control terminal TC2, respectively. It is used to control the connection or disconnection between the enable signal terminal EN and the first control node CS1 under the control of the first scan signal, the second scan signal, the first control signal provided by the first control terminal TC1, and the second control signal provided by the second control terminal TC2. The first control terminal TC1 is electrically connected to the ni-th level first scan signal output terminal, and the second control terminal TC2 is electrically connected to the ni-th level second scan signal output terminal; i is a positive integer.

[0385] The control circuit 132 is connected to the first control node CS1, the drive control terminal DC, and the drive signal output terminal GT, respectively, and is used to provide a drive signal to the drive signal output terminal GT under the control of the potential of the first control node CS1 and the drive control signal provided by the drive control terminal DC.

[0386] In at least one embodiment shown in Figure 13A, the drive control terminal can be the first scan signal output terminal ST or the second scan signal output terminal FT.

[0387] In at least one embodiment shown in Figure 13A, the driving circuit is an nth-stage driving circuit, the first scan signal output terminal is the nth-stage first scan signal output terminal, the second scan signal output terminal is the nth-stage second scan signal output terminal, and n is a positive integer.

[0388] As shown in Figure 13B, based on at least one embodiment of the driving circuit shown in Figure 9, the at least one embodiment of the driving circuit further includes a control signal generation circuit 131 and a control circuit 132; the scanning signal includes a first scanning signal and a second scanning signal.

[0389] The scanning signal generation circuit 50 is electrically connected to the first scanning signal output terminal ST and the second scanning signal output terminal FT, respectively, and is used to provide a first scanning signal through the first scanning signal output terminal ST and a second scanning signal through the second scanning signal output terminal FT.

[0390] The control signal generation circuit 131 is electrically connected to the enable signal terminal EN and the first control node CS1, respectively. The control signal generation circuit 131 is also electrically connected to the first scan signal output terminal ST, the second scan signal output terminal FT, the first control terminal TC1, and the second control terminal TC2, respectively. It is used to control the connection or disconnection between the enable signal terminal EN and the first control node CS1 under the control of the first scan signal, the second scan signal, the first control signal provided by the first control terminal TC1, and the second control signal provided by the second control terminal TC2. The first control terminal TC1 is electrically connected to the ni-th level first scan signal output terminal, and the second control terminal TC2 is electrically connected to the ni-th level second scan signal output terminal; i is a positive integer.

[0391] The control circuit 132 is connected to the first control node CS1, the drive control terminal DC, and the drive signal output terminal GT, respectively, and is used to provide a drive signal to the drive signal output terminal GT under the control of the potential of the first control node CS1 and the drive control signal provided by the drive control terminal DC.

[0392] In at least one embodiment shown in Figure 13B, the drive control terminal can be the first scan signal output terminal ST or the second scan signal output terminal FT.

[0393] In at least one embodiment shown in Figure 13B, the driving circuit is an nth-stage driving circuit, the first scan signal output terminal is the nth-stage first scan signal output terminal, the second scan signal output terminal is the nth-stage second scan signal output terminal, and n is a positive integer.

[0394] As shown in Figure 13C, based on at least one embodiment of the driving circuit shown in Figure 10, the at least one embodiment of the driving circuit further includes a control signal generation circuit 131 and a control circuit 132; the scanning signal includes a first scanning signal and a second scanning signal;

[0395] The scanning signal generation circuit 50 is electrically connected to the first scanning signal output terminal ST and the second scanning signal output terminal FT, respectively, and is used to provide a first scanning signal through the first scanning signal output terminal ST and a second scanning signal through the second scanning signal output terminal FT.

[0396] The control signal generation circuit 131 is electrically connected to the enable signal terminal EN and the first control node CS1, respectively. The control signal generation circuit 131 is also electrically connected to the first scan signal output terminal ST, the second scan signal output terminal FT, the first control terminal TC1, and the second control terminal TC2, respectively. It is used to control the connection or disconnection between the enable signal terminal EN and the first control node CS1 under the control of the first scan signal, the second scan signal, the first control signal provided by the first control terminal TC1, and the second control signal provided by the second control terminal TC2. The first control terminal TC1 is electrically connected to the ni-th level first scan signal output terminal, and the second control terminal TC2 is electrically connected to the ni-th level second scan signal output terminal; i is a positive integer.

[0397] The control circuit 132 is connected to the first control node CS1, the drive control terminal DC, and the drive signal output terminal GT, respectively, and is used to provide a drive signal to the drive signal output terminal GT under the control of the potential of the first control node CS1 and the drive control signal provided by the drive control terminal DC.

[0398] In at least one embodiment shown in Figure 13C, the drive control terminal can be the first scan signal output terminal ST or the second scan signal output terminal FT.

[0399] In at least one embodiment shown in Figure 13C, the driving circuit is an nth-stage driving circuit, the first scan signal output terminal is the nth-stage first scan signal output terminal, the second scan signal output terminal is the nth-stage second scan signal output terminal, and n is a positive integer.

[0400] In at least one embodiment shown in Figures 13C and 13D, the reset circuit is located at the front end of the startup circuit, which is advantageous for layout and wiring and has good compatibility with related schemes.

[0401] As shown in Figure 13D, based on at least one embodiment of the driving circuit shown in Figure 11, the at least one embodiment of the driving circuit further includes a control signal generation circuit 131 and a control circuit 132; the scanning signal includes a first scanning signal and a second scanning signal;

[0402] The scanning signal generation circuit 50 is electrically connected to the first scanning signal output terminal ST and the second scanning signal output terminal FT, respectively, and is used to provide a first scanning signal through the first scanning signal output terminal ST and a second scanning signal through the second scanning signal output terminal FT.

[0403] The control signal generation circuit 131 is electrically connected to the enable signal terminal EN and the first control node CS1, respectively. The control signal generation circuit 131 is also electrically connected to the first scan signal output terminal ST, the second scan signal output terminal FT, the first control terminal TC1, and the second control terminal TC2, respectively. It is used to control the connection or disconnection between the enable signal terminal EN and the first control node CS1 under the control of the first scan signal, the second scan signal, the first control signal provided by the first control terminal TC1, and the second control signal provided by the second control terminal TC2. The first control terminal TC1 is electrically connected to the ni-th level first scan signal output terminal, and the second control terminal TC2 is electrically connected to the ni-th level second scan signal output terminal; i is a positive integer.

[0404] The control circuit 132 is connected to the first control node CS1, the drive control terminal DC, and the drive signal output terminal GT, respectively, and is used to provide a drive signal to the drive signal output terminal GT under the control of the potential of the first control node CS1 and the drive control signal provided by the drive control terminal DC.

[0405] In at least one embodiment shown in Figure 13D, the drive control terminal can be the first scan signal output terminal ST or the second scan signal output terminal FT.

[0406] In at least one embodiment shown in Figure 13D, the driving circuit is an nth-stage driving circuit, the first scan signal output terminal is the nth-stage first scan signal output terminal, the second scan signal output terminal is the nth-stage second scan signal output terminal, and n is a positive integer.

[0407] In at least one embodiment of this disclosure, as shown in FIG14, based on at least one embodiment of the driving circuit shown in FIG13A, the control circuit may include a first control sub-circuit 141, a second control sub-circuit 142 and a first inverting circuit 143.

[0408] The first control sub-circuit 141 is electrically connected to the first control node CS1, the second control node CS2, the first voltage signal terminal V1, and the second voltage signal terminal V2, respectively. It is used to control the second control node CS2 to connect with the first voltage signal terminal V1 or the second voltage signal terminal V2 under the control of the potential of the first control node CS1, and to control the first control node CS1 to connect with the first voltage signal terminal V1 or the second voltage signal terminal V2 under the control of the potential of the second control node CS2.

[0409] The second control sub-circuit 142 is electrically connected to the drive control terminal DC, the third control node CS3, the first voltage signal terminal V1, and the second voltage signal terminal V2, respectively, and is used to control the third control node CS3 to connect with the first voltage signal terminal V1 or the second voltage signal terminal V2 under the control of the drive control signal.

[0410] The first inverting circuit 143 is electrically connected to the third control node CS3 and the drive signal output terminal GT, respectively, and is used to invert the potential of the third control node CS3 to obtain the drive signal.

[0411] Optionally, the first voltage signal terminal can be a first high voltage terminal, and the second voltage signal terminal can be a first low voltage terminal.

[0412] In at least one embodiment of this disclosure, when the display area is in a normal refresh state, the enable signal provided by the enable signal terminal is a valid enable signal;

[0413] When the display area is in the first display state, after the pixel circuit in the area adjacent to the last area completes the display refresh in the at least one holding frame, the enable signal is an invalid enable signal.

[0414] In at least one embodiment of this disclosure, the scanning signal includes a first scanning signal and a second scanning signal; the scanning signal generation circuit further includes a first node control circuit, a second on / off control circuit, a first output node control circuit, a second output node control circuit, a first output circuit, a first energy storage circuit, and a second inverting circuit; the control clock signal terminal includes a first control clock signal terminal, a second control clock signal terminal, and a third control clock signal terminal; the input control clock signal terminal is the first control clock signal terminal;

[0415] The first node control circuit is electrically connected to the first control clock signal terminal, the second voltage signal terminal, the first node, and the first output control node, respectively. It is used to write the second voltage signal provided by the second voltage signal terminal into the first node under the control of the first control clock signal provided by the first control clock signal terminal, and to write the first control clock signal into the first node under the control of the potential of the first output control node.

[0416] The second on / off control circuit is electrically connected to the second voltage signal terminal, the first node, and the second output control node, respectively, and is used to control the connection or disconnection between the first node and the second output control node under the control of the second voltage signal.

[0417] The first output node control circuit is electrically connected to the first output node, the second control clock signal terminal, the second output control node, the first output control node, and the first voltage signal terminal, respectively. It is used to control the potential of the first output node under the control of the potential of the second output control node and the second control clock signal provided by the second control clock signal terminal, and to write the first voltage signal provided by the first voltage signal terminal into the first output node under the control of the potential of the first output control node.

[0418] The second output node control circuit is electrically connected to the second output node, the first output node, the first voltage signal terminal, and the third control clock signal terminal, respectively, and is used to control the potential of the second output node under the control of the potential of the first output node and under the control of the third control clock signal provided by the third control clock signal terminal.

[0419] The first output circuit is electrically connected to the first output node, the first voltage signal terminal and the first scan signal output terminal respectively, and is used to write the first voltage signal to the first scan signal output terminal under the control of the potential of the first output node;

[0420] The first energy storage circuit is electrically connected to the first output node and is used to maintain the potential of the first output node;

[0421] The second inverting circuit is electrically connected to the first scan signal output terminal and the second scan signal output terminal respectively, and is used to invert the first scan signal to obtain and output the second scan signal through the second scan signal output terminal.

[0422] Optionally, the third control clock signal terminal and the first control clock signal terminal can be the same control clock signal terminal.

[0423] As shown in Figure 15, based on at least one embodiment shown in Figure 14, the scanning signal generation circuit may include a first on / off control circuit 151 and a second output circuit 152.

[0424] The first on / off control circuit 151 is electrically connected to the second voltage signal terminal V2, the first output control node PD1, and the second output node PD, respectively, and is used to control the connection or disconnection between the first output control node PD1 and the second output node P1 under the control of the second voltage signal provided by the second voltage signal terminal V2.

[0425] The second output circuit 152 is electrically connected to the second output node PD, the first scan signal output terminal ST, and the second voltage signal terminal V2, respectively, and is used to control the connection or disconnection between the first scan signal output terminal ST and the second voltage signal terminal V2 under the control of the potential of the second output node PD.

[0426] The scanning signal generation circuit further includes a first node control circuit 153, a second on / off control circuit 154, a first output node control circuit 155, a second output node control circuit 156, a first output circuit 157, a first energy storage circuit 158, and a second inverting circuit 159; the control clock signal terminal includes a first control clock signal terminal CK1, a second control clock signal terminal CK2, and a third control clock signal terminal CK3; the input control clock signal terminal is the first control clock signal terminal CK1;

[0427] The first node control circuit 153 is electrically connected to the first control clock signal terminal CK1, the second voltage signal terminal V2, the first node PU1, and the first output control node PD1, respectively. It is used to write the second voltage signal provided by the second voltage signal terminal V2 into the first node under the control of the first control clock signal provided by the first control clock signal terminal CK1, and to write the first control clock signal into the first node PU1 under the control of the potential of the first output control node PD1.

[0428] The second on / off control circuit 154 is electrically connected to the second voltage signal terminal V2, the first node PU1, and the second output control node PU2, respectively, and is used to control the connection or disconnection between the first node PU1 and the second output control node PU2 under the control of the second voltage signal.

[0429] The first output node control circuit 155 is electrically connected to the first output node PU, the second control clock signal terminal CK2, the second output control node PU2, the first output control node PD1, and the first voltage signal terminal V1, respectively. It is used to control the potential of the first output node PU under the control of the potential of the second output control node PU2 and the second control clock signal provided by the second control clock signal terminal CK2, and to write the first voltage signal provided by the first voltage signal terminal V1 into the first output node PU under the control of the potential of the first output control node PD1.

[0430] The second output node control circuit 156 is electrically connected to the second output node PD, the first output node PU, the first voltage signal terminal V1 and the third control clock signal terminal CK3 respectively, and is used to control the potential of the second output node PD under the control of the potential of the first output node PU and under the control of the third control clock signal provided by the third control clock signal terminal CK3.

[0431] The first output circuit 157 is electrically connected to the first output node PU, the first voltage signal terminal V1 and the first scan signal output terminal ST respectively, and is used to write the first voltage signal provided by the first voltage signal terminal V1 into the first scan signal output terminal ST under the control of the potential of the first output node PU.

[0432] The first energy storage circuit 158 ​​is electrically connected to the first output node PU and is used to maintain the potential of the first output node PU.

[0433] The second inverting circuit 159 is electrically connected to the first scan signal output terminal ST and the second scan signal output terminal FT, respectively, and is used to invert the first scan signal to obtain and output the second scan signal through the second scan signal output terminal FT;

[0434] The input control clock signal terminal is the first control clock signal terminal CK1.

[0435] In at least one embodiment of this disclosure, the scanning signal includes a first scanning signal and a second scanning signal; the scanning signal generation circuit further includes a first node control circuit, a second on / off control circuit, a first output node control circuit, a second output node control circuit, a first output circuit, a first energy storage circuit, and a second inverting circuit; the control clock signal terminal includes a first control clock signal terminal, a second control clock signal terminal, and a third control clock signal terminal; the input control clock signal terminal is the first control clock signal terminal;

[0436] The first node control circuit is electrically connected to the second control clock signal terminal, the second voltage signal terminal, the first node, and the first output control node, respectively. It is used to write the second voltage signal provided by the second voltage signal terminal into the first node under the control of the second control clock signal provided by the second control clock signal terminal, and to write the second control clock signal into the first node under the control of the potential of the first output control node.

[0437] The second on / off control circuit is electrically connected to the second voltage signal terminal, the first node, and the second output control node, respectively, and is used to control the connection or disconnection between the first node and the second output control node under the control of the second voltage signal.

[0438] The first output node control circuit is electrically connected to the first output node, the third control clock signal terminal, the second output control node, the first output control node, and the first voltage signal terminal, respectively. It is used to control the potential of the first output node under the control of the potential of the second output control node and the third control clock signal provided by the third control clock signal terminal, and to write the first voltage signal provided by the first voltage signal terminal into the first output node under the control of the potential of the first output control node.

[0439] The second output node control circuit is electrically connected to the second output node, the first output node, the first voltage signal terminal, and the first control clock signal terminal, respectively, and is used to control the potential of the second output node under the control of the potential of the first output node and under the control of the first control clock signal provided by the first control clock signal terminal;

[0440] The first output circuit is electrically connected to the first output node, the first voltage signal terminal and the first scan signal output terminal respectively, and is used to write the first voltage signal to the first scan signal output terminal under the control of the potential of the first output node;

[0441] The first energy storage circuit is electrically connected to the first output node and is used to maintain the potential of the first output node;

[0442] The second inverting circuit is electrically connected to the first scan signal output terminal and the second scan signal output terminal respectively, and is used to invert the first scan signal to obtain and output the second scan signal through the second scan signal output terminal.

[0443] As shown in FIG16, based on at least one embodiment shown in FIG13A, the scanning signal generation circuit may include a first on / off control circuit 151 and a second output circuit 152.

[0444] The first on / off control circuit 151 is electrically connected to the second voltage signal terminal V2, the first output control node PD1, and the second output node PD, respectively, and is used to control the connection or disconnection between the first output control node PD1 and the second output node P1 under the control of the second voltage signal provided by the second voltage signal terminal V2.

[0445] The second output circuit 152 is electrically connected to the second output node PD, the first scan signal output terminal ST, and the second voltage signal terminal V2, respectively, and is used to control the connection or disconnection between the first scan signal output terminal ST and the second voltage signal terminal V2 under the control of the potential of the second output node PD.

[0446] The scanning signal generation circuit further includes a first node control circuit 153, a second on / off control circuit 154, a first output node control circuit 155, a second output node control circuit 156, a first output circuit 157, a first energy storage circuit 158, and a second inverting circuit 159; the control clock signal terminal includes a first control clock signal terminal CK1, a second control clock signal terminal CK2, and a third control clock signal terminal CK3; the input control clock signal terminal is the first control clock signal terminal CK1;

[0447] The first node control circuit 153 is electrically connected to the second control clock signal terminal CK2, the second voltage signal terminal V2, the first node PU1, and the first output control node PD1, respectively. It is used to write the second voltage signal provided by the second voltage signal terminal V2 into the first node PU1 under the control of the second control clock signal provided by the second control clock signal terminal CK2, and to write the second control clock signal into the first node PU1 under the control of the potential of the first output control node PD1.

[0448] The second on / off control circuit 154 is electrically connected to the second voltage signal terminal V2, the first node PU1, and the second output control node PU2, respectively, and is used to control the connection or disconnection between the first node PU1 and the second output control node PU2 under the control of the second voltage signal.

[0449] The first output node control circuit 155 is electrically connected to the first output node PU, the third control clock signal terminal CK3, the second output control node PU2, the first output control node PD1, and the first voltage signal terminal V1, respectively. It is used to control the potential of the first output node PU under the control of the potential of the second output control node PU2 and the third control clock signal provided by the third control clock signal terminal CK3, and to write the first voltage signal provided by the first voltage signal terminal V1 into the first output node PU under the control of the potential of the first output control node PD1.

[0450] The second output node control circuit 156 is electrically connected to the second output node PD, the first output node PU, the first voltage signal terminal V1 and the first control clock signal terminal CK1 respectively, and is used to control the potential of the second output control node PU2 under the control of the potential of the first output node PU and under the control of the first control clock signal provided by the first control clock signal terminal CK1.

[0451] The first output circuit 157 is electrically connected to the first output node PU, the first voltage signal terminal V1 and the first scan signal output terminal ST respectively, and is used to write the first voltage signal into the first scan signal output terminal ST under the control of the potential of the first output node PU.

[0452] The first energy storage circuit 158 ​​is electrically connected to the first output node PU and is used to maintain the potential of the first output node PU.

[0453] The second inverting circuit 159 is electrically connected to the first scan signal output terminal ST and the second scan signal output terminal FT, respectively, and is used to invert the first scan signal to obtain and output the second scan signal through the second scan signal output terminal FT.

[0454] The display substrate described in at least one embodiment of this disclosure includes a driving module; the driving module includes multiple cascaded driving circuits;

[0455] In at least one stage of the driving circuit, the signal input terminal is electrically connected to the start signal line, and the control signal generation circuit is electrically connected to the start signal line and the inverted start signal line respectively.

[0456] In at least one embodiment of this disclosure, the first scan signal output terminal of the nth stage driving circuit is electrically connected to the signal input terminal of the (n+1)th stage driving circuit;

[0457] The first scan signal output terminal of the nth stage driving circuit and the second scan signal output terminal of the nth stage driving circuit are electrically connected to the control signal generation circuit of the (n+1)th stage driving circuit, where n is a positive integer.

[0458] In the 2a-level drive circuit, the first control clock signal terminal is electrically connected to the first clock signal line, the second control clock signal terminal is electrically connected to the second clock signal line, and the third control clock signal terminal is electrically connected to the third clock signal line.

[0459] In the 2a+1 stage drive circuit, the first control clock signal terminal is electrically connected to the third clock signal line, the second control clock signal terminal is electrically connected to the fourth clock signal line, and the third control clock signal terminal is electrically connected to the first clock signal line.

[0460] 'a' is a natural number.

[0461] In at least one embodiment of this disclosure, the first scan signal output terminal of the nth stage driving circuit is electrically connected to the signal input terminal of the (n+1)th stage driving circuit;

[0462] The first scan signal output terminal of the nth stage driving circuit and the second scan signal output terminal of the nth stage driving circuit are electrically connected to the control signal generation circuit of the (n+1)th stage driving circuit, where n is a positive integer.

[0463] In the 4a-level driving circuit, the first control clock signal terminal is connected to the first clock signal line, and the second control clock signal terminal is connected to the second clock signal line; in the 4a+1-level driving circuit, the first control clock signal terminal is connected to the second clock signal line, and the second control clock signal terminal is connected to the third clock signal line; in the 4a+2-level driving circuit, the first control clock signal terminal is connected to the third clock signal line, and the second control clock signal terminal is connected to the fourth clock signal line; in the 4a+3-level driving circuit, the first control clock signal terminal is connected to the fourth clock signal line, and the second control clock signal terminal is connected to the first clock signal line; where 'a' is a natural number.

[0464] In at least one embodiment of this disclosure, the first scan signal output terminal of the nth stage driving circuit is electrically connected to the signal input terminal of the (n+1)th stage driving circuit;

[0465] The first scan signal output terminal of the nth stage driving circuit and the second scan signal output terminal of the nth stage driving circuit are electrically connected to the control signal generation circuit of the (n+1)th stage driving circuit, where n is a positive integer.

[0466] In the 4a-level driving circuit, the first control clock signal terminal is connected to the first clock signal line, the second control clock signal terminal is connected to the second clock signal line, and the third control clock signal terminal is connected to the third clock signal line; in the 4a+1-level driving circuit, the first control clock signal terminal is connected to the second clock signal line, the second control clock signal terminal is connected to the third clock signal line, and the third control clock signal terminal is connected to the fourth clock signal line; in the 4a+2-level driving circuit, the first control clock signal terminal is connected to the third clock signal line, the second control clock signal terminal is connected to the fourth clock signal line, and the third control clock signal terminal is connected to the first clock signal line; in the 4a+3-level driving circuit, the first control clock signal terminal is connected to the fourth clock signal line, the second control clock signal terminal is connected to the first clock signal line, and the third control clock signal terminal is connected to the second clock signal line; where 'a' is a natural number.

[0467] As shown in Figure 17 (where only the scan signal generation circuit, startup circuit, and reset circuit are shown), based on at least one embodiment of the drive circuit shown in Figure 15,

[0468] The first reset sub-circuit 81 includes a first reset transistor RT1, the second reset sub-circuit 82 includes a second reset transistor RT2, and the startup circuit 80 includes an input transistor T0.

[0469] The gate of RT1 is electrically connected to the reset signal terminal Trst, the source of RT1 is electrically connected to the first low voltage terminal VGL1, and the drain of RT1 is electrically connected to the first output control node PD1.

[0470] The gate of RT2 is electrically connected to the reset signal terminal Trst, the source of RT2 is electrically connected to the reset input node Ri, and the drain of RT2 is electrically connected to the first output control node PD1.

[0471] The gate of T0 is electrically connected to the first control clock signal terminal CK1, the source of T0 is electrically connected to the signal input terminal SR, and the drain of T0 is electrically connected to the reset input node Ri.

[0472] The first on / off control circuit 151 includes a first transistor T1; the second output circuit 152 includes a second output transistor TS2; the first node control circuit 153 includes a second transistor T2 and a third transistor T3; the second on / off control circuit 154 includes a fourth transistor T4; the first output node control circuit 155 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1; the second output node control circuit 156 includes an eighth transistor T8, a ninth transistor T9, and a third capacitor C3; the first output circuit 157 includes a first output transistor TS1; the first energy storage circuit 158 ​​includes a second capacitor C2; the second inverting circuit 159 includes a tenth transistor T10 and an eleventh transistor T11; at least one embodiment of the driving circuit further includes a twelfth transistor T12.

[0473] The gate of T1 is electrically connected to the first low voltage terminal VGL1, the source of T1 is electrically connected to the first output control node PD1, and the drain of T1 is electrically connected to the second output node PD.

[0474] The gate of T2 is electrically connected to the first output control node PD1, the source of T2 is electrically connected to the first control clock signal terminal CK1, and the drain of T2 is electrically connected to the first node PU1.

[0475] The gate of T3 is electrically connected to the first control clock signal terminal CK1, the source of T3 is electrically connected to the first low voltage terminal VGL1, and the drain of T3 is electrically connected to the first node PU1.

[0476] The gate of T4 is electrically connected to the first low voltage terminal VGL1, the source of T4 is electrically connected to the first node PU1, and the drain of T4 is electrically connected to the second output control node PU2.

[0477] The gate of T5 is electrically connected to the first output control node PD1, the source of T5 is electrically connected to the first high voltage terminal VGH1, and the drain of T5 is electrically connected to the first output node PU.

[0478] The gate of T6 is electrically connected to the second output control node PU2, the source of T6 is electrically connected to the second control clock signal terminal CK2, and the drain of T6 is electrically connected to the source of T7.

[0479] The gate of T7 is electrically connected to the second control clock signal terminal CK2, and the drain of T7 is electrically connected to the first output node PU.

[0480] The first end of C1 is electrically connected to PU2, and the second end of C1 is electrically connected to the source of T7.

[0481] The gate of T8 is electrically connected to the second output node PD, the source of T8 is electrically connected to the third control clock signal terminal CK3, and the drain of T8 is electrically connected to the source of T9.

[0482] The gate of T9 is electrically connected to the first output node PU, and the drain of T9 is electrically connected to the first high voltage terminal VGH1.

[0483] The first terminal of C3 is electrically connected to the second output node PD, and the second terminal of C3 is electrically connected to the source of T9.

[0484] The gate of TS1 is electrically connected to the first output node PU, the source of TS1 is electrically connected to the first high voltage terminal VGH1, and the drain of TS1 is electrically connected to the first scan signal output terminal ST.

[0485] The first end of C2 is electrically connected to the first output node PU, and the second end of C2 is electrically connected to the first high voltage terminal VGH1.

[0486] The gate of TS2 is electrically connected to the second output node PD, the source of TS2 is electrically connected to the first low voltage terminal VGL1, and the drain of TS2 is electrically connected to the first scan signal output terminal ST.

[0487] The gate of T12 is electrically connected to the control voltage terminal VEL, the source of T12 is electrically connected to the first high voltage terminal VGH1, and the drain of T12 is electrically connected to the first output control node PD1.

[0488] The gate of T10 is electrically connected to the first scan signal output terminal ST, the source of T10 is electrically connected to the first high voltage terminal VGH1, and the drain of T10 is electrically connected to the second scan signal output terminal FT.

[0489] The gate of T11 is electrically connected to the first scan signal output terminal ST, the source of T11 is electrically connected to the first low voltage terminal VGL1, and the drain of T11 is electrically connected to the second scan signal output terminal FT.

[0490] In at least one embodiment shown in Figure 17, RT2 is a p-type transistor, RT1 is an n-type transistor, T0 is a p-type transistor, the transistors included in the scan signal generation circuit are all p-type transistors, and the reset voltage terminal is the first low voltage terminal VGL1.

[0491] The difference between the at least one embodiment shown in Figure 18 and the at least one embodiment shown in Figure 17 is as follows: the gate of RT1 is electrically connected to Ri; the source of RT1 is electrically connected to the first high voltage terminal VGH1.

[0492] Both RT1 and RT2 are p-type transistors.

[0493] In at least one embodiment shown in Figure 18, when Trst provides a high voltage signal, RT2 is turned off, and when Ri provides a low voltage signal, RT1 is turned on, controlling the connection between PD1 and VGH1. T1 is turned on, the potential of PD is high voltage, and TS2 is turned off.

[0494] When the potential of the second control clock signal provided by CK2 is pulled down, the potential of PU is pulled low, TS1 is turned on, and ST provides a high voltage signal; T10 is turned off, T11 is turned on, and FT provides a low voltage signal.

[0495] That is, when ST provides an invalid first scan signal and FT provides an invalid second scan signal, ST provides a high voltage signal and FT provides a low voltage signal;

[0496] Furthermore, in at least one embodiment shown in Figure 18, when Trst provides a high voltage signal and CK1 provides a low voltage signal, only the drive circuit with the low voltage input signal is reset. The input signals of other drive circuits are high voltage signals, so they do not need to be reset, which can reduce the reset load and power consumption.

[0497] The differences between the at least one embodiment shown in Figure 19 and the at least one embodiment shown in Figure 17 are as follows:

[0498] The drain of RT1 is electrically connected to the reset output node Ro;

[0499] The source of RT2 is electrically connected to the signal input terminal SR, and the drain of RT2 is electrically connected to the reset output node Ro.

[0500] The gate of T0 is electrically connected to the first control clock signal terminal CK1, the source of T0 is electrically connected to the reset output node Ro, and the drain of T0 is electrically connected to the first output control node PD1.

[0501] RT2 is an n-type transistor, RT1 is a p-type transistor, and T0 is a p-type transistor.

[0502] In at least one embodiment of this disclosure, the driving circuit may further include a second control capacitor and a third control capacitor;

[0503] The first terminal of the second control capacitor is electrically connected to the first control node, and the second terminal of the second control capacitor is electrically connected to the first low voltage terminal.

[0504] The first terminal of the third control capacitor is electrically connected to the third control node, and the second terminal of the third control capacitor is electrically connected to the first low-voltage terminal.

[0505] For example, Figures 20 and 21 each illustrate a method for reducing power consumption through partial refresh: After the pixel circuit in the second region 102 adjacent to the third region 103 (the last region) completes the display refresh in at least one hold frame, the frequency of the first control clock signal provided by the first control clock signal terminal CK1 and the frequency of the second control clock signal provided by the second control clock signal terminal CK2 are reduced to half of the previous frequency. k , where k is a positive integer, 1 / 2 k For example, it could be 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32, etc.

[0506] As shown in Figure 20, during the frame blanking period between two adjacent frames, the reset signal terminal Trst outputs an effective level (in at least one embodiment shown in Figure 20, the effective level can be a high level), controlling all reset circuits in the display substrate to reset, so that all driving circuits in the display substrate output invalid driving signals, thereby solving the problem that after the control clock signal is down-frequency, it cannot complete the transmission of all unit levels, causing the next frame to continue outputting, which in turn causes pixel charging abnormalities and display abnormalities, and achieves the effect of further reducing local refresh power consumption. Taking at least one embodiment of the driving circuit shown in Figure 23A as an example, when the first scan signal output by the first scan signal output terminal ST outputs a valid first scan signal (in at least one embodiment shown in Figure 23A, the valid first scan signal can be a high voltage signal), CT5 is turned off, CT6 is turned on, and the enable signal is transmitted to the third control node CS3; when the first scan signal output by the first scan signal output terminal ST outputs an invalid first scan signal (in at least one embodiment shown in Figure 23A, the invalid first scan signal can be a low voltage signal), CT5 is turned on, CT6 is turned off, the high voltage signal is transmitted to the third control node CS3, CT7 is turned off, CT8 is turned on, GT provides a low voltage signal, and GT provides an invalid driving signal.

[0507] Taking Figure 20 or Figure 21 as an example, when the potential of the reset signal provided by the reset signal terminal Trst changes from low level to high level, the reset signal is a valid reset signal, which controls the second reset transistor RT2 included in the reset circuit in Figure 23 to turn off, preventing the signal input terminal SR from transmitting the input signal to the gate of the second transistor T2, the gate of the fifth transistor T5, and the gate of the second output transistor TS2; when Trst provides a valid reset signal, it controls the first reset transistor RT1 to turn on, transmitting the reset voltage provided by the reset voltage terminal (the reset voltage terminal can be, for example, the first high voltage terminal or the first low voltage terminal) to the gate of the second transistor T2, the gate of the fifth transistor T5, and the gate of the second output transistor TS2. Taking Figure 23 as an example, the first reset transistor RT1 is connected to the first low-voltage terminal VGL1. When the first reset transistor RT1 is turned on, it transmits a low-level signal to the gate of the fifth transistor T5 and the gate of the second output transistor TS2. At this time, the fifth transistor T5 is turned on, transmitting the high-level signal provided by the first high-voltage terminal VGH1 to the gate of the first output transistor TS1, causing the first output transistor TS1 to turn off. Simultaneously, the second output transistor TS2 is turned on, and the first scan signal output terminal ST outputs an invalid first scan signal. In at least one embodiment shown in Figure 23A, the invalid first scan signal is a low-voltage signal. The second scan signal output terminal FT outputs an invalid second scan signal. In at least one embodiment shown in Figure 23A, the invalid second scan signal is a high-voltage signal. The drive signal output terminal GT outputs an invalid drive signal. In at least one embodiment shown in Figure 23A, the invalid drive signal is a low-voltage signal. After reset, the drive circuit of each row in the non-display area outputs an invalid drive signal, solving the problem of display abnormalities caused by the output pulse continuing to shift during the next refresh frame. In at least one embodiment of this disclosure, when the scan signal generation circuit outputs an invalid first scan signal and an invalid second scan signal, the driving circuit provides an invalid driving signal to the gate of the transistor in the pixel circuit through the driving signal output terminal. When the transistor in the pixel circuit is an n-type transistor, the invalid driving signal can be a low-voltage signal, and when the transistor in the pixel circuit is a p-type transistor, the invalid driving signal can be a high-voltage signal.

[0508] As shown in Figure 21, after the pixel circuit in the second region 102 adjacent to the third region 103 (the third driving region 103 is the last region) completes the display refresh in at least one holding frame, the reset signal terminal Trst outputs a valid reset signal (in at least one embodiment shown in Figure 21, the valid reset signal is a high voltage signal), which controls all reset circuits in the display substrate to reset all driving circuits in the display substrate. This solves the problem that after the control clock signal is down-frequency, it cannot complete all unit-level transmission, causing the second frame to continue outputting again, which in turn causes pixel charging abnormalities and display abnormalities. This achieves the effect of further reducing local refresh power consumption.

[0509] Figure 22 illustrates another method for controlling the clock signal frequency reduction, instead of directly reducing the frequency to half of its previous value. k Instead, it controls the clock signal to periodically switch between a fixed potential and a pulse signal at the original frequency. Specifically, it maintains a fixed potential for a period of time, then gives several periodic pulses, and then maintains a fixed potential for a period of time. The cycle repeats, and the stopping period is generally 100us to 100000us.

[0510] Alternatively, a combination of two frequency reduction methods can be used to achieve irregular frequency reduction, reduce regular flickering, and decrease the visibility of flickering.

[0511] As shown in Figure 23A, based on at least one embodiment of the driving circuit shown in Figure 15,

[0512] The first reset circuit includes a first reset transistor RT1, the second reset circuit includes a second reset transistor RT2, and the startup circuit includes an input transistor T0.

[0513] The gate of RT1 is electrically connected to the reset signal terminal Trst, the source of RT1 is electrically connected to the first low voltage terminal VGL1, and the drain of RT1 is electrically connected to the first output control node PD1.

[0514] The gate of RT2 is electrically connected to the reset signal terminal Trst, the source of RT2 is electrically connected to the reset input node Ri, and the drain of RT2 is electrically connected to the first output control node PD1.

[0515] The gate of T0 is electrically connected to the first control clock signal terminal CK1, the source of T0 is electrically connected to the signal input terminal SR, and the drain of T0 is electrically connected to the reset input node Ri.

[0516] The scanning signal generation circuit further includes a first node control circuit 153, a second on / off control circuit 154, a first output node control circuit 155, a second output node control circuit 156, a first output circuit 157, a first energy storage circuit 158, and a second inverting circuit 159.

[0517] The first on / off control circuit includes a first transistor T1; the second output circuit includes a second output transistor TS2; the first node control circuit includes a second transistor T2 and a third transistor T3; the second on / off control circuit includes a fourth transistor T4; the first output node control circuit includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1; the second output node control circuit includes an eighth transistor T8, a ninth transistor T9, and a third capacitor C3; the first output circuit includes a first output transistor TS1; the first energy storage circuit includes a second capacitor C2; the second inverting circuit includes a tenth transistor T10 and an eleventh transistor T11; at least one embodiment of the driving circuit further includes a twelfth transistor T12.

[0518] The gate of T1 is electrically connected to the first low voltage terminal VGL1, the source of T1 is electrically connected to the first output control node PD1, and the drain of T1 is electrically connected to the second output node PD.

[0519] The gate of T2 is electrically connected to the first output control node PD1, the source of T2 is electrically connected to the first control clock signal terminal CK1, and the drain of T2 is electrically connected to the first node PU1.

[0520] The gate of T3 is electrically connected to the first control clock signal terminal CK1, the source of T3 is electrically connected to the first low voltage terminal VGL1, and the drain of T3 is electrically connected to the first node PU1.

[0521] The gate of T4 is electrically connected to the first low voltage terminal VGL1, the source of T4 is electrically connected to the first node PU1, and the drain of T4 is electrically connected to the second output control node PU2.

[0522] The gate of T5 is electrically connected to the first output control node PD1, the source of T5 is electrically connected to the first high voltage terminal VGH1, and the drain of T5 is electrically connected to the first output node PU.

[0523] The gate of T6 is electrically connected to the second output control node PU2, the source of T6 is electrically connected to the second control clock signal terminal CK2, and the drain of T6 is electrically connected to the source of T7.

[0524] The gate of T7 is electrically connected to the second control clock signal terminal CK2, and the drain of T7 is electrically connected to the first output node PU.

[0525] The first end of C1 is electrically connected to PU2, and the second end of C1 is electrically connected to the source of T7.

[0526] The gate of T8 is electrically connected to the second output node PD, the source of T8 is electrically connected to the third control clock signal terminal CK3, and the drain of T8 is electrically connected to the source of T9.

[0527] The gate of T9 is electrically connected to the first output node PU, and the drain of T9 is electrically connected to the first high voltage terminal VGH1.

[0528] The first terminal of C3 is electrically connected to the second output node PD, and the second terminal of C3 is electrically connected to the source of T9.

[0529] The gate of TS1 is electrically connected to the first output node PU, the source of TS1 is electrically connected to the first high voltage terminal VGH1, and the drain of TS1 is electrically connected to the first scan signal output terminal ST.

[0530] The first end of C2 is electrically connected to the first output node PU, and the second end of C2 is electrically connected to the first high voltage terminal VGH1.

[0531] The gate of TS2 is electrically connected to the second output node PD, the source of TS2 is electrically connected to the first low voltage terminal VGL1, and the drain of TS2 is electrically connected to the first scan signal output terminal ST.

[0532] The gate of T12 is electrically connected to the control voltage terminal VEL, the source of T12 is electrically connected to the first high voltage terminal VGH1, and the drain of T12 is electrically connected to the first output control node PD1.

[0533] The gate of T10 is electrically connected to the first scan signal output terminal ST, the source of T10 is electrically connected to the first high voltage terminal VGH1, and the drain of T10 is electrically connected to the second scan signal output terminal FT.

[0534] The gate of T11 is electrically connected to the first scan signal output terminal ST, the source of T11 is electrically connected to the first low voltage terminal VGL1, and the drain of T11 is electrically connected to the second scan signal output terminal FT.

[0535] The scanning signal generation circuit also includes a first control capacitor CC1;

[0536] The first terminal of CC1 is electrically connected to the first scan signal output terminal ST, and the second terminal of CC1 is electrically connected to the first low voltage terminal VGL1.

[0537] The control signal generation circuit 131 includes a ninth control transistor CT9, a tenth control transistor CT10, an eleventh control transistor CT11, and a twelfth control transistor CT12.

[0538] The gate of CT9 is electrically connected to the second control terminal TC2, the second control terminal TC2 is electrically connected to the output terminal of the second scan signal of the (n-1)th stage, the source of CT9 is electrically connected to the enable signal terminal EN, and the drain of CT9 is electrically connected to the source of CT11.

[0539] The gate of CT10 is electrically connected to the first control terminal TC1, the first control terminal TC1 is electrically connected to the first scan signal output terminal of the (n-1)th stage, the source of CT10 is electrically connected to the enable signal terminal EN, and the drain of CT10 is electrically connected to the source of CT12.

[0540] The gate of CT11 is electrically connected to the first scan signal output terminal ST, and the drain of CT11 is electrically connected to the first control node CS1.

[0541] The gate of CT12 is electrically connected to the second scan signal output terminal FT, and the drain of CT12 is electrically connected to the first control node CS1.

[0542] The first control sub-circuit 141 includes a first control transistor CT1, a second control transistor CT2, a third control transistor CT3, and a fourth control transistor CT4;

[0543] The gate of CT1 is electrically connected to the first control node CS1, the source of CT1 is electrically connected to the first high voltage terminal VGH1, and the drain of CT1 is electrically connected to the second control node CS2.

[0544] The gate of CT2 is electrically connected to the first control node CS1, the source of CT2 is electrically connected to the second control node CS2, and the drain of CT2 is electrically connected to the first low voltage terminal VGL1.

[0545] The gate of CT3 is electrically connected to the second control node CS2, the source of CT3 is electrically connected to the first high voltage terminal VGH1, and the drain of CT3 is electrically connected to the first control node CS1.

[0546] The gate of CT4 is electrically connected to the second control node CS2, the source of CT4 is electrically connected to the first control node CS1, and the drain of CT4 is electrically connected to the first low voltage terminal VGL1.

[0547] The second control sub-circuit 142 includes a fifth control transistor CT5 and a sixth control transistor CT6;

[0548] The gate of CT5 is electrically connected to the first scan signal output terminal ST, the source of CT5 is electrically connected to the first high voltage terminal VGH1, and the drain of CT5 is electrically connected to the third control node CS3.

[0549] The gate of CT6 is electrically connected to the first scan signal output terminal ST, the source of CT6 is electrically connected to the third control node CS3, and the drain of CT6 is electrically connected to the second control node CS2.

[0550] The first inverter circuit 143 includes a seventh control transistor CT7 and an eighth control transistor CT8;

[0551] The gate of CT7 is electrically connected to the third control node CS3, the source of CT7 is electrically connected to the second high voltage terminal VGH2, and the drain of CT7 is electrically connected to the drive signal output terminal GT.

[0552] The gate of CT8 is electrically connected to the third control node CS3, the source of CT8 is electrically connected to the drive signal output terminal GT, and the drain of CT8 is electrically connected to the second low voltage terminal VGL2.

[0553] In at least one embodiment of the driving circuit shown in Figure 23A, the driving control terminal can be the first scan signal output terminal ST, the first scan signal output terminal ST is the nth level first scan signal output terminal, and the second scan signal output terminal FT can be the nth level second scan signal output terminal, where n is a positive integer.

[0554] In at least one embodiment shown in Figure 23A, RT2 is a p-type transistor, RT1 is an n-type transistor, T0 is a p-type transistor, the transistors included in the scan signal generation circuit are all p-type transistors, and the reset voltage terminal is the first low voltage terminal VGL1.

[0555] CT10 is an n-type transistor, CT9 is a p-type transistor, CT12 is an n-type transistor, CT11 is a p-type transistor, CT1 is a p-type transistor, CT2 is an n-type transistor, CT3 is a p-type transistor, CT4 is an n-type transistor, CT5 is a p-type transistor, CT6 is an n-type transistor, CT7 is a p-type transistor, and CT8 is an n-type transistor.

[0556] At least one embodiment of the drive circuit shown in Figure 23A, when in operation,

[0557] When Trst provides a valid reset signal, that is, when Trst provides a high voltage signal, RT1 is turned on, controlling the connection between VGL1 and PD1; T1 is turned on, connecting PD1 and PD, with PD having a low voltage potential; TS2 is turned on, connecting ST and VGL1, with ST providing an invalid first scan signal and a low voltage signal; T10 is turned on, T11 is turned off, connecting FT and VGH1, with FT providing an invalid second scan signal and a high voltage signal; CT5 is turned on, CT6 is turned off, connecting CS3 and VGH1; CT7 is turned off; CT8 is turned on, connecting GT and VGL2, with GT providing an invalid drive signal and a low voltage signal.

[0558] When Trst provides an invalid reset signal, that is, when Trst provides a low voltage signal, RT2 is turned on, controlling the connection between Ri and PD1. When CK1 provides a low voltage signal, the signal input terminal SR can provide an input signal to PD1, controlling the drive circuit to perform display drive normally.

[0559] Figure 23B is a circuit diagram of the scan signal generation circuit, reset circuit and start-up circuit in Figure 23A;

[0560] Figure 23C is a circuit diagram of the control signal generation circuit and control circuit in Figure 23A.

[0561] In at least one embodiment shown in Figure 23A, the drive signal output terminal GT can be electrically connected to the gate of the n-type transistor in the pixel circuit. When GT provides a low voltage signal, the n-type transistor in the pixel circuit is turned off, and GT provides an invalid drive signal.

[0562] Figure 24A is a timing diagram of at least one embodiment of the driving circuit shown in Figure 23A when it is operating in the high refresh rate region, and Figure 24B is a timing diagram of at least one embodiment of the driving circuit shown in Figure 23A when it is operating in the low refresh rate region.

[0563] As shown in Figure 24A, when EN provides a high voltage signal, the drive circuit operates in the high refresh rate region;

[0564] As shown in Figure 24B, when EN provides a low voltage signal, the drive circuit operates in the low refresh rate region.

[0565] In Figures 24A and 24B, the line labeled NCK1 is the first clock signal line, the line labeled NCK2 is the second clock signal line, the line labeled NCK3 is the third clock signal line, and the line labeled NCK4 is the fourth clock signal line.

[0566] The drive module may include at least one embodiment of the multi-stage drive circuit shown in Figure 23;

[0567] In the 2a-level drive circuit, the first control clock signal terminal CK1 is electrically connected to NCK1, the second control clock signal terminal CK2 is electrically connected to NCK2, and the third control clock signal terminal CK3 is electrically connected to NCK3.

[0568] In the 2a+1 stage drive circuit, the first control clock signal terminal CK1 is electrically connected to NCK3, the second control clock signal terminal CK2 is electrically connected to NCK4, and the third control clock signal terminal CK3 is electrically connected to NCK1.

[0569] 'a' is a natural number.

[0570] As shown in Figure 24B, when EN provides a low voltage signal...

[0571] When TC1 and FT both provide high voltage signals, and ST and TC2 both provide low voltage signals, EN is connected to CS1, and the potential of CS1 is low voltage; CT1 is turned on, CT2 is turned off, CS2 is connected to VGH1, and the potential of CS2 is high voltage; CT4 is turned on, CT3 is turned off, CT5 is turned on, CS3 is connected to VGH1, CT8 is turned on, GT outputs a low voltage signal, and GT outputs an invalid drive signal;

[0572] When ST provides a high voltage signal, CT6 is turned on, connecting CS3 and CS2. Since CS2 has a high voltage potential, CS3 also has a high voltage potential, CT8 is turned on, GT outputs a low voltage signal, and GT outputs an invalid drive signal. The difference between at least one embodiment of the drive circuit shown in Figure 25A and at least one embodiment of the drive circuit shown in Figure 23A is as follows: the gates of CT5 and CT6 are both electrically connected to the second scan signal output terminal FT.

[0573] In at least one embodiment shown in Figure 25A, the drive control terminal is the second scan signal output terminal FT.

[0574] In at least one embodiment shown in Figure 25A, the source of CT5 is electrically connected to the second control node CS2, and the drain of CT6 is electrically connected to the first low-voltage terminal VGL1.

[0575] At least one embodiment of the drive circuit shown in Figure 25A, when in operation,

[0576] When Trst provides a valid reset signal, that is, when Trst provides a high voltage signal, RT1 is turned on, controlling the connection between VGL1 and PD1; T1 is turned on, connecting PD1 and PD, with PD having a low voltage potential; TS2 is turned on, connecting ST and VGL1; ST provides an invalid first scan signal and a low voltage signal; T10 is turned on, T11 is turned off, connecting FT and VGH1; FT provides an invalid second scan signal and a high voltage signal; CT5 is turned off, CT6 is turned on, connecting CS3 and VGL1; CT7 is turned on, CT8 is turned off; GT outputs a high voltage signal and an invalid drive signal.

[0577] When Trst provides an invalid reset signal, that is, when Trst provides a low voltage signal, RT2 is turned on, controlling the connection between Ri and PD1. When CK1 provides a low voltage signal, the signal input terminal SR can provide an input signal to PD1, controlling the drive circuit to perform display drive normally.

[0578] Figure 25B is a circuit diagram of the scan signal generation circuit, reset circuit and start-up circuit in Figure 25A;

[0579] Figure 25C is a circuit diagram of the control signal generation circuit and control circuit in Figure 25A.

[0580] In at least one embodiment shown in Figure 25A, the drive signal output terminal GT can be electrically connected to the gate of the p-type transistor in the pixel circuit. When GT provides a high voltage signal, the p-type transistor in the pixel circuit is turned off, and GT provides an invalid drive signal.

[0581] In at least one embodiment shown in FIG25A, two high voltage terminals are used: a first high voltage terminal VGH1 and a second high voltage terminal VGH2, and two low voltage terminals are used: a first low voltage terminal VGL1 and VGL2.

[0582] Under normal circumstances, the voltage value of the first low-voltage signal provided by VGL1 is no higher than the voltage value of the second low-voltage signal provided by VGL2, and the voltage value of the first high-voltage signal provided by VGH1 is no lower than the voltage value of the second high-voltage signal provided by VGH2. Using dual-voltage drive can accelerate the charging and discharging speed of the drive signal output terminal GT, thereby improving the driving capability of the drive circuit. Simultaneously, it can also address the zero-crossing problem of Vth (Vth is the threshold voltage), reduce DC leakage current, increase process adaptability, and improve product yield. Typically, the channel width of the output transistor (e.g., CT7, CT8) is relatively large, and the threshold voltage of the output transistor is closer to 0V. For CT8, if the threshold voltage is less than 0, when using a single low-voltage terminal, the minimum gate-source voltage of CT8 is 0V, making it impossible to turn off CT8. Therefore, when GT outputs a high-voltage signal, there will be prolonged leakage current, increasing the power consumption of the drive circuit. If the threshold voltage of the output transistor is severely negatively biased, it may also prevent the potential of the drive signal provided by GT from being pulled high, thus causing the drive circuit to malfunction. By employing dual low-voltage terminals, the voltage value of the first low-voltage signal provided by VGL1 can be reduced, ensuring that the voltage difference between the first and second low-voltage signals exceeds the absolute value of Vth of CT8. This guarantees that CT8 can switch normally, allowing the drive circuit to operate correctly, while also reducing DC leakage and saving power. Similarly, the dual high-voltage terminal design can also resolve the positive bias zero-crossing issue of CT7.

[0583] As shown in Figure 26, at least one embodiment of the driving module may include at least one embodiment of the multi-stage driving circuit shown in Figure 25;

[0584] In Figure 26, the line labeled STV is the start signal line; the input terminal of inverter INV1 is electrically connected to the start signal line STV, and the output terminal of inverter INV1 is electrically connected to the inverted start signal line STVF. Inverter INV1 is used to invert the start voltage provided by the start signal line to obtain an inverted start voltage, and the inverted start voltage is provided through the inverted start signal line STVF.

[0585] In Figure 26, the line labeled NCK1 is the first clock signal line, the line labeled NCK2 is the second clock signal line, the line labeled NCK3 is the third clock signal line, and the line labeled NCK4 is the fourth clock signal line.

[0586] The circuit labeled GA0 is the zeroth stage drive circuit of the drive module, the circuit labeled GA1 is the first stage drive circuit of the drive module, the circuit labeled GA2 is the second stage drive circuit of the drive module, the circuit labeled GA3 is the third stage drive circuit of the drive module, the circuit labeled GA4 is the fourth stage drive circuit of the drive module, and the circuit labeled GAN is the Nth stage drive circuit of the drive module.

[0587] N is an integer greater than 4.

[0588] In at least one embodiment of the driving module shown in Figure 26, GA0 can be a dummy driving circuit, and the driving signal output terminal of GA0 is the zeroth level driving signal output terminal GT0, which can be a virtual driving signal output terminal.

[0589] The drive signal output terminal of GA1 is the first-stage drive signal output terminal GT1, the drive signal output terminal of GA2 is the second-stage drive signal output terminal GT2, the drive signal output terminal of GA3 is the third-stage drive signal output terminal GT3, the drive signal output terminal of GA4 is the fourth-stage drive signal output terminal GT4, and the drive signal output terminal of GAN is the Nth-stage drive signal output terminal GTN.

[0590] In Figure 26, TC1 is the first control terminal of each stage of the drive circuit, and TC2 is the second control terminal of each stage of the drive circuit; ST is the first scan signal output terminal of each stage of the drive circuit, and FT is the second scan signal output terminal of each stage of the drive circuit.

[0591] STV is electrically connected to the first control terminal of GA0, and STVF is electrically connected to the second control terminal of GA0.

[0592] The first scan signal output terminal of GA0 is electrically connected to the first control terminal of GA1, and the second scan signal output terminal of GA0 is electrically connected to the second control terminal of GA1.

[0593] The first scan signal output terminal of GA1 is electrically connected to the first control terminal of GA2, and the second scan signal output terminal of GA1 is electrically connected to the second control terminal of GA2.

[0594] The first scan signal output terminal of GA2 is electrically connected to the first control terminal of GA3, and the second scan signal output terminal of GA2 is electrically connected to the second control terminal of GA3.

[0595] The first scan signal output terminal of GA3 is electrically connected to the first control terminal of GA4, and the second scan signal output terminal of GA3 is electrically connected to the second control terminal of GA4.

[0596] The first control clock signal terminal of GA0 is electrically connected to the first clock signal line NCK1, the second control clock signal terminal of GA0 is electrically connected to the second clock signal line NCK2, and the third control clock signal terminal of GA0 is electrically connected to the third clock signal line NCK3.

[0597] The first control clock signal terminal of GA1 is electrically connected to the third clock signal line NCK3, the second control clock signal terminal of GA1 is electrically connected to the fourth clock signal line NCK4, and the third control clock signal terminal of GA1 is electrically connected to the first clock signal line NCK1.

[0598] The first control clock signal terminal of GA2 is electrically connected to the first clock signal line NCK1, the second control clock signal terminal of GA2 is electrically connected to the second clock signal line NCK2, and the third control clock signal terminal of GA2 is electrically connected to the third clock signal line NCK3.

[0599] The first control clock signal terminal of GA3 is electrically connected to the third clock signal line NCK3, the second control clock signal terminal of GA3 is electrically connected to the fourth clock signal line NCK4, and the third control clock signal terminal of GA3 is electrically connected to the first clock signal line NCK1.

[0600] The first control clock signal terminal of GA4 is electrically connected to the first clock signal line NCK1, the second control clock signal terminal of GA4 is electrically connected to the second clock signal line NCK2, and the third control clock signal terminal of GA4 is electrically connected to the third clock signal line NCK3.

[0601] The first control clock signal terminal of GAN is electrically connected to the first clock signal line NCK1, the second control clock signal terminal of GAN is electrically connected to the second clock signal line NCK2, and the third control clock signal terminal of GAN is electrically connected to the third clock signal line NCK3.

[0602] Figure 27A is a timing diagram of at least one embodiment of the driving circuit shown in Figure 25 when it operates in the high refresh rate region, and Figure 27B is a timing diagram of at least one embodiment of the driving circuit shown in Figure 25 when it operates in the low refresh rate region.

[0603] As shown in Figures 27A and 27B, the periods of the first clock signal provided by NCK1, the second clock signal provided by NCK2, the second clock signal provided by NCK3, and the fourth clock signal provided by NCK4 can all be 2H, where 1H is the scan time of one line. The second clock signal is delayed by a phase Δ compared to the first clock signal, and the fourth clock signal is delayed by a phase Δ compared to the third clock signal. A phase Δ can be greater than 0 and less than 2μs. The phase Δ is selected based on the load of the drive circuit and the size of the internal capacitor, primarily to eliminate the falling edge reset adjustment of the drive signal provided by GT. During power-on, power-off, or the blanking time between two frames, the potential of the reset signal provided by the reset signal terminal Trst goes high, resetting the drive circuit. As shown in Figure 27A, when EN provides a valid enable signal (i.e., a low voltage signal), the drive circuit can perform normal drive output. As shown in Figure 27B, when EN provides an invalid enable signal (i.e., a high voltage signal), the drive signal provided by the drive circuit is a high voltage signal, and the drive circuit outputs an invalid drive signal.

[0604] The difference between at least one embodiment of the driving circuit shown in Figure 28A and at least one embodiment of the driving circuit shown in Figure 25A is as follows: the source of T8 is electrically connected to the first control clock signal terminal CK1.

[0605] At least one embodiment of the driving circuit shown in Figure 28A uses two control clock signal terminals, which helps to reduce the power consumption of the driving circuit without increasing the bezel.

[0606] Figure 28B is a circuit diagram of the scan signal generation circuit, reset circuit and start-up circuit in Figure 28A;

[0607] Figure 28C is a circuit diagram of the control signal generation circuit and control circuit in Figure 28A.

[0608] As shown in Figure 29, the drive module may include at least one embodiment of the multi-stage drive circuit shown in Figure 28A;

[0609] In Figure 29, the line labeled STV is the start signal line; the input terminal of inverter INV1 is electrically connected to the start signal line STV, and the output terminal of inverter INV1 is electrically connected to the inverted start signal line STVF. Inverter INV1 is used to invert the start voltage provided by the start signal line to obtain an inverted start voltage, and the inverted start voltage is provided through the inverted start signal line STVF.

[0610] In Figure 29, the line labeled NCK1 is the first clock signal line, the line labeled NCK2 is the second clock signal line, the line labeled NCK3 is the third clock signal line, and the line labeled NCK4 is the fourth clock signal line.

[0611] The circuit labeled GA0 is the zeroth stage drive circuit of the drive module, the circuit labeled GA1 is the first stage drive circuit of the drive module, the circuit labeled GA2 is the second stage drive circuit of the drive module, the circuit labeled GA3 is the third stage drive circuit of the drive module, the circuit labeled GA4 is the fourth stage drive circuit of the drive module, and the circuit labeled GAN is the Nth stage drive circuit of the drive module.

[0612] N is an integer greater than 4.

[0613] In at least one embodiment of the driving module shown in Figure 29, GA0 can be a dummy driving circuit, and the driving signal output terminal of GA0 is the zeroth level driving signal output terminal GT0, which can be a virtual driving signal output terminal.

[0614] The drive signal output terminal of GA1 is the first-stage drive signal output terminal GT1, the drive signal output terminal of GA2 is the second-stage drive signal output terminal GT2, the drive signal output terminal of GA3 is the third-stage drive signal output terminal GT3, the drive signal output terminal of GA4 is the fourth-stage drive signal output terminal GT4, and the drive signal output terminal of GAN is the Nth-stage drive signal output terminal GTN.

[0615] In Figure 29, TC1 is the first control terminal of each stage of the drive circuit, and TC2 is the second control terminal of each stage of the drive circuit; ST is the first scan signal output terminal of each stage of the drive circuit, and FT is the second scan signal output terminal of each stage of the drive circuit.

[0616] STV is electrically connected to the first control terminal of GA0, and STVF is electrically connected to the second control terminal of GA0.

[0617] The first scan signal output terminal of GA0 is electrically connected to the first control terminal of GA1, and the second scan signal output terminal of GA0 is electrically connected to the second control terminal of GA1.

[0618] The first scan signal output terminal of GA1 is electrically connected to the first control terminal of GA2, and the second scan signal output terminal of GA1 is electrically connected to the second control terminal of GA2.

[0619] The first scan signal output terminal of GA2 is electrically connected to the first control terminal of GA3, and the second scan signal output terminal of GA2 is electrically connected to the second control terminal of GA3.

[0620] The first scan signal output terminal of GA3 is electrically connected to the first control terminal of GA4, and the second scan signal output terminal of GA3 is electrically connected to the second control terminal of GA4.

[0621] The first control clock signal terminal of GA0 is electrically connected to the first clock signal line NCK1, and the second control clock signal terminal of GA0 is electrically connected to the second clock signal line NCK2.

[0622] The first control clock signal terminal of GA1 is electrically connected to the second clock signal line NCK2, and the second control clock signal terminal of GA1 is electrically connected to the third clock signal line NCK3.

[0623] The first control clock signal terminal of GA2 is electrically connected to the third clock signal line NCK3, and the second control clock signal terminal of GA2 is electrically connected to the fourth clock signal line NCK4.

[0624] The first control clock signal terminal of GA3 is electrically connected to the fourth clock signal line NCK4, and the second control clock signal terminal of GA3 is electrically connected to the first clock signal line NCK1.

[0625] The first control clock signal terminal of GA4 is electrically connected to the first clock signal line NCK1, and the second control clock signal terminal of GA4 is electrically connected to the second clock signal line NCK2.

[0626] The first control clock signal terminal of GAN is electrically connected to the first clock signal line NCK1, and the second control clock signal terminal of GAN is electrically connected to the second clock signal line NCK2.

[0627] Figure 30 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 28A, wherein the period of the first clock signal provided by the first clock signal line NCK1, the second clock signal provided by the second clock signal line NCK2, the third clock signal provided by the third clock signal line NCK3, and the fourth clock signal provided by the fourth clock signal line NCK4 can all be 4 lines of scan time. The second clock signal is delayed by one line of scan time compared to the first clock signal, the third clock signal is delayed by one line of scan time compared to the second clock signal, and the fourth clock signal is delayed by one line of scan time compared to the third clock signal.

[0628] In Figure 30, the period labeled SH is the high refresh rate period and the period labeled SL is the low refresh rate period. During the high refresh rate period SH, EN provides an effective enable signal, that is, EN provides a low voltage signal.

[0629] During the low refresh rate period SL, EN provides an invalid enable signal, that is, EN provides a high voltage signal to control GT to provide an invalid drive signal, that is, GT provides a high voltage signal.

[0630] In Figure 30, GT(n-1) is the output terminal of the (n-1)th stage drive signal, GT is the output terminal of the nth stage drive signal, and n is a positive integer.

[0631] In at least one embodiment shown in Figure 28A, the drive signal output terminal GT can be electrically connected to the gate of the p-type transistor in the pixel circuit. When GT provides a high voltage signal, the p-type transistor in the pixel circuit is turned off, and GT provides an invalid drive signal.

[0632] The difference between at least one embodiment of the driving circuit shown in Figure 31A and at least one embodiment of the driving circuit shown in Figure 28A is that:

[0633] The source of T2 is electrically connected to the second control clock signal terminal CK2, and the gate of T3 is electrically connected to the second control clock signal terminal CK2.

[0634] The source of T6 is electrically connected to the third control clock signal terminal CK3, and the gate of T7 is electrically connected to the third control clock signal terminal CK3.

[0635] TC1 is electrically connected to the first scan signal output terminal of the (n-2)th stage, and TC2 is electrically connected to the second scan signal output terminal of the (n-2)th stage.

[0636] The driving circuit described in at least one embodiment of this disclosure can reduce the power consumption of the driving circuit, reduce the low-level fluctuations of the driving signal provided by the driving circuit, stagger the charging time, reduce the possibility of horizontal stripe defects, and improve the display quality.

[0637] Figure 31B is a circuit diagram of the scan signal generation circuit, reset circuit and start-up circuit in Figure 31A;

[0638] Figure 31C is a circuit diagram of the control signal generation circuit and control circuit in Figure 31A.

[0639] As shown in FIG32, the drive module may include at least one embodiment of the multi-stage drive circuit shown in FIG31A;

[0640] In Figure 32, the line labeled STV is the start signal line; the input terminal of inverter INV1 is electrically connected to the start signal line STV, and the output terminal of inverter INV1 is electrically connected to the inverted start signal line STVF. Inverter INV1 is used to invert the start voltage provided by the start signal line to obtain an inverted start voltage, and the inverted start voltage is provided through the inverted start signal line STVF.

[0641] In Figure 32, the line labeled NCK1 is the first clock signal line, the line labeled NCK2 is the second clock signal line, the line labeled NCK3 is the third clock signal line, and the line labeled NCK4 is the fourth clock signal line.

[0642] The circuit labeled GA0 is the zeroth stage drive circuit of the drive module, the circuit labeled GA1 is the first stage drive circuit of the drive module, the circuit labeled GA2 is the second stage drive circuit of the drive module, the circuit labeled GA3 is the third stage drive circuit of the drive module, the circuit labeled GA4 is the fourth stage drive circuit of the drive module, and the circuit labeled GAN is the Nth stage drive circuit of the drive module.

[0643] N is an integer greater than 4.

[0644] In at least one embodiment of the driving module shown in Figure 32, GA0 can be a dummy driving circuit, and the driving signal output terminal of GA0 is the zeroth level driving signal output terminal GT0, which can be a virtual driving signal output terminal.

[0645] The drive signal output terminal of GA1 is the first-stage drive signal output terminal GT1, the drive signal output terminal of GA2 is the second-stage drive signal output terminal GT2, the drive signal output terminal of GA3 is the third-stage drive signal output terminal GT3, the drive signal output terminal of GA4 is the fourth-stage drive signal output terminal GT4, and the drive signal output terminal of GAN is the Nth-stage drive signal output terminal GTN.

[0646] In Figure 32, TC1 is the first control terminal of each stage of the drive circuit, and TC2 is the second control terminal of each stage of the drive circuit; ST is the first scan signal output terminal of each stage of the drive circuit, and FT is the second scan signal output terminal of each stage of the drive circuit.

[0647] STV is electrically connected to the first control terminal of GA0 and the first control terminal of GA1, and STVF is electrically connected to the second control terminal of GA0 and the second control terminal of GA1.

[0648] The first scan signal output terminal of GA0 is electrically connected to the first control terminal of GA2, and the second scan signal output terminal of GA0 is electrically connected to the second control terminal of GA2.

[0649] The first scan signal output terminal of GA1 is electrically connected to the first control terminal of GA3, and the second scan signal output terminal of GA1 is electrically connected to the second control terminal of GA3.

[0650] The first scan signal output terminal of GA2 is electrically connected to the first control terminal of GA4, and the second scan signal output terminal of GA2 is electrically connected to the second control terminal of GA4.

[0651] The first control clock signal terminal of GA0 is electrically connected to the first clock signal line NCK1, the second control clock signal terminal of GA0 is electrically connected to the second clock signal line NCK2, and the third control clock signal terminal of GA0 is electrically connected to the third clock signal line NCK3.

[0652] The first control clock signal terminal of GA1 is electrically connected to the second clock signal line NCK2, the second control clock signal terminal of GA1 is electrically connected to the third clock signal line NCK3, and the third control clock signal terminal of GA1 is electrically connected to the fourth clock signal line NCK4.

[0653] The first control clock signal terminal of GA2 is electrically connected to the third clock signal line NCK3, the second control clock signal terminal of GA2 is electrically connected to the fourth clock signal line NCK4, and the third control clock signal terminal of GA2 is electrically connected to the first clock signal line NCK1.

[0654] The first control clock signal terminal of GA3 is electrically connected to the fourth clock signal line NCK4, the second control clock signal terminal of GA3 is electrically connected to the first clock signal line NCK1, and the third control clock signal terminal of GA3 is electrically connected to the second clock signal line NCK2.

[0655] The first control clock signal terminal of GA4 is electrically connected to the first clock signal line NCK1, the second control clock signal terminal of GA4 is electrically connected to the second clock signal line NCK2, and the third control clock signal terminal of GA4 is electrically connected to the third clock signal line NCK3.

[0656] The first control clock signal terminal of GAN is electrically connected to the first clock signal line NCK1, the second control clock signal terminal of GAN is electrically connected to the second clock signal line NCK2, and the third control clock signal terminal of GAN is electrically connected to the third clock signal line NCK3.

[0657] In Figure 32, the line labeled VL1 is the first low voltage line, the line labeled VL2 is the second low voltage line, and the line labeled VL3 is the third low voltage line.

[0658] The first low-voltage terminal of GA0 is electrically connected to VL1, and the second low-voltage terminal of GA0 is electrically connected to VL2.

[0659] The first low-voltage terminal of GA1 is electrically connected to VL3, and the second low-voltage terminal of GA1 is electrically connected to VL2.

[0660] The first low-voltage terminal of GA2 is electrically connected to VL1, and the second low-voltage terminal of GA2 is electrically connected to VL2.

[0661] The first low-voltage terminal of GA3 is electrically connected to VL3, and the second low-voltage terminal of GA3 is electrically connected to VL2.

[0662] The first low-voltage terminal of GA4 is electrically connected to VL1, and the second low-voltage terminal of GA4 is electrically connected to VL2.

[0663] The first low-voltage terminal of the GAN is electrically connected to VL1, and the second low-voltage terminal of the GAN is electrically connected to VL2.

[0664] In at least one embodiment shown in Figure 32, three low-voltage lines are used: a first low-voltage line VL1, a second low-voltage line VL2, and a third low-voltage line VL3. The low-voltage signals connected to the first low-voltage terminals of adjacent driving circuits are different.

[0665] Figure 33 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 31A.

[0666] In Figure 33, the period labeled SH is the high refresh rate period and the period labeled SL is the low refresh rate period. During the high refresh rate period SH, EN provides an effective enable signal, that is, EN provides a low voltage signal, and the drive circuit outputs the drive signal normally.

[0667] During the low refresh rate period SL, EN provides an invalid enable signal, that is, EN provides a high voltage signal to control GT to provide an invalid drive signal, that is, GT provides a high voltage signal.

[0668] In Figure 33, GT(n-1) is the output terminal of the (n-1)th stage drive signal, GT is the output terminal of the nth stage drive signal, and n is a positive integer.

[0669] In at least one embodiment shown in Figure 31A, the drive signal output terminal GT can be electrically connected to the gate of the p-type transistor in the pixel circuit. When GT provides a high voltage signal, the p-type transistor in the pixel circuit is turned off, and GT provides an invalid drive signal.

[0670] The differences between at least one embodiment of the driving circuit shown in Figure 34A and at least one embodiment of the driving circuit shown in Figure 23A are as follows:

[0671] The source of T8 is electrically connected to the first control clock signal terminal CK1.

[0672] In at least one embodiment of the drive module including the multi-stage drive circuit shown in Figure 34, four clock signal lines can be used.

[0673] In the 4a-level drive circuit, the first control clock signal terminal CK1 is electrically connected to the first clock signal line NCK1, and the second control clock signal terminal CK2 is electrically connected to the second clock signal line NCK2.

[0674] In the 4a+1 stage drive circuit, the first control clock signal terminal CK1 is electrically connected to the second clock signal line NCK2, and the second control clock signal terminal CK2 is electrically connected to the third clock signal line NCK3.

[0675] In the 4a+2 stage drive circuit, the first control clock signal terminal CK1 is electrically connected to the third clock signal line NCK3, and the second control clock signal terminal CK2 is electrically connected to the fourth clock signal line NCK4.

[0676] In the 4a+3 level drive circuit, the first control clock signal terminal CK1 is electrically connected to the fourth clock signal line NCK4, and the second control clock signal terminal CK2 is electrically connected to the first clock signal line NCK1.

[0677] 'a' is a natural number.

[0678] Figure 34B is a circuit diagram of the scan signal generation circuit, reset circuit and start-up circuit in Figure 34A;

[0679] Figure 34C is a circuit diagram of the control signal generation circuit and control circuit in Figure 34A.

[0680] Figure 35 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 34A.

[0681] In Figure 35, the period labeled SH is the high refresh rate period and the period labeled SL is the low refresh rate period. During the high refresh rate period SH, EN provides an effective enable signal, that is, EN provides a high voltage signal, and the drive circuit normally outputs the drive signal.

[0682] During the low refresh period SL, EN provides an invalid enable signal, that is, EN provides a low voltage signal to control GT to provide an invalid drive signal, that is, GT provides a low voltage signal.

[0683] In Figure 35, GT(n-1) is the output terminal of the (n-1)th stage drive signal, GT is the output terminal of the nth stage drive signal, and n is a positive integer.

[0684] In at least one embodiment shown in Figure 34A, the drive signal output terminal GT can be electrically connected to the gate of the n-type transistor in the pixel circuit. When GT provides a low voltage signal, the n-type transistor in the pixel circuit is turned off, and GT provides an invalid drive signal.

[0685] The differences between at least one embodiment of the driving circuit shown in Figure 36A and at least one embodiment of the driving circuit shown in Figure 34A are as follows:

[0686] The source of T6 is electrically connected to the third control clock signal terminal CK3, and the gate of T7 is electrically connected to the third control clock signal terminal CK3.

[0687] The source of T2 is electrically connected to the second control clock signal terminal CK2;

[0688] The first control terminal TC1 is electrically connected to the output terminal of the first scan signal of the (n-2)th stage, and the second control terminal TC2 is electrically connected to the output terminal of the second scan signal of the (n-2)th stage.

[0689] At least one embodiment of the driving circuit shown in Figure 36A is an nth-stage driving circuit, where n is a positive integer.

[0690] Figure 36B is a circuit diagram of the scan signal generation circuit, reset circuit and start-up circuit in Figure 36A;

[0691] Figure 36C is a circuit diagram of the control signal generation circuit and control circuit in Figure 36A.

[0692] In at least one embodiment of the driving module shown in Figure 37, GA0 can be a dummy driving circuit, and the driving signal output terminal of GA0 is the zeroth level driving signal output terminal GT0, which can be a virtual driving signal output terminal.

[0693] The drive signal output terminal of GA1 is the first-stage drive signal output terminal GT1, the drive signal output terminal of GA2 is the second-stage drive signal output terminal GT2, the drive signal output terminal of GA3 is the third-stage drive signal output terminal GT3, the drive signal output terminal of GA4 is the fourth-stage drive signal output terminal GT4, and the drive signal output terminal of GAN is the Nth-stage drive signal output terminal GTN.

[0694] In Figure 37, TC1 is the first control terminal of each stage of the drive circuit, and TC2 is the second control terminal of each stage of the drive circuit; ST is the first scan signal output terminal of each stage of the drive circuit, and FT is the second scan signal output terminal of each stage of the drive circuit.

[0695] STV is electrically connected to the first control terminal of GA0 and the first control terminal of GA1, and STVF is electrically connected to the second control terminal of GA0 and the second control terminal of GA1.

[0696] The first scan signal output terminal of GA0 is electrically connected to the first control terminal of GA2, and the second scan signal output terminal of GA0 is electrically connected to the second control terminal of GA2.

[0697] The first scan signal output terminal of GA1 is electrically connected to the first control terminal of GA3, and the second scan signal output terminal of GA1 is electrically connected to the second control terminal of GA3.

[0698] The first scan signal output terminal of GA2 is electrically connected to the first control terminal of GA4, and the second scan signal output terminal of GA2 is electrically connected to the second control terminal of GA4.

[0699] The first control clock signal terminal of GA0 is electrically connected to the first clock signal line NCK1, the second control clock signal terminal of GA0 is electrically connected to the second clock signal line NCK2, and the third control clock signal terminal of GA0 is electrically connected to the third clock signal line NCK3.

[0700] The first control clock signal terminal of GA1 is electrically connected to the second clock signal line NCK2, the second control clock signal terminal of GA1 is electrically connected to the third clock signal line NCK3, and the third control clock signal terminal of GA1 is electrically connected to the fourth clock signal line NCK4.

[0701] The first control clock signal terminal of GA2 is electrically connected to the third clock signal line NCK3, the second control clock signal terminal of GA2 is electrically connected to the fourth clock signal line NCK4, and the third control clock signal terminal of GA2 is electrically connected to the first clock signal line NCK1.

[0702] The first control clock signal terminal of GA3 is electrically connected to the fourth clock signal line NCK4, the second control clock signal terminal of GA3 is electrically connected to the first clock signal line NCK1, and the third control clock signal terminal of GA3 is electrically connected to the second clock signal line NCK2.

[0703] The first control clock signal terminal of GA4 is electrically connected to the first clock signal line NCK1, the second control clock signal terminal of GA4 is electrically connected to the second clock signal line NCK2, and the third control clock signal terminal of GA4 is electrically connected to the third clock signal line NCK3.

[0704] The first control clock signal terminal of GAN is electrically connected to the first clock signal line NCK1, the second control clock signal terminal of GAN is electrically connected to the second clock signal line NCK2, and the third control clock signal terminal of GAN is electrically connected to the third clock signal line NCK3.

[0705] In Figure 37, the line labeled VH1 is the first high-voltage line, the line labeled VH2 is the second high-voltage line, and the line labeled VH3 is the high-low voltage line.

[0706] The first high-voltage terminal of GA0 is electrically connected to VG1, and the second high-voltage terminal of GA0 is electrically connected to VG2.

[0707] The first high-voltage terminal of GA1 is electrically connected to VG3, and the second high-voltage terminal of GA1 is electrically connected to VG2.

[0708] The first high-voltage terminal of GA2 is electrically connected to VG1, and the second high-voltage terminal of GA2 is electrically connected to VG2.

[0709] The first high-voltage terminal of GA3 is electrically connected to VG3, and the second high-voltage terminal of GA3 is electrically connected to VG2.

[0710] The first high-voltage terminal of GA4 is electrically connected to VG1, and the second high-voltage terminal of GA4 is electrically connected to VG2.

[0711] The first high-voltage terminal of the GAN is electrically connected to VG1, and the second high-voltage terminal of the GAN is electrically connected to VG2.

[0712] In at least one embodiment shown in Figure 37, three high-voltage lines are used: a first high-voltage line VH1, a second high-voltage line VH2, and a third high-voltage line VH3, with different high-voltage signals connected to the first high-voltage terminals of adjacent driving circuits.

[0713] Figure 38 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 36A.

[0714] In Figure 38, the period labeled SH is the high refresh rate period and the period labeled SL is the low refresh rate period. During the high refresh rate period SH, EN provides an effective enable signal, that is, EN provides a high voltage signal, and the drive circuit normally outputs the drive signal.

[0715] During the low refresh period SL, EN provides an invalid enable signal, that is, EN provides a low voltage signal to control GT to provide an invalid drive signal, that is, GT provides a low voltage signal.

[0716] In Figure 38, GT(n-1) is the output terminal of the (n-1)th stage drive signal, GT is the output terminal of the nth stage drive signal, and n is a positive integer.

[0717] In at least one embodiment shown in Figure 36A, the drive signal output terminal GT can be electrically connected to the gate of the n-type transistor in the pixel circuit. When GT provides a low voltage signal, the n-type transistor in the pixel circuit is turned off, and GT provides an invalid drive signal.

[0718] The display substrate described in at least one embodiment of this disclosure includes: a substrate and a driving circuit disposed on the substrate;

[0719] The driving circuit includes a scan signal generation circuit, which is used to provide at least one scan signal;

[0720] The driving circuit also includes a reset circuit, which is electrically connected to the reset control terminal and the scan signal generation circuit, respectively. During non-refreshing periods, under the control of the reset control terminal, the reset circuit controls the scan signal generation circuit to output an invalid scan signal.

[0721] The non-refreshing periods include, but are not limited to, the frame blanking period between two adjacent frames, and the period when the display substrate is powered on / off.

[0722] In at least one embodiment of this disclosure, the display substrate further includes pixel circuitry disposed on the substrate;

[0723] The display substrate includes a display area and a peripheral area; the driving circuit is disposed in the peripheral area; the pixel circuit is disposed in the display area;

[0724] When the display substrate is in the first display state, the display area includes multiple areas along the scanning direction. When the last area of ​​the display area is displayed, the pixel circuits in the last area do not perform display refresh during at least one hold frame. The display refresh frequencies of two adjacent areas are different.

[0725] The display substrate further includes a clock control circuit disposed on the substrate; the scan signal generation circuit is electrically connected to the control clock signal terminal and is used to provide a scan signal under the control of the control clock signal provided by the control clock signal terminal;

[0726] The clock control circuit is used to control the reduction of the frequency of the control clock signal after the pixel circuit in the region adjacent to the last region completes the display refresh in the holding frame. Reducing the frequency of the control clock signal can save power consumption.

[0727] The driving method described in this embodiment is applied to the above-mentioned display substrate, and the driving method includes:

[0728] When the display substrate is in the first display state, after the pixel circuit in the area adjacent to the last area completes the display refresh in the holding frame, the frequency of the control clock signal is reduced.

[0729] After the pixel circuit in the region adjacent to the last region completes the display refresh, the control scan signal generation circuit outputs an invalid scan signal.

[0730] Optionally, the step of reducing the frequency of the control clock signal includes: reducing the frequency of the control clock signal to half of its original frequency. k , where k is a positive integer.

[0731] The driving method described in at least one embodiment of this disclosure is applied to the above-mentioned display substrate, and the driving method includes:

[0732] When the display substrate is in the first display state, after the pixel circuit in the area adjacent to the last area completes the display refresh in the holding frame, the frequency of the control clock signal is reduced.

[0733] During non-refresh periods, the control scan signal generation circuit outputs an invalid scan signal.

[0734] Optionally, the step of reducing the frequency of the control clock signal includes: reducing the frequency of the control clock signal to half of its original frequency. k , where k is a positive integer.

[0735] The display device described in this disclosure includes the display substrate described above. The above description represents preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display substrate, comprising: A substrate and a driving circuit disposed on the substrate; The driving circuit includes a scan signal generation circuit and a reset circuit; The scan signal generation circuit is used to provide at least one scan signal; The reset circuit is electrically connected to both the reset control terminal and the scan signal generation circuit, and is used to control the scan signal generation circuit to output an invalid scan signal under the control of the reset control terminal.

2. The display substrate as claimed in claim 1, wherein, The display substrate further includes pixel circuits disposed on the substrate; the scan signal generation circuit is electrically connected to the control clock signal terminal and is used to provide a scan signal under the control of the control clock signal provided by the control clock signal terminal; The display substrate includes a display area and a peripheral area; the driving circuit is disposed in the peripheral area. The pixel circuit is disposed in the display area; When the display substrate is in the first display state, the display area includes multiple areas along the scanning direction. When the last area of ​​the display area is displayed, the pixel circuits in the last area do not perform display refresh for at least one hold frame. The display refresh frequencies of two adjacent areas are different. The reset circuit is used to control the scan signal generation circuit to output an invalid scan signal when the display substrate is in the first display state, after the pixel circuit in the region adjacent to the last region in the at least one holding frame has completed the display refresh.

3. The display substrate as described in claim 2, wherein, The display substrate also includes a clock control circuit disposed on the substrate; The clock control circuit is used to reduce the frequency of the control clock signal after the pixel circuit in the region adjacent to the last region completes the display refresh in the holding frame.

4. The display substrate as described in claim 1 or 2, wherein, The driving circuit further includes a startup circuit; the scanning signal generation circuit includes a first output control node. The startup circuit is electrically connected to the input control clock signal terminal, and is used to connect or disconnect the control signal input terminal and the first output control node under the control of the input control clock signal provided by the input control clock signal terminal. The startup circuit is electrically connected to the signal input terminal, and the startup circuit is electrically connected to the first output control node through the reset circuit; or... The reset circuit is electrically connected to the signal input terminal, and the reset circuit is electrically connected to the first output control node through the startup circuit.

5. The display substrate as described in claim 1 or 2, wherein, The driving circuit further includes a startup circuit; the scanning signal generation circuit includes a first output control node; the reset circuit includes a first reset sub-circuit and a second reset circuit; the reset control terminal includes a reset signal terminal and / or a reset input node. The startup circuit is electrically connected to the input control clock signal terminal, the signal input terminal, and the reset input node, respectively, and is used to control the connection or disconnection between the signal input terminal and the reset input node under the control of the input control clock signal provided by the input control clock signal terminal; The first reset sub-circuit is electrically connected to the reset voltage terminal and the first output control node, respectively. The first reset sub-circuit is also electrically connected to the reset signal terminal or the reset input node, and is used to write the reset voltage provided by the reset voltage terminal into the first output control node under the control of the reset signal or the potential of the reset input node. The second reset sub-circuit is electrically connected to the reset signal terminal, the reset input node, and the first output control node, respectively, and is used to control the connection or disconnection between the reset input node and the first output control node under the control of the reset signal.

6. The display substrate as described in claim 1 or 2, wherein, The driving circuit further includes a startup circuit; the scanning signal generation circuit includes a first output control node; the reset circuit includes a first reset sub-circuit and a second reset circuit; the reset control terminal includes a reset signal terminal and / or a signal input terminal. The first reset sub-circuit is electrically connected to the reset output node and the reset voltage terminal respectively. The first reset sub-circuit is also electrically connected to the reset signal terminal or the signal input terminal, and is used to write the reset voltage provided by the reset voltage terminal into the reset output node under the control of the reset signal or the input signal provided by the signal input terminal. The second reset sub-circuit is electrically connected to the signal input terminal, the reset signal terminal, and the reset output node, respectively, and is used to control the connection or disconnection between the signal input terminal and the reset output node under the control of the reset signal; The startup circuit is electrically connected to the input control clock signal terminal, the reset output node, and the first output control node, respectively, and is used to control the connection or disconnection between the reset output node and the first output control node under the control of the input control clock signal provided by the input control clock signal terminal.

7. The display substrate as claimed in claim 4, wherein, The scanning signal generation circuit includes a first on / off control circuit and a second output circuit. The first on / off control circuit is electrically connected to the second voltage signal terminal, the first output control node, and the second output node, respectively, and is used to control the connection or disconnection between the first output control node and the second output node under the control of the second voltage signal provided by the second voltage signal terminal. The second output circuit is electrically connected to the second output node, the first scan signal output terminal, and the second voltage signal terminal, respectively, and is used to control the connection or disconnection between the first scan signal output terminal and the second voltage signal terminal under the control of the potential of the second output node.

8. The display substrate as claimed in claim 1 or 2, wherein, The driving circuit further includes a control signal generation circuit and a control circuit; the scanning signal includes a first scanning signal and a second scanning signal. The scanning signal generation circuit is electrically connected to the first scanning signal output terminal and the second scanning signal output terminal respectively, and is used to provide a first scanning signal through the first scanning signal output terminal and a second scanning signal through the second scanning signal output terminal. The control signal generation circuit is electrically connected to the enable signal terminal and the first control node, respectively. The control signal generation circuit is also electrically connected to the first scan signal output terminal, the second scan signal output terminal, the first control terminal, and the second control terminal, respectively. It is used to control the connection or disconnection between the enable signal terminal and the first control node under the control of the first scan signal, the second scan signal, the first control signal provided by the first control terminal, and the second control signal provided by the second control terminal. The first control terminal is electrically connected to the output terminal of the first scan signal of the adjacent i-th stage, and the second control terminal is electrically connected to the output terminal of the second scan signal of the adjacent i-th stage; i is a positive integer. The control circuit is connected to the first control node, the drive control terminal, and the drive signal output terminal respectively, and is used to provide a drive signal to the drive signal output terminal under the control of the potential of the first control node and the drive control signal provided by the drive control terminal. The drive control terminal is either the first scan signal output terminal or the second scan signal output terminal.

9. The display substrate as claimed in claim 8, wherein, The control circuit includes a first control sub-circuit, a second control sub-circuit, and a first inverting circuit; The first control sub-circuit is electrically connected to the first control node, the second control node, the first voltage signal terminal, and the second voltage signal terminal, respectively, and is used to control the second control node to connect with the first voltage signal terminal or the second voltage signal terminal under the control of the potential of the first control node, and to control the first control node to connect with the first voltage signal terminal or the second voltage signal terminal under the control of the potential of the second control node. The second control sub-circuit is electrically connected to the drive control terminal, the third control node, the first voltage signal terminal, and the second voltage signal terminal, respectively, and is used to control the third control node to connect with the first voltage signal terminal or the second voltage signal terminal under the control of the drive control signal; The first inverting circuit is electrically connected to the third control node and the drive signal output terminal, respectively, and is used to invert the potential of the third control node to obtain the drive signal.

10. The display substrate as claimed in claim 8, wherein, When the display area is in a normal refresh state, the enable signal provided by the enable signal terminal is a valid enable signal; When the display area is in the first display state, after the pixel circuit in the area adjacent to the last area completes the display refresh in the at least one holding frame, the enable signal is an invalid enable signal.

11. The display substrate as claimed in claim 7, wherein, The scanning signal generation circuit further includes a first node control circuit, a second on / off control circuit, a first output node control circuit, a second output node control circuit, a first output circuit, a first energy storage circuit, and a second inverting circuit; the control clock signal terminal includes a first control clock signal terminal, a second control clock signal terminal, and a third control clock signal terminal; the input control clock signal terminal is the first control clock signal terminal; The first node control circuit is electrically connected to the first control clock signal terminal, the second voltage signal terminal, the first node, and the first output control node, respectively. It is used to write the second voltage signal provided by the second voltage signal terminal into the first node under the control of the first control clock signal provided by the first control clock signal terminal, and to write the first control clock signal into the first node under the control of the potential of the first output control node. The second on / off control circuit is electrically connected to the second voltage signal terminal, the first node, and the second output control node, respectively, and is used to control the connection or disconnection between the first node and the second output control node under the control of the second voltage signal. The first output node control circuit is electrically connected to the first output node, the second control clock signal terminal, the second output control node, the first output control node, and the first voltage signal terminal, respectively. It is used to control the potential of the first output node under the control of the potential of the second output control node and the second control clock signal provided by the second control clock signal terminal, and to write the first voltage signal provided by the first voltage signal terminal into the first output node under the control of the potential of the first output control node. The second output node control circuit is electrically connected to the second output node, the first output node, the first voltage signal terminal, and the third control clock signal terminal, respectively, and is used to control the potential of the second output node under the control of the potential of the first output node and under the control of the third control clock signal provided by the third control clock signal terminal. The first output circuit is electrically connected to the first output node, the first voltage signal terminal and the first scan signal output terminal respectively, and is used to write the first voltage signal to the first scan signal output terminal under the control of the potential of the first output node; The first energy storage circuit is electrically connected to the first output node and is used to maintain the potential of the first output node; The second inverting circuit is electrically connected to the first scan signal output terminal and the second scan signal output terminal respectively, and is used to invert the first scan signal to obtain and output the second scan signal through the second scan signal output terminal.

12. The display substrate as claimed in claim 11, wherein, The third control clock signal terminal is the same as the first control clock signal terminal.

13. The display substrate as claimed in claim 7, wherein, The scanning signal generation circuit further includes a first node control circuit, a second on / off control circuit, a first output node control circuit, a second output node control circuit, a first output circuit, a first energy storage circuit, and a second inverting circuit; the control clock signal terminal includes a first control clock signal terminal, a second control clock signal terminal, and a third control clock signal terminal; the input control clock signal terminal is the first control clock signal terminal; The first node control circuit is electrically connected to the second control clock signal terminal, the second voltage signal terminal, the first node, and the first output control node, respectively. It is used to write the second voltage signal provided by the second voltage signal terminal into the first node under the control of the second control clock signal provided by the second control clock signal terminal, and to write the second control clock signal into the first node under the control of the potential of the first output control node. The second on / off control circuit is electrically connected to the second voltage signal terminal, the first node, and the second output control node, respectively, and is used to control the connection or disconnection between the first node and the second output control node under the control of the second voltage signal. The first output node control circuit is electrically connected to the first output node, the third control clock signal terminal, the second output control node, the first output control node, and the first voltage signal terminal, respectively. It is used to control the potential of the first output node under the control of the potential of the second output control node and the third control clock signal provided by the third control clock signal terminal, and to write the first voltage signal provided by the first voltage signal terminal into the first output node under the control of the potential of the first output control node. The second output node control circuit is electrically connected to the second output node, the first output node, the first voltage signal terminal, and the first control clock signal terminal, respectively, and is used to control the potential of the second output node under the control of the potential of the first output node and under the control of the first control clock signal provided by the first control clock signal terminal; The first output circuit is electrically connected to the first output node, the first voltage signal terminal and the first scan signal output terminal respectively, and is used to write the first voltage signal to the first scan signal output terminal under the control of the potential of the first output node; The first energy storage circuit is electrically connected to the first output node and is used to maintain the potential of the first output node; The second inverting circuit is electrically connected to the first scan signal output terminal and the second scan signal output terminal respectively, and is used to invert the first scan signal to obtain and output the second scan signal through the second scan signal output terminal.

14. The display substrate as claimed in claim 5, wherein, The first reset sub-circuit includes a first reset transistor, and the second reset sub-circuit includes a second reset transistor; The control terminal of the first reset transistor is electrically connected to the reset signal terminal, the first terminal of the first reset transistor is electrically connected to the reset voltage terminal, and the second terminal of the first reset transistor is electrically connected to the first output control node. The control terminal of the second reset transistor is electrically connected to the reset signal terminal, the first terminal of the second reset transistor is electrically connected to the reset input node, and the second terminal of the second reset transistor is electrically connected to the first output control node. The first reset transistor is an n-type transistor, and the second reset transistor is a p-type transistor; or, the first reset transistor is a p-type transistor, and the second reset transistor is an n-type transistor. The startup circuit includes an input transistor; The control electrode of the input transistor is electrically connected to the input control clock signal terminal, the first electrode of the input transistor is electrically connected to the signal input terminal, and the second electrode of the input transistor is electrically connected to the reset input node.

15. The display substrate as claimed in claim 5, wherein, The first reset sub-circuit includes a first reset transistor, and the second reset sub-circuit includes a second reset transistor; The control terminal of the first reset transistor is electrically connected to the reset input node, the first terminal of the first reset transistor is electrically connected to the reset voltage terminal, and the second terminal of the first reset transistor is electrically connected to the first output control node. The control terminal of the second reset transistor is electrically connected to the reset signal terminal, the first terminal of the second reset transistor is electrically connected to the reset input node, and the second terminal of the second reset transistor is electrically connected to the first output control node. The startup circuit includes an input transistor; The control electrode of the input transistor is electrically connected to the input control clock signal terminal, the first electrode of the input transistor is electrically connected to the signal input terminal, and the second electrode of the input transistor is electrically connected to the reset input node.

16. The display substrate as claimed in claim 6, wherein, The first reset sub-circuit includes a first reset transistor and a second reset transistor; The control terminal of the first reset transistor is electrically connected to the reset signal terminal, the first terminal of the first reset transistor is electrically connected to the reset voltage terminal, and the second terminal of the first reset transistor is electrically connected to the reset output node. The control electrode of the second reset transistor is electrically connected to the reset signal terminal, the first electrode of the second reset transistor is electrically connected to the signal input terminal, and the second electrode of the second reset transistor is electrically connected to the reset output node. The first reset transistor is an n-type transistor, and the second reset transistor is a p-type transistor; or, the first reset transistor is a p-type transistor, and the second reset transistor is an n-type transistor. The startup circuit includes an input transistor; The control terminal of the input transistor is electrically connected to the input control clock signal terminal, the first terminal of the input transistor is electrically connected to the reset output node, and the second terminal of the input transistor is electrically connected to the first output control node.

17. The display substrate as claimed in claim 6, wherein, The first reset sub-circuit includes a first reset transistor and a second reset transistor; The control terminal of the first reset transistor is electrically connected to the signal input terminal, the first terminal of the first reset transistor is electrically connected to the reset voltage terminal, and the second terminal of the first reset transistor is electrically connected to the reset output node. The control electrode of the second reset transistor is electrically connected to the reset signal terminal, the first electrode of the second reset transistor is electrically connected to the signal input terminal, and the second electrode of the second reset transistor is electrically connected to the reset output node. The startup circuit includes an input transistor; The control terminal of the input transistor is electrically connected to the input control clock signal terminal, the first terminal of the input transistor is electrically connected to the reset output node, and the second terminal of the input transistor is electrically connected to the first output control node.

18. The display substrate as claimed in claim 8, wherein, Includes a drive module; the drive module includes multiple cascaded drive circuits; In at least one stage of the driving circuit, the signal input terminal is electrically connected to the start signal line, and the control signal generation circuit is electrically connected to the start signal line and the inverted start signal line respectively.

19. The display substrate as claimed in claim 18, wherein, The first scan signal output terminal of the nth stage driving circuit is electrically connected to the signal input terminal of the (n+1)th stage driving circuit. The first scan signal output terminal of the nth stage driving circuit and the second scan signal output terminal of the nth stage driving circuit are electrically connected to the control signal generation circuit of the (n+1)th stage driving circuit, where n is a positive integer. In the 2a-level drive circuit, the first control clock signal terminal is electrically connected to the first clock signal line, the second control clock signal terminal is electrically connected to the second clock signal line, and the third control clock signal terminal is electrically connected to the third clock signal line. In the 2a+1 stage drive circuit, the first control clock signal terminal is electrically connected to the third clock signal line, the second control clock signal terminal is electrically connected to the fourth clock signal line, and the third control clock signal terminal is electrically connected to the first clock signal line. 'a' is a natural number.

20. The display substrate as claimed in claim 18, wherein, The first scan signal output terminal of the nth stage driving circuit is electrically connected to the signal input terminal of the (n+1)th stage driving circuit. The first scan signal output terminal of the nth stage driving circuit and the second scan signal output terminal of the nth stage driving circuit are electrically connected to the control signal generation circuit of the (n+1)th stage driving circuit, where n is a positive integer. In the 4a-level driving circuit, the first control clock signal terminal is connected to the first clock signal line, and the second control clock signal terminal is connected to the second clock signal line; in the 4a+1-level driving circuit, the first control clock signal terminal is connected to the second clock signal line, and the second control clock signal terminal is connected to the third clock signal line; in the 4a+2-level driving circuit, the first control clock signal terminal is connected to the third clock signal line, and the second control clock signal terminal is connected to the fourth clock signal line; in the 4a+3-level driving circuit, the first control clock signal terminal is connected to the fourth clock signal line, and the second control clock signal terminal is connected to the first clock signal line; where 'a' is a natural number.

21. The display substrate as claimed in claim 18, wherein, The first scan signal output terminal of the nth stage driving circuit is electrically connected to the signal input terminal of the (n+1)th stage driving circuit. The first scan signal output terminal of the nth stage driving circuit and the second scan signal output terminal of the nth stage driving circuit are electrically connected to the control signal generation circuit of the (n+1)th stage driving circuit, where n is a positive integer. In the 4a-level drive circuit, the first control clock signal terminal is connected to the first clock signal line, the second control clock signal terminal is connected to the second clock signal line, and the third control clock signal terminal is connected to the third clock signal line; in the 4a+1-level drive circuit, the first control clock signal terminal is connected to the second clock signal line, the second control clock signal terminal is connected to the third clock signal line, and the third control clock signal terminal is connected to the fourth clock signal line; in the 4a+2-level drive circuit, the first control clock signal terminal is connected to the third clock signal line, the second control clock signal terminal is connected to the fourth clock signal line, and the third control clock signal terminal is connected to the first clock signal line. In the 4a+3 level drive circuit, the first control clock signal terminal is connected to the fourth clock signal line, the second control clock signal terminal is connected to the first clock signal line, and the third control clock signal terminal is connected to the second clock signal line; where a is a natural number.

22. A display substrate, comprising: A substrate and a driving circuit disposed on the substrate; The driving circuit includes a scan signal generation circuit, which is used to provide at least one scan signal; The driving circuit also includes a reset circuit, which is electrically connected to the reset control terminal and the scan signal generation circuit, respectively. During non-refreshing periods, under the control of the reset control terminal, the reset circuit controls the scan signal generation circuit to output an invalid scan signal.

23. The display substrate as claimed in claim 22, wherein, The display substrate further includes pixel circuits disposed on the substrate; The display substrate includes a display area and a peripheral area; the driving circuit is disposed in the peripheral area; the pixel circuit is disposed in the display area; When the display substrate is in the first display state, the display area includes multiple areas along the scanning direction. When the last area of ​​the display area is displayed, the pixel circuits in the last area do not perform display refresh for at least one hold frame. The display refresh frequencies of two adjacent areas are different. The display substrate further includes a clock control circuit disposed on the substrate; the scan signal generation circuit is electrically connected to the control clock signal terminal and is used to provide a scan signal under the control of the control clock signal provided by the control clock signal terminal; The clock control circuit is used to control the reduction of the frequency of the control clock signal after the pixel circuit in the region adjacent to the last region completes the display refresh in the holding frame.

24. The display substrate as claimed in claim 22 or 23, wherein, The driving circuit further includes a startup circuit; the scanning signal generation circuit includes a first output control node. The startup circuit is electrically connected to the input control clock signal terminal, and is used to connect or disconnect the control signal input terminal and the first output control node under the control of the input control clock signal provided by the input control clock signal terminal. The startup circuit is electrically connected to the signal input terminal, and the startup circuit is electrically connected to the first output control node through the reset circuit; or... The reset circuit is electrically connected to the signal input terminal, and the reset circuit is electrically connected to the first output control node through the startup circuit.

25. The display substrate as claimed in claim 22 or 23, wherein, The driving circuit further includes a startup circuit; the reset circuit includes a first reset sub-circuit and a second reset circuit; the reset control terminal includes a reset signal terminal and / or a reset input node; The startup circuit is electrically connected to the input control clock signal terminal, the signal input terminal, and the reset input node, respectively, and is used to control the connection or disconnection between the signal input terminal and the reset input node under the control of the input control clock signal provided by the input control clock signal terminal; The first reset sub-circuit is electrically connected to the reset voltage terminal and the first output control node, respectively. The first reset sub-circuit is also electrically connected to the reset signal terminal or the reset input node, and is used to write the reset voltage provided by the reset voltage terminal into the first output control node under the control of the reset signal or the potential of the reset input node. The second reset sub-circuit is electrically connected to the reset signal terminal, the reset input node, and the first output control node, respectively, and is used to control the connection or disconnection between the reset input node and the first output control node under the control of the reset signal.

26. The display substrate as claimed in claim 22 or 23, wherein, The driving circuit further includes a startup circuit; the reset circuit includes a first reset sub-circuit and a second reset circuit; the reset control terminal includes a reset signal terminal and / or a signal input terminal. The first reset sub-circuit is electrically connected to the reset output node and the reset voltage terminal respectively. The first reset sub-circuit is also electrically connected to the reset signal terminal or the signal input terminal, and is used to write the reset voltage provided by the reset voltage terminal into the reset output node under the control of the reset signal or the input signal provided by the signal input terminal. The second reset sub-circuit is electrically connected to the signal input terminal, the reset signal terminal, and the reset output node, respectively, and is used to control the connection or disconnection between the signal input terminal and the reset output node under the control of the reset signal; The startup circuit is electrically connected to the input control clock signal terminal, the reset output node, and the first output control node, respectively, and is used to control the connection or disconnection between the reset output node and the first output control node under the control of the input control clock signal provided by the input control clock signal terminal.

27. The display substrate as claimed in claim 24, wherein, The scanning signal generation circuit includes a first on / off control circuit and a second output circuit. The first on / off control circuit is electrically connected to the second voltage signal terminal, the first output control node, and the second output node, respectively, and is used to control the connection or disconnection between the first output control node and the second output node under the control of the second voltage signal provided by the second voltage signal terminal. The second output circuit is electrically connected to the second output node, the first scan signal output terminal, and the second voltage signal terminal, respectively, and is used to control the connection or disconnection between the first scan signal output terminal and the second voltage signal terminal under the control of the potential of the second output node.

28. The display substrate as claimed in claim 22 or 23, wherein, The driving circuit further includes a control signal generation circuit and a control circuit; the scanning signal includes a first scanning signal and a second scanning signal. The scanning signal generation circuit is electrically connected to the first scanning signal output terminal and the second scanning signal output terminal respectively, and is used to provide a first scanning signal through the first scanning signal output terminal and a second scanning signal through the second scanning signal output terminal. The control signal generation circuit is electrically connected to the enable signal terminal and the first control node, respectively. The control signal generation circuit is also electrically connected to the first scan signal output terminal, the second scan signal output terminal, the first control terminal, and the second control terminal, respectively. It is used to control the connection or disconnection between the enable signal terminal and the first control node under the control of the first scan signal, the second scan signal, the first control signal provided by the first control terminal, and the second control signal provided by the second control terminal. The first control terminal is electrically connected to the output terminal of the first scan signal of the adjacent i-th stage, and the second control terminal is electrically connected to the output terminal of the second scan signal of the adjacent i-th stage, where i is a positive integer. The control circuit is connected to the first control node, the drive control terminal, and the drive signal output terminal respectively, and is used to provide a drive signal to the drive signal output terminal under the control of the potential of the first control node and the drive control signal provided by the drive control terminal. The drive control terminal is either the first scan signal output terminal or the second scan signal output terminal.

29. The display substrate as claimed in claim 28, wherein, The control circuit includes a first control sub-circuit, a second control sub-circuit, and a first inverting circuit; The first control sub-circuit is electrically connected to the first control node, the second control node, the first voltage signal terminal, and the second voltage signal terminal, respectively, and is used to control the second control node to connect with the first voltage signal terminal or the second voltage signal terminal under the control of the potential of the first control node, and to control the first control node to connect with the first voltage signal terminal or the second voltage signal terminal under the control of the potential of the second control node. The second control sub-circuit is electrically connected to the drive control terminal, the third control node, the first voltage signal terminal, and the second voltage signal terminal, respectively, and is used to control the third control node to connect with the first voltage signal terminal or the second voltage signal terminal under the control of the drive control signal; The first inverting circuit is electrically connected to the third control node and the drive signal output terminal, respectively, and is used to invert the potential of the third control node to obtain the drive signal.

30. The display substrate as claimed in claim 28, wherein, When the display area is in a normal refresh state, the enable signal provided by the enable signal terminal is a valid enable signal; When the display area is in the first display state, after the pixel circuit in the area adjacent to the last area completes the display refresh in the at least one holding frame, the enable signal is an invalid enable signal.

31. The display substrate as claimed in claim 27, wherein, The scanning signal generation circuit further includes a first node control circuit, a second on / off control circuit, a first output node control circuit, a second output node control circuit, a first output circuit, a first energy storage circuit, and a second inverting circuit; the control clock signal terminal includes a first control clock signal terminal, a second control clock signal terminal, and a third control clock signal terminal; the input control clock signal terminal is the first control clock signal terminal; The first node control circuit is electrically connected to the first control clock signal terminal, the second voltage signal terminal, the first node, and the first output control node, respectively. It is used to write the second voltage signal provided by the second voltage signal terminal into the first node under the control of the first control clock signal provided by the first control clock signal terminal, and to write the first control clock signal into the first node under the control of the potential of the first output control node. The second on / off control circuit is electrically connected to the second voltage signal terminal, the first node, and the second output control node, respectively, and is used to control the connection or disconnection between the first node and the second output control node under the control of the second voltage signal. The first output node control circuit is electrically connected to the first output node, the second control clock signal terminal, the second output control node, the first output control node, and the first voltage signal terminal, respectively. It is used to control the potential of the first output node under the control of the potential of the second output control node and the second control clock signal provided by the second control clock signal terminal, and to write the first voltage signal provided by the first voltage signal terminal into the first output node under the control of the potential of the first output control node. The second output node control circuit is electrically connected to the second output node, the first output node, the first voltage signal terminal, and the third control clock signal terminal, respectively, and is used to control the potential of the second output node under the control of the potential of the first output node and under the control of the third control clock signal provided by the third control clock signal terminal. The first output circuit is electrically connected to the first output node, the first voltage signal terminal and the first scan signal output terminal respectively, and is used to write the first voltage signal to the first scan signal output terminal under the control of the potential of the first output node; The first energy storage circuit is electrically connected to the first output node and is used to maintain the potential of the first output node; The second inverting circuit is electrically connected to the first scan signal output terminal and the second scan signal output terminal respectively, and is used to invert the first scan signal to obtain and output the second scan signal through the second scan signal output terminal.

32. The display substrate as claimed in claim 31, wherein, The third control clock signal terminal is the same as the first control clock signal terminal.

33. The display substrate as claimed in claim 27, wherein, The scanning signal generation circuit further includes a first node control circuit, a second on / off control circuit, a first output node control circuit, a second output node control circuit, a first output circuit, a first energy storage circuit, and a second inverting circuit; the control clock signal terminal includes a first control clock signal terminal, a second control clock signal terminal, and a third control clock signal terminal; the input control clock signal terminal is the first control clock signal terminal; The first node control circuit is electrically connected to the second control clock signal terminal, the second voltage signal terminal, the first node, and the first output control node, respectively. It is used to write the second voltage signal provided by the second voltage signal terminal into the first node under the control of the second control clock signal provided by the second control clock signal terminal, and to write the second control clock signal into the first node under the control of the potential of the first output control node. The second on / off control circuit is electrically connected to the second voltage signal terminal, the first node, and the second output control node, respectively, and is used to control the connection or disconnection between the first node and the second output control node under the control of the second voltage signal. The first output node control circuit is electrically connected to the first output node, the third control clock signal terminal, the second output control node, the first output control node, and the first voltage signal terminal, respectively. It is used to control the potential of the first output node under the control of the potential of the second output control node and the third control clock signal provided by the third control clock signal terminal, and to write the first voltage signal provided by the first voltage signal terminal into the first output node under the control of the potential of the first output control node. The second output node control circuit is electrically connected to the second output node, the first output node, the first voltage signal terminal, and the first control clock signal terminal, respectively, and is used to control the potential of the second output node under the control of the potential of the first output node and under the control of the first control clock signal provided by the first control clock signal terminal; The first output circuit is electrically connected to the first output node, the first voltage signal terminal and the first scan signal output terminal respectively, and is used to write the first voltage signal to the first scan signal output terminal under the control of the potential of the first output node; The first energy storage circuit is electrically connected to the first output node and is used to maintain the potential of the first output node; The second inverting circuit is electrically connected to the first scan signal output terminal and the second scan signal output terminal respectively, and is used to invert the first scan signal to obtain and output the second scan signal through the second scan signal output terminal.

34. A driving method applied to a display substrate as described in any one of claims 2 to 21, wherein, The driving method includes: When the display substrate is in the first display state, after the pixel circuit in the area adjacent to the last area completes the display refresh in the holding frame, the frequency of the control clock signal is reduced. After the pixel circuit in the region adjacent to the last region completes the display refresh, the control scan signal generation circuit outputs an invalid scan signal.

35. The driving method as described in claim 34, wherein, The step of reducing the frequency of the control clock signal includes: reducing the frequency of the control clock signal to half of its original frequency. k , where k is a positive integer.

36. A driving method applied to a display substrate as described in any one of claims 23 to 33, the driving method comprising: When the display substrate is in the first display state, after the pixel circuit in the area adjacent to the last area completes the display refresh in the holding frame, the frequency of the control clock signal is reduced. During non-refresh periods, the control scan signal generation circuit outputs an invalid scan signal.

37. The driving method as described in claim 36, wherein, The step of reducing the frequency of the control clock signal includes: reducing the frequency of the control clock signal to half of its original frequency. k , where k is a positive integer.

38. A display device comprising a display substrate as claimed in any one of claims 1 to 33.

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