Signal processing method, circuit and chip, and electronic device

Abstract

Embodiments of the present application provide a signal processing method, circuit and chip, and an electronic device. The signal processing method comprises: processing an inputted digital signal on the basis of a PWM synchronous clock signal to obtain an analog differential signal; performing chopping processing on an intermediate common-mode voltage signal on the basis of a chopping clock signal to obtain a common-mode voltage signal, wherein the intermediate common-mode voltage signal is used for stabilizing a common-mode voltage of the analog differential signal, and an edge of a pulse comprised in the chopping clock signal and an edge of a pulse comprised in the PWM synchronous clock signal are not aligned in timing; performing noise shaping on the analog differential signal and then performing PWM to obtain a PWM signal; and performing voltage domain conversion on the PWM signal to obtain an output signal. The present solution can improve performance of signal processing.

Description

Signal processing methods, circuits, chips and electronic devices Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to a signal processing method, circuit, chip, and electronic device. Background Technology

[0002] Pulse-Width Modulation (PWM) is a technique that uses the digital output of a microprocessor to control analog circuits. By modulating the width of the pulse, the desired waveform (including shape and amplitude) is obtained, i.e., the voltage and frequency are adjusted by changing the duty cycle. Class D power amplifiers (also known as digital power amplifiers or switching power amplifiers) that employ PWM technology are often used to amplify audio signals.

[0003] Currently, when the input of a Class D power amplifier is a digital signal, the digital signal is converted into an analog signal, and a PWM signal is generated based on the analog signal through PWM modulation.

[0004] However, when the operating voltage of the chip containing the Class D power amplifier is high, the signal fed back to the signal chain or analog loop filter contains a large common-mode feedback current. The presence of this common-mode feedback current will cause significant distortion, which in turn leads to poor performance of the Class D power amplifier. Summary of the Invention

[0005] In view of this, embodiments of this application provide a signal processing method, circuit, chip, and electronic device to at least partially solve the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, a signal processing method is provided, comprising: processing an input digital signal according to a PWM synchronization clock signal to obtain an analog differential signal; chopping an intermediate common-mode voltage signal according to a chopping clock signal to obtain a common-mode voltage signal, wherein the intermediate common-mode voltage signal is used to stabilize the common-mode voltage of the analog differential signal, and the timing of the pulses included in the chopping clock signal is not aligned with the timing of the pulses included in the PWM synchronization clock signal; performing noise shaping on the analog differential signal and then performing PWM modulation to obtain a PWM signal; and performing voltage domain conversion on the PWM signal to obtain an output signal.

[0007] According to a second aspect of the embodiments of this application, a signal processing circuit is provided, comprising: a digital signal processor, configured to process an input digital signal according to a PWM synchronization clock signal to obtain an analog differential signal; a chopper, configured to chop an intermediate common-mode voltage signal according to a chopper clock signal to obtain a common-mode voltage signal, wherein the intermediate common-mode voltage signal is used to stabilize the common-mode voltage of the analog differential signal, and the timing of the pulse edges included in the chopper clock signal is not aligned with the timing of the pulse edges included in the PWM synchronization clock signal; a modulation module, configured to perform noise shaping on the analog differential signal and then perform PWM modulation to obtain a PWM signal; and a power output module, configured to perform voltage domain conversion on the PWM signal to obtain an output signal.

[0008] According to a third aspect of the embodiments of this application, a signal processing chip is provided, the signal processing chip being used to perform the method as described in the first aspect above.

[0009] According to a fourth aspect of the present application, an electronic device is provided, comprising: a signal source, a signal receiver, and a signal processing device, wherein the signal processing device includes a signal processing circuit as described in the second aspect above or a signal processing chip as described in the third aspect above; the signal processing device is connected between the signal source and the signal receiver; the signal source is used to transmit an input digital signal to the signal processing device; and the signal receiver is used to receive an output signal output by the signal processing device.

[0010] According to the scheme of this application embodiment, the input digital signal is processed according to the PWM synchronous clock signal to obtain an analog differential signal, and the intermediate common-mode signal is chopped according to the chopping clock signal to obtain a common-mode voltage signal. The common-mode voltage signal can stabilize the common-mode voltage of the analog differential signal. Moreover, the timing of the pulse edge of the chopping clock signal is not aligned with the timing of the pulse edge of the PWM synchronous clock signal, so that the arrival of the pulse of the analog differential signal at the input common-mode point and the frequency switching do not occur simultaneously. That is, before the pulse of the analog differential signal reaches the input common-mode point, a certain amount of time is left for the intermediate common-mode voltage signal to stabilize, thereby ensuring the suppression effect of noise and harmonics when noise shaping the analog differential signal. This ensures that the analog differential signal is sent to the noise shaping filter without loss and distortion. Then, after the noise-shaped analog differential signal is PWM modulated to obtain the PWM signal, the PWM signal contains less noise and harmonics. Thus, after the PWM signal is voltage domain converted to obtain the output signal, the output signal contains less noise and harmonics, ensuring the performance of signal processing. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0012] Figure 1 is a flowchart of a signal processing method according to an embodiment of this application;

[0013] Figure 2 is a schematic diagram of the chopper clock signal and the PWM synchronization clock signal according to an embodiment of this application;

[0014] Figure 3 is a schematic diagram of the chopper clock signal and the PWM synchronization clock signal according to another embodiment of this application;

[0015] Figure 4 is a schematic diagram of a clock signal according to an embodiment of this application;

[0016] Figure 5 is a schematic diagram of a signal processing circuit according to an embodiment of this application;

[0017] Figure 6 is a schematic diagram of a signal processing circuit according to another embodiment of this application;

[0018] Figure 7 is a schematic diagram of a signal processing circuit according to another embodiment of this application;

[0019] Figure 8 is a schematic diagram of an input common-mode feedback buffer amplifier according to an embodiment of this application;

[0020] Figure 9 is a schematic diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0022] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0023] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0025] Signal processing methods

[0026] Figure 1 is a flowchart of a signal processing method according to an embodiment of this application. As shown in Figure 1, the signal processing method includes the following steps:

[0027] Step 101: Process the input digital signal according to the PWM synchronous clock signal to obtain the analog differential signal.

[0028] Digital signals can be digital audio signals, such as digital audio signals transmitted by a host computer through the integrated circuit's built-in audio bus (Inter-IC Sound, I2S).

[0029] In one example, a digital audio processor (DAP) can preprocess the digital signal (e.g., noise shaping) and convert the preprocessed digital signal into an analog signal to obtain an analog differential signal. A digital audio processor is a type of digital signal processor (DSP). Analog differential signals include positive and negative analog differential signals. Both positive and negative analog differential signals are digital PWM waves. The pulse width of the differential signal in both signals indicates the magnitude of the digital signal; for example, the pulse width of the differential signal is positively correlated with the signal strength of the digital signal. The magnitude of the digital signal can be directly mapped to the duty cycle of the PWM wave. For instance, if the input digital signal value is large, the high-level time of the PWM signal will be longer within one cycle; if the signal value is small, the high-level time will be shorter. The main purpose of using analog differential signals is to improve anti-interference capability.

[0030] The PWM synchronization clock signal is used to synchronize analog differential signals, specifically the positive and negative analog differential signals. When processing digital signals via a DAP, the PWM synchronization clock signal and the digital signal are input to the DAP. After preprocessing the digital signal, the DAP converts the preprocessed digital signal into positive and negative analog differential signals, and then synchronizes these signals according to the PWM synchronization clock signal before outputting them.

[0031] Step 102: Chop the intermediate common-mode voltage signal according to the chopping clock signal to obtain the common-mode voltage signal.

[0032] The intermediate common-mode voltage signal is chopped according to the chopping clock signal to obtain the common-mode voltage signal, which is used to stabilize the common-mode voltage of the analog differential signal. By chopping the intermediate common-mode voltage signal, the flicker noise (also known as 1 / f noise) included in the intermediate common-mode voltage signal can be modulated into the audio frequency band, thereby improving the signal-to-noise ratio (SNR) of the processed audio signal.

[0033] The intermediate common-mode voltage signal can include a positive intermediate common-mode voltage signal and a negative intermediate common-mode voltage signal, and the positive and negative intermediate common-mode voltage signals are identical. The intermediate common-mode voltage signal can be generated through feedback, so that the positive and negative intermediate common-mode voltage signals approach the common-mode voltage reference signal.

[0034] In one example, the common-mode voltage reference signal is a 2.7V DC signal, and the positive and negative intermediate common-mode voltage signals are approximately straight-line waves, that is, the positive and negative intermediate common-mode voltage signals are DC voltage signals with magnitudes close to 2.7V.

[0035] Because the chip operates at voltages ranging from low to high, it generates significant common-mode feedback current when operating at high voltages. An input common-mode feedback buffer amplifier, which generates an intermediate common-mode voltage signal, absorbs this feedback current to ensure the stability of the common-mode voltage of the analog differential signal. In other words, the common-mode voltage signal is used to stabilize the common-mode voltage of the analog differential signal. Analog circuits require a suitable operating point, and the input common-mode feedback buffer amplifier can stabilize the common-mode voltage at the input common-mode point. Stabilizing the common-mode voltage of the analog differential signal through the common-mode voltage signal reduces signal loss and improves the performance of the processed audio signal.

[0036] In one example, chopping the positive intermediate common-mode voltage signal yields a positive common-mode voltage signal, and chopping the negative intermediate common-mode voltage signal yields a negative common-mode voltage signal. The positive common-mode voltage signal is coupled to the positive analog differential signal, and the negative common-mode voltage signal is coupled to the negative analog differential signal to stabilize the common-mode voltages of the positive and negative analog differential signals.

[0037] In one example, the DAP outputs an analog differential signal to an analog loop filter (ALF). The ALF performs noise shaping on the analog differential signal and then performs PWM modulation to obtain a PWM signal. An input common-mode feedback buffer (Input CMFB) processes the common-mode voltage reference signal to obtain an intermediate common-mode voltage signal. A chopper, based on a chopper clock signal, chops the intermediate common-mode voltage signal to obtain a common-mode voltage signal, which is the common-mode signal at the ALF input. The PWM synchronization clock signal is used to synchronize the DAP's output signal, and the chopper clock signal is used to drive the chopper.

[0038] At the leading edge of the pulse included in the PWM synchronization clock signal, the DAP outputs a pulse to the input common-mode point (virtual point) of the ALF. The chopper is also connected to this input common-mode point. The chopper's chopping frequency switches at the edge of the chopper clock signal, and the input common-mode feedback buffer amplifier needs time to stabilize. If the edges of the pulses included in the PWM synchronization clock signal and the chopper clock signal are synchronized, the chopping switching occurs simultaneously with the DAP output pulse. At this time, the output of the input common-mode feedback buffer amplifier has not yet stabilized, causing a drop in the impedance of the input common-mode point. This reduces the loop's suppression of noise and harmonics, leading to a decrease in signal processing performance. Therefore, the edges of the pulses included in the chopper clock signal are not time-aligned with the edges of the pulses included in the PWM synchronous clock signal. That is, the chopper clock signal and the PWM synchronous clock signal are out of phase. The leading edge of the pulses included in the chopper clock signal is not time-aligned with the leading edge and trailing edge of the pulses included in the PWM synchronous clock signal, and the trailing edge of the pulses included in the chopper clock signal is not time-aligned with the leading edge and trailing edge of the pulses included in the PWM synchronous clock signal. Before the pulses output by the DAP reach the input common-mode point, a certain amount of time is allowed for the output of the input common-mode feedback buffer amplifier to stabilize, thereby ensuring the loop's suppression effect on noise and harmonics and ensuring the performance of signal processing.

[0039] Step 103: After noise shaping of the analog differential signal, perform PWM modulation to obtain the PWM signal.

[0040] Noise shaping of analog differential signals can filter out high-order PWM modulation harmonics in the analog differential signals. PWM modulation of the noise-shaped analog differential signals can obtain PWM signals, which include positive and negative PWM signals.

[0041] In one example, the analog differential signal includes a positive analog differential signal and a negative analog differential signal. The positive and negative analog differential signals are coupled to the input of the ALF, and after noise shaping, they are sent to a comparator for comparison with a triangular wave. The comparison result is then processed logically to obtain the positive and negative PWM signals.

[0042] Step 104: Perform voltage domain conversion on the PWM signal to obtain the output signal.

[0043] After obtaining the PWM signal, a voltage domain conversion can be performed to obtain the output signal, which can include both positive and negative output signals. The purpose of voltage domain conversion is to change the amplitude of the PWM signal while maintaining its duty cycle. For example, if the PWM signal has an amplitude of 2.7V and a duty cycle of 30%, voltage domain conversion will result in an output signal with an amplitude of 24V and a duty cycle of 30%. In one example, when the digital signal is a digital audio signal, the output signal, after filtering (such as LC filtering or low-pass filtering), can be used to drive a speaker.

[0044] In this embodiment, the input digital signal is processed according to the PWM synchronous clock signal to obtain an analog differential signal, and the intermediate common-mode signal is chopped according to the chopping clock signal to obtain a common-mode voltage signal. The common-mode voltage signal can stabilize the common-mode voltage of the analog differential signal. The timing of the pulse edges included in the chopping clock signal and the pulse edges included in the PWM synchronous clock signal is not aligned, so that the arrival of the pulses included in the analog differential signal at the input common-mode point and the frequency switching do not occur simultaneously. That is, a certain amount of time is allowed before the pulses included in the analog differential signal reach the input common-mode point to stabilize the intermediate common-mode voltage signal, thereby ensuring the suppression effect of noise and harmonics when noise shaping is performed on the analog differential signal. Then, after the noise-shaped analog differential signal is PWM modulated to obtain the PWM signal, the PWM signal contains less noise and harmonics. Thus, after the PWM signal is voltage domain converted to obtain the output signal, the output signal contains less noise and harmonics, ensuring the performance of signal processing.

[0045] In one possible implementation, the leading edge of the pulse included in the chopper clock signal is located between the leading edge and trailing edge of the first pulse included in the PWM synchronous clock signal in timing, and the phase delay range of the leading edge of the pulse included in the chopper clock signal relative to the leading edge of the first pulse is [45°, 135°].

[0046] For any pulse included in the chopper clock signal, the first pulse is the pulse in the PWM synchronous clock signal that corresponds to the pulse in terms of timing. The leading edge of the first pulse is located between the leading edge and the trailing edge of the corresponding first pulse in terms of timing, and the phase delay range between the leading edge of the first pulse and the leading edge of the corresponding first pulse is [45°, 135°].

[0047] The chopper clock signal can consist of pulses that are either low or high. In a chopper clock signal, if the pulse is low, the leading edge of the pulse is a falling edge and the trailing edge is a rising edge; if the pulse is high, the leading edge of the pulse is a rising edge and the trailing edge is a falling edge.

[0048] The pulses in a PWM synchronization clock signal can be either low or high. In a PWM synchronization clock signal, if the pulse is low, its leading edge is a falling edge and its trailing edge is a rising edge; if the pulse is high, its leading edge is a rising edge and its trailing edge is a falling edge. The pulses in a chopper clock signal can also be either low or high.

[0049] Taking the example that both the chopper clock signal and the PWM synchronization clock signal consist of high-level pulses, Figure 2 shows a schematic diagram of the chopper clock signal and the PWM synchronization clock signal according to an embodiment of this application. As shown in Figure 2, the pulse A included in the chopper clock signal and the pulse B included in the PWM synchronization clock signal are two pulses that are corresponding in timing. The rising edge of pulse A is located between the rising edge and the falling edge of pulse B in timing, and the phase delay of the rising edge of pulse A relative to the rising edge of pulse B is θ, where 45°≤θ≤135°.

[0050] It should be noted that the frequency of the PWM synchronization clock signal is an integer multiple of the frequency of the chopper clock signal. When the leading edge of a pulse included in the chopper clock signal is located between the leading edge and trailing edge of a certain pulse included in the PWM synchronization clock signal in terms of timing, the trailing edge of that pulse included in the chopper clock signal is located between the leading edge and trailing edge of the fourth pulse included in the PWM synchronization clock signal in terms of timing. Furthermore, the phase delay of the trailing edge of the pulse included in the chopper clock signal relative to the leading edge of the fourth pulse is the same as the phase delay of the leading edge of that pulse included in the chopper clock signal relative to the leading edge of the first pulse. That is, the phase delay range of the trailing edge of the pulse included in the chopper clock signal relative to the leading edge of the fourth pulse is [45°, 135°]. In terms of timing, the fourth pulse is located after the first pulse. The first and fourth pulses can be adjacent pulses in the PWM synchronization clock signal, or there can be one or more pulses between the first and fourth pulses.

[0051] As shown in Figure 2, the rising edge of pulse A is located between the rising and falling edges of pulse B in terms of timing, and the phase delay of the rising edge of pulse A relative to the rising edge of pulse B is θ. The falling edge of pulse A is located between the rising and falling edges of pulse C, and the phase delay of the falling edge of pulse A relative to the rising edge of pulse C is θ.

[0052] In this embodiment, the leading edge of the pulse included in the chopper clock signal is located between the leading edge and trailing edge of the first pulse included in the PWM synchronous clock signal in terms of timing, and the phase delay range of the leading edge of the pulse included in the chopper clock signal relative to the leading edge of the first pulse is [45°, 135°]. The PWM synchronous clock signal is used to synchronize the analog differential signal, thereby ensuring that the arrival of the pulse included in the analog differential signal at the input common mode point and the chopping switching of the chopper clock signal do not occur simultaneously. Furthermore, before the pulse included in the analog differential signal reaches the input common mode point, there is sufficient time for the intermediate common mode voltage signal to stabilize, thereby ensuring the suppression effect of noise and harmonics when performing noise shaping on the analog differential signal.

[0053] In one possible implementation, the leading edge of the chopping clock signal includes a pulse that is 90° phase-delayed relative to the leading edge of the first pulse.

[0054] The leading edge of the pulse included in the chopper clock signal is located between the leading edge and trailing edge of the first pulse in the PWM synchronous clock signal in terms of timing. When the leading edge of the pulse included in the chopper clock signal is time-aligned with the leading edge of the first pulse, the phase delay of the leading edge of the pulse included in the chopper clock signal relative to the leading edge of the first pulse is 0. When the leading edge of the pulse included in the chopper clock signal is time-aligned with the trailing edge of the first pulse, the phase delay of the leading edge of the pulse included in the chopper clock signal relative to the leading edge of the first pulse is 180°.

[0055] As shown in Figure 2, when the leading edge of pulse A is time-aligned with the leading edge of pulse B, θ equals 0, and when the leading edge of pulse A is time-aligned with the trailing edge of pulse B, θ equals 180°.

[0056] In this embodiment, the leading edge of the pulse included in the chopper clock signal is delayed by 90° relative to the leading edge of the first pulse in the PWM synchronous clock signal. The phase difference between the leading edge of the pulse included in the chopper clock signal and the leading edge and trailing edge of the first pulse is 90°. The leading edge of the pulse included in the chopper clock signal has a large phase difference with the leading edge and trailing edge of the first pulse. This ensures that the arrival of the pulse included in the analog differential signal at the input common-mode point and the frequency chopping switch do not occur simultaneously. At the same time, the intermediate common-mode voltage signal has enough time to stabilize, avoiding the impedance drop at the input common-mode point. This ensures the suppression effect of noise and harmonics when performing noise shaping on the analog differential signal.

[0057] In one possible implementation, the leading edge of the pulse included in the chopper clock signal is time-sequentially located between the trailing edge of the second pulse and the leading edge of the third pulse included in the PWM synchronization clock signal, and the phase delay range of the leading edge of the pulse included in the chopper clock signal relative to the trailing edge of the second pulse is [45°, 135°]. In the PWM synchronization clock signal, the second pulse and the third pulse are time-adjacent pulses.

[0058] For any pulse included in the chopper clock signal, the second pulse and the third pulse are two adjacent pulses in the PWM synchronous clock signal that correspond to the leading edge of the pulse in terms of timing, and the leading edge of the pulse is located between the trailing edge of the second pulse and the leading edge of the third pulse.

[0059] The pulses in a PWM synchronization clock signal can be either low or high. In a PWM synchronization clock signal, if the pulse is low, its leading edge is a falling edge and its trailing edge is a rising edge; if the pulse is high, its leading edge is a rising edge and its trailing edge is a falling edge. The pulses in a chopper clock signal can also be either low or high.

[0060] Taking the example where both the chopper clock signal and the PWM synchronization clock signal consist of high-level pulses, Figure 3 shows a schematic diagram of the chopper clock signal and the PWM synchronization clock signal according to an embodiment of this application. As shown in Figure 3, the chopper clock signal includes pulse A, and the PWM synchronization clock signal includes pulses D and E. The rising edge of pulse A is located between the falling edge of pulse D and the rising edge of pulse E in timing, and the phase delay of the rising edge of pulse A relative to the falling edge of pulse D is α, where 45°≤α≤135°.

[0061] It should be noted that the frequency of the PWM synchronization clock signal is an integer multiple of the frequency of the chopper clock signal. When the leading edge of the pulse included in the chopper clock signal is located between the second and third pulses in timing, the trailing edge of the pulse included in the chopper clock signal is located between the other two adjacent pulses included in the PWM synchronization clock signal in timing. The phase delay of the trailing edge of the pulse included in the chopper clock signal relative to the leading edge of the preceding pulse in the other two adjacent pulses is the same as the phase delay of the leading edge of the pulse included in the chopper clock signal relative to the leading edge of the second pulse. That is, the phase delay range of the trailing edge of the pulse included in the chopper clock signal relative to the leading edge of the preceding pulse in the other two adjacent pulses is [45°, 135°].

[0062] As shown in Figure 3, pulses D and E are two adjacent pulses in the PWM synchronization clock signal, and pulses F and G are also two adjacent pulses in the PWM synchronization clock signal. Timing-wise, pulse E follows pulse D, pulse F follows pulse E, and pulse G follows pulse F. The rising edge of pulse A is time-wise located between the falling edge of pulse D and the rising edge of pulse E, with a phase delay of α relative to the falling edge of pulse D. The falling edge of pulse A is time-wise located between the falling edge of pulse F and the rising edge of pulse G, with a phase delay of α relative to the falling edge of pulse F.

[0063] In this embodiment, the leading edge of the pulse included in the chopper clock signal is located between the trailing edge of the second pulse and the leading edge of the third pulse included in the PWM synchronous clock signal in terms of timing. The second pulse and the third pulse are two adjacent pulses in the PWM synchronous clock signal, and the phase delay range between the leading edge of the pulse included in the chopper clock signal and the leading edge of the second pulse is [45°, 135°]. The PWM synchronous clock signal is used to synchronize the analog differential signal, thereby ensuring that the arrival of the pulse included in the analog differential signal at the input common mode point and the frequency switching of the chopper clock signal do not occur simultaneously. Furthermore, before the pulse included in the analog differential signal reaches the input common mode point, there is sufficient time for the intermediate common mode voltage signal to stabilize, thereby ensuring the suppression effect of noise and harmonics when performing noise shaping on the analog differential signal.

[0064] In one possible implementation, the leading edge of the chopping clock signal is delayed by 90° relative to the trailing edge of the second pulse.

[0065] The leading edge of the pulse included in the chopper clock signal is located between the trailing edge of the second pulse and the leading edge of the third pulse in the PWM synchronous clock signal in terms of timing. When the leading edge of the pulse included in the chopper clock signal is time-aligned with the trailing edge of the second pulse, the phase delay of the leading edge of the pulse included in the chopper clock signal relative to the trailing edge of the second pulse is 0. When the leading edge of the pulse included in the chopper clock signal is time-aligned with the leading edge of the third pulse, the phase delay of the leading edge of the pulse included in the chopper clock signal relative to the trailing edge of the second pulse is 180°.

[0066] As shown in Figure 3, when the leading edge of pulse A is aligned with the trailing edge of pulse D, α equals 0; when the leading edge of pulse A is aligned with the leading edge of pulse E, α equals 180°.

[0067] In this embodiment, the leading edge of the pulse included in the chopper clock signal is located between the adjacent second and third pulses in the PWM synchronous clock signal in terms of timing, and the phase delay of the leading edge of the pulse included in the chopper clock signal relative to the trailing edge of the second pulse is 90°. Therefore, the phase difference between the leading edge of the pulse included in the chopper clock signal and the trailing edges of the second and third pulses is 90°. This ensures that the leading edge of the pulse included in the chopper clock signal has a large phase difference with the trailing edges of the second and third pulses. This ensures that the arrival of the pulse included in the analog differential signal at the input common-mode point and the frequency switching of the chopper clock signal do not occur simultaneously. At the same time, the intermediate common-mode voltage signal has enough time to stabilize, avoiding the impedance drop at the input common-mode point. This, in turn, ensures the suppression effect of noise and harmonics when performing noise shaping on the analog differential signal.

[0068] In one possible implementation, the chopper clock signal and the PWM synchronization clock signal can be from the same source clock. Before chopping the intermediate common-mode voltage signal according to the chopper clock signal to obtain the common-mode voltage signal, the PWM synchronization clock signal can be divided to obtain a frequency-divided signal. Then, the frequency-divided signal can be resampled according to the resampling clock signal to obtain the chopper clock signal.

[0069] By dividing the PWM synchronous clock signal, a divided signal can be obtained, the frequency of which is less than the frequency of the PWM synchronous clock signal. The division factor for the PWM synchronous clock signal is an integer. This application does not limit the division factor when dividing the PWM synchronous clock signal; for example, the division factor can be 2, 4, etc.

[0070] A chopper clock signal can be obtained by resampling the frequency-divided signal using the resampling clock signal. By controlling the frequency and number of resampling operations of the resampling clock signal, the phase delay of the leading edge of the pulse in the chopper clock signal relative to the leading edge of the first pulse or the trailing edge of the second pulse can be controlled. The resampling clock signal can be obtained based on the PWM synchronization clock signal, and the frequency of the resampling clock signal is greater than the frequency of the PWM synchronization clock signal, for example, the frequency of the resampling clock signal is an integer multiple of the frequency of the PWM synchronization clock signal.

[0071] In this embodiment, after obtaining a frequency-divided signal by dividing the PWM synchronous clock signal, the frequency-divided signal is resampled according to the resampled clock signal to obtain a chopper clock signal. That is, the chopper clock signal and the PWM synchronous clock signal are from the same source clock, ensuring that the timing of the pulses included in the chopper clock signal and the pulses included in the PWM synchronous clock signal is correct. That is, the timing of the pulse edges in the chopper clock signal is not aligned with the timing of the pulse edges in the PWM synchronous clock signal, ensuring that the arrival of the pulses included in the analog differential signal at the input common-mode point and the frequency switching of the chopper clock signal do not occur simultaneously, avoiding the situation of the input common-mode point impedance dropping, thereby ensuring the suppression effect of noise and harmonics when performing noise shaping on the analog differential signal.

[0072] In one possible implementation, when resampling the frequency-divided signal to obtain the chopper clock signal, the frequency-divided signal can be resampled at least once based on the resampled clock signal to obtain the chopper clock signal. The frequency of the resampled clock signal is greater than or equal to four times the frequency of the PWM synchronization clock signal.

[0073] After acquiring the frequency-divided signal, it can be resampled according to the resampled clock signal to obtain the chopper clock signal. When obtaining the chopper clock signal by sampling the frequency-divided signal according to the resampled clock signal, the number of resampling and the frequency of the resampled clock signal will determine the phase delay of the leading edge of the pulse in the chopper clock signal relative to the leading edge of the first pulse or the trailing edge of the second pulse in the PWM synchronization clock signal.

[0074] The resampling clock signal and the PWM synchronization clock signal can be from the same source clock. The frequency of the resampling clock signal is greater than the frequency of the PWM synchronization clock signal. The frequency of the resampling clock signal can be an integer multiple of the PWM synchronization clock signal, such as 4 times, 8 times or 16 times the frequency of the PWM synchronization clock signal.

[0075] In one example, when the frequency of the resampling clock signal is 4 times the frequency of the PWM synchronization clock signal, if the number of resampling is 1, the leading edge of the pulse in the chopper clock signal is delayed by 90° relative to the leading edge of the first pulse in the PWM synchronization clock signal. If the number of resampling is 3, the leading edge of the pulse in the chopper clock signal is delayed by 90° relative to the trailing edge of the second pulse in the PWM synchronization clock signal.

[0076] In another example, when the frequency of the resampled clock signal is 8 times the frequency of the PWM synchronization clock signal, if the number of resampling is 1, the leading edge of the pulse in the chopper clock signal is delayed by 45° relative to the leading edge of the first pulse in the PWM synchronization clock signal; if the number of resampling is 2, the leading edge of the pulse in the chopper clock signal is delayed by 90° relative to the leading edge of the first pulse in the PWM synchronization clock signal; if the number of resampling is 3, the leading edge of the pulse in the chopper clock signal is delayed by 135° relative to the leading edge of the first pulse in the PWM synchronization clock signal; if the number of resampling is 5, the leading edge of the pulse in the chopper clock signal is delayed by 45° relative to the trailing edge of the second pulse in the PWM synchronization clock signal; if the number of resampling is 6, the leading edge of the pulse in the chopper clock signal is delayed by 90° relative to the trailing edge of the second pulse in the PWM synchronization clock signal; and if the number of resampling is 7, the leading edge of the pulse in the chopper clock signal is delayed by 135° relative to the trailing edge of the second pulse in the PWM synchronization clock signal.

[0077] In this embodiment, when resampling the frequency-divided signal according to the resampling clock signal, the phase delay of the leading edge of the pulse in the chopper clock signal relative to the leading edge of the first pulse or the trailing edge of the second pulse in the PWM synchronous clock signal can be controlled by controlling the frequency and the number of resampling cycles of the resampling clock signal, thus meeting the requirements for different phase delays. The frequency of the resampling clock signal is greater than or equal to four times the frequency of the PWM synchronous clock signal, which ensures that the timing of the pulse edges in the chopper clock signal is misaligned with that in the PWM synchronous clock signal, thereby guaranteeing the suppression effect of noise and harmonics when the analog differential signal is noise-shaped.

[0078] In one possible implementation, when resampling the frequency-divided signal to obtain the chopper clock signal, the resampled clock signal can be delayed, and then the frequency-divided signal can be resampled based on the delayed resampled clock signal to obtain the chopper clock signal.

[0079] By delaying the resampled clock signal and resampling the frequency-divided signal based on the delayed resampled clock signal to obtain the chopper clock signal, the leading edge of the pulse in the chopper clock signal can be phase-delayed relative to the leading edge of the first pulse or the trailing edge of the second pulse in the PWM synchronous clock signal. For example, when the frequency of the resampled clock signal is equal to the frequency of the PWM synchronous clock signal and the number of resampling times is 1, delaying the phase of the resampled clock signal by 45° will delay the leading edge of the pulse in the chopper clock signal by 45° relative to the leading edge of the first pulse in the PWM synchronous clock signal. Delaying the phase of the resampled clock signal by 90° will delay the leading edge of the pulse in the chopper clock signal by 90° relative to the leading edge of the first pulse in the PWM synchronous clock signal. Delaying the phase of the resampled clock signal by 135° will delay the leading edge of the pulse in the chopper clock signal by 135° relative to the leading edge of the first pulse in the PWM synchronous clock signal.

[0080] It should be noted that after delaying the resampled clock signal, the frequency division signal can be resampled once or multiple times based on the delayed resampled clock signal to adjust the phase delay of the leading edge of the pulse in the obtained chopper clock signal relative to the leading edge of the first pulse or the trailing edge of the second pulse in the PWM synchronous clock signal.

[0081] In this embodiment, since the PWM synchronous clock signal and the resampling clock signal are from the same source, by delaying the resampling clock signal and then resampling the frequency division signal at least once using the delayed resampling clock signal to obtain the chopper clock signal, the timing of the pulse edges included in the chopper clock signal is misaligned with the timing of the pulse edges in the PWM synchronous clock signal. This ensures that the arrival of the pulses included in the analog differential signal at the input common-mode point and the frequency switching do not occur simultaneously. That is, before the pulses included in the analog differential signal reach the input common-mode point, a certain amount of time is allowed for the intermediate common-mode voltage signal to stabilize, thereby ensuring the suppression effect of noise and harmonics when performing noise shaping on the analog differential signal.

[0082] In one possible implementation, when generating a PWM signal based on an analog differential signal, noise shaping can be performed on the analog differential signal according to the analog sampling clock signal to obtain the PWM input differential signal. Then, the PWM input differential signal is compared with a triangular wave clock signal, and the PWM signal is generated based on the comparison result. The analog sampling clock signal and the PWM synchronization clock signal have the same frequency, the triangular wave clock signal and the PWM synchronization clock signal have the same frequency, and the inflection point of the triangular wave clock signal is aligned with the rising or falling edge of the pulses included in the PWM synchronization clock signal.

[0083] The analog sampling clock signal and the PWM synchronization clock signal can be from the same source clock, have the same frequency, and their phases can be the same or opposite. As shown in Figure 4, the analog sampling clock signal and the PWM synchronization clock signal have the same frequency but opposite phases.

[0084] The triangular wave clock signal and the PWM synchronization clock signal can be from the same source clock. They have the same frequency, and the inflection points of the triangular wave clock signal are aligned with the rising or falling edge of the pulse in the PWM synchronization clock signal. As shown in Figure 4, for adjacent first and second inflection points in the triangular wave clock signal, if the first inflection point is aligned with the rising edge of the pulse in the PWM synchronization clock signal, then the second inflection point is aligned with the falling edge of the pulse in the PWM synchronization clock signal; conversely, if the first inflection point is aligned with the falling edge of the pulse in the PWM synchronization clock signal, then the second inflection point is aligned with the rising edge of the pulse in the PWM synchronization clock signal.

[0085] When performing noise shaping on analog differential signals, an analog loop filter (ALF) can be used to filter the analog differential signals, removing high-order harmonics and suppressing quantization noise generated during PWM modulation and noise within the ALF loop, thereby obtaining the PWM input differential signal. The analog loop filter includes a sample-and-hold circuit. The analog sampling clock signal can drive the sample-and-hold circuit to sample and hold the output of the analog loop filter, thus filtering out high-order harmonics at the ALF output and preventing aliasing during PWM modulation.

[0086] The PWM input differential signal can include a positive PWM input differential signal and a negative PWM input differential signal. The positive PWM input differential signal is compared with a triangular wave clock signal, and a positive PWM signal is generated based on the comparison result. Similarly, the negative PWM input differential signal is compared with the triangular wave clock signal, and a negative PWM signal is generated based on the comparison result. Both the positive and negative PWM signals have the same frequency as the triangular wave clock signal.

[0087] In this embodiment, noise shaping of the analog differential signal based on the analog sampling clock signal can filter out high-order PWM modulation harmonics in the analog differential signal. Then, the obtained PWM input differential signal is compared with the triangular wave clock signal to obtain a normal PWM signal, thus ensuring the signal quality of the generated PWM signal.

[0088] In one possible implementation, an intermediate common-mode voltage signal can be generated based on a common-mode voltage reference signal. This intermediate common-mode voltage signal is generated through feedback, making it approach the common-mode voltage reference signal. Specifically, the positive and negative voltage signals of the input common-mode point voltage signal from the previous moment are added together to obtain a first reference signal. Amplifying the first reference signal by a factor of 0.5 yields a second reference signal, which approximates the common-mode voltage reference signal. Amplifying the second reference signal based on the common-mode voltage reference signal yields a third reference signal. The intermediate common-mode voltage signal at the current moment can then be generated based on the third reference signal. Chopping this intermediate common-mode voltage signal yields the common-mode voltage signal at the current moment, making it approach the common-mode voltage reference signal. Here, the input common-mode point is the coupling point between the common-mode voltage signal and the analog differential signal.

[0089] The common-mode voltage reference signal is a constant-voltage DC signal, and its voltage value is equal to the common-mode voltage required at the input common-mode point. For example, the common-mode voltage reference signal is a 2.7V DC signal.

[0090] The positive and negative intermediate common-mode voltage signals, which are included in the intermediate common-mode voltage signal at the previous moment, are added together to obtain the first reference signal. If the positive and negative intermediate common-mode voltage signals at the previous moment are equal, the voltage value of the first reference signal is equal to twice the positive (negative) intermediate common-mode voltage signal at the previous moment.

[0091] The first reference signal is amplified by 0.5 times, that is, the voltage value of the first reference signal is reduced by half to obtain the second reference signal. If the positive and negative intermediate common-mode voltage signals at the previous moment are equal, then the voltage value of the second reference signal is equal to the positive (negative) intermediate common-mode voltage signal at the previous moment.

[0092] In this embodiment, the positive and negative intermediate common-mode voltage signals from the previous moment are added together to obtain a first reference signal. The first reference signal is amplified by 0.5 times to obtain a second reference signal, making the second reference signal approach the common-mode reference signal. The second reference signal is amplified based on the common-mode voltage reference signal to obtain a third reference signal. The third reference signal is amplified by an amplifier (the second stage of the input common-mode feedback buffer amplifier) ​​to obtain the current intermediate common-mode voltage signal, which includes the positive and negative intermediate common-mode voltage signals, making the intermediate common-mode voltage signal approach the common-mode voltage reference signal. This absorbs the common-mode feedback current generated during chip operation and ensures the stability of the input common-mode voltage.

[0093] In one possible implementation, the input digital signal can be an audio signal, and the output signal can be used to drive a speaker, which then plays the processed audio signal. In one example, the output signal includes a positive output signal and a negative output signal. The positive output signal, after being filtered (e.g., LC filtering, low-pass filtering), can be used as the positive input to the speaker, and the negative output signal, after being filtered (e.g., LC filtering, low-pass filtering), can be used as the negative input to the speaker.

[0094] In this embodiment, the digital audio signal is processed using the signal processing method described in the foregoing embodiments. By chopping the intermediate common-mode voltage signal, flicker noise can be modulated out of the audio frequency band, improving the signal-to-noise ratio of the processed audio signal. By controlling the phase of the chopping clock signal and the PWM synchronization clock signal, the suppression effect of noise and harmonics during noise shaping of the analog differential signal can be guaranteed. This ensures that the processed audio signal contains less noise while guaranteeing the total harmonic distortion plus noise (THDN) of the signal processing circuit implementing the signal processing method in this embodiment.

[0095] Signal processing circuit

[0096] Figure 5 shows a schematic diagram of a signal processing circuit according to an embodiment of this application. As shown in Figure 5, the signal processing circuit 50 includes a digital signal processor 51, a chopper 53, a modulation module 54, and a power output module 55. The digital signal processor 51 processes the input digital signal according to the PWM synchronization clock signal to obtain an analog differential signal. The chopper 53 chops the intermediate common-mode voltage signal according to the chopping clock signal to obtain a common-mode voltage signal, wherein the intermediate common-mode voltage signal is used to stabilize the common-mode voltage of the analog differential signal, and the timing of the pulse edges included in the chopping clock signal is not aligned with the timing of the pulse edges included in the PWM synchronization clock signal. The modulation module 54 can perform noise shaping on the analog differential signal and then perform PWM modulation to obtain a PWM signal. The power output module 55 can perform voltage domain conversion on the PWM signal to obtain an output signal.

[0097] The digital signal processor 51 can preprocess (noise shaping) the input digital signal transmitted from the host computer and convert it into an analog differential signal, and then input the analog differential signal into the modulation module 54.

[0098] In this embodiment, the digital signal processor 51 processes the input digital signal according to the PWM synchronization clock signal to obtain an analog differential signal, and the chopper 53 performs chopping processing on the intermediate common-mode signal according to the chopping clock signal to obtain a common-mode voltage signal. The common-mode voltage signal can stabilize the common-mode voltage of the analog differential signal, and the timing of the pulses included in the chopping clock signal and the pulses included in the PWM synchronization clock signal is not aligned, so that the arrival of the pulses included in the analog differential signal at the input common-mode point and the frequency switching will not occur simultaneously. That is, before the pulses included in the analog differential signal reach the input common-mode point, a certain amount of time is left for the intermediate common-mode voltage signal to stabilize, thereby ensuring the noise and harmonic suppression effect of the modulation module 54 when performing noise shaping on the analog differential signal. Then, after the noise-shaped analog differential signal is modulated by PWM to obtain the PWM signal, the PWM signal contains less noise and harmonics. Thus, after the power output module 55 performs voltage domain conversion on the PWM signal to obtain the output signal, the output signal contains less noise and harmonics, ensuring the performance of signal processing.

[0099] In one possible implementation, as shown in Figure 6, the signal processing circuit 50 further includes a signal generation module 56. The signal generation module 56 can perform frequency division processing on the PWM synchronous clock signal to obtain a frequency-divided signal, and resample the frequency-divided signal according to the resampled clock signal to obtain a chopper clock signal.

[0100] In one possible implementation, as shown in Figure 6, the signal generation module 56 can resample the frequency division signal at least once according to the resampled clock signal to obtain the chopper clock signal, wherein the frequency of the resampled clock signal is greater than or equal to 4 times the frequency of the -PWM synchronization clock signal.

[0101] In one possible implementation, as shown in Figure 6, the signal generation module 56 can resample the frequency division signal based on the delayed resampled clock signal to obtain the chopper clock signal.

[0102] In one possible implementation, as shown in FIG6, the signal processing circuit 50 may include an input common-mode feedback buffer amplifier 52, which can generate an intermediate common-mode voltage signal based on the common-mode voltage reference signal.

[0103] In one possible implementation, as shown in the signal processing circuit 50 of FIG7, the modulation module 54 includes an analog loop filter 541, a sample-and-hold circuit 542, and a PWM comparator 543.

[0104] The analog loop filter 541 can perform noise shaping on the analog differential signal to obtain the PWM input differential signal. The sample-and-hold circuit 542 can hold the output of the analog loop filter 541 according to the analog sampling clock signal, which has the same frequency as the PWM synchronization clock signal. The PWM comparator 543 can compare the PWM input differential signal with the triangular wave clock signal and generate a PWM signal according to the comparison result. The triangular wave clock signal has the same frequency as the PWM synchronization clock signal, and the rising edge of the triangular wave clock signal is time-aligned with the rising edge of the pulses included in the PWM synchronization clock signal. The inflection point of the triangular wave clock signal is time-aligned with the rising or falling edge of the pulses included in the PWM synchronization clock signal.

[0105] After receiving the input digital signal, the digital signal processor 51 can preprocess the input digital signal (noise shaping) according to the PWM synchronization clock signal, and convert the preprocessed input digital signal into an analog differential signal, which is then input to the analog loop filter 541. In some embodiments, the output of the digital signal processor 51 can be converted into a current input to the input common-mode point through the resistor between the digital signal processor 51 and the input common-mode point. In other embodiments, the resistor between the digital signal processor 51 and the input common-mode point can be replaced with a current-mode digital-to-analog converter (IDAC), which converts the output of the digital signal processor 51 into a current input to the input common-mode point.

[0106] The integrator in analog loop filter 541 can provide high in-band audio gain to suppress harmonics and noise, improving total harmonic distortion plus noise. Sample-and-hold circuit 542 can suppress higher harmonics. In one example, sample-and-hold circuit 542 can be located within analog loop filter 541, i.e., analog loop filter 541 includes sample-and-hold circuit 542.

[0107] The PWM synchronization clock signal is used to synchronize the output signal of the digital signal processor 51, and the chopper clock signal is used to drive the chopper 53. The analog sampling clock signal is used to sample and hold the output of the analog loop filter 541 to filter out high-order harmonics. The triangular wave clock signal is used for PWM modulation.

[0108] By incorporating a chopper 53 into the signal processing circuit 50, noise in the processed signal can be reduced. The chopper 53 can modulate flicker noise out of the audio frequency band, improving the signal-to-noise ratio. Due to manufacturing mismatches, there will be a DC offset at the input common-mode point; the chopper 53 can reduce this DC offset.

[0109] The chip operates within a voltage range from low to high. When operating at high voltage, a significant common-mode feedback current exists. The input common-mode feedback buffer amplifier 52 absorbs this common-mode feedback current to ensure the stability of the common-mode voltage at the input point of the analog loop filter 541. A stable common-mode voltage ensures that the output of the digital signal processor 51 is input to the analog loop filter 541 with minimal loss, thereby improving signal processing performance.

[0110] It should be noted that the phase difference between the PWM synchronization clock signal and the analog sampling clock signal is adjustable. The phase of the analog sampling clock signal can be configured to lag behind or lead the phase of the PWM synchronization clock signal, which can be adjusted according to the actual situation and signal magnitude. The phase difference between the PWM synchronization clock signal and the analog sampling clock signal can be controlled digitally.

[0111] It should be noted that the digital signal processor 51, input common-mode feedback buffer amplifier 52, chopper 53, analog loop filter 541, sample-and-hold circuit 542, PWM comparator 543, and power output module 55 in Figure 7 can be included within the chip, while the low-pass filter 60 and speaker 70 are located outside the chip. After the power output module 55 inputs the output signal to the low-pass filter 60, the low-pass filter 60 can filter the output signal (such as LC filtering or low-pass filtering), and then transmit the filtered output signal to the speaker 70 to drive the speaker 70 to work.

[0112] The timing of the pulse edges in the chopper clock signal is misaligned with the timing of the pulse edges in the PWM synchronization clock signal, i.e., the chopper clock signal and the PWM synchronization clock signal are staggered. The digital signal processor 51 outputs a pulse at the leading edge of the PWM synchronization clock signal to the input common-mode point of the analog loop filter 541. The input common-mode feedback buffer amplifier 52 also receives the input common-mode point. When the chopper switches at the clock edge, the input common-mode feedback buffer amplifier 52 needs time to stabilize. If the chopper switching occurs simultaneously with the pulse output by the digital signal processor 51, and the input common-mode feedback buffer amplifier 52 is not yet stable, the impedance at the input common-mode point of the analog loop filter 541 will decrease, thereby reducing the suppression of noise and harmonics by the analog loop filter 541 and ultimately reducing signal processing performance. If the chopper clock signal and the PWM synchronization clock signal are staggered by a certain phase, so that the edges of the chopper clock signal and the PWM synchronization clock signal do not collide, a certain amount of time is allowed for the output of the input common-mode feedback buffer amplifier 52 to stabilize before the pulse output by the digital signal processor 51 reaches the input common-mode point of the analog loop filter 541, thereby ensuring the suppression effect of the analog loop filter 541 on noise and harmonics.

[0113] In one possible implementation, as shown in Figure 8, the input common-mode feedback buffer amplifier 52 can generate an intermediate common-mode voltage signal based on a common-mode voltage reference signal. The input common-mode feedback buffer amplifier 52 includes an adder 521, a first amplifier 522, a second amplifier 523, and a third amplifier 524.

[0114] Adder 521 adds the positive intermediate common-mode voltage signal VINN1 and the negative intermediate common-mode voltage signal VINN2 from the input common-mode point voltage signal of the previous moment to obtain a first reference signal. The input common-mode point is the connection point between chopper 53 and analog loop filter 541. First amplifier 522 amplifies the first reference signal by 0.5 times to obtain a second reference signal VCM, the magnitude of which approaches the common-mode voltage reference signal VINP. Second amplifier 523 amplifies the second reference signal VCM based on the common-mode voltage reference signal VINP to obtain a third reference signal. Third amplifier 524 amplifies the third reference signal to generate the intermediate common-mode voltage signal at the current moment. Chopper 53 chops the intermediate common-mode voltage signal to obtain a common-mode voltage signal, making the positive common-mode voltage signal VO1 and the negative common-mode voltage signal VO2 approach the common-mode voltage reference signal VINP.

[0115] The third amplifier 524 can be the second stage of the input common-mode feedback buffer amplifier. The third amplifier 524 amplifies the third reference signal to obtain an intermediate common-mode voltage signal, which includes a positive intermediate common-mode voltage signal and a negative intermediate common-mode voltage signal. The positive and negative intermediate common-mode voltage signals are identical. The chopper 53 chops the positive and negative intermediate common-mode voltage signals to obtain an intermediate common-mode voltage signal. The intermediate common-mode voltage signal, including the positive common-mode voltage signal VO1 and the negative common-mode voltage signal VO2, approximates the common-mode voltage reference signal VINP.

[0116] It should be noted that the signal processing circuit in this application embodiment is used to execute the signal processing method in the foregoing embodiment, and is based on the same concept as the foregoing signal processing method embodiment. For details and beneficial effects, please refer to the description in the foregoing signal processing method embodiment, which will not be repeated here.

[0117] signal processing chip

[0118] One embodiment of this application provides a signal processing chip for executing the signal processing method in any of the above embodiments. The signal processing chip may include the signal processing circuit 50 in any of the above embodiments, that is, the signal processing circuit 50 in the above embodiments is packaged in the signal processing chip. The signal processing chip can be arranged in an electronic device with signal processing requirements such as audio signals and power supply signals for signal processing.

[0119] It should be noted that the signal processing chip in this application embodiment is used to execute the signal processing method in the foregoing embodiment, and is based on the same concept as the foregoing signal processing method embodiment. For details and beneficial effects, please refer to the description in the foregoing signal processing method embodiment, which will not be repeated here.

[0120] electronic devices

[0121] Figure 9 shows a schematic diagram of an electronic device according to an embodiment of the present application. As shown in Figure 9, the electronic device 90 includes a signal source 91, a signal processing device 92, and a signal receiving terminal 93. The signal processing device 92 may include the signal processing circuit 50 or the signal processing chip in any of the foregoing embodiments.

[0122] The signal processing device 92 is connected between the signal source 91 and the signal receiving terminal 93. The signal source 91 is used to transmit input digital signals to the signal processing device 92, and the signal receiving terminal 93 is used to receive the output signals output by the signal processing device 92.

[0123] The input digital signal transmitted from the signal source 91 to the signal processing device 92 can be a digital audio signal. After receiving the output signal, the signal receiving end 93 can perform LC filtering on the output signal and then transmit it to the speaker to drive the speaker to produce sound.

[0124] It should be noted that the electronic device in this application embodiment is based on the signal processing circuit 50 or signal processing chip in the foregoing embodiment, and is a specific application of the signal processing circuit 50 and signal processing chip in the foregoing embodiment. For details and beneficial effects, please refer to the description in the foregoing signal processing unit embodiment and signal processing chip embodiment, which will not be repeated here.

[0125] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0126] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0127] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0128] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A signal processing method, characterized by, include: The input digital signal is processed according to the PWM synchronous clock signal to obtain an analog differential signal; The intermediate common-mode voltage signal is chopping the intermediate common-mode voltage signal according to the chopping clock signal to obtain the common-mode voltage signal. The intermediate common-mode voltage signal is used to stabilize the common-mode voltage of the analog differential signal. The timing of the pulse edges included in the chopping clock signal is not aligned with the timing of the pulse edges included in the PWM synchronization clock signal. The analog differential signal is noise shaped and then PWM modulated to obtain a PWM signal; The PWM signal is converted to voltage domain to obtain the output signal.

2. The method according to claim 1, characterized in that, The leading edge of the pulse included in the chopper clock signal is located between the leading edge and trailing edge of the first pulse included in the PWM synchronous clock signal in terms of timing, and the phase delay range of the leading edge of the pulse included in the chopper clock signal relative to the leading edge of the first pulse is [45°, 135°].

3. The method according to claim 2, characterized in that, The chopper clock signal includes a pulse whose leading edge is delayed by 90° relative to the leading edge of the first pulse.

4. The method according to claim 1, characterized in that, The leading edge of the pulse included in the chopper clock signal is located between the trailing edge of the second pulse and the leading edge of the third pulse included in the PWM synchronization clock signal in terms of timing, and the phase delay range of the leading edge of the pulse included in the chopper clock signal relative to the trailing edge of the second pulse is [45°, 135°], wherein the second pulse and the third pulse are pulses that are time-adjacent in the PWM synchronization clock signal.

5. The method according to claim 4, characterized in that, The chopper clock signal includes a pulse whose leading edge is delayed by 90° relative to the trailing edge of the second pulse.

6. The method of claim 1, wherein, The method further includes: The PWM synchronous clock signal is divided to obtain a frequency-divided signal; The frequency division signal is resampled according to the resampling clock signal to obtain the chopper clock signal.

7. The method of claim 6, wherein, The step of resampling the frequency-divided signal based on the resampled clock signal to obtain the chopper clock signal includes: The frequency division signal is resampled at least once according to the resampled clock signal to obtain the chopper clock signal, wherein the frequency of the resampled clock signal is greater than or equal to 4 times the frequency of the PWM synchronization clock signal.

8. The method of claim 6, wherein, The step of resampling the frequency-divided signal based on the resampled clock signal to obtain the chopper clock signal includes: The frequency-divided signal is resampled based on the delayed resampled clock signal to obtain the chopper clock signal.

9. The method of claim 1, wherein, The step of performing noise shaping on the analog differential signal followed by PWM modulation to obtain a PWM signal includes: The analog differential signal is noise shaped according to the analog sampling clock signal to obtain the PWM input differential signal, wherein the analog sampling clock signal has the same frequency as the PWM synchronization clock signal; The PWM input differential signal is compared with the triangular wave clock signal, and the PWM signal is generated based on the comparison result. The triangular wave clock signal has the same frequency as the PWM synchronization clock signal, and the turning point of the triangular wave clock signal is aligned with the rising or falling edge timing of the pulses included in the PWM synchronization clock signal.

10. The method of claim 1, wherein, The method further includes: generating the intermediate common-mode voltage signal based on the common-mode voltage reference signal; The step of generating the intermediate common-mode voltage signal based on the common-mode voltage reference signal includes: The voltage signal at the input common-mode point of the previous moment, including the positive intermediate common-mode voltage signal and the negative intermediate common-mode voltage signal, is added together to obtain the first reference signal. The input common-mode point is the coupling point between the common-mode voltage signal and the analog differential signal. The first reference signal is amplified by 0.5 times to obtain a second reference signal, wherein the second reference signal is close to the common-mode voltage reference signal; The second reference signal is amplified based on the common-mode voltage reference signal to obtain the third reference signal; Based on the third reference signal, an intermediate common-mode voltage signal at the current moment is generated, such that the common-mode voltage signal obtained by chopping the intermediate common-mode voltage signal at the current moment approaches the common-mode voltage reference signal.

11. The method of any one of claims 1-10, wherein, The input digital signal is a digital audio signal, and the output signal is used to drive a speaker. The speaker is used to play the digital audio signal after signal processing.

12. A signal processing circuit, characterized by comprising: include: A digital signal processor is used to process input digital signals according to a PWM synchronization clock signal to obtain analog differential signals; A chopper is used to chop an intermediate common-mode voltage signal according to a chopper clock signal to obtain a common-mode voltage signal. The intermediate common-mode voltage signal is used to stabilize the common-mode voltage of the analog differential signal. The timing of the pulse edges included in the chopper clock signal is not aligned with the timing of the pulse edges included in the PWM synchronization clock signal. The modulation module is used to perform noise shaping on the analog differential signal and then perform PWM modulation to obtain a PWM signal; The power output module is used to perform voltage domain conversion on the PWM signal to obtain an output signal.

13. The circuit of claim 12, wherein, The circuit also includes: The signal generation module is used to perform frequency division processing on the PWM synchronous clock signal to obtain a frequency division signal, and to resample the frequency division signal according to the resampling clock signal to obtain the chopping clock signal.

14. The circuit according to claim 13, characterized in that, The signal generation module is used to resample the frequency division signal at least once according to the resampled clock signal to obtain the chopper clock signal, wherein the frequency of the resampled clock signal is greater than or equal to 4 times the frequency of the PWM synchronization clock signal.

15. The circuit according to claim 13, characterized in that, The signal generation module is used to resample the frequency division signal according to the delayed resampled clock signal to obtain the chopper clock signal.

16. The circuit of claim 12, wherein, The modulation module includes: An analog loop filter is used to perform noise shaping on the analog differential signal to obtain a PWM input differential signal; A sample-and-hold circuit is used to hold the output of the analog loop filter according to an analog sampling clock signal, wherein the analog sampling clock signal has the same frequency as the PWM synchronization clock signal; A PWM comparator is used to compare the PWM input differential signal with a triangular wave clock signal and generate the PWM signal based on the comparison result. The triangular wave clock signal has the same frequency as the PWM synchronization clock signal, and the inflection point of the triangular wave clock signal is aligned with the rising or falling edge timing of the pulses included in the PWM synchronization clock signal.

17. The circuit of any one of claims 12-16, wherein, The signal processing circuit includes an input common-mode feedback buffer amplifier, which comprises: The adder is used to add the positive intermediate common-mode voltage signal and the negative intermediate common-mode voltage signal, which are included in the voltage signal of the input common-mode point of the previous moment, to obtain the first reference signal. The input common-mode point is the connection point between the chopper and the analog loop filter. A first amplifier is used to amplify the first reference signal by 0.5 times to obtain a second reference signal, wherein the second reference signal is close to the common-mode voltage reference signal; The second amplifier is used to amplify the second reference signal according to the common-mode voltage reference signal to obtain the third reference signal; A third amplifier is used to amplify the third reference signal to generate an intermediate common-mode voltage signal at the current moment, so that the common-mode voltage signal obtained by chopping the intermediate common-mode voltage signal at the current moment approaches the common-mode voltage reference signal.

18. A signal processing chip, characterized by The signal processing chip is used to perform the method as described in any one of claims 1-11.

19. An electronic device, comprising: include: A signal source, a signal receiver, and a signal processing device, wherein the signal processing device includes a signal processing circuit as described in any one of claims 12-17 or a signal processing chip as described in claim 18; The signal processing device is connected between the signal source and the signal receiving end; The signal source is used to transmit input digital signals to the signal processing device; The signal receiving end is used to receive the output signal output by the signal processing device.

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