Load driver, audio amplifier, chip and electronic device

Abstract

Provided in the embodiments of the present application are a load driver, an audio amplifier, a chip and an electronic device. The load driver comprises an output stage and a control module, the control module being connected to the output stage. The control module is configured to control the output stage such that an output node of the output stage outputs a load driving signal. The rising edge of the load driving signal has a plurality of segments, wherein, among the plurality of segments of the rising edge, a rising slope of a preceding segment is greater than a rising slope of a subsequent segment. The foregoing solution enables the load driver provided in the embodiments of the present application to have higher turn-on speed and meet an EMI requirement.

Description

Load drivers, audio amplifiers, chips and electronic devices Technical Field

[0001] This application relates to the field of audio amplification, and more particularly to a load driver, audio amplifier, chip, and electronic device. Background Technology

[0002] Class D audio amplifiers are widely used in the audio field due to their ability to provide efficient audio drive. A Class D audio amplifier typically includes an audio modulation circuit and a load driver (e.g., an H-bridge driver) coupled to the modulation circuit. The audio modulation circuit performs pulse width modulation (PWM) on the received audio signal to obtain the modulated audio signal. The load driver controls the on / off state of multiple power output transistors in its output stage based on the modulated audio signal to apply a load drive signal to the load (e.g., a speaker). With the development of audio modulation technology, audio modulation circuits can output audio modulated signals with higher frequencies and shorter pulse widths. This requires the load driver to have a smaller output width (e.g., a pulse width of less than 10 ns). ～ The ability to generate pulses of 20 ns.

[0003] To enable the load driver to output pulses with narrow widths, related technologies reduce output stage delay and increase turn-on speed by increasing the slew rate of the voltage applied to the gate of the output power transistor. However, excessively fast turn-on speed can lead to power supply disturbances and electromagnetic interference (EMI) at the output of the load driver.

[0004] Therefore, there is an urgent need for a load driver that can have a fast start-up speed and meet EMI requirements. Summary of the Invention

[0005] In view of this, embodiments of this application provide a load driver, an audio amplifier, a chip, and an electronic device to at least partially solve the above-mentioned problems.

[0006] According to a first aspect of the present application, a load driver is provided, including an output stage and a control module; the control module is connected to the output stage; the control module is used to control the output stage so that the output node of the output stage outputs a load drive signal, the rising edge of the load drive signal having multiple segments, and the rising slope of the first segment of the multiple segments of the rising edge is greater than the rising slope of the second segment.

[0007] According to a second aspect of the present application, an audio amplifier is provided, comprising: an audio modulation circuit and a load driver according to a first aspect; wherein the audio modulation circuit is configured to generate an audio modulation signal based on an audio signal; and the load driver is configured to generate a load drive signal based on the audio modulation signal.

[0008] According to a third aspect of the embodiments of this application, a chip is provided, including a load driver provided according to the first aspect.

[0009] According to a fourth aspect of the embodiments of this application, an electronic device is provided, including a chip provided according to a third aspect.

[0010] The load driver provided in this embodiment has a control module connected to the output stage. The control module controls the output stage to output a load drive signal at its output node. The rising edge of the load drive signal has multiple segments, and the rising slope of the first segment is greater than that of the last segment. The larger rising slope of the first segment indicates a rapid rise in the load drive signal, meaning a faster turn-on speed and less delay for the output stage. Conversely, the smaller rising slope of the last segment indicates a slower change in the load drive signal, preventing large peak currents on the power supply that could cause power supply disturbances and EMI degradation. Therefore, the load driver provided in this embodiment can have a high turn-on speed while meeting EMI requirements. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0012] Figure 1 is a schematic diagram of a load driver provided in an embodiment of this application;

[0013] Figure 2 is a schematic diagram of another load driver provided in an embodiment of this application;

[0014] Figure 3 is a waveform diagram of the relevant signal timing provided in the embodiments of this application;

[0015] Figure 4 is a schematic diagram of another load driver provided in an embodiment of this application;

[0016] Figure 5 is a waveform diagram of the timing of the first control signal and related signals provided in the embodiment of this application;

[0017] Figure 6 is a schematic diagram of the first rate control module in the load driver shown in Figure 4;

[0018] Figure 7 is a schematic diagram of the first rate control module in the load driver shown in Figure 4;

[0019] Figure 8 is a schematic diagram of the first rate control module in the load driver shown in Figure 4;

[0020] Figure 9 is a schematic diagram of another load driver provided in an embodiment of this application;

[0021] Figure 10 is a schematic diagram of another load driver provided in an embodiment of this application;

[0022] Figure 11 is a schematic diagram of the structure of the audio amplifier provided in the embodiment of this application. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0024] The specific implementation of the embodiments of this application will be further described below with reference to the accompanying drawings.

[0025] First, referring to FIG1, a schematic diagram of a load driver according to an embodiment of the present application is shown. The load driver 10 provided in this embodiment can be applied to an audio power amplifier to provide a load drive signal to a connected load (e.g., a speaker).

[0026] As shown in Figure 1, the load driver 10 includes an output stage 11 and a control module 12. The control module 12 is connected to the output stage 11. The control module 12 controls the output stage 11 so that the output node of the output stage 11 outputs a load drive signal So. The rising edge of the load drive signal So has multiple segments, and the rising slope of the first segment of the rising edge is greater than the rising slope of the second segment.

[0027] For ease of understanding, Figure 1 shows an exemplary waveform of the load drive signal So. As shown in Figure 1, the rising edge of the load drive signal So includes segments A and B, with the rising slope of segment A being significantly greater than that of segment B. It should be understood that the load drive signal So shown in Figure 1 is merely an example; in practical applications, the load drive signal So may include more than two segments, and this embodiment does not limit this.

[0028] In this embodiment, a large rising slope in the first segment of the rising edge of the load drive signal indicates a rapid rise in the load drive signal, meaning a faster turn-on speed and less output stage delay. Simultaneously, a small rising slope in the later segments of the rising edge of the load drive signal indicates a slower change in the load drive signal, preventing large peak currents on the power supply that could cause power supply disturbances and EMI degradation. Therefore, the load driver provided in this embodiment can have a fast turn-on speed while meeting EMI requirements.

[0029] Based on the load drive signal 10 shown in Figure 1, Figure 2 shows a schematic diagram of another load drive signal provided in an embodiment of this application. The load driver 20 shown in Figure 2 exemplarily illustrates the internal structure of the output stage 11 and the control module 12.

[0030] As shown in Figure 2, the output stage 11 includes a first output power transistor MH coupled between the power supply terminal PVDD and the output node OUT, and a second output power transistor ML coupled between the output node OUT and the ground terminal. The output node OUT is used to connect to a load (not shown). The load driver 20 provides a load drive signal So to the load connected to the load driver 20 through the output node OUT.

[0031] The control module 12 includes a non-overlapping signal generation circuit 121, a first rate control module 122, and a second rate control module 123.

[0032] A non-overlapping signal generation circuit 121 receives an audio modulation signal Sp and generates a first signal SH and a second signal SL that do not overlap in phase based on the audio modulation signal Sp. The first signal SH and the second signal SL are phase-shifted to ensure that when one signal is high, the other signal is always low. For example, the non-overlapping signal generation circuit 121 can use digital logic gates (e.g., a series of flip-flops and logic gates) to ensure the time interval between the first signal SH and the second signal SL, while utilizing the rising and falling edges of the audio modulation signal Sp to generate the first signal SH and the second signal SL. The non-overlapping phase of the first signal SH and the second signal SL avoids shoot-through current due to the simultaneous conduction of the first output power transistor MH and the second output power transistor ML. The audio modulation signal Sp is generated by an audio modulation circuit (not shown) and is used to adjust the duty cycle of the first signal SH and the second signal SL. Specifically, the non-overlapping signal generation circuit 121 includes an input terminal, a first output terminal, and a second output terminal. The input terminal of the non-overlapping signal generation circuit 121 is connected to the audio modulation circuit to receive the audio modulation signal Sp. The first output terminal of the non-overlapping signal generation circuit 121 is connected to the first rate control module 122 to provide a first signal SH to the first rate control module 122. The second output terminal of the non-overlapping signal generation circuit 121 is connected to the second rate control module 123 to provide a second signal SL to the second rate control module 123. For ease of understanding, Figure 3 shows exemplary waveforms of the audio modulation signal Sp, the first signal SH, and the second signal SL.

[0033] The first rate control module 122 is used to control the on and off of the first output power transistor MH based on the first signal SH. The second rate control module 123 is used to control the on and off of the second output power transistor ML based on the second signal SL.

[0034] In this embodiment, to enable the load driver 20 to output pulses with a narrow width while meeting EMI requirements, the first rate control module 122 is further configured to: control the voltage conversion rate of the gate voltage of the first output power transistor MH based on the first signal SH and its delay signal, such that the rising edge of the load drive signal So output by the load driver 20 has multiple segments, and the rising slope of the first segment is greater than the rising slope of the later segment. For example, the load drive signal So is output as shown in Figures 1 and 3.

[0035] In this embodiment, the rising edge waveform of the load drive signal So is mainly achieved by the first rate control module 122 controlling the conduction of the first output power transistor MH. As shown in Figure 3, as the first signal SH switches from low level to high level, that is, in response to the rising edge of the first signal SH, the first output power transistor MH changes from off to on, and the load drive signal So gradually rises from the first voltage level to the second voltage level. During the period when the first signal SH is held at a high level, the first output power transistor MH remains on, and the load drive signal remains at the second voltage level.

[0036] The rising slope of the load drive signal So as it gradually increases from the first voltage level to the second voltage level is related to the slew rate of the gate voltage of the first output power transistor MH. Specifically, the rising slope of the load drive signal So is positively correlated with the slew rate of the gate voltage of the first output power transistor MH. The slew rate of the gate voltage is the magnitude by which the gate voltage increases per unit time. The larger the slew rate of the gate voltage, the greater the magnitude by which the gate voltage increases per unit time; conversely, the smaller the magnitude by which the gate voltage increases per unit time.

[0037] The first output power transistor MH will only turn on when its gate voltage reaches the threshold voltage Vth. When the gate voltage of the first output power transistor MH does not reach its threshold voltage Vth, the first output power transistor MH will not turn on and will not affect the output. Therefore, in the first stage when the first output power transistor MH switches from off to on, its gate voltage can be controlled to increase rapidly to Vth with a large voltage slew rate, thereby improving the turn-on speed of the first output power transistor MH and reducing the output stage delay. As shown in Figure 3, within the first duration T1 starting from the rising edge of the first signal SH, the amplitude of the gate voltage GDRV_HS of the first output power transistor MH increases rapidly, that is, the gate voltage GDRV_HS of the first output power transistor MH has a large voltage slew rate. Correspondingly, the waveform of the load drive signal So at the output node has a large rising slope.

[0038] Subsequently, in the second stage when the first output power transistor MH switches from off to on, the gate voltage of the first output power transistor MH can be controlled to increase at a smaller voltage slew rate, thereby slowing down the rise speed of the load drive signal at the output node. This avoids power supply disturbances and EMI degradation caused by large peak currents on the power supply. As shown in Figure 3, after a first duration T1 from the rising edge of the first signal, the amplitude of the gate voltage GDRV_HS of the first output power transistor MH increases slowly, that is, the gate voltage GDRV_HS of the first output power transistor MH has a relatively small voltage slew rate. Correspondingly, the waveform of the load drive signal So at the output node has a smaller rising slope.

[0039] In this embodiment, the voltage conversion rate of the gate voltage of the first output power transistor is controlled in segments based on the first signal and the delay signal of the first signal. This allows the first output power transistor MH to be turned on quickly during the first stage when it switches from off to on. After a first duration T1 from the rising edge of the first signal, the load drive signal at the output node rises slowly, avoiding the occurrence of a large peak current on the power supply, which would cause power supply disturbances and EMI degradation.

[0040] In order to further improve the turn-on speed of the load driver while ensuring that the load driver meets EMI requirements, in one embodiment of this application, the second rate control module 123 is used to control the gate voltage of the second output power transistor ML based on the second signal SL and the delay signal of the second signal SL, so that the rising edge of the gate voltage of the second output power transistor ML includes multiple segments, and the slew rate in the first segment is greater than the slew rate in the second segment.

[0041] Similar to the first output power transistor MH, the second output power transistor ML only turns on when its gate voltage reaches its threshold voltage Vth. Before the second output power transistor ML reaches its threshold voltage Vth, it remains off and has no effect on the output. Therefore, as shown in Figure 3, during the first stage of the second output power transistor ML switching from off to on (i.e., within the second duration T2 starting from the rising edge of the second signal SL), the amplitude of the gate voltage GDRV_LS of the second output power transistor ML increases rapidly. This means that the gate voltage GDRV_LS of the second output power transistor ML has a large voltage slew rate, thereby improving the turn-on speed of the second output power transistor ML and reducing the output stage delay. Subsequently, in the second stage when the second output power transistor ML switches from off to on (that is, after the second duration T2 starting from the rising edge of the second signal SL), the amplitude of the gate voltage GDRV_LS of the second output power transistor ML increases slowly. That is, the gate voltage GDRV_LS of the second output power transistor ML has a relatively small voltage slew rate, thereby avoiding the occurrence of large peak currents on the power supply, which would cause power supply disturbances and EMI degradation.

[0042] In this embodiment, the power supply terminal PVDD is used to receive high voltages, such as the power supply voltage provided by a power supply. The ground terminal GND is used to receive low voltages, for example, it can be electrically connected to ground to receive the ground voltage. Since the electron mobility of an NMOS transistor is greater than that of a PMOS transistor, the NMOS transistor can be smaller in size while achieving the same drain-source on-resistance. Therefore, to save chip area, as shown in Figure 2, the first output power transistor MH and the second output power transistor ML can be NMOS transistors. Specifically, the drain of the first output power transistor MH is coupled to the power supply terminal PVDD, and the source of the first output power transistor MH is coupled to the output node. The drain of the second output power transistor ML is coupled to the output node, and the source of the second output power transistor ML is coupled to the ground terminal. The gates of the first output power transistor MH and the second output power transistor ML are respectively connected to the first rate control module 122 and the second rate control module 123.

[0043] For NMOS transistors, in order to output a first voltage level equal to the power supply voltage at the output node, a boost voltage higher than the power supply voltage provided by the power supply terminal PVDD can be used to power the first rate control module 122 and the circuit corresponding to the first output power transistor MH. Therefore, an additional boost circuit can be provided to boost the power supply voltage provided by the power supply terminal PVDD and provide the boosted voltage to power the first rate control module 122 and the circuit corresponding to the first output power transistor MH.

[0044] However, to simplify the circuit structure, in another embodiment of this application, the first output power transistor MH is a PMOS transistor, and the second output power transistor ML is an NMOS transistor. Specifically, the source of the first output power transistor MH is coupled to the power supply terminal PVDD, and the drain of the first output power transistor MH is coupled to the output node. The drain of the second output power transistor ML is coupled to the output node, and the source of the second output power transistor ML is coupled to the ground terminal. The gates of the first output power transistor MH and the second output power transistor ML are respectively connected to the first rate control module 122 and the second rate control module 123. In this case, the voltage of the first rate control module 122 and other parts corresponding to the first output power transistor MH are directly powered by the power supply voltage provided by the power supply terminal PVDD, without the need for an additional boost circuit.

[0045] Based on the load drivers shown in Figures 1 and 2, Figure 4 illustrates a schematic diagram of another load driver provided in an embodiment of this application. An exemplary structure of the first rate control module 122 is shown in the load driver 30 shown in Figure 4. As shown in Figure 4, the first rate control module 122 includes a first charging circuit 1221 and a first logic circuit 1222.

[0046] The first charging circuit 1221 is connected to the gate of the first output power transistor MH and is used to provide a gate voltage to the gate of the first output power transistor MH.

[0047] The first logic circuit 1222 is used to generate a first control signal Sc based on the first signal SH and the delayed signal SH' of the first signal, and to control the charging rate of the first charging circuit 1221 based on the first control signal Sc, so as to control the voltage conversion rate of the gate voltage supplied to the first output power transistor MH.

[0048] Specifically, the first charging circuit 122 is used to provide a gate voltage to the gate of the first output power transistor MH. The higher the charging rate of the first charging circuit 1221, the higher the voltage slew rate of the gate voltage of the first output power transistor MH; conversely, the lower the charging rate, the lower the voltage slew rate. That is, the charging rate of the first charging circuit 1221 is positively correlated with the voltage slew rate of the gate voltage of the first output power transistor MH. Therefore, the first logic circuit 1222 generates a first control signal Sc based on the first signal SH and its delayed signal SH', and controls the charging rate of the first charging circuit 1221 based on the first control signal Sc, thereby controlling the gate voltage of the first output power transistor MH to have different voltage slew rates.

[0049] In one implementation of this application, the rising edge of the first control signal Sc is synchronized with the rising edge of the first signal SH, and the falling edge of the first control signal Sc is synchronized with the rising edge of the delayed signal SH' of the first signal; the first logic circuit 1222 is used to: control the first charging circuit to operate at a first charging rate based on the rising edge of the first control signal Sc; and control the first charging circuit to operate at a second charging rate based on the falling edge of the first control signal Sc, wherein the second charging rate is less than the first charging rate.

[0050] Since the second charging rate is lower than the first charging rate, in the first stage when the first output power transistor MH switches from off to on, the first charging circuit charges the first output power transistor MH at a higher charging rate. This causes the gate voltage of the first output power transistor MH to increase at a higher voltage slew rate, improving the turn-on speed of the first output power transistor MH and reducing the output stage delay. Subsequently, in the second stage when the first output power transistor MH switches from off to on, the first charging circuit charges the first output power transistor MH at a lower charging rate. This causes the gate voltage of the first output power transistor MH to increase at a relatively lower voltage slew rate, slowing down the rise time of the load drive signal at the output node. This avoids power supply disturbances and EMI degradation caused by large peak currents on the power supply.

[0051] In this embodiment, as shown in FIG4, the delayed signal SH' of the first signal can be obtained by processing the first signal SH using the first delay circuit 1223. Therefore, in one possible implementation, the first rate control module 122 may further include the first delay circuit 1223. The first delay circuit 1223 is coupled between the first output terminal of the non-overlapping signal generation circuit 121 and the input terminal of the first logic circuit 1222. The first delay circuit 1223 is used to delay the rising edge of the first signal SH for a first duration T1 to obtain the first delayed signal SH' as the delayed signal of the first signal; the first logic circuit 1222 is used to perform an XOR operation on the first signal SH and the first delayed signal SH' to obtain the first control signal Sc.

[0052] For example, in this embodiment, the first delay circuit 1223 can be implemented using an asymmetric inverter, allowing the first delay circuit 1223 to delay only the rising edge of the first signal, thereby obtaining the delayed signal SH' of the first signal as shown in FIG. 5. The rising edge of the first control signal Sc output by the first logic circuit 1222 based on the first signal SH and the delayed signal SH' of the first signal is synchronized with the rising edge of the first signal SH, and the falling edge of the first control signal Sc output by the first logic circuit 1222 is synchronized with the rising edge of the delayed signal SH' of the first signal. The first control signal Sc is a pulse signal with a width equal to the first duration T1. In this embodiment, other logic circuits can also be used to generate the first control signal based on the first delay circuit 1223, and this embodiment does not limit this.

[0053] Based on the load driver shown in Figure 4, this application embodiment provides another load driver. In this embodiment, the first charging circuit is an RC charging circuit. The first charging circuit includes a first adjustable resistor module and / or a first adjustable capacitor module. A first logic circuit is used to control the resistance value of the first adjustable resistor module and / or the capacitance value of the first adjustable capacitor module based on a first control signal, so that the first charging circuit has different charging rates. The resistance value of the first adjustable resistor module and the capacitance value of the first adjustable capacitor module are negatively correlated with the charging rate of the first charging circuit.

[0054] Specifically, the charging rate of an RC charging circuit is negatively correlated with its charging time constant. Specifically, a larger RC charging time constant results in a slower charging rate; conversely, a smaller RC charging time constant results in a faster charging rate. Furthermore, the charging time constant of an RC charging circuit is positively correlated with its resistance and capacitance values. Specifically, a larger resistance and / or capacitance value results in a larger charging time constant; conversely, a smaller charging time constant results in a smaller charging time constant. Based on this, in this embodiment, the first charging circuit is configured as an RC charging circuit, and includes a first adjustable resistor module and / or a first adjustable capacitor module. The resistance value of the first adjustable resistor module and / or the capacitance value of the first adjustable capacitor module are then controlled based on a first control signal to give the first charging circuit different charging time constants, thereby allowing the first charging circuit to have different charging rates.

[0055] For example, in one implementation of this application, the rising edge of the first control signal Sc is synchronized with the rising edge of the first signal SH, and the falling edge of the first control signal Sc is synchronized with the rising edge of the delay signal SH' of the first signal; the first logic circuit 1022 is used to: control the first adjustable resistor module to have a first resistance value and / or the first adjustable capacitor module to have a first capacitance value based on the rising edge of the first control signal Sc; control the first adjustable resistor module to have a second resistance value and / or the first adjustable capacitor module to have a second capacitance value based on the falling edge of the first control signal Sc, wherein the first resistance value is less than the second resistance value, and the first capacitance value is less than the second capacitance value.

[0056] Because the first resistor value is smaller than the second resistor value, and the first capacitor value is smaller than the second capacitor value, the first charging circuit has a smaller charging time constant in response to the rising edge of the first control signal Sc. This allows the first charging circuit to operate at a larger charging rate in the first stage when the first output power transistor MH switches from off to on, resulting in a larger voltage slew rate increase in the gate voltage of the first output power transistor, thereby improving the turn-on speed of the first output power transistor MH and reducing the output stage delay. Subsequently, in the second stage when the first output power transistor MH switches from off to on, the first charging circuit has a larger charging time constant in response to the falling edge of the first control signal Sc. The first charging circuit operates at a smaller charging rate, resulting in a smaller voltage slew rate increase in the gate voltage of the first output power transistor MH, thus slowing down the rise time of the load drive signal at the output node. This avoids large peak currents on the power supply, preventing power supply disturbances and EMI degradation.

[0057] For ease of understanding, two possible implementations of the first charging circuit as an RC charging circuit are shown below with reference to Figures 6 and 7. As shown in Figures 6 and 7, both first charging circuits 1221a and 1221b are RC charging circuits. The first input terminals of first charging circuits 1221a and 1221b are connected to the first output terminal of the non-overlapping signal generation circuit 121 to receive the first signal SH. The second input terminals of first charging circuits 1221a and 1221b are connected to the output terminal of the first logic circuit 1222 to receive the first control signal Sc. The output terminals of first charging circuits 1221a and 1221b are connected to the gate of the first output power transistor MH to provide a gate voltage to the first output power transistor MH. The difference between the first charging circuits 1221a and 1221b shown in Figures 6 and 7 is that the first charging circuit 1221a shown in Figure 6 includes a first adjustable resistor module 12211a, while the first charging circuit 1221b shown in Figure 7 includes a first adjustable capacitor module 12211b.

[0058] Specifically, as shown in Figure 6, the first charging circuit 1221a includes a first inverter INV1, a second inverter INV2, a first adjustable resistor module 12211a, a first capacitor C1, and a first switch S1. The first terminal of the first adjustable resistor module 12211a is connected to the first output terminal of the non-overlapping signal generation circuit 121 via the series-connected first inverter INV1 and second inverter INV2, for receiving the first signal SH. The second terminal of the first adjustable resistor module 12211a is connected to the gate of the first output power transistor MH and is connected to the ground terminal GND via the first capacitor C1. The first signal SH charges the first capacitor C1 via the first adjustable resistor module 12211a to provide a gate voltage to the gate of the first output power transistor MH.

[0059] In this embodiment, the first adjustable resistor module 12211a includes a first resistor R1, a second resistor R2, and a first switch S1. The first resistor R1 and the second resistor R2 are connected in series, and the first switch S1 is connected in parallel across the two ends of the second resistor R2. The first switch S1 is configured to: be turned on in response to the rising edge of the first control signal Sc output by the first logic circuit 1222; and be turned off in response to the falling edge of the first control signal Sc output by the first logic circuit 1222.

[0060] When the load driver is operating, the first logic circuit 1222 controls the first switch S1 to turn on based on the rising edge of the first control signal Sc, making the resistance value of the first charging circuit 1221a equal to the resistance value of the first resistor R1. At this time, the first charging circuit 1221a has a first charging time constant, and the charging rate corresponding to the first charging time constant is the first charging rate. Subsequently, the first logic circuit 1222 controls the first switch S1 to turn off based on the falling edge of the first control signal Sc, making the resistance value of the first charging circuit 1221a equal to the sum of the resistance values ​​of the first resistor R1 and the second resistor R2. At this time, the first charging circuit 1221a has a second charging time constant, and the charging rate corresponding to the second charging time constant is the second charging rate. Since the charging time constant of an RC circuit is proportional to the resistance value of the RC circuit, the first charging time constant is less than the second charging time constant, and correspondingly, the first charging rate is greater than the second charging rate. Therefore, in the first stage when the first output power transistor MH switches from off to on, the first charging circuit 1221a operates at a relatively large first charging rate, causing the gate voltage of the first output power transistor MH to increase at a large voltage slew rate, thereby improving the turn-on speed of the first output power transistor MH and reducing the output stage delay. Subsequently, in the second stage when the first output power transistor MH switches from off to on, it operates at a smaller charging rate, causing the gate voltage of the first output power transistor MH to increase at a relatively smaller voltage slew rate, thus slowing down the rise rate of the load drive signal at the output node and avoiding large peak currents on the power supply that could cause power supply disturbances and EMI degradation.

[0061] In the implementation shown in Figure 7, the first charging circuit 1221b includes a first inverter INV1, a second inverter INV2, a first resistor R1, and a first adjustable capacitor module 12211b. The first terminal of the first resistor R1 is connected to the first output terminal of the non-overlapping signal generation circuit 1032 via the first inverter INV1 and the second inverter INV2, for receiving the first signal SH. The second terminal of the first resistor R1 is connected to the gate of the first output power transistor MH and is grounded via the first adjustable capacitor module 12211b. The first signal SH charges the first adjustable capacitor module 12211b via the first resistor R1 to provide a gate voltage to the gate of the first output power transistor MH.

[0062] In this embodiment, the first adjustable capacitor module 12211b includes a first capacitor C1, a second capacitor C2, and a second switch S2. A first terminal of the second capacitor C2 is connected to a first terminal of the first capacitor C1, and a second terminal of the second capacitor C2 is connected to a second terminal of the first capacitor C1 via the second switch S2. The second switch S2 is configured to: be disconnected in response to the rising edge of the first control signal Sc output by the first logic circuit 1222; and be connected in response to the falling edge of the first control signal Sc output by the first logic circuit 1222.

[0063] When the load driver is operating, the first logic circuit 1222 controls the second switch S2 to open based on the rising edge of the first control signal Sc, making the capacitance value of the first charging circuit 1221b equal to the capacitance value of the first capacitor C1. At this time, the first charging circuit 1221b has a first charging time constant, and the charging rate corresponding to the first charging time constant is the first charging rate. Subsequently, the first logic circuit 1222 controls the second switch S2 to open based on the falling edge of the first control signal Sc, making the capacitance value of the first charging circuit 1221b equal to the parallel capacitance value of the first capacitor C1 and the second capacitor C2. At this time, the first charging circuit 1221b has a second charging time constant, and the charging rate corresponding to the second charging time constant is the second charging rate. Since the charging time constant of the RC circuit is proportional to the capacitance value of the RC circuit, the first charging time constant is less than the second charging time constant. Correspondingly, the first charging rate is greater than the second charging rate, thereby achieving a larger voltage slew rate increase in the gate voltage of the first output power transistor MH during the first stage when the first output power transistor MH switches from off to on in the first stage. Subsequently, in the second stage when the first output power transistor MH switches from off to on, the gate voltage of the first output power transistor MH is increased at a relatively small voltage slew rate.

[0064] It should be understood that Figures 6 and 7 are merely examples. In other implementations, the first charging circuit may simultaneously include a first adjustable resistor module and a first adjustable capacitor module. Furthermore, the circuit structures of the first adjustable circuit module and the first adjustable capacitor module can be configured according to actual needs, as long as the resistance and / or capacitance values ​​of the first charging circuit can be varied. This embodiment does not impose any limitations on this.

[0065] To accurately control the current flowing into the gate of the first output power transistor, Figure 8 shows a schematic diagram of another first rate control module provided in an embodiment of this application. In the first rate control module 122c shown in Figure 8, the first charging circuit 1221c is a constant current charging circuit, and the first charging circuit 1221c includes a first adjustable current source module 12211c. A first logic circuit 1222 is used to control the current provided by the first adjustable current source module 12211c based on a first control signal Sc, so that the first charging circuit 1221c has different charging rates.

[0066] As shown in Figure 8, the first input terminal of the first charging circuit 1221c is connected to the first output terminal of the non-overlapping signal generation circuit 121, the second input terminal of the first charging circuit 1221c is connected to the output terminal of the first logic circuit 1222, and the output terminal of the first charging circuit 1221c is connected to the gate of the first output power transistor MH.

[0067] Specifically, as shown in Figure 8, in addition to the first adjustable current source module 12211c, the first charging circuit 1221c also includes a resistor R1, a capacitor C1, and a first switch S1. The first terminal of the first adjustable current source module 12211c is connected to the voltage input terminal A, and the second terminal of the first adjustable current source module 12211c is connected to the gate of the first output power transistor MH via the first switch S1. The resistor R1 and capacitor C1 are connected in parallel between the gate of the first output power transistor MH and ground. The first switch S1 is configured to: be turned on in response to the rising edge of the first signal SH output from the first output terminal of the non-overlapping signal generation circuit 121; and be turned off in response to the falling edge of the first signal SH output from the first output terminal of the non-overlapping signal generation circuit 121.

[0068] In this embodiment, when the first output power transistor MH is a PMOS transistor, the voltage input terminal A is the power supply terminal PVCC. When the first output power transistor MH is an NMOS transistor, the voltage input terminal A is the output terminal of a boost circuit used to boost the power supply voltage provided by the power supply terminal PVCC.

[0069] In this embodiment, the first adjustable current source module 12211c can provide different currents. As shown in FIG8, the first adjustable current source module 12211c includes a first current source I1, a second current source I2, and a second switch S2. The first terminal of the second current source I2 is connected to the first terminal of the first current source I1, and the second terminal of the second current source I2 is connected to the second terminal of the first current source I1 via the second switch S2. The second switch S2 is configured to: be turned on in response to the rising edge of the first control signal Sc provided by the first logic circuit 1222; and be turned off in response to the falling edge of the first control signal Sc provided by the first logic circuit 1222.

[0070] When the load driver is operating, the first switch S1 is turned on in response to the rising edge of the first signal SH. The first adjustable current source module 12211c is connected to the gate of the first output power transistor MH and is used to provide the gate voltage to the first output power transistor MH by charging the capacitor C1. Since the rising edges of the first control signal Sc and the first signal SH are synchronized, when the first switch S1 is turned on in response to the rising edge of the first signal SH, the second switch S2 is turned on in response to the rising edge of the first control signal Sc, causing the first adjustable current source module 12211c to output a first current. The first current is equal to the sum of the currents provided by the first current source I1 and the second current source I2. At this time, the first charging circuit 1221c charges the capacitor C1 with the first current, and correspondingly, the first charging circuit 1221c operates at a first charging rate. Thereafter, the second switch S2 is turned off in response to the falling edge of the first control signal Sc, causing the first adjustable current source module 12211c to output a second current. The second current is equal to the current provided by the first current source I1. At this time, the first charging circuit 1221 charges the capacitor C1 with the second current, and correspondingly, the first charging circuit operates at the second charging rate. When the falling edge of the first signal SH arrives, in response to the falling edge of the first signal SH, the first switch S1 is opened, and the gate of the first output power transistor MH discharges through the resistor R1 and the capacitor C1, so as to turn off the first output power transistor MH.

[0071] Since the first current is equal to the sum of the currents provided by the first current source I1 and the second current source I2, and the second current is equal to the current provided by the first current source I1, the first current is greater than the second current. Correspondingly, the first charging rate is greater than the second charging rate. Therefore, in the first stage when the first output power transistor MH switches from off to on, the first charging circuit 12211c operates at a higher charging rate, causing the gate voltage of the first output power transistor MH to increase at a higher voltage slew rate, thereby increasing the turn-on speed of the first output power transistor MH and reducing the output stage delay. Subsequently, in the second stage when the first output power transistor MH switches from off to on, the first charging circuit 12211c operates at a lower charging rate, causing the gate voltage of the first output power transistor MH to increase at a relatively lower voltage slew rate, thus slowing down the rise time of the load drive signal at the output node and avoiding power supply disturbances and EMI degradation caused by large peak currents on the power supply.

[0072] It should be understood that Figure 8 only illustrates how the switching rate of the gate voltage of the first output power transistor MH is controlled by controlling the charging current of the constant current source charging circuit. In other embodiments, for the constant current source charging circuit, the switching rate of the gate voltage of the first output power transistor MH can also be controlled by adjusting the size of the capacitor in the constant current charging circuit, or by adjusting the charging current of the constant current source charging circuit and the size of the capacitor. This embodiment does not limit the comparison.

[0073] Based on the embodiment shown in FIG4, FIG9 shows a schematic diagram of the structure of a load driver provided in an embodiment of this application. The difference between the load driver provided in this embodiment and the load driver shown in FIG4 is that the load driver shown in FIG9 illustrates the specific structure of the second rate control module 123.

[0074] As shown in Figure 9, the second rate control module 123 includes a second charging circuit 1041 and a second logic circuit 1042. The second charging circuit 1041 is connected to the gate of the second output power transistor ML and is used to provide a gate voltage to the gate of the second output power transistor ML. The second logic circuit 1042 is used to generate a second control signal Sc' based on a second signal SL and a delay signal SL' of the second signal, and to control the charging rate of the second charging circuit 1041 based on the second control signal Sc', thereby controlling the voltage conversion rate of the gate voltage of the second output power transistor ML. The charging rate of the second charging circuit 1041 is positively correlated with the voltage conversion rate of the gate voltage of the second output power transistor ML.

[0075] In one implementation of this application, the rising edge of the second control signal Sc' is synchronized with the rising edge of the second signal SL, and the falling edge of the second control signal Sc' is synchronized with the rising edge of the delayed signal SL' of the second signal. A second logic circuit is configured to: control the second charging circuit 1041 to operate at a third charging rate based on the rising edge of the second control signal Sc'; and control the second charging circuit 1041 to operate at a fourth charging rate, where the fourth charging rate is less than the third charging rate, based on the falling edge of the second control signal Sc'.

[0076] In one implementation of this application, the second charging circuit 1041 is an RC charging circuit, comprising: a second adjustable resistor module and / or a second adjustable capacitor module; and a second logic circuit 1042 for controlling the resistance value of the second adjustable resistor module and / or the capacitance value of the second adjustable capacitor module based on a second control signal, so that the second charging circuit has different charging rates, wherein the resistance value of the second adjustable resistor module and the capacitance value of the second adjustable capacitor module are negatively correlated with the charging rate of the second charging circuit.

[0077] In one implementation of this application, the rising edge of the second control signal Sc' is synchronized with the rising edge of the second signal SL, and the falling edge of the second control signal Sc' is synchronized with the rising edge of the delayed signal SL' of the second signal. The second logic circuit 1042 is configured to: control the second adjustable resistor module to have a third resistance value and / or the second adjustable capacitor module to have a third capacitance value based on the rising edge of the second control signal Sc'; and control the second adjustable resistor module to have a fourth resistance value and / or the second adjustable capacitor module to have a fourth capacitance value based on the falling edge of the second control signal Sc', wherein the third resistance value is less than the fourth resistance value, and the third capacitance value is less than the fourth capacitance value.

[0078] The third resistance value, third capacitance value, fourth resistance value, and fourth capacitance value in this embodiment may be the same as or different from the first resistance value, first capacitance value, second resistance value, and second capacitance value in the foregoing embodiments, and this embodiment does not limit this.

[0079] In one implementation of this application, the second charging circuit 1041 is a constant current charging circuit, and the second charging circuit 1041 includes a second adjustable current module. A second logic circuit 1042 is used to control the current output by the second adjustable current source module based on a second control signal Sc', so that the second charging circuit 1041 has different charging rates, wherein the current output by the second adjustable current source module is positively correlated with the charging rate of the second charging circuit 1041.

[0080] In one implementation of this application, the rising edge of the second control signal Sc' is synchronized with the rising edge of the second signal SL, and the falling edge of the second control signal Sc' is synchronized with the rising edge of the delayed signal SL' of the second signal. The second logic circuit 1042 is used to: control the second adjustable current source module to output a third current based on the rising edge of the second control signal Sc'; and control the second adjustable current source module to output a fourth current in response to the falling edge of the second control signal Sc', wherein the third current is greater than the fourth current.

[0081] The third current and the fourth current in this embodiment may be the same as or different from the first current and the second current in the foregoing embodiments, and this embodiment does not limit this.

[0082] In one implementation of this application, the second rate control module 123 further includes a second delay circuit 1043, coupled to the second output terminal of the non-overlapping signal generation circuit 121 and the input terminal of the second logic circuit 1042. The second delay circuit 1043 is used to delay the rising edge of the second signal SL for a second duration to obtain a second delayed signal SL' as a delayed signal of the second signal; the second logic circuit 1042 is used to perform an XOR operation on the second signal SL and the second delayed signal SL' to obtain a second control signal Sc'.

[0083] In this embodiment, the second control signal Sc' is a pulse signal with a width equal to the second duration. The second duration may be the same as or different from the first duration in the aforementioned embodiments, and this application does not limit it in this regard.

[0084] In this embodiment, the second charging circuit 1041, the second logic circuit 1042, and the second delay circuit 1043 in the second rate control module 123 are similar in circuit implementation, working principle, and effect to the first charging circuit 1221, the first logic circuit 1222, and the first delay circuit 1223 in the first rate control module 122 in the aforementioned embodiment. To avoid redundancy, they will not be described again here.

[0085] Based on the load driver provided in the foregoing embodiments, FIG10 illustrates another load driver according to an embodiment of this application. The load driver 50 shown in FIG10 includes a first load driver branch 51 and a second load driver branch 52. The circuit structure and working principle of the first load driver branch 52 and the second load driver branch 52 are similar to those of the load driver provided in the foregoing embodiments.

[0086] For example, the output stage 511 of the first load driver branch 51 includes a first output power transistor MH1 and a second output power transistor ML1. The control module 512 of the first load driver branch 51 includes a first non-overlapping signal generation circuit 5121, a first rate control module 5122, and a second rate control module 5123. The output stage 521 of the second load driver branch 52 includes a third output power transistor MH2 and a fourth output power transistor ML2. The control module 522 of the second load driver branch 52 includes a second non-overlapping signal generation circuit 5221, a third rate control module 5222, and a fourth rate control module 5223. The circuit structure, control method, and effect of each module in the first load driver branch 51 and the second load driver branch 52 can be referred to the circuit structure, control method, and effect of the corresponding module in the aforementioned load driver, and will not be repeated here.

[0087] In this embodiment, the load L is connected between the output node of the output stage 511 of the first load driver branch 51 (i.e., the connection node between the first output power transistor MH1 and the second output power transistor ML1) and the output node of the output stage 521 of the second load driver branch 52 (i.e., the connection node between the third output power transistor MH2 and the fourth output power transistor ML2), so that the output stages 511 of the first load driver branch 51 and the output stages of the second load driver branch 52 are connected through the load L to form an H-bridge circuit. When the load driver 50 is working, one of the first output power transistor MH1 and the second output power transistor ML1 in the first load driver branch 51 is turned on, and one of the third output power transistor MH2 and the fourth output power transistor ML2 in the second load driver branch 52 is turned on, so as to form a current path and provide a load drive signal to the load.

[0088] The control methods for the first output power transistor MH1 and the second output power transistor ML1 in the first load driver branch 51, and the control methods for the third output power transistor MH2 and the fourth output power transistor ML2 in the second load driver branch 52 in this embodiment are the same as the control methods for the first output power transistor and the second output power transistor in the load driver provided in the previous embodiment, and the effects are the same, so they will not be described again here.

[0089] As shown in Figure 11, this embodiment of the application also provides an audio amplifier 1, including: an audio modulation circuit 20 and a load driver 11. The audio modulation circuit 20 is used to generate an audio modulation signal based on an audio signal. The load driver 11 is used to generate a load drive signal based on the audio modulation signal.

[0090] In this embodiment, the load driver 10 can be any of the load drivers provided in the foregoing embodiments. The audio amplifier 1 can be a Class D audio amplifier. The audio modulation circuit 20 can be any suitable audio modulation circuit, and this embodiment is not limited thereto.

[0091] This application also provides a chip including the load driver provided according to the foregoing embodiments.

[0092] This application also provides an electronic device, including the chip provided according to the foregoing embodiments. The electronic device may be, for example, a portable electronic device such as a mobile phone or tablet, or an in-vehicle device, etc., and this embodiment does not limit it in this way.

[0093] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0094] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A load driver, characterized by, Includes: output stage and control module; The control module is connected to the output stage; The control module is used to control the output stage so that the output node of the output stage outputs a load drive signal. The rising edge of the load drive signal has multiple segments, and the rising slope of the first segment of the multiple segments of the rising edge is greater than the rising slope of the second segment.

2. The load driver according to claim 1, characterized in that, The output stage includes a first output power transistor coupled between the power supply terminal and the output node; The control module is used to control the voltage conversion rate of the gate voltage of the first output power transistor, so that the load drive signal has the multiple segments, wherein the voltage conversion rate of the gate voltage of the first output power transistor is positively correlated with the rising slope of the rising edge of the load drive signal.

3. The load driver of claim 1, wherein, The control module includes a non-overlapping signal generation circuit and a first rate control module. The non-overlapping signal generation circuit is used to generate a first signal based on the audio modulation signal, and the first signal is used to control the on and off of the first output power transistor. The first rate control module is used to control the voltage conversion rate of the gate voltage of the first output power transistor based on the first signal and the delay signal of the first signal, so that the load drive signal has the multiple segments.

4. The load driver of claim 3, wherein, The first rate control module includes a first charging circuit and a first logic circuit; The first charging circuit is connected to the gate of the first output power transistor and is used to provide a gate voltage to the gate of the first output power transistor. The first logic circuit is configured to generate a first control signal based on the first signal and a delay signal of the first signal, and control the charging rate of the first charging circuit based on the first control signal, so as to control the voltage conversion rate of the gate voltage supplied to the first output power transistor, wherein the charging rate of the first charging circuit is positively correlated with the voltage conversion rate of the gate voltage of the first output power transistor.

5. The load driver of claim 4, wherein, The rising edge of the first control signal is synchronized with the rising edge of the first signal, and the falling edge of the first control signal is synchronized with the rising edge of the delayed signal of the first signal. The first logic circuit is used for: Based on the rising edge of the first control signal, the first charging circuit is controlled to operate at a first charging rate. Based on the falling edge of the first control signal, the first charging circuit is controlled to operate at a second charging rate, which is less than the first charging rate.

6. The load driver of claim 4, wherein, The first charging circuit is an RC charging circuit, which includes a first adjustable resistor module and / or a first adjustable capacitor module. The first logic circuit is used to control the resistance value of the first adjustable resistor module and / or the capacitance value of the first adjustable capacitor module based on the first control signal, so that the first charging circuit has different charging rates, wherein the resistance value of the first adjustable resistor module and the capacitance value of the first adjustable capacitor module are negatively correlated with the charging rate of the first charging circuit.

7. The load driver of claim 6, wherein, The rising edge of the first control signal is synchronized with the rising edge of the first signal, and the falling edge of the first control signal is synchronized with the rising edge of the delayed signal of the first signal. The first logic circuit is used for: Based on the rising edge of the first control signal, the first adjustable resistor module is controlled to have a first resistance value and / or the first adjustable capacitor module has a first capacitance value. Based on the falling edge of the first control signal, the first adjustable resistor module is controlled to have a second resistance value and / or the first adjustable capacitor module has a second capacitance value, wherein the first resistance value is less than the second resistance value and the first capacitance value is less than the second capacitance value.

8. The load driver of claim 4, wherein, The first charging circuit is a constant current charging circuit, and the first charging circuit includes a first adjustable current source module; The first logic circuit is used to control the current output by the first adjustable current source module based on the first control signal, so that the first charging circuit has different charging rates, wherein the current output by the first adjustable current source module is positively correlated with the charging rate of the first charging circuit.

9. The load driver of claim 8, wherein, The rising edge of the first control signal is synchronized with the rising edge of the first signal, and the falling edge of the first control signal is synchronized with the rising edge of the delayed signal of the first signal. The first logic circuit is used for: Based on the rising edge of the first control signal, the first adjustable current source module is controlled to output a first current. Based on the falling edge of the first control signal, the first adjustable current source module is controlled to output a second current, wherein the first current is greater than the second current.

10. The load driver according to any one of claims 3 to 9, characterized by, The first rate control module further includes a first delay circuit, which is coupled between the first output terminal of the non-overlapping signal generation circuit and the input terminal of the first logic circuit. The first delay circuit is used to delay the rising edge of the first signal for a first duration to obtain a first delayed signal as the delayed signal of the first signal; The first logic circuit is used to perform an XOR operation on the first signal and the first delayed signal to obtain the first control signal. The first control signal is a pulse signal with a width equal to the first duration.

11. The load driver according to claim 3, characterized in that, The output stage also includes a second output power transistor coupled between the output node and the ground terminal; The non-overlapping signal generation circuit is further configured to generate a second signal that does not overlap with the first signal based on the audio modulation signal, and the second signal is used to control the on and off of the second output power transistor. The control module further includes a second rate control module, which controls the gate voltage of the second output power transistor based on the second signal and the delay signal of the second signal, such that the rising edge of the gate voltage of the second output power transistor has multiple segments, and the voltage conversion rate in the first segment is greater than the voltage conversion rate in the second segment.

12. The load driver of claim 11, wherein, The second rate control module includes a second charging circuit and a second logic circuit. The second charging circuit is connected to the gate of the second output power transistor and is used to provide a gate voltage to the gate of the second output power transistor. The second logic circuit is used to generate a second control signal based on the second signal and a delay signal of the second signal, and to control the charging rate of the second charging circuit based on the second control signal, so as to control the voltage conversion rate of the gate voltage of the second output power transistor, wherein the charging rate of the second charging circuit is positively correlated with the voltage conversion rate of the gate voltage of the second output power transistor.

13. The load driver of claim 12, wherein, The rising edge of the second control signal is synchronized with the rising edge of the second signal, and the falling edge of the second control signal is synchronized with the rising edge of the delayed signal of the second signal. The second logic circuit is used for: Based on the rising edge of the second control signal, the second charging circuit is controlled to operate at the third charging rate. Based on the falling edge of the second control signal, the second charging circuit is controlled to operate at a fourth charging rate, which is less than the third charging rate.

14. The load driver of claim 13, wherein, The second charging circuit is an RC charging circuit, which includes a second adjustable resistor module and / or a second adjustable capacitor module. The second logic circuit is used to control the resistance value of the second adjustable resistor module and / or the capacitance value of the second adjustable capacitor module based on the second control signal, so that the second charging circuit has different charging rates, wherein the resistance value of the second adjustable resistor module and the capacitance value of the second adjustable capacitor module are negatively correlated with the charging rate of the second charging circuit.

15. The load driver of claim 14, wherein, The rising edge of the second control signal is synchronized with the rising edge of the second signal, and the falling edge of the second control signal is synchronized with the rising edge of the delayed signal of the second signal. The second logic circuit is used for: Based on the rising edge of the second control signal, the second adjustable resistor module is controlled to have a third resistance value and / or the second adjustable capacitor module has a third capacitance value. Based on the falling edge of the second control signal, the second adjustable resistor module is controlled to have a fourth resistance value and / or the second adjustable capacitor module has a fourth capacitance value, wherein the third resistance value is less than the fourth resistance value and the third capacitance value is less than the fourth capacitance value.

16. The load driver of claim 13, wherein, The second charging circuit is a constant current charging circuit, and the second charging circuit includes a second adjustable current source module; The second logic circuit is used to control the current output by the second adjustable current source module based on the second control signal, so that the second charging circuit has different charging rates, wherein the current output by the second adjustable current source module is positively correlated with the charging rate of the second charging circuit.

17. The load driver of claim 16, wherein, The rising edge of the second control signal is synchronized with the rising edge of the second signal, and the falling edge of the second control signal is synchronized with the rising edge of the delayed signal of the second signal. The second logic circuit is used for: Based on the rising edge of the second control signal, the second adjustable current source module is controlled to output a third current. Based on the falling edge of the second control signal, the second adjustable current source module is controlled to output a fourth current, wherein the third current is greater than the fourth current.

18. The load driver of any one of claims 12 to 17, wherein, The second rate control module also includes a second delay circuit, which is coupled between the second output terminal of the non-overlapping signal generation circuit and the input terminal of the second logic circuit. The second delay circuit is used to delay the rising edge of the second signal for a second duration to obtain a second delayed signal as the delayed signal of the second signal; The second logic circuit is used to perform an XOR operation on the second signal and the second delayed signal to obtain the second control signal. The second control signal is a pulse signal with a width equal to the second duration.

19. An audio amplifier characterized by include: Audio modulation circuit and load driver according to any one of claims 1-18; The audio modulation circuit is used to generate an audio modulation signal from the audio signal; The load driver is used to generate a load drive signal based on the audio modulation signal.

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