Display apparatus and electronic device

Abstract

Embodiments of the present application provide a display apparatus and an electronic device. In the display apparatus, a display panel comprises a first binding portion and a second binding portion; one end of a driving chip is bound to the first binding portion; a flexible circuit board is connected to the other end of the driving chip by means of the second binding portion; the first binding portion comprises at least one first invalid pin and at least one test line; the first invalid pin is connected to the test line. The present application improves the efficiency and accuracy of detection.

Description

Display devices and electronic devices Technical Field

[0001] This application relates to the field of display technology, and in particular to a display device and electronic device. Background Technology

[0002] With the development of display technology, display panels are used in various electronic products, such as mobile phones, tablets, laptops, and automotive displays. During the use of these display devices, signal transmission primarily employs protocols such as Mobile Industry Processor Interface (MIPI), Low-Voltage Differential Signaling (LVDS), Embedded Display Port (EDP), Integrated-Stream Protocol (ISP), and Point-to-Point High-speed Interface (PHI). In actual display processes, these signals are transmitted from the main unit to the display panel. Due to the long transmission distance and high bit rate, these signals are susceptible to noise, distortion, insertion / loop loss, and crosstalk, leading to signal distortion, errors, and even system malfunctions, resulting in abnormal display images. To prevent display abnormalities caused by signal anomalies, display devices are tested. However, current testing processes are time-consuming, have low success rates, and yield inaccurate results, meaning that signal anomalies can still cause display abnormalities.

[0003] Therefore, the existing display devices have a technical problem of inaccurate detection results due to their method of detecting transmitted signals. Invention Overview

[0004] This application provides a display device and an electronic device to solve the technical problem that the detection results of existing display devices are inaccurate in the way they detect transmitted signals.

[0005] In a first aspect, embodiments of this application provide a display device, including:

[0006] The display panel includes a display area and a non-display area, wherein the non-display area is provided with a first binding part and a second binding part;

[0007] A driver chip, one end of which is bonded and connected to the first bonding part;

[0008] A flexible circuit board, wherein the other end of the flexible circuit board is connected to the other end of the driver chip via the second bonding part;

[0009] The first bonding part includes at least one first invalid pin and at least one test line, the test line being disposed on the side close to the display area, and the first invalid pin being connected to the test line.

[0010] Secondly, embodiments of this application provide an electronic device that includes a display device as described in any of the above embodiments. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0013] Figure 1 is a schematic diagram of the structure of the comparison display device provided in an embodiment of this application.

[0014] Figure 2 is a schematic diagram of signal transmission of the comparison display device in Figure 1.

[0015] Figure 3 is a schematic diagram of the specific structure of the circuit board, chip and panel of the comparison display device in Figure 1.

[0016] Figure 4 is a plan view of the display device provided in an embodiment of this application.

[0017] Figure 5 is a schematic diagram of a first type of stacking of a display panel, a flexible circuit board, and a driver chip in a display device provided in an embodiment of this application.

[0018] Figure 6 is an exploded view of the display panel, flexible circuit board, and driver chip in the display device shown in Figure 5.

[0019] Figure 7 is a schematic diagram of a second type of stacking of a display panel, a flexible circuit board, and a driver chip in a display device provided in an embodiment of this application.

[0020] Figure 8 is an exploded view of the display panel, flexible circuit board, and driver chip in the display device shown in Figure 7.

[0021] Figure 9 is a schematic diagram of the driver chip provided in an embodiment of this application.

[0022] Figure 10 is a schematic diagram of a third type of stacking of a display panel, a flexible circuit board, and a driver chip in a display device provided in an embodiment of this application.

[0023] Figure 11 is a first schematic diagram of a differential probe used to detect a display device according to an embodiment of this application.

[0024] Figure 12 is a second schematic diagram of a differential probe used to detect a display device according to an embodiment of this application.

[0025] Figure 13 is a schematic diagram of an electronic device provided in an embodiment of this application. Embodiments of the present invention

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0027] In the description of this application, it should be understood that the terms "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, and "at least one" can mean one, two, or more, unless otherwise explicitly specified. In the description of this application, "perpendicular" means completely perpendicular to 90° or almost completely perpendicular, for example, the range of included angles between 80° and 100° is considered perpendicular. Similarly, "parallel" means completely parallel or almost completely parallel, for example, the range of completely parallel angles between 10° is considered parallel.

[0028] In the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" refers to a direct connection between two things, and "electrical connection" refers to a connection that can be direct or indirect through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0029] To illustrate the principle behind the technical problem addressed in this application, an embodiment of this application provides a comparison display device. It should be understood that this comparison display device is not considered prior art. As shown in Figure 1, the comparison display device includes a main unit 11, a circuit board 12, a chip 13, and a panel 14. The main unit 11 can be a system motherboard, the circuit board 12 can be a flexible circuit board, the chip 13 can be a driver chip, and the panel 14 can be a display panel. The main unit 11 is connected to the panel 14 via the circuit board 12, and the chip 13 is bonded to the panel 14. When the comparison display device is working, as shown in Figure 2, taking the comparison display device using a mobile industry processor interface for data transmission as an example, the main unit 11 sends a high-speed signal to the circuit board 12, and the circuit board 12 transmits the high-speed signal to the chip 13. The chip 13 is bonded to the panel 14, thus enabling signal transmission to the panel 14 for display.

[0030] Specifically, as shown in Figure 3, the circuit board 12 is provided with circuit pins 121, and the chip 13 is provided with receiving pins 131 and driving pins. The driving pins include active driving pins 132a and inactive driving pins 132b. The circuit pins 121, receiving pins 131, and driving pins are all bound to the terminals on the panel, and the first trace 141 is connected to the terminals on the panel to realize the connection between the circuit pins 121 and the receiving pins 131. The second trace 142 is connected to the active driving pins 132a to realize signal transmission.

[0031] However, during high-speed signal transmission, noise, distortion, insertion / loop loss, and crosstalk can occur, leading to signal distortion, errors, and even system malfunctions, resulting in abnormal screen display. To address this issue, testing is performed during the manufacturing process of comparative display devices. Specifically, the circuit pins 121 on the circuit board 12 are scraped open, and gold wires are led out for signal measurement. However, this method is costly, has a low success rate, cannot be performed in the factory, and has a long cycle. Furthermore, since the signal being tested is from the circuit board end, and the signal still needs to pass through the traces and chips on the panel to reach the signal lines of the display panel, these processes are also affected by noise, distortion, insertion / loop loss, and crosstalk. Even if the test results at the circuit board end are normal, the signal received by the panel may still be abnormal, leading to display abnormalities. Therefore, existing display devices suffer from the technical problem of inaccurate detection results due to the current method of detecting transmitted signals.

[0032] This application provides a display device and an electronic device to address the aforementioned technical problems.

[0033] Figure 4 is a plan view of the display device provided in an embodiment of this application. Figure 5 is a first stacked view of the display panel, flexible circuit board, and driver chip in the display device provided in an embodiment of this application. Figure 6 is an exploded view of the display panel, flexible circuit board, and driver chip in the display device of Figure 5; Figure 6(a) is an exploded view of the flexible circuit board in the display device of Figure 5; Figure 6(b) is an exploded view of the display panel in the display device of Figure 5; Figure 6(c) is an exploded view of the driver chip in the display device of Figure 5. Figure 7 is a second stacked view of the display panel, flexible circuit board, and driver chip in the display device provided in an embodiment of this application. Figure 8 is an exploded view of the display panel, flexible circuit board, and driver chip in the display device of Figure 7; Figure 8(a) is an exploded view of the flexible circuit board in the display device of Figure 7; Figure 8(b) is an exploded view of the display panel in the display device of Figure 7; Figure 8(c) is an exploded view of the driver chip in the display device of Figure 7. Figure 9 is a schematic diagram of the driver chip provided in an embodiment of this application. Figure 10 is a schematic diagram of a third type of stacking of the display panel, flexible circuit board, and driver chip in the display device provided in an embodiment of this application. Figure 11 is a schematic diagram of a first type of detection of the display device using a differential probe provided in an embodiment of this application. Figure 12 is a schematic diagram of a second type of detection of the display device using a differential probe provided in an embodiment of this application. Figure 13 is a schematic diagram of an electronic device provided in an embodiment of this application.

[0034] As shown in Figures 4 to 9, this application provides a display device 2, which includes a display panel 21, a driver chip 22, and a flexible circuit board 23. The display panel 21 includes a display area 201 and a non-display area 202. The non-display area 202 is provided with a first binding part 21a and a second binding part 21b. One end of the driver chip 22 is bound to the first binding part 21a. The flexible circuit board 23 is connected to the other end of the driver chip 22 through the second binding part 21b. The first binding part 21a includes at least one first invalid pin 213b and at least one test line 211b. The test line 211b is disposed on the side close to the display area 201, and the first invalid pin 213b is connected to the test line 211b.

[0035] This application provides a display device. The display device includes a display panel comprising a first bonding portion and a second bonding portion. One end of a driver chip is bonded to the first bonding portion, and the other end of a flexible circuit board is connected to the driver chip via the second bonding portion. The first bonding portion includes at least one first invalid pin and at least one test line. The first invalid pin is connected to the test line, so that when detecting the signal transmitted by the display device, it can be detected through the test line. Since the test line is a trace inside the display panel, the accuracy of the detected signal is high, and the display device can be directly detected without testing the flexible circuit board. The detection cycle is short, improving the efficiency and accuracy of the detection.

[0036] In some embodiments, as shown in Figures 4 to 9, the first bonding portion 21a includes a first connecting line group 211 and a first bonding pin group 213; the second bonding portion 21b includes a second bonding pin group 214, a second connecting line group 212, and a third bonding pin group 215; the first connecting line group 211 is connected to the first bonding pin group 213; the second connecting line group 212 is connected to the second bonding pin group 214 and the third bonding pin group 215; the driver chip 22 includes an input pin group 221 and an output pin group 222; the output pin group 222 is bonded to the first bonding pin group 213; the input pin group 221 is bonded to the second bonding pin group 214; and the flexible circuit board 23 includes a fourth bonding pin group 231, which is bonded to the third bonding pin group 215.

[0037] The first bonding pin group 213 includes the first invalid pin 213b, and the first connecting line group 211 includes the test line 211b. By including the first invalid pin in the first bonding pin group and the test line in the first connecting line group, the signal transmitted by the display device can be detected through the test line. Since the test line is a trace within the display panel, the accuracy of the detected signal is high, and the display device can be directly tested without testing the flexible circuit board. This shortens the testing cycle and improves the efficiency and accuracy of the testing.

[0038] In some embodiments, as shown in Figures 4 to 9, the first bonding pin group 213 further includes a plurality of first valid pins 213a, the output pin group 222 includes a plurality of second valid pins 222a and at least one second invalid pin 222b, and the first connection line group 211 further includes a plurality of signal transmission lines 211a. The first valid pins 213a are bonded to the second valid pins 222a, the first invalid pins 213b are connected to the second invalid pins 222b, and the signal transmission lines 211a are connected to the first valid pins 213a. By including second valid pins and second invalid pins in the output pin group of the driver chip, bonding the first valid pins to the second valid pins, bonding the first invalid pins to the second invalid pins, connecting the test lines to the first invalid pins, and connecting the signal transmission lines to the first valid pins, the signal transmitted by the display device can be detected through the test lines. Since the test lines are traces within the display panel, the accuracy of the detected signal is high, and the display device can be directly tested without testing the flexible circuit board, resulting in a shorter testing cycle and improved testing efficiency and accuracy.

[0039] Specifically, as shown in Figure 4, the display device 2 also includes a printed circuit board 24, which is connected to the flexible circuit board 23.

[0040] Specifically, as shown in Figure 4, the display panel 21 includes a display area 201 and a non-display area 202. The non-display area includes a bonding area 202a. The display panel 21 and the driver chip 22 are bonded in the bonding area 202a, and the display panel 21 and the flexible circuit board 23 are bonded in the bonding area 202a.

[0041] Specifically, it is understood that in this embodiment, the non-display area is only the binding area 202a, and the non-display area is located on one side of the display area 201. However, this embodiment is not limited to this, and non-display areas may be provided around the display area 201. Specifically, the number of pins in the output pin group is greater than the number of pins in the input pin group. By making the number of pins in the output pin group greater than the number of pins in the input pin group, when transmitting signals to the display panel, each pin in the output pin group can be connected to each trace, thereby achieving individual output of signals for each trace.

[0042] Specifically, it can be understood that the pins in the input pin group and the pins in the output pin group are not necessarily connected in a one-to-one correspondence. After receiving a signal, the pins in the input pin group are processed by the driver chip and then sent to the pins in the output pin group. The signals of the pins in the input pin group may not be directly transmitted to the pins in the output pin group.

[0043] It is understandable that, since the pins in the input pin group are pins that receive signals transmitted from the flexible circuit board to the driver chip, these signals are unprocessed signals, such as some voltage signals, and the pins in the output pin group are pins that transmit signals to the display panel, each pin can be connected to a trace, resulting in a large number of pins in the output pin group. When setting the pins in the output pin group and the traces electrically connected to the pins in the output pin group, in order to prevent the traces from being too close together, some pins in the output pin group will not transmit signals (i.e., the second invalid pins), and the pins in the output pin group that transmit signals will be separated (i.e., the second valid pins), resulting in a larger spacing between the traces. In the embodiments of this application, by binding the second invalid pins to the first invalid pins and connecting the first invalid pins to the test lines, the display device can be tested through the test lines.

[0044] Specifically, the input pin group includes 500 to 600 pins spaced apart; the output pin group includes at least 2,000 pins.

[0045] Specifically, it is understood that in order to illustrate the design and connection relationship of each structure in the embodiments of this application, different names will be used to describe different parts of the same structure. In fact, the same name can be used for this structure. For example, the structures marked by the first connecting line group and the first binding pin group can be formed simultaneously in practice and connected together. The first connecting line group and the first binding pin group actually mark multiple parts of the same structure and can be marked with the same name. For example, this structure can be named the first structure, one part of the first structure is named the first connecting line group, and another part is named the first binding pin group. Similarly, other markings can also refer to this description.

[0046] It is understandable that different parts of the same structure may actually have differences. For example, the thickness or width of the first bonding pin group and the first connecting line group may be different, so that the first bonding pin group and the first connecting line group may have differences.

[0047] Specifically, in contrast, display devices often use invalid drive pins on the chip, and the display panel does not have traces connected to these invalid drive pins. This results in a larger spacing between the second traces, preventing short circuits. In this embodiment, test lines are set up, connected to the first invalid pin and then to the second invalid pin. This allows for testing of the display device's signals. Since the test lines are traces on the display panel side, the signals do not pass through other devices, resulting in more accurate test results. Furthermore, since testing can be performed directly on the display panel traces, the testing cycle can be shortened. The test lines do not need to extend into the display area; only a portion of the test lines are reserved in the bonding area for testing, minimizing space usage and maintaining a large spacing between signal transmission lines to prevent short circuits.

[0048] Specifically, the first invalid pin is only bonded to the second invalid pin. Both the first and second invalid pins serve only a testing function, transmitting display signals during display device testing and not transmitting any signals when the display device is not being tested, or even not transmitting any signals at all. Test lines can be placed only within the bonding area and not connected to signal lines within the display panel. The test lines serve only a testing function; when not testing, such as when the display panel is displaying, the test lines do not transmit display signals (including but not limited to data signals). Signal transmission lines can extend into the display area of ​​the display panel and can be connected to signal lines to transmit display signals. For example, signal transmission lines can be connected to data lines to transmit data signals.

[0049] In some embodiments, when the display device is configured for a test phase, a display signal is input to the second invalid pin; when the display device is configured for a non-test phase, no signal is input to the second invalid pin. By allowing the second invalid pin to input a display signal during the test phase, the display device can be tested during the test phase, preventing display defects caused by abnormal signal transmission from the display device. Furthermore, when the display device is in a non-test phase, the second invalid pin does not input a signal, ensuring that the second invalid pin does not affect the display.

[0050] Specifically, the testing phase refers to the stage where the display device is tested. During this phase, test signals can be input through the flexible circuit board and driver chip, and these test signals can be the same as the normal display signals. The non-testing phase refers to the stage where the display device is not tested; this can be the normal display phase or the off phase of the display device.

[0051] Specifically, the above embodiment is illustrated by taking the example that the second invalid pin does not input a signal when the display device is configured in a non-test phase. However, the embodiments of this application are not limited to this. When the display device is configured in a non-test phase, the second invalid pin can input a signal.

[0052] In some embodiments, the first bound pin group includes a plurality of first invalid pins, and the output pin group includes a plurality of second invalid pins. The number of first invalid pins is equal to the number of second invalid pins, and the first invalid pins and the second invalid pins are bound together in a one-to-one correspondence.

[0053] In some embodiments, as shown in Figures 5 to 8, the first connection line group 211 includes at least two test lines 211b, and the first bonding pin group 213 includes at least two first invalid pins 213b, with each test line 211b connected to one of the first invalid pins 213b. By including at least two test lines in the first connection line group and at least two first invalid pins in the first bonding pin group, with each test line connected to one of the invalid pins, the signal of the display device can be detected by connecting the probes of the differential probe to the two test lines respectively.

[0054] In some embodiments, as shown in Figures 7 and 8, the test line 211b includes a connecting line 217 and a bonding terminal 216. Each connecting line 217 is connected to a first invalid pin 213b, and each bonding terminal 216 is connected to a connecting line 217. The width L3 of the bonding terminal 216 is greater than the width L4 of the connecting line 217. By including a connecting line and a bonding terminal in the test line, with each connecting line connected to a first invalid pin and each bonding terminal connected to a connecting line, and the width of the bonding terminal being greater than the width of the connecting line, the probe can easily contact the bonding terminal when testing the display device, avoiding misalignment between the probe and the test line that could lead to display defects.

[0055] Specifically, due to the large number of output terminals, there are correspondingly more invalid first pins and more test leads. When testing directly through the test leads, the test lead width may be too small, making it difficult to accurately align the probe with the test lead, resulting in inaccurate test results. By making the width of the output terminal larger than the width of the connecting wire, the difficulty of aligning the probe with the bonding terminal can be reduced, thus improving test accuracy.

[0056] Specifically, the area of ​​the bonding terminal can be larger than the area of ​​the connecting wire, thereby reducing the difficulty of aligning the probe with the bonding terminal and improving the accuracy of the test.

[0057] Specifically, the number of connecting wires can be the same as the number of bonding terminals, and the number of bonding terminals can be less than the number of second invalid pins, thereby saving space and reducing the risk of short circuits in signal transmission lines.

[0058] Specifically, the distance between the left side of the leftmost bonding terminal and the right side of the rightmost bonding terminal is smaller than the distance between the left side of the leftmost second invalid pin and the right side of the rightmost second invalid pin. This avoids the bonding terminals occupying too much space, reduces the space occupied by the bonding terminals, increases the spacing of the signal transmission lines, and reduces the risk of short circuits in the signal transmission lines.

[0059] Specifically, the above embodiments are illustrated using the example of a test lead including a bonding terminal and a connecting wire. However, the embodiments of this application are not limited to this. The test lead may only include a bonding terminal, which is directly connected to the first invalid pin. In this case, the width of the bonding terminal is greater than the width of the first invalid pin.

[0060] Specifically, as shown in Figure 8, the positions of the various structures on the flexible circuit board, display panel, and driver chip can be seen from Figure 8(a), Figure 8(b), and Figure 8(c).

[0061] In some embodiments, when the display device is configured in a test state, the bonding terminal receives different signals at different times. By receiving different signals at different times while the display device is in a test state, the various signals transmitted by the display device can be detected, preventing display abnormalities caused by abnormal partial signals.

[0062] Specifically, it is understandable that since the driver chip can transmit different signals, such as different data signals or different types of signals, such as power signals and data signals, when detecting the signals transmitted by the display device, since the number of bonding terminals is relatively small, it is not possible to make different bonding terminals transmit different signals separately. Therefore, different signals can be input into the bonding terminals at different times, and different signals can be detected at different times by differential probes to determine whether each signal is abnormal, so as to prevent some signals from being normal and some signals from being abnormal, which would lead to poor display.

[0063] In some embodiments, as shown in Figures 5 and 6, the number of the first invalid pins 213b is equal to the number of the second invalid pins 222b, and the number of test lines 211b is equal to the number of the first invalid pins 213b. The first invalid pins 213b and the second invalid pins 222b are bound one-to-one, and the first invalid pins 213b are connected one-to-one with the test lines 211b. By making the number of the first invalid pins equal to the number of the second invalid pins, the number of test lines equal to the number of the first invalid pins, and binding the first invalid pins and the second invalid pins one-to-one, and connecting the first invalid pins to the test lines one-to-one, different test lines can transmit different signals. By connecting probes to different test lines, different signals can be detected, preventing abnormal signals from causing display defects.

[0064] Specifically, as shown in Figure 6, the positions of the various structures on the flexible circuit board, display panel, and driver chip can be seen from Figure 6(a), Figure 6(b), and Figure 6(c).

[0065] In some embodiments, as shown in FIG10, the number of the first invalid pins 213b is equal to the number of the second invalid pins 222b, and the number of test lines 211b is less than the number of the first invalid pins 213b. The first invalid pins 213b and the second invalid pins 222b are bound one-to-one, and some of the first invalid pins 213b are connected to the test lines 211b. By making the number of test lines less than the number of the first invalid pins, different signals can be detected through the test lines while the space occupied by the test lines is smaller, allowing for a larger space for signal transmission lines and avoiding display defects.

[0066] Specifically, when testing the signals of a display device through test leads, different test leads can transmit different signals, or test leads can transmit different signals at different times, thereby enabling the transmission of different signals and detecting different signals to prevent abnormal signals from causing display defects.

[0067] Specifically, the design of the flexible circuit board, display panel, and driver chip of the display device in Figure 10 can be referenced in Figure 6.

[0068] In some embodiments, as shown in FIG5, the line width L1 of the test line 211b is equal to the line width L2 of the signal transmission line 211a. By making the line width of the test line equal to the line width of the signal transmission line, the problem of excessively large test lines occupying too much space leading to excessively small line width or spacing of the signal transmission line, resulting in excessive signal voltage drop or short circuits, is avoided when setting the test lines and signal transmission lines, thereby improving the yield of the display panel.

[0069] Specifically, the spacing between two adjacent test lines can be equal to the spacing between two adjacent signal transmission lines, and the distance between the test line and the signal transmission line can be equal to the spacing between two adjacent signal transmission lines, thereby avoiding short circuits caused by excessively small spacing between the traces and improving the yield of the display panel.

[0070] In some embodiments, as shown in FIG9, the driver chip 22 further includes a thin-film transistor T0 and a control line 223. The gate of the thin-film transistor T0 is connected to the control line 223, one electrode of the thin-film transistor T0 is electrically connected to the input pin group 221, and the other electrode of the thin-film transistor T0 is electrically connected to the second invalid pin 222b. By connecting the gate of the thin-film transistor to the control line, one electrode of the thin-film transistor to the input pin group, and the other electrode of the thin-film transistor to the second invalid pin, a signal can be input or not input to the second invalid pin under the control of the control line, thereby enabling or disabling testing of the display device.

[0071] Specifically, it is understandable that after the signal is transmitted to the input pin group of the driver chip, the driver chip will process the signal and may not transmit it directly to the output pin group. Therefore, the connection method of the thin film transistor here is only for illustration. The thin film transistor can realize the control signal transmission to the second invalid pin or not transmit it to the second invalid pin. The specific connection method can be set according to the requirements.

[0072] Specifically, the input pin group includes multiple signal pins, which can be connected to one electrode of multiple thin-film transistors (TFTs), and the other electrodes of the TFTs can be connected to multiple second invalid pins, so that each TFT controls one signal pin and one second invalid pin. Alternatively, multiple signal pins can be connected to one electrode of a single TFT, and the other electrode of the TFT can be connected to multiple second invalid pins, so that the single TFT controls multiple signal pins and multiple second invalid pins. Or, multiple signal pins can be connected to one electrode of multiple TFTs, and the other electrodes of the TFTs can be connected to a second invalid pin, so that the single TFT controls multiple signal pins and one second invalid pin.

[0073] In some embodiments, when the display device 2 is in a test state, the control line 223 outputs an active level; when the display device 2 is in a non-test state, the control line 223 outputs an inactive level. By making the control line output an active level in the test state, the thin-film transistor is turned on, allowing a signal to be transmitted on the second inactive pin, which enables signal detection of the display device. By making the control line output an inactive level in the non-test state, the thin-film transistor is turned off, thus preventing signal input to the second inactive pin when the display device is in a non-test state, avoiding interference with the display.

[0074] Specifically, it can be understood that the effective voltage level refers to the voltage level that enables a thin-film transistor (TFT), while the ineffective voltage level refers to the voltage level that prevents it from turning on. Since different types of TFTs require different voltage levels to be turned on, the effective voltage levels also differ. For example, when a low-level signal is input to the gate of a P-type TFT, the TFT turns on; when a high-level signal is input to the gate, the TFT turns off. In this case, the low-level signal is the effective voltage level, and the high-level signal is the ineffective voltage level. Conversely, when a high-level signal is input to the gate of an N-type TFT, the TFT turns on; when a low-level signal is input to the gate, the TFT turns off. In this case, the high-level signal is the effective voltage level, and the low-level signal is the ineffective voltage level.

[0075] Specifically, the orthographic projection of the first bonding pin group can coincide with the orthographic projection of the output pin group.

[0076] Specifically, the orthographic projection of the second bonding pin group can coincide with the orthographic projection of the input pin group.

[0077] Specifically, the orthographic projection of the third bonding pin group can coincide with the orthographic projection of the fourth bonding pin group.

[0078] Specifically, the number of pins in the fourth bonding pin group can be equal to the number of pins in the input pin group.

[0079] Specifically, the above embodiments have provided a detailed description of the display device from aspects such as the setting position and connection relationship of each structure. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the line width of the test line is equal to the width of the signal transmission line. The driving chip also includes a thin film transistor and a control line. The gate of the thin film transistor is connected to the control line. One electrode of the thin film transistor is electrically connected to the input pin group. The other electrode of the thin film transistor is electrically connected to the second invalid pin.

[0080] Specifically, the display panel can be one of the following: liquid crystal display panel, organic light-emitting diode display panel, micro light-emitting diode display panel, or quantum dot display panel.

[0081] Specifically, the driver chip can be a source driver chip, which transmits data signals.

[0082] As shown in Figures 11 and 12, when detecting the signal of the display device, a differential probe 25 can be used to detect the display device. Specifically, as shown in Figure 11, the probes (e.g., two probes) of the differential probe 25 can be brought into contact with the test lines (e.g., two test lines) to detect the signal. Alternatively, as shown in Figure 12, the probes (e.g., two probes) of the differential probe 25 can be brought into contact with the bonding terminals (e.g., two bonding terminals) to detect the signal.

[0083] Meanwhile, this application provides an electronic device that includes a display device as described in any of the above embodiments.

[0084] Specifically, as shown in Figure 13, the electronic device 3 includes a display device 2 and a system motherboard 31. The system motherboard 31 is connected to the display device 2 through wiring, specifically to a printed circuit board through wiring.

[0085] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0086] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0087] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0088] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display device comprising: The display panel includes a display area and a non-display area, wherein the non-display area is provided with a first binding part and a second binding part; A driver chip, one end of which is bonded and connected to the first bonding part; A flexible circuit board, wherein the other end of the flexible circuit board is connected to the other end of the driver chip via the second bonding part; The first bonding part includes at least one first invalid pin and at least one test line, the test line being disposed on the side close to the display area, and the first invalid pin being connected to the test line.

2. The display device according to claim 1, wherein The first bonding part includes a first connecting wire group and a first bonding pin group, and the second bonding part includes a second bonding pin group, a second connecting wire group and a third bonding pin group. The first connecting wire group is connected to the first bonding pin group, and the second connecting wire group is connected to the second bonding pin group and the third bonding pin group. The driver chip includes an input pin group and an output pin group. The output pin group is bonded to the first bonded pin group, and the input pin group is bonded to the second bonded pin group. The flexible circuit board includes a fourth bonding pin group, which is bonded to the third bonding pin group. The first bonding pin group includes the first invalid pin, and the first connection line group includes the test line.

3. The display device according to claim 2, wherein The first bonded pin group further includes multiple first valid pins, the output pin group includes multiple second valid pins and at least one second invalid pin, the first connection line group further includes multiple signal transmission lines, the first valid pins are bonded to the second valid pins, the first invalid pins are bonded to the second invalid pins, and the signal transmission lines are connected to the first valid pins.

4. The display device according to claim 3, wherein The first connection line group includes at least two test lines, and the first bonding pin group includes at least two first invalid pins, with each test line connected to one of the first invalid pins.

5. The display device of claim 4, wherein, The test line includes a connecting wire and a bonding terminal. Each connecting wire is connected to a first invalid pin, and each bonding terminal is connected to a connecting wire. The width of the bonding terminal is greater than the width of the connecting wire.

6. The display device of claim 5, wherein, When the display device is configured for testing, the bonding terminal receives different signals at different times.

7. The display device according to claim 4, wherein The number of the first invalid pins is equal to the number of the second invalid pins, the number of the test lines is equal to the number of the first invalid pins, the first invalid pins and the second invalid pins are bound one-to-one, and the first invalid pins and the test lines are connected one-to-one.

8. The display device according to claim 4, wherein The number of the first invalid pins is equal to the number of the second invalid pins, the number of test lines is less than the number of the first invalid pins, the first invalid pins and the second invalid pins are bound one-to-one, and some of the first invalid pins are connected to the test lines.

9. A display device according to any one of claims 3 to 8, wherein, The width of the test line is equal to the width of the signal transmission line.

10. A display device according to any one of claims 3 to 8, wherein, The driver chip also includes a thin-film transistor and a control line. The gate of the thin-film transistor is connected to the control line, one electrode of the thin-film transistor is electrically connected to the input pin group, and the other electrode of the thin-film transistor is electrically connected to the second invalid pin.

11. The display device of claim 10, wherein, When the display device is in test mode, the control line outputs an active level; when the display device is in non-test mode, the control line outputs an inactive level.

12. An electronic device comprising a display device, the display device comprising: The display panel includes a display area and a non-display area, wherein the non-display area is provided with a first binding part and a second binding part; A driver chip, one end of which is bonded and connected to the first bonding part; A flexible circuit board, wherein the other end of the flexible circuit board is connected to the other end of the driver chip via the second bonding part; The first bonding part includes at least one first invalid pin and at least one test line, the test line being disposed on the side close to the display area, and the first invalid pin being connected to the test line.

13. The electronic device of claim 12, wherein, The first bonding part includes a first connecting wire group and a first bonding pin group, and the second bonding part includes a second bonding pin group, a second connecting wire group and a third bonding pin group. The first connecting wire group is connected to the first bonding pin group, and the second connecting wire group is connected to the second bonding pin group and the third bonding pin group. The driver chip includes an input pin group and an output pin group. The output pin group is bonded to the first bonded pin group, and the input pin group is bonded to the second bonded pin group. The flexible circuit board includes a fourth bonding pin group, which is bonded to the third bonding pin group. The first bonding pin group includes the first invalid pin, and the first connection line group includes the test line.

14. The electronic device of claim 13, wherein, The first bonded pin group further includes multiple first valid pins, the output pin group includes multiple second valid pins and at least one second invalid pin, the first connection line group further includes multiple signal transmission lines, the first valid pins are bonded to the second valid pins, the first invalid pins are bonded to the second invalid pins, and the signal transmission lines are connected to the first valid pins.

15. The electronic device of claim 14, wherein, The first connection line group includes at least two test lines, and the first bonding pin group includes at least two first invalid pins, with each test line connected to one of the first invalid pins.

16. The electronic device of claim 15, wherein, The test line includes a connecting wire and a bonding terminal. Each connecting wire is connected to a first invalid pin, and each bonding terminal is connected to a connecting wire. The width of the bonding terminal is greater than the width of the connecting wire.

17. The electronic device of claim 16, wherein, When the display device is configured for testing, the bonding terminal receives different signals at different times.

18. The electronic device of claim 15, wherein, The number of the first invalid pins is equal to the number of the second invalid pins, the number of the test lines is equal to the number of the first invalid pins, the first invalid pins and the second invalid pins are bound one-to-one, and the first invalid pins and the test lines are connected one-to-one.

19. The electronic device of claim 15, wherein, The number of the first invalid pins is equal to the number of the second invalid pins, the number of the test lines is less than the number of the first invalid pins, the first invalid pins are bound one by one with the second invalid pins, and part of the first invalid pins are connected with the test lines.

20. The electronic device of any one of claims 14 to 19, wherein, The line width of the test lines is equal to the width of the signal transmission lines.

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