Semiconductor device and preparation method therefor, and electronic device

Abstract

Provided in the embodiments of the present disclosure are a semiconductor device and a preparation method therefor, and an electronic device. The semiconductor device comprises: a memory cell array, which comprises a plurality of layers of memory cells stacked in a first direction, wherein a plurality of memory cells located in the same layer are arranged in columns in a second direction and arranged in rows in a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; each memory cell comprises a transistor; the transistor comprises a first semiconductor layer and a gate electrode surrounding a channel region of the first semiconductor layer; and first semiconductor layers of the plurality of memory cells arranged in the first direction are of an interconnected integral structure.

Description

A semiconductor device and its fabrication method, and an electronic device.

[0001] Cross-reference to related applications

[0002] This disclosure is based on and claims priority to Chinese Patent Application No. 202411855561.X, filed on December 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0004] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0005] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands.

[0006] Application content

[0007] In view of the above, this disclosure provides a semiconductor device and a method for fabricating the same, as well as an electronic device.

[0008] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0009] This disclosure provides a semiconductor device, including: a memory cell array, comprising multiple layers of memory cells stacked in a first direction; wherein, a plurality of memory cells located on the same layer are arranged in columns in a second direction and in rows in a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; the memory cells include transistors; the transistors include a first semiconductor layer and a gate of a channel region surrounding the first semiconductor layer; the first semiconductor layer of the plurality of memory cells arranged along the first direction is an integral structure interconnected with each other.

[0010] This disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate including a base and a stacked structure formed on the base, the stacked structure including alternating first insulating layer and second insulating layer; forming a first etching trench extending through the stacked structure in a third direction, the first etching trench having a size larger in the first insulating layer than in the second insulating layer; forming an initial gate connection structure within the first etching trench; forming a first hole extending through the stacked structure, and laterally etching the initial gate connection structure through the first hole to form a second lateral groove located on both sides of the first hole; forming a gate on the inner wall of the second lateral groove; forming a first semiconductor layer on the inner wall of the first hole and the second lateral groove; the first semiconductor layer within the second lateral groove and the gate surrounding the first semiconductor layer are used to form a transistor.

[0011] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device manufactured according to any of the methods described above for manufacturing semiconductor devices. Attached Figure Description

[0012] Figure 1 is a schematic diagram of the steps of a semiconductor device fabrication method provided in an embodiment of this disclosure;

[0013] Figure 2 is a schematic diagram of the structure of a substrate provided in an embodiment of this disclosure;

[0014] Figures 3 to 5 are schematic diagrams of the process of forming an initial gate connection structure according to an embodiment of the present disclosure; wherein, (a) is a top view and (b) is a cross-sectional view of the structure shown in (a) along line AA;

[0015] Figures 6 to 12 are schematic diagrams of a structure during the formation of a gate according to an embodiment of the present disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and in Figures 9 to 12, (d) is a cross-sectional view of the structure shown in (a) along line CC.

[0016] Figures 13 to 19 are schematic diagrams of a capacitor forming process provided in an embodiment of the present disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and (d) is a cross-sectional view of the structure shown in (a) along line CC.

[0017] Figure 20 is a schematic diagram of the structure during the formation of a first semiconductor layer according to an embodiment of the present disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and (d) is a cross-sectional view of the structure shown in (a) along line CC.

[0018] Figure 21 is a schematic diagram of the structure during the formation of a bit line according to an embodiment of the present disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and (d) is a cross-sectional view of the structure shown in (a) along line CC.

[0019] Figure 22 is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Detailed Implementation

[0020] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0021] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0022] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0024] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0026] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0027] This disclosure provides a semiconductor device, including: a memory cell array comprising multiple layers of memory cells stacked in a first direction; wherein a plurality of the memory cells located on the same layer are arranged in a column in a second direction and in a row in a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; each memory cell includes a transistor; each transistor includes a first semiconductor layer and a gate of a channel region surrounding the first semiconductor layer; the first semiconductor layers of the plurality of memory cells arranged along the first direction are an integral structure interconnected.

[0028] In this embodiment of the disclosure, multiple storage cells can be arranged in a single layer or stacked in multiple layers along a first direction. The storage cells in each layer can be distributed in an array along a second direction and a third direction.

[0029] The memory cells in the semiconductor device provided in this disclosure can not only be stacked in a direction perpendicular to the substrate, but also arranged in an array in a plane parallel to the substrate, which is beneficial to improving the integration density of the memory cells.

[0030] Figure 1 is a schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of this disclosure. As shown in Figure 1, the fabrication method includes the following steps:

[0031] Step S101: Provide a substrate, the substrate including a substrate and a stacked structure formed on the substrate, the stacked structure including an alternately arranged first insulating layer and a second insulating layer.

[0032] Step S102: Form a first etch trench that penetrates the stacked structure and extends along the third direction, wherein the size of the first etch trench in the first insulating layer is larger than the size in the second insulating layer.

[0033] Step S103: Form an initial gate connection structure in the first etch trench.

[0034] Step S104: Form a first hole through the stacked structure, and perform lateral etching on the initial gate connection structure through the first hole to form a second lateral groove located on both sides of the first hole.

[0035] Step S105: Form a gate on the inner wall of the second transverse groove.

[0036] Step S106: A first semiconductor layer is formed on the inner wall of the first hole and the second transverse groove; the first semiconductor layer in the second transverse groove and the gate surrounding the first semiconductor layer are used to form a transistor.

[0037] It should be understood that the steps shown in Figure 1 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in the operation.

[0038] In some embodiments, step S102 includes: forming a first trench that penetrates the stacked structure and extends in a third direction; and laterally etching the first insulating layer through the first trench to form first lateral grooves located on both sides of the first trench; the first trench and the first lateral grooves constitute a first etched trench. At this time, the size of the first etched trench in the first insulating layer is larger than the size of the first etched trench in the second insulating layer.

[0039] In some embodiments, step S103 includes: filling and forming a metal layer in the first lateral groove; or, filling and forming a connection layer in the first lateral groove; or, forming a metal layer on the inner wall of the first lateral groove and filling and forming a connection layer. In other words, in embodiments of this disclosure, the initial gate connection structure includes a metal layer; or, the initial gate connection structure includes a connection layer; or, the initial gate connection structure includes both a metal layer and a connection layer.

[0040] In this embodiment of the disclosure, the material of the interconnect layer includes doped polycrystalline silicon.

[0041] It should be noted that the following description uses the initial gate connection structure including a metal layer as an example.

[0042] In some embodiments, step S104 includes: forming a first filling structure in a first trench; forming a plurality of first holes extending along a first direction and spaced apart along a third direction in the first filling structure; and laterally etching the initial gate connection structure through the first holes to form second lateral grooves located on both sides of the first holes.

[0043] In some embodiments, after step S105, the method further includes: forming a second filling layer that fills the second transverse groove.

[0044] In some embodiments, the method further includes: forming a second hole through the stacked structure on one side of the first hole along a second direction; laterally etching the first insulating layer through the second hole to form a third lateral groove; etching away the gate and second filler layers of the bottom wall of the second lateral groove exposed by the third lateral groove to make the third lateral groove and the second lateral groove interconnected; forming a gate dielectric layer covering the inner walls of the first hole, the second lateral groove, the second hole, and the third lateral groove, and a third filler layer filling the first hole, the second lateral groove, the second hole, and the third lateral groove through the first hole and the second hole.

[0045] In some embodiments, the method further includes: removing a third filling layer in the second hole and the third transverse groove; forming a first electrode plate of a capacitor on the inner wall of the third transverse groove; forming a first dielectric layer of a capacitor that at least covers the first electrode plate in the second hole and the third transverse groove; and filling the second electrode plate of the capacitor.

[0046] In some embodiments, the method further includes: forming a second initial trench along a second direction on the side of the second hole opposite to the first hole, penetrating the stacked structure and extending along a third direction; laterally etching the stacked structure through the second initial trench to form the second trench; and filling the second trench to form a third electrode plate of a capacitor.

[0047] In some embodiments, prior to step S106, the method further includes: removing a third filler layer within the first hole and the second lateral groove to expose the gate dielectric layer within the second lateral groove.

[0048] In some embodiments, the method further includes: filling the first hole and the second lateral groove to form a fourth fill layer; replacing the fourth fill layer in the first hole with the bit line; the bit line contacting the first semiconductor layer.

[0049] Figures 2, 3 to 5, 6 to 12, 13 to 19, 20, and 21 are schematic diagrams of the semiconductor device structure at various stages in the fabrication method of the semiconductor device provided in the embodiments of this disclosure. It should be noted that Figures 2, 3 to 5, 6 to 12, 13 to 19, 20, and 21 constitute a complete schematic diagram reflecting the implementation process of the semiconductor device fabrication method, and parts not marked in some of the figures can be shared. The fabrication method of the semiconductor device provided in the embodiments of this disclosure will be described in detail below with reference to Figures 1, 2 to 21.

[0050] It should be noted that, for ease of description, the various directions that may be used in the following description are defined first. A first direction (Z direction) is defined in a plane perpendicular to the substrate, and a second direction (X direction) and a third direction (Y direction) are defined in a plane parallel to the substrate. The X, Y, and Z directions can be mutually perpendicular.

[0051] The deposition processes involved in the embodiments of this disclosure include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0052] The etching processes involved in the embodiments of this disclosure include, but are not limited to, dry etching, wet etching, and combinations thereof.

[0053] The "patterning process" involved in the embodiments of this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. Deposition can be performed using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be performed using known coating processes; and etching can be performed using known methods. No specific limitations are made here.

[0054] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may be a memory, such as Dynamic Random Access Memory (DRAM), or other memory chips or processing chips that contain DRAM memory cells.

[0055] Figure 2 is a schematic diagram of the substrate structure provided in an embodiment of this disclosure. Referring to Figure 2, step S101 includes: providing a substrate 1, and alternately stacking a first insulating layer 21 and a second insulating layer 22 on the substrate 1 through a deposition process to form a stacked structure 20. Exemplarily, the first insulating layer 21 and the second insulating layer 22 may have the same thickness or different thicknesses, and neither of them is zero. The first insulating layer 21 may be formed of silicon nitride, and the second insulating layer 22 may be formed of silicon oxide, such that the stacked structure 20 is a nitride-oxide (NO) stack. It should be noted that the number of layers of the first insulating layer 21 and the second insulating layer 22 in the stacked structure 20 shown in Figure 2 is only an example, and the specific number of layers of the first insulating layer 21 and the second insulating layer 22 in this disclosure is not limited to the number of layers shown in the figure.

[0056] In some embodiments, after the stacked structure 20 is formed on the substrate 1, a hard mask layer 23 can be deposited on the top surface of the stacked structure 20 away from the substrate 1 by a deposition process. The hard mask layer 23 is used for subsequent patterning processes of the stacked structure 20. Exemplarily, the material of the hard mask layer 23 may include oxides and / or amorphous carbon, and the thickness of the hard mask layer 23 is approximately 50 nm to 400 nm.

[0057] In some embodiments, to avoid electrical connections between multiple rows of memory cells via the substrate 1, at least one insulating layer 24 may be included between the substrate 1 and the stacked structure 20. The material of the insulating layer 24 is an insulating material. For example, the insulating layer 24 between the substrate 1 and the stacked structure 20 may be a second insulating layer. It should be noted that, in the embodiments of this disclosure, identical structures located in the same layer (or in the same stacked layer) and arranged along a third direction (Y direction) are called rows, and identical structures arranged along a second direction (X direction) are called columns. For example, memory cells arranged along a third direction (Y direction) and located in the same layer are called a row of memory cells or a row of memory cells, and memory cells arranged along the second direction (X direction) are called a column of memory cells or a column of memory cells.

[0058] This disclosure does not specifically limit the constituent materials of substrate 1. As an example, substrate 1 can be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, the substrate can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0059] The insulating and dielectric materials involved in this disclosure can all be insulating materials with high dielectric constant (High-K, HK), such as dielectric materials with a dielectric constant K greater than or equal to 3.9. These include, but are not limited to, HK materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2); the conductive materials can be materials containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; the semiconductor materials can be at least one of monocrystalline silicon, amorphous silicon, polycrystalline silicon, or doped polycrystalline silicon, and the semiconductor materials can also be metal oxide semiconductors.

[0060] The material of the gate dielectric layer involved in this disclosure can be selected from one or more of silicon oxide (e.g., SiO2), hafnium oxide (e.g., HfO2), zirconium oxide (e.g., ZrO), and aluminum oxide (e.g., Al2O3). The gate dielectric layer can be a single-layer structure or a multi-layer structure; for example, it can include a two-layer structure formed of silicon oxide and hafnium oxide, wherein the silicon oxide layer contacts the channel region, and the hafnium oxide layer contacts the gate. The thickness of the gate dielectric layer can be set according to actual electrical requirements, for example, it can be from 2 nm to 5 nm.

[0061] Figures 3 to 5 are cross-sectional schematic diagrams illustrating the process of forming an initial gate connection structure according to an embodiment of this disclosure; wherein, (a) is a top view, and (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA. The formation process of the initial gate connection structure will be described in detail below with reference to the accompanying drawings. Referring to Figure 3, a patterned photoresist layer 25 is formed on the hard mask layer 23. The patterned photoresist layer 25 is used to etch the hard mask layer 23 and the stacked structure 20 to form a first trench 31 that penetrates the stacked structure 20 and extends along a third direction. The patterned photoresist layer 25 can be removed after the first trench is formed. It should be noted that the number of first trenches shown in Figure 3 is only an example, and this disclosure does not limit the number of first trenches.

[0062] Referring to Figure 4, the first insulating layer 21 is laterally etched through the first trench 31 to form first lateral grooves 32 located on both sides of the first trench 31. The first trench 31 and the first lateral grooves 32 constitute the first etched trench.

[0063] Here, the first lateral groove 32 is used to define the word line formation area, which includes the gate and the gate connection structure, wherein the gate connection structure and the gate are formed in different process steps. Since the first trench 31 extends along the third direction (Y direction), the first lateral groove 32 also extends along the third direction (Y direction), and the first lateral grooves 32 of different layers are isolated from each other by the second insulating layer 22.

[0064] Referring to FIG5, an initial gate connection structure 41 is formed within a first lateral groove 32, and a word line isolation structure 42 is formed within a first trench 31. In the structure shown in FIG5, the initial gate connection structure 41 includes a first dielectric layer 411 and a metal layer 412. In embodiments of this disclosure, the constituent material of the metal layer may include a metal element; the metal may be, for example, tungsten or copper (Cu).

[0065] Forming an initial gate connection structure 41 within the first lateral groove 32 specifically includes: depositing dielectric material within the first lateral groove 32; performing lateral back etching on the dielectric material within the first lateral groove 32 to form a first dielectric layer 411 with the remaining dielectric material on the bottom wall of the first lateral groove 32; and filling the first lateral groove 32 to form a metal layer 412.

[0066] The formation of a metal layer 412 within the first lateral groove 32 includes: filling the first trench 31 and the first lateral groove 32 with metal material; replacing the metal material in the first trench 31 with dielectric material; the dielectric material in the first trench 31 forming a word line isolation structure 42; and the metal material in the first lateral groove 32 forming a metal layer 412. At this time, the first dielectric layer 411 and the metal layer 412 within the first lateral groove 32 constitute an initial gate connection structure 41.

[0067] In other embodiments, a connection layer is formed within the first lateral groove, comprising: filling the first trench and the first lateral groove with doped semiconductor material; replacing the doped semiconductor material in the first trench with dielectric material; the dielectric material in the first trench forming a word line isolation structure; and the doped semiconductor material in the first lateral groove forming a connection layer. In this case, the first dielectric layer and the connection layer within the first lateral groove constitute an initial gate connection structure.

[0068] In other embodiments, a metal layer is formed on the inner wall of the first lateral groove, and a connection layer is formed therein. This includes: forming an initial metal layer on the inner wall of the first trench and the first lateral groove, and forming an initial connection layer therein; etching away the initial connection layer and the initial metal layer in the first trench, leaving the remaining initial metal layer on the inner wall of the first lateral groove as a metal layer, and leaving the remaining initial connection layer in the first lateral groove as a connection layer. In this case, the metal layer and the connection layer in the first lateral groove constitute an initial gate connection structure.

[0069] Figures 6 to 12 are schematic diagrams of a gate formation process provided in an embodiment of this disclosure. Figure (a) is a top view, Figure (b) is a cross-sectional view of the structure shown in Figure (a) along line AA, Figure (c) is a cross-sectional view of the structure shown in Figure (a) along line BB, and in Figures 9 to 12, Figure (d) is a cross-sectional view of the structure shown in Figure (a) along line CC. The gate formation process will now be described in detail with reference to the accompanying drawings. Referring to Figure 6, forming a first filling structure within a first trench includes: patterning a word line isolation structure 42 using a patterning process to form first initial holes 33 within the word line isolation structure 42. A plurality of first initial holes 33 may extend along a first direction Z and be spaced apart along a third direction.

[0070] In some embodiments, the first initial holes 33 are arranged in an array in the stacked structure, specifically including a plurality of first initial holes 33 arranged along the second direction (X direction) and a plurality of first initial holes 33 arranged along the third direction (Y direction). It should be noted that the number of first initial holes 33 shown in FIG6 is only an example, and the number of first initial holes 33 in this disclosure is not limited to the number shown in FIG6.

[0071] Referring to Figure 7, forming a first filling structure within the first trench further includes filling the first initial via 33 with sacrificial material to form a sacrificial structure 43. The remaining word line isolation structure 42 and the sacrificial structure 43 within the first trench constitute the first filling structure. Here, the sacrificial material can be the same as the material of the initial gate connection structure.

[0072] Referring to Figure 8, forming a first hole within a first filling structure includes: patterning a sacrificial structure 43 in the first filling structure using a patterning process to form a first hole 34 within the sacrificial structure 43.

[0073] In some embodiments, the first holes 34 are arranged in an array in the stacked structure, specifically including a plurality of first holes 34 arranged along a second direction (X direction) and a plurality of first holes 34 arranged along a third direction (Y direction). It should be noted that the number of first holes 34 shown in FIG8 is only an example, and the number of first holes 34 in this disclosure is not limited to the number shown in FIG8.

[0074] Referring to Figure 9, the process includes: laterally etching the initial gate connection structure 41 through a first hole 34 to form second lateral grooves 35 located on both sides of the first hole 34. The first hole 34 and the second lateral grooves 35 constitute a first etch hole. The first hole 34 and the second lateral grooves 35 are used to define the transistor formation region, wherein the second lateral groove 35 is used to define the transistor channel region and the gate formation region.

[0075] Here, when the initial gate connection structure 41 is laterally etched through the first hole 34 to form the second lateral groove 35, the first insulating layer 21 serves as an etching stop layer. Therefore, the dimension of the second lateral groove along the second direction (X direction) is the same as the dimension of the first lateral groove along the second direction (X direction). Thus, the initial gate connection structure can be isolated by the second lateral groove. The initial gate connection structure isolated by the second lateral groove is the gate connection structure 41'.

[0076] Referring to Figure 10, the process includes: forming an initial gate layer 44 on the inner wall of the first hole 34 and the second lateral groove 35, and filling material filling the first hole 34 and the second lateral groove 35. Here, the filling material can be a dielectric material.

[0077] In some embodiments, the word line includes gates 44' alternately arranged in a third direction and gate connection structures 41' (metal layer 412) connecting adjacent gates 44', the gate connection structures 41' (metal layer 412) extending along the third direction and contacting adjacent gates 44'.

[0078] In some embodiments, the initial gate layer 44 may be a thin film covering the inner walls of the first hole 34 and the second lateral groove 35. In embodiments of this disclosure, the material of the initial gate layer 44 is a conductive material.

[0079] Referring to Figure 11, after removing the initial gate layer 44 and filler material within the first hole 34, the remaining initial gate layer 44 on the bottom and sidewalls of the second lateral groove 35 is used to form the gate 44'. Here, the filler material can be a dielectric material.

[0080] It should be noted that the bottom wall of the second transverse groove refers to the bottom wall of the second transverse groove in the second direction (X direction) that exposes the first insulating layer, and the side walls of the second transverse groove refer to the four sides of the second transverse groove in the first direction (Z direction) and the third direction (Y direction). The bottom wall and side walls of the second transverse groove constitute the inner wall of the second transverse groove.

[0081] In this embodiment of the disclosure, the material of the gate connection structure and the material of the gate 44' can be the same or different.

[0082] Referring to Figure 12, a filler material is deposited in the first hole 34, and the filler material in the first hole 34 and the remaining filler material in the second transverse groove 35 form a second filler layer 45. Here, the filler material can be a dielectric material.

[0083] Figures 13 to 19 are schematic diagrams of the structure during the formation of a capacitor according to an embodiment of the present disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and (d) is a cross-sectional view of the structure shown in (a) along line CC. The formation process of the capacitor will be described in detail below with reference to the accompanying drawings. Referring to Figure 13, a second hole 36 is formed through the stacked structure 20 on one side of the first hole 34 along the second direction. The first insulating layer 21 is laterally etched through the second hole 36 to expose the gate, thereby forming a third lateral groove 37; the gate 44' exposed by the third lateral groove 37 is etched away. That is, the gate 44' of the bottom wall of the second lateral groove is etched away. The gate of the side wall of the second lateral groove is the final gate. In some embodiments, the second hole is located on both sides of the transistor formation region along the second direction (X direction).

[0084] Here, the second hole 36 and the third transverse groove 37 are used to define the forming area of ​​the capacitor, wherein the third transverse groove 37 is used to define the forming area of ​​the first plate of the capacitor.

[0085] In some embodiments, the second holes 36 are arranged in an array in the stacked structure, specifically including a plurality of second holes 36 arranged along a second direction (X direction) and a plurality of second holes 36 arranged along a third direction (Y direction). It should be noted that the number of second holes 36 shown in FIG13 is only an example, and the number of second holes 36 in this disclosure is not limited to the number shown in FIG13.

[0086] Referring to Figure 14, the second filling layer 45 within the second transverse groove 35 and the filling material within the first hole 34 are etched away. At this point, the third transverse groove 37 and the second transverse groove 35 are connected, thereby connecting the first hole 34 and the second hole 36.

[0087] In some embodiments, the second holes 36 are located on both sides of the first holes 34 along the second direction (X direction), and there are two second holes 36 between two adjacent first holes 34 along the second direction (X direction).

[0088] Referring to Figure 15, a gate dielectric layer 46 is formed through the first hole 34 and the second hole 36, covering the inner walls of the first hole 34, the second lateral groove 35, the second hole 36, and the third lateral groove 37, and a third filling layer 47 is formed to fill the first hole 34, the second lateral groove 35, the second hole 36, and the third lateral groove 37.

[0089] Referring to Figure 16, remove the third filler layer 47 from the second hole 36 and the third transverse groove 37.

[0090] Referring to Figure 17, the first electrode 51, the first dielectric layer 52, and the second electrode 53 of the capacitor are formed in the second hole 36 and the third transverse groove 37.

[0091] In some embodiments, forming a first electrode 51, a first dielectric layer 52, and a second electrode 53 of a capacitor includes: forming the first electrode 51 of the capacitor on the inner wall of a third transverse groove 37; forming the first dielectric layer 52 of the capacitor, at least covering the first electrode 51, within the second hole 36 and the third transverse groove 37; and filling the second electrode 53 of the capacitor. The first electrode 51, the first dielectric layer 52, and the second electrode 53 of the capacitor constitute a single-layer capacitor 50.

[0092] In some embodiments, forming a first electrode plate of a capacitor on the inner wall of a third transverse groove includes: forming a first electrode layer on the inner wall of a second hole and a third transverse groove; depositing a filler material in the second hole and a third transverse groove; etching away the filler material in the second hole to expose the first electrode layer on the inner wall of the second hole; etching away the first electrode layer on the inner wall of the second hole; and forming the first electrode layer of the capacitor with the remaining first electrode layer in the third transverse groove.

[0093] In some embodiments, the first plates of the capacitors of different layers are arranged at intervals in a first direction (Z direction); the first plate is an annular plate, and the second plate fills the annular cavity formed by the annular plate. The second plate can be a cavity structure or a solid structure.

[0094] In some embodiments, the end of the second electrode extends along a first direction (Z direction) and a second direction (X direction). The second electrode of the plurality of memory cells arranged along the first direction (Z direction) is a single structure.

[0095] In some embodiments, forming a first dielectric layer of a capacitor that at least covers the first electrode plate within the second hole and the third lateral groove includes: etching away the filling material within the third lateral groove, and depositing the first dielectric layer of a capacitor that at least covers the first electrode plate through the second hole.

[0096] Referring to FIG18, a second initial trench is formed that penetrates the stacked structure and extends along a third direction (Y direction). The second initial trench is located between two adjacent monolayer capacitors 50 along the second direction (X direction). The stacked structure 20 is laterally etched through the second initial trench to form a second trench 38. Here, the size of the second trench 38 in the stacked structure 20 is larger than the minimum distance between two adjacent monolayer capacitors 50 along the second direction (X direction) and smaller than the maximum distance between two adjacent monolayer capacitors 50 along the second direction (X direction). Continuing to refer to FIG18, the gate dielectric layer 46 exposed after the stacked structure is further etched away through the second trench 38.

[0097] Referring to Figure 19, a third electrode 54 forming a capacitor is filled in the second trench 38. The third electrode 54 at least partially surrounds the outside of the first electrode 51; multiple single-layer capacitors 50 arranged along the first direction (Z direction) share the same third electrode 54, and two adjacent rows of single-layer capacitors 50 along the second direction (X direction) share the same third electrode 54. In this embodiment, the second electrode 53 and the third electrode 54 are respectively disposed on the inner and outer sides of the first electrode 51, thereby forming a double-layer capacitor with two adjacent single-layer capacitors 50 and the third electrode 54. Compared with a single-layer capacitor with only two electrodes, the double-layer capacitor occupies a smaller area and has a shorter length for the same capacitance, which helps to reduce the size of the semiconductor device and also prevents the stacked structure from collapsing during fabrication. It should be noted that the gate dielectric layer 46 between the first electrode plate 51 and the third electrode plate 54 can be reused as the second dielectric layer between the first electrode plate 51 and the third electrode plate 54, and the gate dielectric layer 46 and the first dielectric layer 52 between the second electrode plate 53 and the third electrode plate 54 are also used to isolate the second electrode plate 53 and the third electrode plate 54.

[0098] Referring again to Figure 19, before filling the second trench 38 to form the third electrode plate 54, a dielectric thin film can also be formed in the second trench 38 as a second dielectric layer 55 to isolate the first electrode plate 51 from the third electrode plate 54.

[0099] Figure 20 is a schematic diagram of the structure during the formation of a first semiconductor layer according to an embodiment of this disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and (d) is a cross-sectional view of the structure shown in (a) along line CC. The formation process of the first semiconductor layer will now be described in detail with reference to the accompanying drawings. Referring to Figure 20, the third filling layer 47 in the first hole 34 and the second lateral groove 35 is removed; a first semiconductor layer 61 is formed on the inner walls of the first hole 34 and the second lateral groove 35, and a fourth filling layer 62 is formed by filling. The first semiconductor layer 61 in the second lateral groove 35 and the gate 44' surrounding the first semiconductor layer 61 are used to form a transistor.

[0100] In this embodiment, the first semiconductor layer is formed after the capacitor is formed, which helps to reduce the thermal impact on the transistor. Furthermore, the first semiconductor layer does not require further etching after its formation, thus avoiding damage to the channel caused by etching and ensuring transistor performance.

[0101] In some embodiments, the first semiconductor layer 61 is a thin film covering the inner walls of the first hole 34 and the second lateral groove 35. This avoids the first semiconductor layer 61 from being too large, thereby improving the channel performance of the transistor.

[0102] In some embodiments, the first semiconductor layers of the plurality of memory cells arranged along a first direction are interconnected as a single structure. The single structure includes alternating first and second portions, wherein the first portion may be a first semiconductor layer formed in a first hole 34, and the second portion may be a first semiconductor layer formed in a second lateral groove 35. The first portion extends along the first direction and surrounds the sidewalls of subsequently formed bit lines, and the second portion may extend along a second direction, with the gate surrounding the sidewalls of the second portion.

[0103] In this embodiment, the transistor employs a gate-around structure (the gate surrounds the channel region) to achieve better switching control of the channel. Furthermore, the gate connection structure and the gate-around structure together form word lines, which further reduces the RC delay between word lines, improves the device response rate, and thus enhances the overall performance of the device.

[0104] In some embodiments, the material of the first semiconductor layer 61 includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten. The metal oxide semiconductor may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain other small amounts of doping elements. Furthermore, compared to other semiconductor materials, using metal oxide semiconductors allows for better control of the manufacturing cost of semiconductor devices.

[0105] In some embodiments, the metal-oxide semiconductor material can be indium gallium zinc oxide (IGZO). When the metal-oxide material is IGZO, the transistor has a smaller leakage current (leaking current less than or equal to 10). -15A), which ensures a low refresh rate for the storage unit. It should be noted that the metal oxide material can also be ITO or InSnOx (Indium Tin Oxide), IWO or InWO (Indium Tungsten Oxide), ZnOx (Zinc Oxide), InOx (Indium Oxide), In2O3 (Indium Oxide), SnO2 (Tin Dioxide), TiOx (Tin Dioxide), ZnxOyNz (Zinc Nitride Oxide), MgxZnyOz (Magnesium Zinc Oxide), InxZnyOz (Indium Zinc Oxide), InxGayZnzOa (Indium Gallium Zinc Oxide), ZrxInyZnzOa (Zirconium Indium Zinc Oxide), HfxInyZnzOa (Hafnium Indium Zinc Oxide). Indium Zinc Oxide, SnxInyZnzOa (Tin Indium Zinc Oxide), AlxSnyInzZnaOd (Aluminum Tin Indium Zinc Oxide), SixInyZnzOa (Silicon Indium Zinc Oxide), ZnxSnyOz (Zinc Tin Oxide), AlxZnySnzOa (Aluminum Indium Tin Oxide), GaxZnySnzOa (Gallium Indium Tin Oxide), ZrxZnySnzOa (Zirconium Indium Tin Oxide), InGaSiO (Indium Gallium Silicon Oxide), IAZO (Indium Aluminum Zinc Oxide), IGO (Indium Gallium Oxide). Materials such as indium gallium oxide (IGAO), indium zinc oxide (IZO), and indium zinc oxide (IZOx) are acceptable, as long as the leakage current of the transistor meets the requirements. The specific requirements can be adjusted according to the actual situation.

[0106] Figure 21 is a schematic diagram of a bit line formation process according to an embodiment of this disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and (d) is a cross-sectional view of the structure shown in (a) along line CC. The bit line formation process will now be described in detail with reference to the accompanying drawings. Referring to Figure 21, forming a bit line in a stacked structure includes replacing the fourth filling layer 62 within the first hole 34 with a bit line 63. Specifically, the fourth filling layer within the first hole is etched away, and a conductive material is filled to form the bit line.

[0107] This disclosure does not specifically limit the constituent materials of the bit lines. As an example, the constituent materials of the bit lines may include, but are not limited to, materials containing titanium (Ti) or tungsten (W).

[0108] In some embodiments, by setting the bit line 63 to extend along a first direction (Z direction) and two adjacent memory cells along a second direction (X direction) to be connected to the same bit line, there is at least a pair of transistors and a pair of capacitors between the two adjacent bit lines 63 along the second direction (X direction). Based on this, the bit line spacing is greatly increased, the coupling between the bit lines is reduced, the bit line capacitance is effectively reduced, and the process complexity is reduced.

[0109] In some embodiments, a transistor and a capacitor constitute a memory cell. Bit lines extend along a first direction, and multiple memory cells arranged along the first direction are connected to the same bit line. Two adjacent memory cells along a second direction are also connected to the same bit line. The first semiconductor layer connecting the memory cells to the same bit line is an interconnected integral structure. In this embodiment, after forming the first semiconductor layer, no further etching process is required, thereby avoiding damage to the channel caused by the etching process.

[0110] Figure 22 is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present disclosure. As shown in Figure 22, the semiconductor device includes: a memory cell array, including multiple layers of memory cells stacked in a first direction; wherein, multiple memory cells located in the same layer are arranged in columns in a second direction and in rows in a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; the memory cell includes a transistor T; the transistor T includes a first semiconductor layer 61 and a gate 44' surrounding a channel region of the first semiconductor layer; the first semiconductor layer 61 of the multiple memory cells arranged along the first direction is an integral structure interconnected with each other.

[0111] In this embodiment, the transistor employs a gate-around structure (the gate surrounds the channel region) to achieve better switching control of the channel. Furthermore, the gate connection structure and the gate-around structure together form word lines, which further reduces the RC delay between word lines, improves the device response rate, and thus enhances the overall performance of the device.

[0112] In some embodiments, the memory cell further includes a capacitor C; the transistor T and capacitor C of the same memory cell are arranged along a second direction.

[0113] In some embodiments, the semiconductor device further includes: a bit line 63 extending along a first direction; a plurality of memory cells arranged along the first direction connected to the same bit line 63, and two adjacent memory cells along a second direction connected to the same bit line 63; a first semiconductor layer 61 of the memory cells connected to the same bit line 63 is an integral structure interconnected and at least partially surrounds the sidewall of the bit line 63.

[0114] In this embodiment of the disclosure, by setting the bit line 63 to extend along the first direction (Z direction) and two adjacent memory cells along the second direction (X direction) to be connected to the same bit line, there is at least a pair of transistors and a pair of capacitors between the two adjacent bit lines 63 along the second direction (X direction). Based on this, the bit line spacing is greatly increased, the coupling between the bit lines is reduced, the bit line capacitance is effectively reduced, and the process complexity is reduced.

[0115] In some embodiments, the integral structure includes alternating first portions 611 and second portions 612; the first portions 611 extend along a first direction (Z direction) and surround the sidewall of the bit line 63, the second portions 612 extend along a second direction (X direction), and the gate 44' surrounds the sidewall of the second portions 612.

[0116] In some embodiments, the second portion 612 has a cylindrical structure with an opening facing the bit line, and a filling layer is disposed inside the cylindrical structure, namely the aforementioned fourth filling layer 62.

[0117] In some embodiments, the gates 44' of multiple memory cells in each row of the same layer are connected by a gate connection structure to form a word line; the gate connection structure includes a metal layer and / or a connection layer.

[0118] In some embodiments, the word line includes gates 44' and gate connection structures alternately arranged in a third direction (Y direction). The gate connection structure includes a metal layer or a connection layer extending in the third direction, and the two ends of the metal layer or connection layer in the third direction are in contact with adjacent gates 44'; or, the gate connection structure includes a connection layer extending in the third direction and a metal layer surrounding the sidewall of the connection layer, and the two ends of the metal layer and the connection layer in the third direction are in contact with adjacent gates 44'.

[0119] In some embodiments, capacitor C includes a first electrode plate 51 and a second electrode plate 53; the first electrode plate 51 is connected to a first semiconductor layer 61, and the first electrode plates 51 in capacitors C of different layers are spaced apart in a first direction; the first electrode plate 51 is an annular electrode plate, the second electrode plate 53 is filled in the annular cavity formed by the annular electrode plate, and multiple memory cells arranged along the first direction share the same second electrode plate.

[0120] In some embodiments, one end of the second portion 612 is connected to the first portion 611 along the second direction, and the other end is connected to the first electrode plate 51.

[0121] In some embodiments, the capacitor further includes a third electrode plate 54, which at least partially surrounds the outside of the first electrode plate 51; a plurality of memory cells arranged along a first direction share the same third electrode plate 54, and two adjacent rows of memory cells along a second direction share the same third electrode plate 54.

[0122] In some embodiments, the capacitor C further includes a first dielectric layer 52 located between the first electrode 51 and the second electrode 53, and a second dielectric layer 55 located between the first electrode 51 and the third electrode 54; the first dielectric layer 52 and the second dielectric layer 55 are also used to isolate the second electrode 53 and the third electrode 54.

[0123] In this embodiment, the second electrode 53 and the third electrode 54 are respectively disposed on the inner and outer sides of the first electrode 51, thereby forming a capacitor with two layers. Compared with a single-layer capacitor with only two electrodes, the double-layer capacitor occupies a smaller area and has a shorter length for the same capacitance, which helps to reduce the size of the semiconductor device and can also prevent the stacked structure from collapsing during fabrication.

[0124] In some embodiments, the material of the first semiconductor layer 61 includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin and tungsten.

[0125] In some embodiments, the first semiconductor layer 61 may include end faces and side faces, with the source contact region and drain contact region located at least on the end faces, and the channel region located at least on the side faces. Of the two end faces of the first semiconductor layer 61 along the direction parallel to the substrate, one is connected to a capacitor, and the other is connected to a bit line 63. The side faces (channel regions) of the first semiconductor layer are surrounded by a gate 44'.

[0126] In a specific example, the first electrode 51 of the capacitor can be connected to the source contact area of ​​the first semiconductor layer 61 to form a storage node (SN); then the bit line 63 is connected to the drain contact area of ​​the first semiconductor layer 61.

[0127] In some embodiments, the orthographic projections of transistor T and capacitor C onto a two-dimensional plane formed by the second direction (X direction) and the third direction (Y direction) do not overlap.

[0128] In some embodiments, bit line 63 is surrounded by a first semiconductor layer 61.

[0129] The semiconductor devices involved in the embodiments of this disclosure may be memory, such as DRAM, or other memory chips or processing chips containing DRAM memory cells.

[0130] Here, the specific structure and other details of the semiconductor device are similar to those of the semiconductor device obtained by the aforementioned preparation method. For any parts not mentioned, please refer to the above preparation method embodiments, which will not be repeated here.

[0131] This disclosure also provides an electronic device, including the semiconductor device described above or a semiconductor device manufactured according to the semiconductor device fabrication method described above. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0132] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0133] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, comprising: A storage cell array includes multiple layers of storage cells stacked in a first direction; wherein multiple storage cells located in the same layer are arranged in columns in a second direction and in rows in a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; The memory cell includes a transistor; the transistor includes a first semiconductor layer (61) and a gate (44') surrounding a channel region of the first semiconductor layer (61); The first semiconductor layer (61) of the plurality of memory cells arranged along the first direction is an integral structure that is interconnected.

2. The semiconductor device according to claim 1, wherein, Also includes: Bit line (63) extends along the first direction; The plurality of memory cells arranged along the first direction are connected to the same bit line (63), and two adjacent memory cells along the second direction are connected to the same bit line (63); The first semiconductor layer (61) of the memory cell connected to the same bit line (63) is an integral structure that is interconnected and at least partially surrounds the sidewall of the bit line (63).

3. The semiconductor device according to claim 2, wherein, The integrated structure includes a first portion (611) and a second portion (612) alternately arranged along the first direction; the first portion (611) extends along the first direction and surrounds the sidewall of the bit line (63), the second portion (612) extends along the second direction, and the gate (44') surrounds the sidewall of the second portion (612).

4. The semiconductor device according to claim 3, wherein, The second portion (612) has a cylindrical structure with an opening facing the bit line (63), and the semiconductor device further includes a filling layer (62); The filling layer (62) is located inside the cylindrical structure.

5. The semiconductor device according to claim 1, wherein, The gates (44') of multiple memory cells in each row of the same layer are connected by a gate connection structure to form a word line; The gate connection structure includes a metal layer and / or a connection layer.

6. The semiconductor device according to claim 5, wherein, The word line includes the gate (44') and the gate connection structure alternately arranged upwards on the third side; The gate connection structure includes a metal layer or a connection layer extending along the third direction, wherein the two ends of the metal layer or the connection layer along the third direction are in contact with the adjacent gate; or, The gate connection structure includes a connection layer extending along the third direction and a metal layer surrounding the sidewall of the connection layer, wherein both ends of the metal layer and the connection layer along the third direction are in contact with the adjacent gate.

7. The semiconductor device according to claim 3, wherein, The storage cell further includes: a capacitor; the transistors and the capacitors in the same storage cell are arranged along the second direction; The capacitor includes a first electrode plate (51) and a second electrode plate (53); the first electrode plate (51) is connected to one end of the first semiconductor layer, and the first electrode plates (51) in the capacitors of different layers are arranged at intervals in the first direction; the first electrode plate (51) is an annular electrode plate, the second electrode plate (53) is filled in the annular cavity formed by the annular electrode plate, and the multiple memory cells arranged along the first direction share the same second electrode plate (53).

8. The semiconductor device according to claim 7, wherein, The second part (612) is connected to the first part (611) at one end and to the first electrode plate (51) at the other end along the second direction.

9. The semiconductor device according to claim 7, wherein, The capacitor also includes a third plate (54), which is at least partially surrounding the outside of the first plate (51); The plurality of storage cells arranged along the first direction share the same third electrode plate (54), and two adjacent rows of storage cells along the second direction share the same third electrode plate (54).

10. The semiconductor device according to claim 9, wherein, The capacitor further includes a first dielectric layer (52) located between the first electrode (51) and the second electrode (53), and a second dielectric layer (55) located between the first electrode (51) and the third electrode (54); the first dielectric layer (52) and the second dielectric layer (55) are also used to isolate the second electrode (53) and the third electrode (54).

11. The semiconductor device according to claim 1, wherein, The material of the first semiconductor layer (61) includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin and tungsten.

12. The semiconductor device according to claim 5, wherein, The material of the connecting layer includes doped polycrystalline silicon.

13. A method for fabricating a semiconductor device, comprising: A substrate is provided, the substrate including a substrate (1) and a stacked structure (20) formed on the substrate (1), the stacked structure (20) including an alternately disposed first insulating layer (21) and a second insulating layer (22); A first etch trench is formed that penetrates the stacked structure (20) and extends in a third direction, wherein the size of the first etch trench in the first insulating layer (21) is larger than the size in the second insulating layer (22); An initial gate connection structure (41) is formed in the first etched trench; A first hole (34) is formed through the stacked structure (20), and the initial gate connection structure (41) is laterally etched through the first hole (34) to form a second lateral groove (35) located on both sides of the first hole (34); A gate (44') is formed on the inner wall of the second transverse groove (35); A first semiconductor layer (61) is formed on the inner wall of the first hole (34) and the second transverse groove (35); the first semiconductor layer (61) in the second transverse groove (35) and the gate (44') surrounding the first semiconductor layer (61) are used to form a transistor.

14. The preparation method according to claim 13, wherein, Forming a first etch trench that penetrates the stacked structure (20) and extends along the third direction includes: A first trench (31) is formed that penetrates the stacked structure (20) and extends along the third direction. The first insulating layer (21) is laterally etched through the first trench (31) to form a first lateral groove (32) located on both sides of the first trench (31). The first trench (31) and the first lateral groove (32) constitute the first etched trench.

15. The preparation method according to claim 14, wherein, An initial gate connection structure (41) is formed within the first etched trench, including: A metal layer (412) is formed by filling the first transverse groove (32); or, A connecting layer is formed by filling the first transverse groove (32); or, A metal layer is formed on the inner wall of the first transverse groove (32), and a connecting layer is formed by filling it.

16. The preparation method according to claim 14, wherein, Forming a first hole (34) through the stacked structure (20) includes: A first filling structure is formed within the first trench (31); A plurality of first holes (34) are formed within the first filling structure, extending along a first direction and spaced apart along the third direction.

17. The preparation method according to claim 13, wherein, After forming a gate (44') on the inner wall of the second transverse groove (35), the method further includes: A second filling layer (45) is formed to fill the second transverse groove (35).

18. The preparation method according to claim 17, wherein, The method further includes: A second hole (36) is formed on one side of the first hole (34) along the second direction, penetrating the stacked structure (20), and the first insulating layer (21) is laterally etched through the second hole (36) to form a third lateral groove (37); The gate (44') and the second fill layer (45) of the bottom wall of the second lateral groove (35) exposed by the third lateral groove (37) are etched away to make the third lateral groove (37) and the second lateral groove (35) interconnected; A gate dielectric layer (46) is formed through the first hole (34) and the second hole (36) covering the inner walls of the first hole (34), the second lateral groove (35), the second hole (36), and the third lateral groove (37), and a third filling layer (47) filling the first hole (34), the second lateral groove (35), the second hole (36), and the third lateral groove (37).

19. The preparation method according to claim 18, wherein, The method further includes: Remove the third filler layer (47) from the second hole (36) and the third transverse groove (37); A first electrode plate (51) of a capacitor is formed on the inner wall of the third transverse groove (37). A first dielectric layer (52) of the capacitor, which at least covers the first electrode plate (51), is formed in the second hole (36) and the third transverse groove (37), and a second electrode plate (53) of the capacitor is filled in.

20. The preparation method according to claim 19, wherein, The method further includes: A second initial trench is formed along the second direction on the side of the second hole (36) opposite to the first hole (34) that penetrates the stacked structure (20) and extends along the third direction; the stacked structure (20) is laterally etched through the second initial trench to form the second trench (38); The second trench (38) is filled with the third electrode plate (54) forming the capacitor.

21. The preparation method according to claim 20, wherein, Before forming a first semiconductor layer (61) on the inner walls of the first hole (34) and the second transverse groove (35), the method further includes: Remove the third filler layer (47) within the first hole (34) and the second lateral groove (35) to expose the gate dielectric layer (46) within the second lateral groove (35).

22. The preparation method according to claim 21, wherein, The method further includes: A fourth filling layer (62) is formed by filling the first hole (34) and the second transverse groove (35); Replace the fourth filling layer (62) in the first hole (34) with a bit line (63); The bit line (63) is in contact with the first semiconductor layer (61).

23. An electronic device comprising a semiconductor device as described in any one of claims 1 to 12, or a semiconductor device manufactured according to the method of manufacturing a semiconductor device as described in any one of claims 13 to 22.

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