Semiconductor device and manufacturing method therefor, and electronic apparatus

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic apparatus. The semiconductor device comprises a memory cell array, comprising a plurality of layers of memory cells stacked in a first direction, wherein the plurality of memory cells located in the same layer are arranged in columns in a second direction and arranged in rows in a third direction, and the second direction and the third direction intersect and are both perpendicular to the first direction; each memory cell comprises a transistor (T) and a first electrode (51), the transistor (T) comprises a first semiconductor layer (61) and a gate (44') surrounding a channel region of the first semiconductor layer (61), and the first semiconductor layer (61) surrounds an outer side of the first electrode (51).

Description

A semiconductor device and its fabrication method, and an electronic device.

[0001] Cross-reference to related applications

[0002] This disclosure is based on and claims priority to Chinese Patent Application No. 202411858173.7, filed on December 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0004] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0005] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands.

[0006] Application content

[0007] In view of the above, this disclosure provides a semiconductor device and a method for fabricating the same, as well as an electronic device.

[0008] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0009] This disclosure provides a semiconductor device, including: a memory cell array including multiple layers of memory cells stacked in a first direction; wherein, a plurality of memory cells located in the same layer are arranged in columns in a second direction and in rows in a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; the memory cells include transistors and first electrodes; the transistors include a first semiconductor layer and a gate of a channel region surrounding the first semiconductor layer; the first semiconductor layer surrounds the outside of the first electrode.

[0010] This disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate including a base and a stacked structure formed on the base, the stacked structure including a first insulating layer and a second insulating layer alternately disposed along a first direction; forming a first etching trench penetrating the stacked structure and extending along a third direction, the first etching trench having a size in the first insulating layer larger than the size in the second insulating layer; forming an initial gate connection structure within the first etching trench; forming a first hole extending along the first direction within the first etching trench, and laterally etching the initial gate connection structure through the first hole to form a second lateral groove located on both sides of the first hole; forming a gate on the inner wall of the second lateral groove; forming a second hole penetrating the stacked structure on one side of the first hole along a second direction, and laterally etching the first insulating layer through the second hole to form a third lateral groove; the second direction and the third direction intersect and are both perpendicular to the first direction; forming a first semiconductor layer on the inner wall of the first hole, the second lateral groove, and the third lateral groove, and forming a first electrode covering the inner wall of the first semiconductor layer within the third lateral groove.

[0011] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device manufactured according to any of the methods described above for manufacturing semiconductor devices. Attached Figure Description

[0012] Figure 1 is a schematic diagram of the steps of a semiconductor device fabrication method provided in an embodiment of this disclosure;

[0013] Figure 2 is a schematic diagram of the structure of a substrate provided in an embodiment of this disclosure;

[0014] Figures 3 to 8 are schematic diagrams of the process of forming an initial gate connection structure according to an embodiment of the present disclosure; wherein, (a) is a top view and (b) is a cross-sectional view of the structure shown in (a) along line AA;

[0015] Figures 9 to 14 are schematic diagrams of a structure during the formation of a gate according to an embodiment of the present disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and in Figures 11 to 14, (d) is a cross-sectional view of the structure shown in (a) along line CC.

[0016] Figures 15 to 19 are schematic diagrams of the structure during the formation of a first semiconductor layer according to an embodiment of the present disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and (d) is a cross-sectional view of the structure shown in (a) along line CC.

[0017] Figures 20 to 24 are schematic diagrams of a capacitor forming process provided in an embodiment of the present disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and (d) is a cross-sectional view of the structure shown in (a) along line CC.

[0018] Figure 25 is a structural schematic diagram of a bit line formation process provided in an embodiment of the present disclosure, wherein (a) is a top view, (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA, (c) is a cross-sectional schematic diagram of the structure shown in (a) along line BB, and (d) is a cross-sectional schematic diagram of the structure shown in (a) along line CC.

[0019] Figure 26 is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Detailed Implementation

[0020] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0021] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0022] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0024] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0026] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0027] This disclosure provides a semiconductor device, including: a memory cell array including multiple layers of memory cells stacked in a first direction; wherein a plurality of the memory cells located in the same layer are arranged in columns in a second direction and in rows in a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; each memory cell includes a transistor and a first electrode; the transistor includes a first semiconductor layer and a gate of a channel region surrounding the first semiconductor layer; the first semiconductor layer surrounds the outside of the first electrode.

[0028] In this embodiment, the first electrode can be reused as the first electrode of a capacitor. The first semiconductor layer of the transistor surrounds the outside of the first electrode of the capacitor, which increases the contact area between the capacitor electrode and the transistor channel, thereby reducing contact resistance and improving the performance of the capacitor and the transistor. In this embodiment, multiple memory cells can be arranged in a single layer or stacked in multiple layers along a first direction. The memory cells in each layer can be arranged in an array along a second direction and a third direction. The memory cells in the semiconductor device provided in this embodiment can be stacked not only in a direction perpendicular to the substrate but also arranged in an array in a plane parallel to the substrate, which is beneficial for improving the integration density of memory cells.

[0029] Figure 1 is a schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of this disclosure. As shown in Figure 1, the fabrication method includes the following steps:

[0030] Step S101: Provide a substrate, the substrate including a substrate and a stacked structure formed on the substrate, the stacked structure including an alternately arranged first insulating layer and a second insulating layer.

[0031] Step S102: Form a first etch trench that penetrates the stacked structure and extends in a third direction, wherein the size of the first etch trench in the first insulating layer is larger than the size of the second insulating layer.

[0032] Step S103: Form an initial gate connection structure in the first etch trench.

[0033] Step S104: A first hole extending in the first direction is formed in the first etching trench, and the initial gate connection structure is laterally etched through the first hole to form a second lateral groove located on both sides of the first hole.

[0034] Step S105: Form a gate on the inner wall of the second transverse groove.

[0035] Step S106: A second hole is formed through the stacked structure on one side of the first hole along the second direction, and the first insulating layer is laterally etched through the second hole to form a third lateral groove; the second direction and the third direction intersect and are both perpendicular to the first direction.

[0036] Step S107: A first semiconductor layer is formed on the inner wall of the first hole, the second transverse groove and the third transverse groove, and a first electrode covering the inner wall of the first semiconductor layer is formed in the third transverse groove.

[0037] It should be understood that the steps shown in Figure 1 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in the operation.

[0038] In some embodiments, step S102 includes: forming a first trench that penetrates the stacked structure and extends in a third direction; and laterally etching a first insulating layer through the first trench to form first lateral grooves located on both sides of the first trench; the first trench and the first lateral grooves constitute a first etched trench. The size of the first etched trench in the first insulating layer is larger than the size of the first etched trench in the second insulating layer.

[0039] In some embodiments, step S103 includes: filling and forming a metal layer within the first lateral groove; or, filling and forming a connection layer within the first lateral groove; or, forming a metal layer on the inner wall of the first lateral groove and filling and forming a connection layer. In other words, in the embodiments of this disclosure, the initial gate connection structure includes a metal layer; or, the initial gate connection structure includes a connection layer; or, the initial gate connection structure includes both a metal layer and a connection layer. It should be noted that the following description uses an initial gate connection structure including both a metal layer and a connection layer as an example.

[0040] In some embodiments, step S104 includes: forming a first filling structure in a first trench; forming a plurality of first holes extending along a first direction and spaced apart along a third direction in the first filling structure; and laterally etching the initial gate connection structure through the first holes to form second lateral grooves located on both sides of the first holes.

[0041] In some embodiments, step S105 includes: forming a gate covering the bottom wall and sidewalls of the second transverse groove and a second filling layer filling the second transverse groove within the second transverse groove.

[0042] In some embodiments, prior to step S107, the method further includes: etching away the gate and the second fill layer of the bottom wall of the second lateral groove exposed by the third lateral groove, so that the third lateral groove and the second lateral groove are connected.

[0043] In some embodiments, step S107 includes: forming a gate dielectric layer and an initial first semiconductor layer covering the inner walls of the first hole, the second lateral groove, the second hole, and the third lateral groove through the first hole and the second hole, and filling the first hole, the second lateral groove, the second hole, and the third lateral groove with a third filling layer; removing the initial first semiconductor layer and the third filling layer in the second hole; removing the third filling layer in the third lateral groove; and using the remaining initial first semiconductor layer in the first hole, the second lateral groove, and the third lateral groove as the first semiconductor layer.

[0044] In some embodiments, the method further includes: forming a first dielectric layer of the capacitor that at least covers the first electrode within the second hole and the third transverse groove, and filling the second electrode plate forming the capacitor.

[0045] In some embodiments, the method further includes: forming a second initial trench that extends through the stacked structure and along a third direction; laterally etching the stacked structure through the second initial trench to form the second trench; and filling the second trench with a third electrode plate forming a capacitor.

[0046] In some embodiments, the method further includes: replacing a third filling layer in the first hole with a bit line; the bit line is in contact with the first semiconductor layer.

[0047] Figures 2, 3 to 8, 9 to 14, 15 to 19, 20 to 24, and 25 are schematic diagrams of the semiconductor device structure at various stages in the fabrication method of the semiconductor device provided in the embodiments of this disclosure. It should be noted that Figures 2, 3 to 8, 9 to 14, 15 to 19, 20 to 24, and 25 constitute a complete schematic diagram reflecting the implementation process of the semiconductor device fabrication method, and parts not marked in some of the figures can be shared with each other. The fabrication method of the semiconductor device provided in the embodiments of this disclosure will be described in detail below with reference to Figures 1, 2 to 25.

[0048] It should be noted that, for ease of description, the various directions that may be used in the following description are first defined. A first direction (Z direction) is defined in a plane perpendicular to the substrate, and a second direction (X direction) and a third direction (Y direction) are defined in a plane parallel to the substrate. The X, Y, and Z directions can be mutually perpendicular. The third direction (Y direction) is the extension direction of the word line, and the first direction (Z direction) is the extension direction of the bit line.

[0049] The deposition processes involved in the embodiments of this disclosure include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0050] The etching processes involved in the embodiments of this disclosure include, but are not limited to, dry etching, wet etching, and combinations thereof.

[0051] The "patterning process" involved in the embodiments of this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. Deposition can be performed using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be performed using known coating processes; and etching can be performed using known methods. No specific limitations are made here.

[0052] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may be a memory, such as Dynamic Random Access Memory (DRAM), or other memory chips or processing chips that contain DRAM memory cells.

[0053] Figure 2 is a schematic diagram of the substrate structure provided in an embodiment of this disclosure. Referring to Figure 2, a substrate 1 is provided, and a first insulating layer 21 and a second insulating layer 22 are alternately stacked on the substrate 1 by a deposition process to form a stacked structure 20. Exemplarily, the first insulating layer 21 and the second insulating layer 22 may have the same thickness or different thicknesses, and neither of them is zero. The first insulating layer 21 may be formed of silicon nitride, and the second insulating layer 22 may be formed of silicon oxide, such that the stacked structure 20 is a nitride-oxide (NO) stack. It should be noted that the number of layers of the first insulating layer 21 and the second insulating layer 22 in the stacked structure 20 shown in Figure 2 is only an example, and the specific number of layers of the first insulating layer 21 and the second insulating layer 22 in this disclosure is not limited to the number of layers shown in the figure.

[0054] In some embodiments, after the stacked structure 20 is formed on the substrate 1, a hard mask layer 23 can be deposited on the top surface of the stacked structure 20 away from the substrate 1 by a deposition process. The hard mask layer 23 is used for subsequent patterning processes of the stacked structure 20. Exemplarily, the material of the hard mask layer 23 may include oxides and / or amorphous carbon, and the thickness of the hard mask layer 23 is approximately 50 nm to 400 nm.

[0055] In some embodiments, to avoid electrical connections between multiple rows of memory cells via the substrate 1, at least one insulating layer 24 may be included between the substrate 1 and the stacked structure 20. The material of the insulating layer 24 is an insulating material. For example, the insulating layer 24 between the substrate 1 and the stacked structure 20 may be a second insulating layer. It should be noted that, in the embodiments of this disclosure, identical structures located in the same layer (or in the same stacked layer) and arranged along a third direction (Y direction) are called rows, and identical structures arranged along a second direction (X direction) are called columns. For example, memory cells arranged along a third direction (Y direction) and located in the same layer are called a row of memory cells or a row of memory cells, and memory cells arranged along the second direction (X direction) are called a column of memory cells or a column of memory cells.

[0056] This disclosure does not specifically limit the constituent materials of substrate 1. As an example, substrate 1 can be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, the substrate can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0057] The insulating and dielectric materials involved in this disclosure can all be insulating materials with high dielectric constant (High-K, HK), such as dielectric materials with a dielectric constant K greater than or equal to 3.9. These include, but are not limited to, HK materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2); the conductive materials can be materials containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; the semiconductor materials can be at least one of monocrystalline silicon, amorphous silicon, polycrystalline silicon, or doped polycrystalline silicon, and the semiconductor materials can also be metal oxide semiconductors.

[0058] The material of the gate dielectric layer involved in this disclosure can be selected from one or more of silicon oxide (e.g., SiO2), hafnium oxide (e.g., HfO2), zirconium oxide (e.g., ZrO), and aluminum oxide (e.g., Al2O3). The gate dielectric layer can be a single-layer structure or a multi-layer structure; for example, it can include a two-layer structure formed of silicon oxide and hafnium oxide, wherein the silicon oxide layer contacts the channel region, and the hafnium oxide layer contacts the gate. The thickness of the gate dielectric layer can be set according to actual electrical requirements, for example, it can be from 2 nm to 5 nm.

[0059] Figures 3 to 8 are cross-sectional schematic diagrams illustrating the process of forming an initial gate connection structure according to an embodiment of this disclosure; wherein, (a) is a top view, and (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA. The formation process of the initial gate connection structure will be described in detail below with reference to the accompanying drawings. Referring to Figure 3, a patterned photoresist layer 25 is formed on the hard mask layer 23. The patterned photoresist layer 25 is used to etch the hard mask layer 23 and the stacked structure 20 to form a first trench 31 that penetrates the stacked structure 20 and extends along a third direction. The patterned photoresist layer 25 can be removed after the first trench is formed. It should be noted that the number of first trenches shown in Figure 3 is only an example, and this disclosure does not limit the number of first trenches.

[0060] Referring to Figure 4, the first insulating layer 21 is laterally etched through the first trench 31 to form first lateral grooves 32 located on both sides of the first trench 31. The first trench 31 and the first lateral grooves 32 constitute the first etched trench. At this time, the size of the first etched trench in the first insulating layer is larger than the size of the first etched trench in the second insulating layer. Here, the first lateral grooves 32 are used to define the word line formation area, which includes the gate and the gate connection structure, wherein the gate connection structure and the gate are formed in different process steps. Since the first trench 31 extends along the third direction (Y direction), the first lateral grooves 32 also extend along the third direction (Y direction), and the first lateral grooves 32 of different layers are isolated by the second insulating layer 22.

[0061] In some embodiments, a metal layer 411 is formed on the inner wall of the first lateral groove 32, and a connection layer 412 is formed therein. This includes: depositing an initial metal layer on the inner wall of the first trench 31 and the first lateral groove 32, and filling the first trench 31 and the first lateral groove 32 with an initial connection layer; etching away the initial connection layer and the initial metal layer in the first trench 31, leaving the remaining initial metal layer on the inner wall of the first lateral groove 32 as the metal layer 411, and leaving the remaining initial connection layer in the first lateral groove 32 as the connection layer 412. At this time, the metal layer and the connection layer in the first lateral groove constitute an initial gate connection structure.

[0062] In this embodiment of the disclosure, the constituent material of the metal layer may include a metal element; such as tungsten or copper (Cu).

[0063] In this embodiment of the disclosure, the material of the connecting layer is doped polycrystalline silicon.

[0064] In other embodiments, filling the first lateral groove with a metal layer includes: filling the first trench and the first lateral groove with metal material, replacing the metal material in the first trench with dielectric material, the dielectric material in the first trench forming a word line isolation structure, and the metal material in the first lateral groove forming a metal layer. In this case, the metal layer in the first lateral groove constitutes the initial gate connection structure.

[0065] In other embodiments, a connection layer is formed within the first lateral groove, comprising: filling the first trench and the first lateral groove with doped semiconductor material; replacing the doped semiconductor material in the first trench with dielectric material; the dielectric material in the first trench forming a word line isolation structure; and the doped semiconductor material in the first lateral groove forming a connection layer. In this case, the connection layer in the first lateral groove constitutes an initial gate connection structure.

[0066] Referring to FIG5, an initial metal layer 411' is deposited and formed on the inner wall of the first trench 31 and the first transverse groove 32, and an initial bonding layer 412' is formed by filling the first trench 31 and the first transverse groove 32. In some embodiments, the initial metal layer 411' may be a thin film covering the inner wall of the first trench 31 and the first transverse groove 32.

[0067] Referring to Figure 6, the initial interconnect layer 412' within the first trench 31 is etched away.

[0068] Referring to FIG7, the initial metal layer 411' within the first trench 31 is etched away. The remaining initial metal layer on the inner wall of the first lateral groove 32 serves as the metal layer 411, and the remaining initial interconnect layer within the first lateral groove 32 serves as the interconnect layer 412. In the structure shown in FIG7, the initial gate interconnect structure 41 includes the metal layer 411 and the interconnect layer 412. Here, the initial gate interconnect structure 41 is subsequently used to form the gate interconnect structure.

[0069] Referring to Figure 8, the first groove 31 is filled to form a word line isolation structure 42.

[0070] Figures 9 to 14 are schematic diagrams of a gate formation process according to an embodiment of the present disclosure. Figure (a) is a top view, Figure (b) is a cross-sectional view of the structure shown in Figure (a) along line AA, Figure (c) is a cross-sectional view of the structure shown in Figure (a) along line BB, and in Figures 11 to 14, Figure (d) is a cross-sectional view of the structure shown in Figure (a) along line CC. The gate formation process will now be described in detail with reference to the accompanying drawings. Referring to Figure 9, forming a first filling structure in a first trench includes: patterning a word line isolation structure 42 using a patterning process to form a first initial hole within the word line isolation structure 42, the first initial hole being arranged along a third direction within the word line isolation structure 42; filling the first initial hole with sacrificial material to form a sacrificial structure 43, the remaining word line isolation structure 42 and sacrificial structure 43 in the first trench constituting the first filling structure. Here, the sacrificial material can be the same as the material of the interconnect layer.

[0071] Referring to Figure 10, forming a first hole within a first filling structure includes: patterning a sacrificial structure 43 in the first filling structure using a patterning process to form a first hole 34 within the sacrificial structure 43.

[0072] In some embodiments, the first holes 34 are arranged in an array in the stacked structure, specifically including a plurality of first holes 34 arranged along a second direction (X direction) and a plurality of first holes 34 arranged along a third direction (Y direction). It should be noted that the number of first holes 34 shown in FIG10 is only an example, and the number of first holes 34 in this disclosure is not limited to the number shown in FIG10.

[0073] Referring to Figure 11, the initial gate connection structure 41 is laterally etched through the first hole 34 to form second lateral grooves 35 located on both sides of the first hole 34. The first hole 34 and the second lateral grooves 35 are used to define the transistor formation region, wherein the second lateral groove 35 is used to define the transistor channel region and the gate formation region.

[0074] Here, when the initial gate connection structure 41 is laterally etched through the first hole 34 to form the second lateral groove 35, the first insulating layer 21 serves as an etching stop layer. Therefore, the dimension of the second lateral groove along the second direction (X direction) is the same as the dimension of the first lateral groove along the second direction (X direction). Thus, the initial gate connection structure can be isolated by the second lateral groove. The initial gate connection structure isolated by the second lateral groove is the gate connection structure 41'.

[0075] Referring to Figure 12, an initial gate layer 44 is deposited on the inner walls of the first hole 34 and the second lateral groove 35, and a filler material is deposited within the first hole 34 and the second lateral groove 35. Here, the filler material can be a dielectric material.

[0076] In some embodiments, the initial gate layer 44 may be a thin film covering the inner walls of the first hole 34 and the second lateral groove 35. In embodiments of this disclosure, the material of the initial gate layer 44 is a conductive material.

[0077] Referring to Figure 13, after removing the initial gate layer 44 and the filler material within the first hole 34, the remaining initial gate layer 44 on the bottom and sidewalls of the second lateral groove 35 forms the gate 44'. Here, the filler material can be a dielectric material. It should be noted that the bottom wall of the second lateral groove refers to the bottom wall of the second lateral groove in the second direction (X direction) that exposes the first insulating layer, and the sidewalls of the second lateral groove refer to the four sides of the second lateral groove in the first direction (Z direction) and the third direction (Y direction). The bottom wall and sidewalls of the second lateral groove constitute the inner wall of the second lateral groove.

[0078] In some embodiments, the word line includes alternating gates 44' in a third-direction orientation and a gate connection structure 41' connecting adjacent gates 44', the gate connection structure 41' extending in a third-direction orientation and contacting the adjacent gate 44'. In embodiments of this disclosure, the material of the metal layer in the gate connection structure and the material of the gate 44' may be the same or different.

[0079] Referring to Figure 14, a filler material is deposited in the first hole 34, and the filler material in the first hole 34 and the remaining filler material in the second transverse groove 35 form a second filler layer 45. Here, the filler material can be a dielectric material.

[0080] Figures 15 to 19 are schematic diagrams of the structure during the formation of a first semiconductor layer according to an embodiment of the present disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and (d) is a cross-sectional view of the structure shown in (a) along line CC. The formation process of the first semiconductor layer is described in detail below with reference to the accompanying drawings. Referring to Figure 15, a second hole 36 is formed through the stacked structure 20 on one side of the first hole 34 along the second direction X. The first insulating layer 21 is laterally etched through the second hole 36 to expose the gate, thereby forming a third lateral groove 37; the gate 44' exposed by the third lateral groove 37 is etched away. That is, the gate 44' of the bottom wall of the second lateral groove is etched away. The gate of the side wall of the second lateral groove is the final gate. In some embodiments, the second hole is located on both sides of the transistor formation region along the second direction (X direction). Here, the second hole 36 and the third transverse groove 37 are used to define the forming area of ​​the capacitor, wherein the third transverse groove 37 is used to define the forming area of ​​the first plate of the capacitor.

[0081] In some embodiments, the second holes 36 are arranged in an array in the stacked structure, specifically including a plurality of second holes 36 arranged along a second direction (X direction) and a plurality of second holes 36 arranged along a third direction (Y direction). It should be noted that the number of second holes 36 shown in FIG15 is only an example, and the number of second holes 36 in this disclosure is not limited to the number shown in FIG15.

[0082] Referring to Figure 16, the second filling layer 45 within the second transverse groove 35 and the filling material within the first hole 34 are etched away. At this time, the third transverse groove 37 and the second transverse groove 35 are connected, thereby connecting the first hole 34 and the second hole 36. In some embodiments, the second holes 36 are located on both sides of the first holes 34 along the second direction (X direction), and there are two second holes 36 between two adjacent first holes 34 along the second direction (X direction).

[0083] Referring to FIG17, a gate dielectric layer 46 and an initial first semiconductor layer 61' are deposited through the first hole 34 and the second hole 36 to cover the inner walls of the first hole 34, the second lateral groove 35, the second hole 36 and the third lateral groove 37, and a third filling layer 47 is deposited to fill the first hole 34, the second lateral groove 35, the second hole 36 and the third lateral groove 37.

[0084] Referring to Figure 18, the initial first semiconductor layer 61' and the third filling layer 47 within the second hole 36 are etched away. At this time, the remaining initial first semiconductor layer 61' on the inner walls of the first hole 34, the second lateral groove 35, and the third lateral groove 37 serves as the first semiconductor layer 61.

[0085] In some embodiments, the first semiconductor layers 61 of a plurality of memory cells arranged along a first direction are interconnected to form an integral structure. Furthermore, since the initial first semiconductor layer 61' within the second hole 36 is removed, the first semiconductor layers 61 of the plurality of memory cells arranged along the first direction are disconnected in the region near the capacitor and connected in the region near the bit line.

[0086] Referring to Figure 19, the third filling layer 47 within the third transverse groove 37 is etched away.

[0087] In this embodiment of the disclosure, the first semiconductor layer 61 and the gate 44' of the channel region surrounding the first semiconductor layer are used to form a transistor.

[0088] In some embodiments, the first semiconductor layer 61 is a thin film covering the inner walls of the first hole 34 and the second lateral groove 35. This avoids the first semiconductor layer 61 from being too large, thereby improving the channel performance of the transistor.

[0089] In this embodiment, the transistor employs a gate-around structure (the gate surrounds the channel region) to achieve better switching control of the channel. Furthermore, the gate connection structure and the gate-around structure together form word lines, which further reduces the RC delay between word lines, improves the device response rate, and thus enhances the overall performance of the device.

[0090] In some embodiments, the material of the first semiconductor layer 61 includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten. The metal oxide semiconductor may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain other small amounts of doping elements. Furthermore, compared to other semiconductor materials, using metal oxide semiconductors allows for better control of the manufacturing cost of semiconductor devices.

[0091] In some embodiments, the metal-oxide semiconductor material can be indium gallium zinc oxide (IGZO). When the metal-oxide material is IGZO, the transistor has a smaller leakage current (leaking current less than or equal to 10). -15A), which ensures a low refresh rate for the storage unit. It should be noted that the metal oxide material can also be ITO or InSnOx (Indium Tin Oxide), IWO or InWO (Indium Tungsten Oxide), ZnOx (Zinc Oxide), InOx (Indium Oxide), In2O3 (Indium Oxide), SnO2 (Tin Dioxide), TiOx (Tin Dioxide), ZnxOyNz (Zinc Nitride Oxide), MgxZnyOz (Magnesium Zinc Oxide), InxZnyOz (Indium Zinc Oxide), InxGayZnzOa (Indium Gallium Zinc Oxide), ZrxInyZnzOa (Zirconium Indium Zinc Oxide), HfxInyZnzOa (Hafnium Indium Zinc Oxide). Indium Zinc Oxide, SnxInyZnzOa (Tin Indium Zinc Oxide), AlxSnyInzZnaOd (Aluminum Tin Indium Zinc Oxide), SixInyZnzOa (Silicon Indium Zinc Oxide), ZnxSnyOz (Zinc Tin Oxide), AlxZnySnzOa (Aluminum Indium Tin Oxide), GaxZnySnzOa (Gallium Indium Tin Oxide), ZrxZnySnzOa (Zirconium Indium Tin Oxide), InGaSiO (Indium Gallium Silicon Oxide), IAZO (Indium Aluminum Zinc Oxide), IGO (Indium Gallium Oxide). Materials such as indium gallium oxide (IGAO), indium zinc oxide (IZO), and indium zinc oxide (IZOx) are acceptable, as long as the leakage current of the transistor meets the requirements. The specific requirements can be adjusted according to the actual situation.

[0092] Figures 20 to 24 are schematic diagrams of the structure during the formation of a capacitor according to an embodiment of the present disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and (d) is a cross-sectional view of the structure shown in (a) along line CC. The formation process of the capacitor will now be described in detail with reference to the accompanying drawings. Referring to Figure 20, a first electrode layer 51' is deposited and formed on the inner wall of the second hole 36 and the third transverse groove 37, and a filling material is deposited in the second hole 36 and the third transverse groove 37.

[0093] Referring to FIG21, the filling material in the second hole 36 is etched away to expose the first electrode layer 51' on the inner wall of the second hole 36. After the first electrode layer 51' on the inner wall of the second hole 36 is etched away, the remaining first electrode layer 51' in the third transverse groove 37 forms the first electrode 51. In the embodiment of this disclosure, the first electrode 51 is reused as the first plate of a capacitor.

[0094] Referring to Figure 22, the filling material in the third lateral groove 37 is etched away, and a first dielectric layer 52 covering at least the first electrode 51 is deposited through the second hole 36, forming a second electrode plate 53 that fills the second hole 36 and the third lateral groove 37. The single-layer capacitor 50 includes a first electrode 51, a first dielectric layer 52, and a second electrode plate 53.

[0095] In some embodiments, the first plates of the capacitors of different layers are arranged at intervals in a first direction (Z direction); the first plate is an annular plate, and the second plate fills the annular cavity formed by the annular plate. The second plate can be a cavity structure or a solid structure.

[0096] In some embodiments, the end of the second electrode extends along a first direction (Z direction) and a second direction (X direction). The second electrodes of a plurality of capacitors arranged along the first direction (Z direction) are connected to form an integral structure.

[0097] Referring to Figure 23, a second initial trench is formed that penetrates the stacked structure and extends along a third direction (Y direction). The second initial trench is located between two adjacent monolayer capacitors 50 along the second direction (X direction). The stacked structure 20 is laterally etched through the second initial trench to form a second trench 38. Here, the size of the second trench 38 in the stacked structure 20 is larger than the minimum distance between two adjacent monolayer capacitors 50 along the second direction (X direction) and smaller than the maximum distance between two adjacent monolayer capacitors 50 along the second direction (X direction).

[0098] Referring to Figure 24, a third electrode 54 forming a capacitor is filled in the second trench 38. The third electrodes of a plurality of capacitors arranged along a first direction and the third electrodes of two adjacent rows of capacitors along a second direction are connected to form an integral structure. The third electrode 54 at least partially surrounds the outside of the first electrode 51; a plurality of single-layer capacitors 50 arranged along the first direction (Z direction) share the same third electrode 54, and two adjacent rows of single-layer capacitors 50 along the second direction (X direction) also share the same third electrode 54. In this embodiment, the second electrode 53 and the third electrode 54 are respectively disposed on the inner and outer sides of the first electrode 51, thereby forming a double-layer capacitor with two adjacent single-layer capacitors 50 and the third electrode 54. Compared to a single-layer capacitor with only two electrodes, the double-layer capacitor occupies a smaller area and has a shorter length for the same capacitance, which helps to reduce the size of the semiconductor device and also prevents the stacked structure from collapsing during fabrication.

[0099] It should be noted that the gate dielectric layer 46 between the first electrode 51 and the third electrode 54 can be reused as the second dielectric layer between the first electrode 51 and the third electrode 54, and the gate dielectric layer 46 and the first dielectric layer 52 between the second electrode 53 and the third electrode 54 are also used to isolate the second electrode 53 and the third electrode 54.

[0100] In some embodiments, the gate dielectric layer 46 surrounds the outside of the first semiconductor layer 61 and is located between the first semiconductor layer 61 and the third electrode 54.

[0101] In other embodiments, when the stacked structure is laterally etched through the second initial trench to form the second trench, the exposed gate dielectric layer after the stacked structure is further etched away. Therefore, before filling the second trench to form the third electrode plate, a dielectric film needs to be formed within the second trench to isolate the first electrode plate from the subsequently formed third electrode plate.

[0102] Figure 25 is a schematic diagram of the structure during the formation of a bit line according to an embodiment of this disclosure, wherein (a) is a top view, (b) is a cross-sectional view of the structure shown in (a) along line AA, (c) is a cross-sectional view of the structure shown in (a) along line BB, and (d) is a cross-sectional view of the structure shown in (a) along line CC. The bit line formation process will now be described in detail with reference to the accompanying drawings. Referring to Figure 25, the third filling layer 47 in the first hole 34 is replaced with a bit line 62; the bit line 62 is in contact with the first semiconductor layer 61. Specifically, the fourth filling layer in the first hole is etched away, and a conductive material is filled into the first hole to form a bit line. This disclosure does not specifically limit the constituent materials of the bit line. As an example, the constituent materials of the bit line may include, but are not limited to, materials containing titanium or tungsten.

[0103] In some embodiments, by setting the bit line 62 to extend along a first direction (Z direction) and two adjacent memory cells along a second direction (X direction) to be connected to the same bit line, there is at least a pair of transistors and a pair of capacitors between the two adjacent bit lines 62 along the second direction (X direction). Based on this, the bit line spacing is greatly increased, the coupling between the bit lines is reduced, the bit line capacitance is effectively reduced, and the process complexity is reduced.

[0104] In some embodiments, a transistor and a capacitor constitute a memory cell. A bit line extends along a first direction, and a plurality of memory cells arranged along the first direction are connected to the same bit line, and two adjacent memory cells along a second direction are connected to the same bit line; the first semiconductor layer of the memory cells connected to the same bit line can be an integral structure interconnected with each other.

[0105] Figure 26 is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present disclosure. As shown in Figure 26, the semiconductor device includes: a memory cell array, including multiple layers of memory cells stacked in a first direction; wherein, multiple memory cells located in the same layer are arranged in columns in a second direction and in rows in a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; the memory cell includes a transistor T and a first electrode 51; the transistor T includes a first semiconductor layer 61 and a gate 44' of a channel region surrounding the first semiconductor layer 61; the first semiconductor layer 61 surrounds the outside of the first electrode 51.

[0106] In this embodiment, the transistor employs a gate-around structure (the gate surrounds the channel region) to achieve better switching control of the channel. Furthermore, the gate connection structure and the gate-around structure together form word lines, which further reduces the RC delay between word lines, improves the device response rate, and thus enhances the overall performance of the device.

[0107] In some embodiments, the memory cell further includes a capacitor C; the transistor T and capacitor C of the same memory cell are arranged along a second direction.

[0108] In some embodiments, the semiconductor device further includes: a bit line 62 extending along a first direction; a plurality of memory cells arranged along the first direction connected to the same bit line 62, and two adjacent memory cells along a second direction connected to the same bit line 62; and a first semiconductor layer 61 of the memory cells connected to the same bit line 62 interconnected and at least partially surrounding the sidewall of the bit line 62.

[0109] In this embodiment of the disclosure, by setting the bit line 62 to extend along the first direction (Z direction) and two adjacent memory cells along the second direction (X direction) to be connected to the same bit line, there is at least a pair of transistors and a pair of capacitors between the two adjacent bit lines 62 along the second direction (X direction). Based on this, the bit line spacing is greatly increased, the coupling between the bit lines is reduced, the bit line capacitance is effectively reduced, and the process complexity is reduced.

[0110] In some embodiments, the first semiconductor layers 61 of memory cells connected to the same bit line 62 can be interconnected to form an integral structure; the integral structure includes a first portion and a second portion alternately arranged along a first direction; the first portion extends along the first direction and surrounds the sidewall of the bit line 62, and the second portion extends along a second direction and has a cylindrical structure with an opening facing the bit line 62; the portion of the sidewall of the cylindrical structure near the bit line 62 is surrounded by a gate 44', and the portion of the sidewall away from the bit line 62 surrounds the first electrode 51; a filling layer is provided in the region of the cylindrical structure near the bit line 62.

[0111] In some embodiments, the gates 44' of multiple memory cells in each row of the same layer are connected by a gate connection structure to form a word line; the gate connection structure includes a metal layer and / or a connection layer.

[0112] In some embodiments, the word line includes alternating gates 44' in the third direction and a gate connection structure connecting adjacent gates 44'. The gate connection structure includes a metal layer or a connection layer extending in the third direction, with both ends of the metal layer or connection layer contacting adjacent gates in the third direction; or, the gate connection structure includes a connection layer extending in the third direction and a metal layer surrounding the sidewall of the connection layer, with both ends of the metal layer and the connection layer contacting adjacent gates in the third direction.

[0113] In some embodiments, the first electrode 51 is reused as the first plate of the capacitor C.

[0114] In some embodiments, the first electrodes 51 in the storage cells of different layers are arranged at intervals in a first direction; the first electrode 51 is an annular plate, the capacitor C includes a second plate 53, the second plate 53 is filled in the annular cavity formed by the annular plate, and the second plates 53 of the multiple capacitors arranged in the first direction are connected to form an integral structure.

[0115] In some embodiments, capacitor C further includes a third electrode plate 54, which at least partially surrounds the outside of the first electrode 51; the third electrodes 54 of a plurality of capacitors arranged along a first direction and the third electrodes 54 of two adjacent rows of capacitors arranged along a second direction are connected to form an integral structure. In other words, a plurality of memory cells arranged along the first direction share the same third electrode plate 54, and two adjacent rows of memory cells arranged along the second direction share the same third electrode plate 54.

[0116] In some embodiments, capacitor C further includes a first dielectric layer 52 located between the first electrode 51 and the second electrode 53, and a second dielectric layer located between the first electrode 51 and the third electrode 54; the first dielectric layer and the second dielectric layer are also used to isolate the second electrode 53 and the third electrode 54. It should be noted that the gate dielectric layer 46 between the first electrode 51 and the third electrode 54 can be reused as the second dielectric layer between the first electrode 51 and the third electrode 54.

[0117] In this embodiment, the second electrode 53 and the third electrode 54 are respectively disposed on the inner and outer sides of the first electrode 51, thereby forming a capacitor with two layers. Compared with a single-layer capacitor with only two electrodes, the double-layer capacitor occupies a smaller area and has a shorter length for the same capacitance, which is beneficial for reducing the size of semiconductor devices and preventing the stacked structure from collapsing.

[0118] In some embodiments, the first semiconductor layer 61 is also located between the third electrode 54 and the first electrode 51; the second dielectric layer 55 is located between the first semiconductor layer 61 and the third electrode 54.

[0119] In some embodiments, transistor T further includes a gate dielectric layer 46 located between gate 44' and first semiconductor layer 61, gate dielectric layer 46 surrounding the outside of first semiconductor layer 61, and gate dielectric layer 46 located between first semiconductor layer 61 and third electrode 54.

[0120] In some embodiments, the material of the first semiconductor layer 61 includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin and tungsten.

[0121] In some embodiments, the material of the interconnect layer includes doped polycrystalline silicon.

[0122] In some embodiments, the first semiconductor layer 61 may include end faces and side faces, with the source contact region and drain contact region located at least on the end faces, and the channel region located at least on the side faces. Of the two end faces of the first semiconductor layer 61 parallel to the substrate direction, one is connected to a capacitor, and the other is connected to a bit line 62. The side faces (channel regions) of the first semiconductor layer are surrounded by a gate 44'. In a specific example, the region of the first semiconductor layer 61 that contacts the first plate of the capacitor is the source contact region, and the region of the first semiconductor layer 61 that contacts the bit line is the drain contact region.

[0123] In a specific example, the first plate of the capacitor can be connected to the source contact area of ​​the first semiconductor layer 61 to form a storage node (SN); then the bit line 62 is connected to the drain contact area of ​​the first semiconductor layer 61.

[0124] In some embodiments, the orthographic projections of transistor T and capacitor C onto a two-dimensional plane formed by the second direction (X direction) and the third direction (Y direction) overlap. Specifically, the orthographic projections of the first semiconductor layer 61 of transistor T and the first electrode 51 of capacitor C onto a two-dimensional plane formed by the second direction (X direction) and the third direction (Y direction) overlap.

[0125] In some embodiments, bit line 62 is surrounded by a first semiconductor layer 61.

[0126] The semiconductor devices involved in the embodiments of this disclosure may be memory, such as DRAM, or other memory chips or processing chips containing DRAM memory cells.

[0127] Here, the specific structure and other details of the semiconductor device are similar to those of the semiconductor device obtained by the aforementioned preparation method. For any parts not mentioned, please refer to the above preparation method embodiments, which will not be repeated here.

[0128] This disclosure also provides an electronic device, including the semiconductor device described above, or a semiconductor device manufactured according to the method described above. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0129] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0130] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, comprising: A memory cell array includes multiple layers of memory cells stacked in a first direction; wherein multiple memory cells located in the same layer are arranged in columns in a second direction and in rows in a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; the memory cell includes a transistor and a first electrode (51); The transistor includes a first semiconductor layer (61) and a gate (44') surrounding a channel region of the first semiconductor layer (61); The first semiconductor layer (61) surrounds the outside of the first electrode (51).

2. The semiconductor device of claim 1, wherein, The gates (44') of multiple memory cells in each row of the same layer are connected by a gate connection structure to form a word line; The gate connection structure includes a metal layer and / or a connection layer.

3. The semiconductor device of claim 2, wherein, The word line includes the gate (44') and the gate connection structure alternately arranged upwards on the third side; The gate connection structure includes a metal layer or a connection layer extending along the third direction, wherein the two ends of the metal layer or the connection layer along the third direction are in contact with the adjacent gate (44'); or, The gate connection structure includes a connection layer extending along the third direction and a metal layer surrounding the sidewall of the connection layer, wherein both ends of the metal layer and the connection layer along the third direction are in contact with the adjacent gate (44').

4. The semiconductor device of claim 1, wherein, The storage cell further includes: a capacitor; the transistors and the capacitors in the same storage cell are arranged along the second direction; The first electrodes (51) in the storage cells of different layers are arranged at intervals in the first direction, and the first electrodes (51) are annular plates; The capacitor includes a second electrode plate (53), which is filled in the annular cavity formed by the annular electrode plate. The second electrodes plate (53) of a plurality of capacitors arranged along the first direction are connected to form an integral structure.

5. The semiconductor device of claim 4, wherein, The capacitor also includes a third electrode plate (54), which is at least partially surrounding the outside of the first electrode (51); The third plates (54) of a plurality of capacitors arranged along the first direction and the third plates (54) of two adjacent rows of capacitors along the second direction are connected to form an integral structure.

6. The semiconductor device according to claim 5, wherein, The capacitor further includes a first dielectric layer (52) located between the first electrode (51) and the second electrode (53), and a second dielectric layer (55) located between the first electrode (51) and the third electrode (54); the first dielectric layer (52) and the second dielectric layer (55) are also used to isolate the second electrode (53) and the third electrode (54).

7. The semiconductor device according to claim 6, wherein, The first semiconductor layer (61) is also located between the third electrode plate (54) and the first electrode (51); the second dielectric layer (55) is located between the first semiconductor layer and the third electrode plate.

8. The semiconductor device according to claim 5, wherein, The transistor further includes a gate dielectric layer (46) located between the gate (44') and the first semiconductor layer (61), the gate dielectric layer (46) surrounding the outside of the first semiconductor layer (61), and the gate dielectric layer (61) located between the first semiconductor layer (61) and the third electrode (54).

9. The semiconductor device according to claim 1, wherein, Bit line (62) extends along the first direction; a plurality of memory cells arranged along the first direction are connected to the same bit line (62), and two adjacent memory cells along the second direction are connected to the same bit line (62).

10. The semiconductor device according to claim 9, wherein, The first semiconductor layers (61) of the memory cells connected to the same bit line (62) are interconnected to form an integral structure; The integrated structure includes a first part and a second part that are alternately arranged along the first direction; the first part extends along the first direction and surrounds the sidewall of the bit line (62), and the second part extends along the second direction and has a cylindrical structure with an opening facing the bit line (62); The cylindrical structure is surrounded by the gate on a portion of its sidewalls near the bit line (62), and surrounded by the first electrode (51) on a portion of its sidewalls away from the bit line (62); a filling layer is provided in the region of the cylindrical structure near the bit line (62).

11. The semiconductor device according to claim 1, wherein, The material of the first semiconductor layer (61) includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin and tungsten.

12. The semiconductor device according to claim 2, wherein, The material of the connecting layer includes doped polycrystalline silicon.

13. A method for fabricating a semiconductor device, comprising: A substrate is provided, the substrate including a substrate (1) and a stacked structure (20) formed on the substrate (1), the stacked structure (20) including a first insulating layer (21) and a second insulating layer (22) alternately disposed along a first direction; A first etch trench is formed that penetrates the stacked structure (20) and extends in a third direction, wherein the size of the first etch trench in the first insulating layer (21) is larger than the size in the second insulating layer (22); An initial gate connection structure (41) is formed in the first etched trench; A first hole (34) extending along the first direction is formed in the first etch trench, and the initial gate connection structure (41) is laterally etched through the first hole (34) to form a second lateral groove (35) located on both sides of the first hole (34). A gate (44') is formed on the inner wall of the second transverse groove (35); A second hole (36) is formed on one side of the first hole (34) along the second direction, penetrating the stacked structure (20), and the first insulating layer (21) is laterally etched through the second hole to form a third lateral groove (37); the second direction and the third direction intersect and are both perpendicular to the first direction; A first semiconductor layer (61) is formed on the inner wall of the first hole (34), the second transverse groove (35) and the third transverse groove (37), and a first electrode (51) covering the inner wall of the first semiconductor layer (61) is formed in the third transverse groove (37).

14. The preparation method according to claim 13, wherein, Forming a first etch trench that penetrates the stacked structure (20) and extends along a third direction includes: forming a first trench (31) that penetrates the stacked structure (20) and extends along a third direction; laterally etching the first insulating layer (21) through the first trench (31) to form a first lateral groove (32) located on both sides of the first trench (31); the first trench (31) and the first lateral groove (32) constitute the first etch trench.

15. The preparation method according to claim 14, wherein, Forming an initial gate connection structure (41) within the first etched trench includes: filling and forming a metal layer (411) within the first lateral groove (32); or filling and forming a connection layer (412) within the first lateral groove (32); or forming a metal layer on the inner wall of the first lateral groove (32) and filling and forming a connection layer.

16. The preparation method according to claim 14, wherein, Forming a first hole (34) extending along the first direction within the first etched trench includes: forming a first filling structure within the first trench (31); and forming a plurality of first holes (34) extending along the first direction and spaced apart along the third direction within the first filling structure.

17. The preparation method according to claim 13, wherein, Forming a gate (44') on the inner wall of the second transverse groove (35) includes: forming a gate (44') covering the bottom wall and side wall of the second transverse groove (35) and a second filling layer (45) filling the second transverse groove (35).

18. The preparation method according to claim 17, wherein, Before forming a first semiconductor layer (61) on the inner walls of the first hole (34), the second lateral groove (35) and the third lateral groove (37), the method further includes etching away the gate (44') and the second fill layer (45) of the bottom wall of the second lateral groove (35) exposed by the third lateral groove (37) to make the third lateral groove (37) and the second lateral groove (35) interconnected.

19. The preparation method according to claim 18, wherein, Forming a first semiconductor layer (61) on the inner walls of the first hole (34), the second lateral groove (35), and the third lateral groove (37) includes: forming a gate dielectric layer (46) and an initial first semiconductor layer (61') covering the inner walls of the first hole (34), the second lateral groove (35), the second hole (36), and the third lateral groove (37) through the first hole (34) and the second hole (36); filling the first hole (34), the second lateral groove (35), the second hole (36), and the third lateral groove (37) with a third filling layer (47); removing the initial first semiconductor layer (61') and the third filling layer (47) in the second hole; removing the third filling layer (47) in the third lateral groove (37); and using the remaining initial first semiconductor layer (61') in the first hole (34), the second lateral groove (35), and the third lateral groove (37) as the first semiconductor layer (61).

20. The preparation method according to claim 19, wherein, The method further includes: forming a first dielectric layer (52) of a capacitor that at least covers the first electrode (51) in the second hole (36) and the third transverse groove (37), and filling the second electrode plate (53) forming the capacitor.

21. The preparation method according to claim 20, wherein, The method further includes: forming a second initial trench along the second direction on the side of the second hole (36) away from the first hole (34) that penetrates the stacked structure (20) and extends along the third direction; laterally etching the stacked structure (20) through the second initial trench to form a second trench (38); and filling the second trench (38) to form a third electrode plate (54) of the capacitor.

22. The preparation method according to claim 19, wherein, The method further includes replacing the third filling layer (47) in the first hole (34) with a bit line (62); the bit line (62) is in contact with the first semiconductor layer (61).

23. An electronic device comprising a semiconductor device as described in any one of claims 1 to 12, or a semiconductor device manufactured according to the method of manufacturing a semiconductor device as described in any one of claims 13 to 22.

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