Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor that can improve deflection resistance.　A multilayer ceramic capacitor 1 comprises: a laminate 10 which has a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 disposed above the dielectric layers 20, the laminate including a first main surface TS1 and a second main surface TS2 facing each other in the height direction T, a first lateral surface WS1 and a second lateral surface WS2 facing each other in the width direction W orthogonal to the height direction T, and a first end surface LS1 and a second end surface LS2 facing each other in the length direction L orthogonal to the height direction T and the width direction W; and a pair of external electrodes 40 disposed spaced apart at the ends of the laminate 10 in the length direction L. Each of the external electrodes 40 includes: a base electrode layer 50 containing a metal component; a conductive resin layer 60 disposed above the base electrode layer 50 and containing filler powder and a resin component; and a plating layer 70 disposed above the conductive resin layer 60. An interstice CP is provided inside the conductive resin layer 60 or in contact with the conductive resin layer 60.

Description

Multilayer ceramic capacitor

[0001] This invention relates to a multilayer ceramic capacitor.

[0002] In conventional multilayer ceramic capacitors using resin electrodes as external electrodes (for example, Patent Document 1), a thick film of Cu is used as the base electrode, and resin electrodes, Ni, and Sn plating are arranged in that order on top of it. In the above configuration, Ag is used as the conductive filler and epoxy resin is used for the resin part of the resin electrode, ensuring conductivity of the terminal electrodes through contact with the conductive filler while mitigating the bending stress generated in the multilayer ceramic capacitor.

[0003] Japanese Patent Application Publication No. 11-162771

[0004] However, when excessive flexural stress is applied to a multilayer ceramic capacitor, the stress is transmitted to the laminate via the resin electrode (conductive resin layer), causing cracks and reducing its flexural resistance.

[0005] The object of the present invention is to provide a multilayer ceramic capacitor capable of improving deflection resistance.

[0006] The multilayer ceramic capacitor according to the present invention comprises a plurality of stacked dielectric layers and a plurality of internal electrode layers disposed on the dielectric layers, and a laminate having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction, and a pair of external electrodes disposed spaced apart from each other at both ends of the laminate in the length direction, wherein the external electrodes have a base electrode layer containing a metal component, a conductive resin layer disposed on the base electrode layer containing filler powder and a resin component, and a plating layer disposed on the conductive resin layer, and at least a crack is disposed inside the conductive resin layer or in contact with the conductive resin layer.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can improve deflection resistance.

[0008] This is an external perspective view of the multilayer ceramic capacitor of the embodiment. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along the line II-II. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line III-III. This is an enlarged view of the cross-section of the external electrode at section IV of the multilayer ceramic capacitor shown in Figure 2. This is a diagram corresponding to Figure 4 in the multilayer ceramic capacitor according to the first modified example. This is a diagram corresponding to Figure 4 in the multilayer ceramic capacitor according to the second modified example. This is a diagram corresponding to Figure 4 in the multilayer ceramic capacitor according to the third modified example. This is a diagram corresponding to Figure 4 in the multilayer ceramic capacitor according to the fourth modified example. This is a schematic diagram for explaining the arrangement of cracks when the multilayer ceramic capacitor shown in Figure 8 is viewed from the first main surface side. This is a schematic diagram for explaining the arrangement of cracks according to the fifth modified example when the multilayer ceramic capacitor is viewed from the first main surface side. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 10 along the line XI-XI. This is a diagram corresponding to Figure 10 when each crack has expanded due to stress applied to the external electrode from the mounting surface. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 12 along the line XIII-XIII. The sixth modified example is a diagram corresponding to Figure 11 in multilayer ceramic capacitors. This diagram shows a double-gang multilayer ceramic capacitor. This diagram shows a triple-gang multilayer ceramic capacitor. This diagram shows a quadruple-gang multilayer ceramic capacitor.

[0009] <Embodiment> Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to one embodiment of the present disclosure will be described with reference to Figures 1 to 3. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 1 along the line II-II. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line III-III.

[0010] Furthermore, the drawings may be schematically simplified to illustrate the content of the invention, and the ratios of the dimensions of the depicted components or between components may not match the ratios of those dimensions described in the specification. In addition, components described in the specification may be omitted in the drawings, or their number may be omitted. For example, the number of internal electrode layers described in Figures 2 and 3 is 10 for the sake of explanation, but this does not represent the actual number of internal electrode layers 30. Furthermore, the terms used in this invention to specify shapes, geometric conditions, and their degree, such as terms like "parallel," "orthogonal," and "identical," as well as values ​​of length and angle, should not be interpreted strictly, but rather as including a range to which similar functionality can be expected.

[0011] The multilayer ceramic capacitor 1 comprises a laminate 10 and an external electrode 40.

[0012] Figures 1 to 3 show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T, which is the height direction of the multilayer ceramic capacitor 1 and the laminate 10, corresponds to the Z direction. Here, the cross section shown in Figure 2 is also called the LT cross section. The cross section shown in Figure 3 is also called the WT cross section. Furthermore, the cross section in the multilayer ceramic capacitor that is approximately perpendicular to the LT cross section and the WT cross section is also called the LW cross section.

[0013] As shown in Figures 1 to 3, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing the lamination direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the lamination direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the lamination direction T and the width direction W.

[0014] Furthermore, the multilayer ceramic capacitor 1 is generally symmetrical with respect to the central LW cross-section in the height direction T. Therefore, in the following description, unless it is necessary to distinguish between the first main surface TS1 and the second main surface TS2, the first main surface TS1 and the second main surface TS2 may be collectively referred to as the main surface TS.

[0015] Similarly, the multilayer ceramic capacitor 1 is generally symmetrical with respect to the WT cross section at the center of the length L. Therefore, in the following description, when it is not necessary to distinguish between the first end face LS1 and the second end face LS2, the first end face LS1 and the second end face LS2 may be collectively referred to as end face LS.

[0016] As shown in Figure 1, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Some or all of the surfaces constituting the laminate 10 may have irregularities or bumps formed on them.

[0017] The dimensions of the laminate 10 are not particularly limited, but if the dimension in the length direction L of the laminate 10 is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 10 mm or less. If the dimension in the stacking direction T of the laminate 10 is denoted as dimension T, then it is preferable that dimension T is 0.1 mm or more and 10 mm or less. If the dimension in the width direction W of the laminate 10 is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 10 mm or less.

[0018] As shown in Figures 2 and 3, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12A and a second main surface-side outer layer 12B, which are arranged to sandwich the inner layer 11 in the lamination direction T.

[0019] The inner layer 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The inner layer 11 includes the internal electrode layer 30 located on the first main surface TS1 side to the internal electrode layer 30 located on the second main surface TS2 side in the stacking direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0020] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ The dielectric ceramic may contain components such as those mentioned above. Furthermore, the dielectric material may be obtained by adding minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds to these main components.

[0021] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 15 μm or less. The number of dielectric layers 20 to be stacked is preferably 10 or more and 700 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers in the inner layer portion 11 and the number of dielectric layers in the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B.

[0022] The plurality of internal electrode layers 30 have a plurality of first internal electrode layers 31 as a plurality of first internal conductor layers and a plurality of second internal electrode layers 32 as a plurality of second internal conductor layers. The plurality of first internal electrode layers 31 are arranged on a plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on a plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10 via the dielectric layers 20. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20.

[0023] The first internal electrode layer 31 has a first opposing portion 31A that faces the second internal electrode layer 32, and a first leading portion 31B that is drawn out from the first opposing portion 31A to the first end face LS1. The first leading portion 31B is exposed to the first end face LS1.

[0024] The second internal electrode layer 32 has a second opposing portion 32A that faces the first internal electrode layer 31, and a second leading portion 32B that is drawn out from the second opposing portion 32A to the second end face LS2. The second leading portion 32B is exposed to the second end face LS2.

[0025] Furthermore, the multilayer ceramic capacitor 1 is generally symmetrical with respect to the WT cross section in the center of the length L. Therefore, in the following description, when it is not necessary to distinguish between the first lead portion 31B and the second lead portion 32B, the first lead portion 31B and the second lead portion 32B may be collectively referred to as the lead portion 30B. Similarly, when it is not necessary to distinguish between the first opposing portion 31A and the second opposing portion 32A, the first opposing portion 31A and the second opposing portion 32A may be collectively referred to as the opposing portion 30A.

[0026] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0027] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first pull-out portion 31B and the second pull-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0028] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0029] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0030] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 10 or more and 700 or less.

[0031] The first main surface-side outer layer 12A is located on the first main surface TS1 side of the laminate 10. The first main surface-side outer layer 12A is an aggregate of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface-side outer layer 12A may be the same as the dielectric layers 20 used in the inner layer 11, or they may be dielectric layers made of different materials.

[0032] The second main surface-side outer layer 12B is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 12B is an aggregate of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface-side outer layer 12B may be the same as the dielectric layers 20 used in the inner layer 11, or they may be dielectric layers made of different materials.

[0033] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figures 2 and 3 show the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0034] The laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figure 3 shows the width direction W range of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called a W gap or side gap.

[0035] The laminate 10 has an end-face outer layer. The end-face outer layer has a first end-face outer layer LG1 and a second end-face outer layer LG2. The first end-face outer layer LG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first end face LS1. The second end-face outer layer LG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second end face LS2. Figure 2 shows the range L in the longitudinal direction of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer is also called an L gap or end gap.

[0036] Furthermore, the multilayer ceramic capacitor 1 is generally symmetrical with respect to the WT cross-section at the center of the length L. Therefore, in the following description, when it is not necessary to distinguish between the first end-face outer layer LG1 and the second end-face outer layer LG2, the first end-face outer layer LG1 and the second end-face outer layer LG2 may be collectively referred to as the end-face outer layer LG.

[0037] The external electrode 40 has a first external electrode 40A disposed on the first end face LS1 side and a second external electrode 40B disposed on the second end face LS2 side.

[0038] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A is disposed on a part of the first main surface TS1 and a part of the second main surface TS2. The first external electrode 40A may also be disposed on a part of the first side surface WS1 and a part of the second side surface WS2. In the present embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2.

[0039] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B is disposed on a part of the first main surface TS1 and a part of the second main surface TS2. The second external electrode 40B may also be disposed on a part of the first side surface WS1 and a part of the second side surface WS2. In the present embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2.

[0040] As described above, in the laminate 10, a capacitance is formed by the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 facing each other through the dielectric layer 20. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0041] Note that the basic configurations of the layers constituting the first external electrode 40A and the second external electrode 40B are the same. Also, the first external electrode 40A and the second external electrode 40B are substantially plane-symmetric with respect to the LW cross-section at the center of the length direction L of the multilayer ceramic capacitor 1. Therefore, when there is no need to particularly distinguish between the first external electrode 40A and the second external electrode 40B for explanation, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrode 40.

[0042] The first external electrode 40A includes a first base electrode layer 50A containing a metal component, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plating layer 70A disposed on the first conductive resin layer 60A.

[0043] The second external electrode 40B includes a second base electrode layer 50B containing a metal component, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plating layer 70B disposed on the second conductive resin layer 60B.

[0044] The base electrode layer 50 includes the first base electrode layer 50A and the second base electrode layer 50B.

[0045] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. The first base electrode layer 50A is disposed on a part of the first main face TS1 and a part of the second main face TS2. Also, the first base electrode layer 50A may be disposed on a part of the first side face WS1 and a part of the second side face WS2. In the present embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a part of the first main face TS1 and a part of the second main face TS2, as well as a part of the first side face WS1 and a part of the second side face WS2.

[0046] The second base electrode layer 50B is disposed on the second end surface LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. The second base electrode layer 50B is disposed on a part of the first main surface TS1 and a part of the second main surface TS2. Further, the second base electrode layer 50B may also be disposed on a part of the first side surface WS1 and a part of the second side surface WS2. In the present embodiment, the second base electrode layer 50B is formed to extend from the second end surface LS2 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2.

[0047] The first base electrode layer 50A has at least one layer selected from a fired layer, a thin film layer, and the like.

[0048] The second base electrode layer 50B has at least one layer selected from a fired layer, a thin film layer, and the like.

[0049] The fired layer preferably contains either a metal component and a glass component or a ceramic component, or both. Thereby, the adhesion between the laminate 10 and the base electrode layer can be improved. The metal component contains at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, and the like. The glass component contains at least one selected from, for example, B, Si, Ba, Mg, Al, Li, and the like. When there is a glass component, it can assist the sintering of the metal component in the base electrode layer and promote the sintering. The ceramic component may be the same type of ceramic material as the dielectric layer 20 or a different type of ceramic material. The ceramic component contains at least one selected from, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ and the like.

[0050] The baked layer is, for example, formed by applying a conductive paste containing glass and metal to a laminate and baking it. The baked layer may be formed by simultaneously firing a laminated chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminated chip, or by firing a laminated chip having internal electrodes and a dielectric layer to obtain a laminate, and then applying the conductive paste to the laminate and baking it. When simultaneously firing a laminated chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminated chip, it is preferable to form the baked layer by baking a material with a ceramic component added instead of glass. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may consist of multiple layers.

[0051] The thin film layer is a layer of 1 μm or less in thickness on which metal particles are deposited. Preferably, the thin film layer contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This increases the adhesion force of the external electrode 40 to the laminate 10. The thin film layer may be a single layer or formed by multiple layers. For example, it may be formed by a two-layer structure consisting of a NiCr layer and a NiCu layer.

[0052] The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. When the thin film layer as the base electrode is formed by a sputtering electrode using the sputtering method, it is preferable that the sputtering electrode is formed on a part of the first main surface TS1 and a part of the second main surface TS2 of the laminate 10. The sputtering electrode preferably contains at least one metal selected from, for example, Ni, Cr, Cu, etc. The thickness of the sputtering electrode is preferably 50 nm to 400 nm, and more preferably 50 nm to 130 nm.

[0053] As a base electrode layer, sputter electrodes may be formed on a portion of the first main surface TS1 and a portion of the second main surface TS2 of the laminate 10, while a baking layer may be formed on the first end surface LS1 and the second end surface LS2. Alternatively, the plating layer described later may be formed directly on the laminate 10 without forming a base electrode layer on the first end surface LS1 and the second end surface LS2. When a baking layer is formed on the first end surface LS1 and the second end surface LS2, the baking layer may extend not only to the first end surface LS1 and the second end surface LS2, but also to a portion of the first main surface TS1 and a portion of the second main surface TS2. In this case, the sputter electrodes may be arranged to overlap the baking layer.

[0054] In this embodiment, the first base electrode layer 50A and the second base electrode layer 50B are baked-on layers.

[0055] The thickness of the first base electrode layer 50A located at the first end face LS1 in the longitudinal direction L is preferably, for example, 2 μm to 220 μm in the central part of the first base electrode layer 50A in the lamination direction T and width direction W.

[0056] The thickness of the second base electrode layer 50B located at the second end face LS2 in the longitudinal direction L is preferably, for example, 2 μm to 220 μm in the central part of the stacking direction T and width direction W of the second base electrode layer 50B.

[0057] When the first base electrode layer 50A is provided on a part of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the first base electrode layer 50A provided in this part in the lamination direction T is, for example, 4 μm or more and 40 μm or less at the center of the length direction L and width direction W of the first base electrode layer 50A provided in this part.

[0058] When the first base electrode layer 50A is provided on a part of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness of the first base electrode layer 50A in the width direction W provided in this portion is, for example, 4 μm or more and 40 μm or less in the central part of the first base electrode layer 50A in the length direction L and the lamination direction T provided in this portion.

[0059] When a second base electrode layer 50B is provided on at least one of the surfaces of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided in this portion in the lamination direction T is preferably, for example, 4 μm or more and 40 μm or less in the central part of the length direction L and width direction W of the second base electrode layer 50B provided in this portion.

[0060] When a second base electrode layer 50B is provided on at least one of the surfaces of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B in the width direction W provided in this portion is preferably, for example, 4 μm or more and 40 μm or less in the central part of the second base electrode layer 50B in the length direction L and the lamination direction T.

[0061] The basic structure of each layer constituting the first external electrode 40A and the second external electrode 40B is the same. Furthermore, the first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to the cross-section LW at the center of the length L of the multilayer ceramic capacitor 1. Therefore, when there is no need to specifically distinguish between the first base electrode layer 50A and the second base electrode layer 50B, they may be collectively referred to as the base electrode layer 50.

[0062] The external electrode 40 has a conductive resin layer 60 containing resin and metal components, which is placed on the base electrode layer 50. The conductive resin layer 60 has a first conductive resin layer 60A and a second conductive resin layer 60B.

[0063] The first conductive resin layer 60A is arranged to cover the first base electrode layer 50A. In this embodiment, the first conductive resin layer 60A is arranged to extend from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as a part of the first side surface WS1 and a part of the second side surface WS2.

[0064] The second conductive resin layer 60B is arranged to cover the second base electrode layer 50B. In this embodiment, the second conductive resin layer 60B is arranged to extend from the second end face LS2 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as a part of the first side surface WS1 and a part of the second side surface WS2.

[0065] The thickness of the first conductive resin layer 60A located on the first end face LS1 side in the longitudinal direction L is preferably, for example, 10 μm to 200 μm in the central part of the lamination direction T and width direction W of the first conductive resin layer 60A.

[0066] The thickness of the second conductive resin layer 60B located on the second end face LS2 side in the longitudinal direction L is preferably, for example, 10 μm to 200 μm in the central part of the lamination direction T and width direction W of the second conductive resin layer 60B.

[0067] When the first conductive resin layer 60A is also provided on a portion of the first main surface TS1 and a portion of the second main surface TS2, the thickness of the first conductive resin layer 60A in the lamination direction T provided in these portions is preferably, for example, 10 μm or more and 200 μm or less at the center of the length direction L and width direction W of the first conductive resin layer 60A provided in these portions.

[0068] When the first conductive resin layer 60A is also provided on a portion of the first side surface WS1 and a portion of the second side surface WS2, it is preferable that the thickness of the first conductive resin layer 60A in the width direction W provided on this portion is, for example, 10 μm or more and 200 μm or less at the center of the first conductive resin layer 60A in the length direction L and the lamination direction T provided on this portion.

[0069] When a second conductive resin layer 60B is provided on a portion of the first main surface TS1 and a portion of the second main surface TS2, the thickness of the second conductive resin layer 60B provided in this portion in the lamination direction T is preferably, for example, 10 μm to 200 μm at the center of the length direction L and width direction W of the second conductive resin layer 60B provided in this portion.

[0070] When a second conductive resin layer 60B is provided on a portion of the first side surface WS1 and a portion of the second side surface WS2, the thickness of the second conductive resin layer 60B in the width direction W provided on this portion is preferably, for example, 10 μm or more and 200 μm or less at the center of the second conductive resin layer 60B in the length direction L and the lamination direction T.

[0071] The conductive resin layer 60 is a layer having a resin portion and a conductive filler dispersed within the resin portion.

[0072] The resin portion of the conductive resin layer 60 may contain at least one selected from various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin portion of the conductive resin layer 60 contains a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0073] Because the conductive resin layer 60 includes such resin components, it is more flexible than, for example, the base electrode layer 50 which consists of a plated film or a fired product of metal and glass components. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer 60 functions as a buffer layer. Thus, the conductive resin layer 60 suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0074] The conductive filler is dispersed within the resin portion in a substantially uniform distribution. The conductive filler is primarily responsible for the conductivity of the conductive resin layer 60. Specifically, when multiple conductive fillers come into contact with each other, a conductive path is formed inside the conductive resin layer 60, and electrical conductivity is established between the base electrode layer 50 and the plating layer 70.

[0075] The metal constituting the conductive filler may be pure silver (Ag), an alloy containing Ag, or a metal powder with an Ag coating on its surface. Ag has the lowest resistivity among metals, making it suitable for electrode materials. Furthermore, as a noble metal, Ag is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as a conductive filler. When using a metal powder with an Ag coating on its surface, it is preferable to use Cu, Ni, Sn, Bi, or alloy powders containing these metals.

[0076] Furthermore, the conductive filler may be Cu or Ni that has been treated to prevent oxidation. Alternatively, the conductive filler may be metal powder coated with Sn, Ni, or Cu on its surface. When using metal powder coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0077] The shape of the conductive filler is not particularly limited. Conductive fillers can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0078] The average particle size of the conductive filler may be, for example, 0.3 μm or more and 10 μm or less.

[0079] The average particle size of the conductive filler contained in the conductive resin layer is calculated using the laser diffraction particle size measurement method based on ISO 13320, regardless of the shape of the conductive filler.

[0080] The basic structure of each layer constituting the first external electrode 40A and the second external electrode 40B is the same. Furthermore, the first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to the cross-section LW at the center of the length L of the multilayer ceramic capacitor 1. Therefore, when there is no need to specifically distinguish between the first conductive resin layer 60A and the second conductive resin layer 60B, they may be collectively referred to as the conductive resin layer 60.

[0081] The plating layer 70 has a first plating layer 70A and a second plating layer 70B.

[0082] The first plating layer 70A is arranged to cover the first conductive resin layer 60A. In this embodiment, the first plating layer 70A is arranged to extend from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as a part of the first side surface WS1 and a part of the second side surface WS2.

[0083] The second plating layer 70B is arranged to cover the second conductive resin layer 60B. In this embodiment, the second plating layer 70B is arranged to extend from the second end face LS2 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as a part of the first side surface WS1 and a part of the second side surface WS2.

[0084] The plating layer 70 preferably has a two-layer structure consisting of a Ni plating layer 71 and a Sn plating layer 72. Preferably, the first Sn plating layer 72A is arranged on the first Ni plating layer 71A, and preferably, the second Sn plating layer 72B is arranged on the second Ni plating layer 71B.

[0085] In other words, the first plating layer 70A has a first Ni plating layer 71A as an underlayer plating layer and a first Sn plating layer 72A as an upper layer plating layer. The second plating layer 70B has a second Ni plating layer 71B as an underlayer plating layer and a second Sn plating layer 72B as an upper layer plating layer.

[0086] The Ni plating layer 71 prevents the underlying electrode layer 50 and the conductive resin layer 60 from being corroded by the solder used when mounting the multilayer ceramic capacitor 1. The Sn plating layer 72 improves the wettability of the solder used when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1.

[0087] The thickness of the first Ni plating layer 71A and the first Sn plating layer 72A are preferably 1 μm or more and 15 μm or less.

[0088] The thickness of the second Ni plating layer 71B and the second Sn plating layer 72B are preferably 1 μm or more and 15 μm or less.

[0089] Furthermore, the basic structure of each layer constituting the first external electrode 40A and the second external electrode 40B is the same. Also, the first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to the cross-section LW at the center of the length L of the multilayer ceramic capacitor 1. Therefore, when there is no need to specifically distinguish between the first plating layer 70A and the second plating layer 70B, the first plating layer 70A and the second plating layer 70B may be collectively referred to as the plating layer 70.

[0090] Similarly, when there is no need to distinguish between the first Ni plating layer 71A and the second Ni plating layer 71B, the first Ni plating layer 71A and the second Ni plating layer 71B may be collectively referred to as the Ni plating layer 71.

[0091] Similarly, when there is no need to distinguish between the first Sn plating layer 72A and the second Sn plating layer 72B, the first Sn plating layer 72A and the second Sn plating layer 72B may be collectively referred to as the Sn plating layer 72.

[0092] Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminated body 10 and the external electrodes 40, is denoted as dimension L, then it is preferable that dimension L is between 0.2 mm and 10 mm. Also, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is between 0.1 mm and 10 mm. Furthermore, if the widthwise dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is between 0.1 mm and 10 mm.

[0093] Here, the inventors of the present invention have found, through repeated studies, experiments, and simulations, that it is desirable to place the crack portion at an appropriate position in the multilayer ceramic capacitor in order to improve deflection resistance. The present embodiment will be described in detail below with reference to Figure 4. Figure 4 is an enlarged view of the cross-section of the external electrode in section IV of the multilayer ceramic capacitor shown in Figure 2.

[0094] In the multilayer ceramic capacitor 1 according to this embodiment, as shown in Figure 4, the crack portion CP is arranged at least inside the conductive resin layer 60 or in contact with the conductive resin layer 60. In the multilayer ceramic capacitor 1, it is preferable that the crack portion CP is arranged at least inside the conductive resin layer 60 on the first main surface TS1 side or in contact with the surface of the conductive resin layer 60.

[0095] In the multilayer ceramic capacitor 1 according to this embodiment, the crack portion CP is positioned in contact with the surface of the conductive resin layer 60, at least on the side of the first main surface TS1. More specifically, in the multilayer ceramic capacitor 1 according to this embodiment, the crack portion CP1, as the crack portion CP, is positioned at the interface between the laminate 10 and the conductive resin layer 60, as shown in Figure 4.

[0096] However, in the multilayer ceramic capacitor 1, the crack portion CP is not limited to being located at the interface between the laminate 10 and the conductive resin layer 60. Below, multilayer ceramic capacitors 1 according to the first to fourth modified examples, which differ in the arrangement of the crack portion CP, will be described with reference to Figures 5 to 8.

[0097] Figure 5 is a diagram corresponding to Figure 4 in a multilayer ceramic capacitor according to the first modified example. Figure 6 is a diagram corresponding to Figure 4 in a multilayer ceramic capacitor according to the second modified example. Figure 7 is a diagram corresponding to Figure 4 in a multilayer ceramic capacitor according to the third modified example. Figure 8 is a diagram corresponding to Figure 4 in a multilayer ceramic capacitor according to the fourth modified example.

[0098] In the first modified example, the multilayer ceramic capacitor 1 may have, for example, a crack portion CP2 as a crack portion CP, which may be arranged inside the conductive resin layer 60, as shown in Figure 5. In this case, the crack portion CP2 is formed to extend in the longitudinal direction L. In this case, one end of the crack portion CP2 may be formed in contact with the laminate 10.

[0099] Furthermore, as shown in Figure 5, in a cross-sectional view perpendicular to the length direction L and the height direction T, the outer end of the crack portion CP2 in the length direction L may be positioned further outward in the length direction L than the opposing portion 30A. In other words, as shown in Figure 5, in a cross-sectional view perpendicular to the length direction L and the height direction T, the outer end of the crack portion CP2 in the length direction L may be positioned further away from the center of the laminate 10 than the opposing portion 30A. In other words, as shown in Figure 5, in a cross-sectional view perpendicular to the length direction L and the height direction T, the outer end of the crack portion CP2 in the length direction L may be positioned on the surface side of the plating layer 70 than the opposing portion 30A. As a result, since the crack portion is positioned further outward in the length direction than the opposing portion, the propagation of cracks originating from the crack portion into the internal electrode layer due to stress generated during mounting can be suppressed, while the transmission of stress between the conductive resin layer and the laminate can be suppressed, thereby more effectively improving deflection resistance.

[0100] Furthermore, the outer end L in the longitudinal direction of the crack portion CP2 may be positioned closer to the center of the laminate 10 than the end face LS. This ensures that the propagation of cracks originating from the crack portion into the internal electrode layer is suppressed, while also suppressing bonding defects caused by damage to the external electrodes during mounting.

[0101] In the first modified multilayer ceramic capacitor 1, the outer end of the crack portion CP2 in the longitudinal direction L was positioned further out in the longitudinal direction L than the opposing portion 30A, but this is not limited to this. For example, as shown in Figure 6, in the second modified multilayer ceramic capacitor 1, in a cross-sectional view perpendicular to the longitudinal direction L and the height direction T, the outer end of the crack portion CP2 in the longitudinal direction L may be positioned further out in the longitudinal direction L than the laminate 10. In other words, as shown in Figure 5, in a cross-sectional view perpendicular to the longitudinal direction L and the height direction T, the outer end of the crack portion CP2 in the longitudinal direction L may be positioned further away from the center of the laminate 10 than the laminate 10. Also, in other words, as shown in Figure 5, in a cross-sectional view perpendicular to the longitudinal direction L and the height direction T, the outer end of the crack portion CP2 in the longitudinal direction L may be positioned on the surface side of the plating layer 70 than the laminate 10. As a result, the crack is positioned longitudinally outward from the laminate, which more reliably suppresses the propagation of cracks from the crack to the internal electrode layer due to stress generated during mounting, while also suppressing the transmission of stress between the conductive resin layer and the laminate, thereby more effectively improving deflection resistance.

[0102] Furthermore, the outer ends of the crack portion CP2 in the longitudinal direction L may be positioned closer to the center of the laminate 10 than the outer ends of the base electrode layer 50 in the longitudinal direction L. This makes it possible to more reliably suppress the propagation of cracks originating from the crack portion into the internal electrode layer, while also suppressing bonding defects caused by damage to the external electrodes during mounting.

[0103] Furthermore, in the multilayer ceramic capacitor 1 according to the third modified example, the crack portion CP3, which is the crack portion CP, may be arranged at the interface between the conductive resin layer 60 and the plating layer 70, as shown in Figure 7. In this case, the crack portion CP3 is formed to extend in the longitudinal direction L. Also, in this case, one end of the crack portion CP3 may be formed in contact with the laminate 10.

[0104] Furthermore, similar to the crack portion CP2, in a cross-sectional view perpendicular to the length direction L and height direction T, the end of the crack portion CP3 that is on the outer side in the length direction L may be positioned further outward in the length direction L than the opposing portion 30A. As a result, since the crack portion is positioned further outward in the length direction than the opposing portion, the propagation of cracks originating from the crack portion into the internal electrode layer due to stress generated during mounting can be suppressed, while the transmission of stress between the conductive resin layer and the laminate can be suppressed, thereby more effectively improving deflection resistance.

[0105] Furthermore, the outer end L in the longitudinal direction of the crack portion CP3 may be positioned closer to the center of the laminate 10 than the end face LS. This makes it possible to more reliably suppress the propagation of cracks originating from the crack portion into the internal electrode layer, while also suppressing bonding defects caused by damage to the external electrodes during mounting.

[0106] Furthermore, similar to the crack portion CP2, in a cross-sectional view perpendicular to the length direction L and height direction T, the end of the crack portion CP3 that is on the outer side in the length direction L may be positioned further outward in the length direction L than the laminate 10. As a result, since the crack portion is positioned further outward in the length direction than the laminate, the propagation of cracks originating from the crack portion into the internal electrode layer due to stress generated during mounting can be more reliably suppressed, while the transmission of stress between the conductive resin layer and the laminate can be suppressed, thereby more effectively improving deflection resistance.

[0107] Furthermore, the outer ends of the crack portion CP3 in the longitudinal direction L may be positioned closer to the center of the laminate 10 than the outer ends of the base electrode layer 50 in the longitudinal direction L. This makes it possible to more reliably suppress the propagation of cracks originating from the crack portion into the internal electrode layer, while also suppressing bonding defects caused by damage to the external electrodes during mounting.

[0108] Furthermore, in the multilayer ceramic capacitor 1 according to the fourth modified example, the crack portion CP4, which is a crack portion CP, may be located at the interface between the base electrode layer 50 and the conductive resin layer 60. Moreover, as shown in Figure 8, the crack portion CP4, which is a second crack portion, may be located together with the crack portion CP1, which is a first crack portion, as shown in Figure 4. That is, the crack portion CP may have a crack portion CP1, which is a first crack portion located at the interface between the laminate 10 and the conductive resin layer 60, and a crack portion CP4, which is a second crack portion located at the interface between the base electrode layer 50 and the conductive resin layer 60.

[0109] In this case, the first crack portion CP1 and the second crack portion CP4 may be in contact, or they may be separated.

[0110] Furthermore, similar to the crack portion CP2, in a cross-sectional view perpendicular to the length direction L and height direction T, the end of the crack portion CP4 that is on the outer side in the length direction L may be positioned further outward in the length direction L than the opposing portion 30A. As a result, since the crack portion is positioned further outward in the length direction than the opposing portion, the propagation of cracks originating from the crack portion into the internal electrode layer due to stress generated during mounting can be suppressed, while the transmission of stress between the conductive resin layer and the laminate can be suppressed, thereby more effectively improving deflection resistance.

[0111] Furthermore, the outer end of the crack portion CP4 in the longitudinal direction L may be positioned closer to the center of the laminate 10 than the end face LS. This makes it possible to more reliably suppress the propagation of cracks originating from the crack portion into the internal electrode layer, while also suppressing bonding defects caused by damage to the external electrodes during mounting.

[0112] Furthermore, similar to the crack portion CP2, in a cross-sectional view perpendicular to the length direction L and height direction T, the end of the crack portion CP4 that is on the outer side in the length direction L may be positioned further outward in the length direction L than the laminate 10. As a result, since the crack portion is positioned further outward in the length direction than the laminate, the propagation of cracks originating from the crack portion into the internal electrode layer due to stress generated during mounting can be more reliably suppressed, while the transmission of stress between the conductive resin layer and the laminate can be suppressed, thereby more effectively improving deflection resistance.

[0113] Furthermore, the outer ends of the crack portion CP2 in the longitudinal direction L may be positioned closer to the center of the laminate 10 than the outer ends of the base electrode layer 50 in the longitudinal direction L. This makes it possible to more reliably suppress the propagation of cracks originating from the crack portion into the internal electrode layer, while also suppressing bonding defects caused by damage to the external electrodes during mounting.

[0114] Here, the preferred size of the crack portion CP will be explained using Figure 9, which shows a multilayer ceramic capacitor 1 according to the fourth modified example of Figure 8. Figure 9 is a hypothetical diagram for explaining the arrangement of the crack portion when the multilayer ceramic capacitor shown in Figure 8 is viewed from the first main surface TS1 side.

[0115] As shown in Figure 9, when one crack is present, when the external electrode 40 is viewed from the height direction T, the projected area Sc of the crack CP on the interface between the laminate 10 and the external electrode 40 is preferably 10% or more of the interface area Sm between the laminate 10 and the external electrode 40. The projected area Sc of the crack CP on the interface between the laminate 10 and the external electrode 40 is the area of ​​the hatched portion showing cracks CP1 and CP4 in Figure 9. The interface area Sm between the laminate 10 and the external electrode 40 is the area of ​​the substantially rectangular portion of the laminate 10 that overlaps with the external electrode 40 in Figure 9.

[0116] In the embodiments and modifications described above, the case in which one crack portion CP is arranged has been explained, but this is not the only case. For example, in the multilayer ceramic capacitor 1 according to the fifth modification, multiple crack portions CP may be arranged. The multilayer ceramic capacitor 1 according to the fifth modification will be explained with reference to Figures 10 to 13.

[0117] Figure 10 is a hypothetical diagram illustrating the arrangement of cracks in a fifth modified example of a multilayer ceramic capacitor viewed from the first main surface. Figure 11 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 10 along the line XI-XI. Figure 12 is a diagram corresponding to Figure 10 when each crack has expanded due to stress applied to the external electrodes from the mounting surface. Figure 13 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 12 along the line XIII-XIII.

[0118] In the multilayer ceramic capacitor 1 according to the fifth modification, as shown in Figures 10 and 11, multiple cracks CP are arranged. As a result, compared to the case where only one crack CP is arranged, each individual crack is smaller, and the strength of the external electrode 40 can be ensured to be higher.

[0119] Furthermore, as shown in Figures 10 and 11, it is preferable that the multiple cracks CP be arranged in a line along the length L. For example, in Figure 10, multiple cracks CP2 are arranged in a line along the line XIII-XIII in the length L. This allows the individual cracks to be small, ensuring higher strength for the external electrode 40, while, for example, when stress is applied to the mounting surface from the substrate after mounting, the cracks propagate in the length direction as shown in Figures 12 and 13, connecting adjacent cracks in the length direction to form a larger crack CP2C, which allows for greater stress relief.

[0120] Furthermore, it is preferable that the multiple crack portions CP be arranged in the direction of extension of other crack portions, as shown in Figure 11. This ensures that when stress is applied to the mounting surface from the substrate after mounting, the cracks propagate more reliably in the longitudinal direction L, as shown in Figures 12 and 13, and the multiple adjacent crack portions CP connect with each other in the longitudinal direction L, forming a larger crack portion CP2C, which allows for greater stress relief.

[0121] In the fifth modification, as an example of an example where multiple cracks CP are arranged, multiple cracks CP2 arranged inside the conductive resin layer 60 were described, but the invention is not limited to this. For example, multiple cracks CP1 may be arranged at the interface between the laminate 10 and the conductive resin layer 60, multiple cracks CP3 may be arranged at the interface between the laminate 10 and the plating layer 70, or multiple cracks CP4 may be arranged at the interface between the laminate 10 and the base electrode layer 50. In these cases as well, the individual cracks are smaller compared to the case where only one crack CP is arranged, and the strength of the external electrode 40 can be ensured to be higher.

[0122] Furthermore, as shown in Figure 14, in the multilayer ceramic capacitor 1 according to the sixth modified example, the multiple first cracks CP1 arranged at the interface between the laminate 10 and the conductive resin layer 60, and the multiple second cracks CP4 arranged at the interface between the laminate 10 and the base electrode layer 50, may be spaced apart. Even in these cases, the individual cracks are smaller compared to the case where only one crack CP is arranged, and the strength of the external electrode 40 can be ensured to be higher.

[0123] Furthermore, in the multilayer ceramic capacitor 1 according to the sixth modified example, the multiple cracks CP are arranged along the interface between the laminate 10 and the base electrode layer 50. Therefore, when stress is applied to the mounting surface from the substrate or the like, the cracks propagate along the interface in the longitudinal direction, connecting with adjacent cracks, forming larger cracks, and allowing for greater stress relief.

[0124] Here, as shown in Figure 10, even when multiple cracks are arranged, it is preferable that the projected area Sc of the total of the multiple cracks CP on the interface between the laminate 10 and the external electrode 40 is 10% or more of the interface area Sm between the laminate 10 and the external electrode 40 when the external electrode 40 is viewed from the height direction T.

[0125] Furthermore, the crack portions CPs according to the first to fifth modified examples described above may be combined and arranged. This allows for a more effective improvement in deflection resistance.

[0126] <Measurement Method> Next, we will explain the method for measuring the projected area Sc at the interface between the laminated body 10 and the external electrode 40 at the crack, and the method for observing the crack in the LT cross-section.

[0127] First, the method for measuring the projected area Sc of the crack at the interface between the laminated body 10 and the external electrode 40 will be explained. First, using an ultrasonic flaw detection device, 50 MHz ultrasonic waves are irradiated onto the sample, and the crack inside the laminated chip is detected from the difference between the incident wave and the reflected wave. Here, the presence and location of the crack are observed using the ultrasonic flaw detection device. Specifically, first, the sample, a multilayer ceramic capacitor, is positioned so that its main surface faces upward. Next, ultrasonic waves are irradiated onto the upper surface of the multilayer ceramic capacitor using an ultrasonic probe and scanned. The reflected waves of the ultrasonic waves at this time are observed, and the presence and location of the crack are confirmed by detecting the reflected waves that return earlier than the bottom wave. The projected shape of the crack is identified from the position measurement result, and the area is calculated based on that shape.

[0128] Next, a method for observing cracks in the LT cross section will be described. First, the multilayer ceramic capacitor 1 is embedded in resin and polished from the first side WS1 or the second side WS2 to a position halfway across the width W dimension. This exposes the LT cross section at the middle position in the width W of the multilayer ceramic capacitor 1. Then, the portion of the LT cross section exposed by polishing, including the crack, is observed using a metallurgical microscope with a 10x eyepiece and a 100x objective lens to observe the crack in the LT cross section.

[0129] <Manufacturing Method> Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor 1 of this embodiment is not limited as long as the above requirements are satisfied. However, a preferred manufacturing method comprises the following steps. The details of each step are described below.

[0130] The process for forming the characteristic cracks in the multilayer ceramic capacitor 1 according to this embodiment differs depending on where the cracks are located. For example, when the cracks are located at the interface between the conductive resin layer and the base body (laminated body) or the base electrode layer, the process of forming the cracks begins after the base electrode layer is formed. When the cracks are located at the interface between the conductive resin layer and the plating layer, the process of forming the cracks begins after the conductive resin layer is formed. When the cracks are located inside the conductive resin layer, the process of forming the cracks begins when the plating layer has been completed. Details of each will be described later.

[0131] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known.

[0132] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer 31 formed on it, and a dielectric sheet with the pattern for the second internal electrode layer 32 formed on it.

[0133] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first main surface outer layer portion 12A on the first main surface TS1 side. On top of this, dielectric sheets with printed patterns for the first internal electrode layer 31 and dielectric sheets with printed patterns for the second internal electrode layer 32 are sequentially stacked to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second main surface outer layer portion 12B on the second main surface TS2 side. This completes the production of the laminated sheet.

[0134] Laminated sheets are pressed in the lamination direction by means of hydrostatic pressing or other methods to produce laminated blocks.

[0135] The laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or the like.

[0136] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C.

[0137] A conductive paste, which will become the base electrode layer 50, is applied to both end faces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. A conductive paste containing glass components and metal is applied to the laminate 10 by a method such as dipping. After that, a baking process is performed to form the base electrode layer 50. The temperature of this baking process is preferably 700°C to 950°C.

[0138] Alternatively, the laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, it is preferable to form the baked layer by baking a material with a ceramic component added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminated body 10 with a baked layer.

[0139] Next, a conductive resin layer 60 is formed. In this embodiment, the conductive resin layer 60 is formed on the surface of the base electrode layer 50. Here, when the crack portion is placed at the interface with the base body (laminated body 10) or the base electrode layer 50 as described above, the process of forming the crack portion CP is started after the base electrode layer 50 has been formed. Specifically, the process of forming the crack portion CP involves, after the base electrode layer 50 has been formed, applying a coating using a fluorine-based coupling agent to the areas on the surface of the laminate 10 or the base electrode layer 50 where the crack portion CP is to be formed.

[0140] Subsequently, with the laminate 10 and the base electrode layer 50 coated, a conductive resin layer 60 and a plating layer 70 are formed. First, a conductive resin paste is prepared by dispersing a conductive filler in a thermosetting resin, which will serve as the base resin for the resin portion. This conductive resin paste is produced by stirring and mixing the thermosetting resin and the conductive filler. Therefore, the conductive filler is dispersed in a uniform distribution within the conductive resin paste. Here, the thermosetting resin is, for example, an epoxy resin. The conductive filler is, for example, Ag metal powder.

[0141] Subsequently, a conductive resin paste is applied to the base electrode layer 50 using a dipping method, and heat treatment is performed at a temperature of 160°C to 550°C. This causes the resin to heat-cur, forming a conductive resin layer 60. The atmosphere during this heat treatment is N ２It is preferable that the atmosphere is such that the oxygen concentration is kept below 100 ppm in order to prevent the scattering of resin and to prevent oxidation of various metal components. Although stress is generated at the interface due to the difference in the coefficient of linear expansion of each part during this heat treatment (high or low temperature), the above-mentioned coating makes it easy to peel off, and peeling occurs at the interface between the conductive resin layer 60 and the laminate 10 or the base electrode layer 50, forming a crack CP.

[0142] Subsequently, a plating layer 70 is formed on the surface of the conductive resin layer 60. Here, if the crack portion CP is placed at the interface between the conductive resin layer 60 and the plating layer 70 as described above, the process of forming the crack portion CP is started after the conductive resin layer 60 has been formed. Specifically, the process of forming the crack portion CP is carried out after the formation of the conductive resin layer 60, for example, by applying a coating using a fluorine-based coupling.

[0143] Plating is then performed. In this embodiment, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60. The Ni plating layer 71 and the Sn plating layer 72 are formed sequentially using an electroplating method. For the plating method, it is preferable to use, for example, barrel plating. Due to the heat treatment (high or low temperature) during plating, stress is generated at the interface due to the difference in the coefficient of linear expansion of each part, but the above-mentioned coating makes it easy to peel off, and peeling occurs at the interface between the conductive resin layer 60 and the plating layer 70, forming a crack CP.

[0144] Here, as described above, when the crack portion CP is placed inside the conductive resin layer 60, the process of forming the crack portion CP is started at the same time as the formation of the plating layer 70 is completed. With the formation of the plating layer 70 completed, a punch or the like is used to make an indentation in the area to be peeled off, thereby causing cohesive failure inside the conductive resin layer 60 and forming the crack portion CP.

[0145] Furthermore, the tool used to form the crack portion CP is not limited to the punch described above. For example, the terminal of the inspection tool may be pressed against the end face during the characteristic inspection process after the formation of the plating layer 70 to partially crush the external electrode, thereby causing cohesive failure in the internal resin electrode and forming a crack portion. This allows the inspection tool to also serve as a tool for forming the crack portion, shortening the process and reducing the cost of manufacturing equipment.

[0146] A multilayer ceramic capacitor 1 is manufactured using the above manufacturing method.

[0147] The multilayer ceramic capacitor 1 of this embodiment provides the following effects.

[0148] One example of a conventional multilayer ceramic capacitor using resin electrodes as external electrodes is a configuration in which a thick Cu underlayer electrode layer, a resin electrode layer (conductive resin layer), Ni, and Sn plating are arranged in that order on top of it. In the above example configuration, the resin electrode layer uses Ag as a conductive filler and epoxy resin in the resin part, ensuring conductivity of the terminal electrodes through contact with the conductive filler while mitigating the flexural stress generated in the multilayer ceramic capacitor. However, when excessive flexural stress is applied to the multilayer chip (laminated body) of the multilayer ceramic capacitor, the stress is transmitted to the laminate via the resin electrode layer, causing cracks and reducing flexural resistance.

[0149] (1) The multilayer ceramic capacitor 1 according to this embodiment has a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 disposed on the dielectric layers 20, and a laminate 10 having a first main surface TS1 and a second main surface TS2 facing the height direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the height direction T and the width direction W, and a pair of external electrodes 40 disposed spaced apart from each other at both ends of the laminate 10 in the length direction L, the external electrodes 40 having a base electrode layer 50 containing a metal component, a conductive resin layer 60 containing filler powder and a resin component disposed on the base electrode layer 50, and a plating layer 70 disposed on the conductive resin layer 60, and at least a crack portion CP is disposed inside the conductive resin layer 60 or in contact with the conductive resin layer 60. As a result, by having cracks in the conductive resin electrode layer during manufacturing, it is possible to suppress the transmission of stress at the interface between the conductive resin layer and the laminate or plating layer, and within the conductive resin layer, thereby improving deflection resistance. Therefore, it is possible to provide a multilayer ceramic capacitor 1 that can improve deflection resistance.

[0150] (2) In the multilayer ceramic capacitor 1 of this embodiment, the crack portion CP is located at least inside the conductive resin layer 60 on the first main surface TS1 side, or in contact with the surface of the conductive resin layer 60. This makes it possible to more reliably suppress the transmission of stress at the interface between the conductive resin layer and the laminate or plating layer, etc., and inside the conductive resin layer, when the surface of the external electrode on the first main surface TS1 side is a mounting surface to which external stress is transmitted, thereby improving deflection resistance.

[0151] (3) In the multilayer ceramic capacitor 1 of this embodiment, the crack portion CP is located at the interface between the laminate 10 and the conductive resin layer 60. Stress tends to concentrate at the interface between the laminate and the conductive resin layer, but by arranging the crack portion at the interface between the laminate and the conductive resin layer, the transmission of stress between the conductive resin layer and the laminate can be suppressed more effectively when stress occurs, thereby improving deflection resistance.

[0152] (4) In the multilayer ceramic capacitor 1 of this embodiment, the crack portion CP is located inside the conductive resin layer 60. As a result, since the crack portion is located inside the conductive resin layer, when stress occurs, the transmission of stress between the conductive resin layer and the laminate can be suppressed more effectively, thereby improving deflection resistance.

[0153] (5) In the multilayer ceramic capacitor 1 of this embodiment, the crack portion CP is located at the interface between the conductive resin layer 60 and the plating layer 70. As a result, since the crack portion is located at the interface between the conductive resin layer and the plating layer, stress generated during or after mounting can suppress the propagation of cracks originating from the crack portion into the laminate inside the conductive resin layer, and the transmission of stress between the conductive resin layer and the laminate can be suppressed, thereby improving deflection resistance.

[0154] (6) In the multilayer ceramic capacitor 1 of this embodiment, the crack portion CP is located at the interface between the base electrode layer 50 and the conductive resin layer 60. By locating the crack portion at the interface between the base electrode layer and the conductive resin layer, it is possible to suppress the propagation of cracks originating from the crack portion into the laminate further inside the base electrode layer, and to more effectively suppress the transmission of stress between the conductive resin layer and the laminate, thereby improving deflection resistance.

[0155] (7) In the multilayer ceramic capacitor of this embodiment, the crack portion CP has a crack portion CP4 located at the interface between the laminate 10 and the conductive resin layer 60, and a crack portion CP1 located at the interface between the base electrode layer 50 and the conductive resin layer 60, and the crack portion CP4 and the crack portion CP1 are in contact. Stress tends to concentrate at the interface between the laminate and the conductive resin layer, but by placing the crack portion at the interface between the laminate and the conductive resin layer, the transmission of stress between the conductive resin layer and the laminate can be suppressed more effectively when stress occurs. Furthermore, by placing the crack portion at the interface between the base electrode layer and the conductive resin layer, the propagation of cracks originating from the crack portion into the laminate further inside the base electrode layer can be suppressed. In addition, since the two cracks are in contact and connected, the transmission of stress between the conductive resin layer and the laminate can be suppressed even more effectively, thereby improving deflection resistance.

[0156] (8) In the multilayer ceramic capacitor 1 of this embodiment, the crack portion CP has a crack portion CP4 located at the interface between the laminate 10 and the conductive resin layer 60, and a crack portion CP1 located at the interface between the base electrode layer 50 and the conductive resin layer 60, with the crack portion CP4 and the crack portion CP1 being spaced apart. Stress tends to concentrate at the interface between the laminate and the conductive resin layer, but by placing the crack portion at the interface between the laminate and the conductive resin layer, the transmission of stress between the conductive resin layer and the laminate can be suppressed more effectively when stress occurs. Furthermore, by placing the crack portion at the interface between the base electrode layer and the conductive resin layer, the propagation of cracks originating from the crack portion into the laminate further inside the base electrode layer can be suppressed, and the transmission of stress between the conductive resin layer and the laminate can be suppressed more effectively, thereby improving deflection resistance. Furthermore, by dividing the cracks into those located at the interface between the laminate and the conductive resin layer, and those located at the interface between the base electrode layer and the conductive resin layer, the individual cracks can be made smaller, thereby ensuring greater strength for the external electrode 40. In addition, when stress is applied to the mounting surface from the substrate after mounting, the separated individual cracks propagate along the interface between the laminate and the conductive resin layer, and the interface between the base electrode layer and the conductive resin layer, respectively. These cracks connect with adjacent cracks, forming larger cracks that allow for greater stress release.

[0157] (9) In the multilayer ceramic capacitor 1 of this embodiment, the crack portion CP is formed to extend in the longitudinal direction L. As a result, external stress is directed in the longitudinal direction L along the crack portion, which suppresses the transmission of stress between the conductive resin layer and the laminate, thereby providing a multilayer ceramic capacitor 1 that can more effectively improve deflection resistance.

[0158] (10) In the multilayer ceramic capacitor 1 of this embodiment, when the external electrode 40 is viewed from the height direction T, the projected area Sc of the crack portion CP at the interface between the laminate 10 and the external electrode 40 is 10% or more of the area Sm of the interface between the laminate 10 and the external electrode 40. This makes it possible to suppress the transmission of stress between the conductive resin layer and the laminate over a wider area, thereby providing a multilayer ceramic capacitor 1 that can improve deflection resistance.

[0159] (11) In this embodiment, the multilayer ceramic capacitor 1 has a plurality of internal electrode layers 30, each having a lead-out portion 30B at one end that is drawn out to a first end face LS1 or a second end face LS2 and connected to an external electrode 40, and a facing portion 30A connected to the lead-out portion 30B and facing the other internal electrode layers 30. In a cross-sectional view perpendicular to the length direction L and the height direction T, the end on the outer side in the length direction L of both ends of the crack portion CP is positioned further out in the length direction L than the facing portion 30A. This ensures sufficient bonding strength, and because the crack portion is positioned further out in the length direction than the facing portion, it is possible to suppress the propagation of cracks from the crack portion into the internal electrode layers due to stress generated during mounting, and to suppress the transmission of stress between the conductive resin layer and the laminate, thereby more effectively improving deflection resistance.

[0160] (12) In this embodiment, the multilayer ceramic capacitor 1 has a plurality of internal electrode layers 30, each having a lead-out portion 30B at one end that is drawn out to a first end face LS1 or a second end face LS2 and connected to an external electrode 40, and a facing portion 30A connected to the lead-out portion 30B and facing the other internal electrode layers 30. In a cross-sectional view perpendicular to the length direction L and the height direction T, the end on the outer side in the length direction L of both ends of the crack portion CP is positioned further out in the length direction L than the first end face LS1 or the second end face LS2. As a result, the crack portion is positioned further out in the length direction than the laminate, so that the propagation of cracks from the crack portion to the internal electrode layers can be more reliably suppressed by the stress generated during mounting, and the transmission of stress between the conductive resin layer and the laminate can be suppressed, thereby more effectively improving deflection resistance.

[0161] (13) In the multilayer ceramic capacitor 1 of this embodiment, the multiple cracks CP are arranged to be aligned in the longitudinal direction L. As a result, before stress is applied, the multiple cracks are small, so strength can be ensured as external electrodes. After stress is applied, the cracks in the multiple cracks propagate in the longitudinal direction and connect to form a larger crack, which allows for greater stress relief. This suppresses the transmission of stress at the interface between the conductive resin layer and the laminate or plating layer, etc., and within the conductive resin layer, thereby improving deflection resistance.

[0162] Note that the configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 3. For example, the multilayer ceramic capacitor 1 may be a double-gang, triple-gang, or quadruple-gang multilayer ceramic capacitor as shown in Figures 15, 16, and 17.

[0163] The multilayer ceramic capacitor 1 shown in Figure 15 is a double-gang multilayer ceramic capacitor 1, and as an internal electrode layer 30, it includes a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that is not led out to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in Figure 16 is a triple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in Figure 17 is a quadruple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the voltage rating of the multilayer ceramic capacitor 1 can be increased. It goes without saying that the multilayer ceramic capacitor 1 in this embodiment may also have a multi-gang structure of four or more units.

[0164] The multilayer ceramic capacitor 1 may be a two-terminal type with two external electrodes, or a multi-terminal type with multiple external electrodes.

[0165] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the individual desirable configurations described in the above embodiments also constitutes the present invention.

[0166] 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 50 Underlay electrode layer 60 Conductive resin layer 70 Plating layer CP Crack CP1 Crack CP2 Crack CP2C Crack CP3 Crack CP4 Crack T Lamination direction (height direction) TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second side surface L Length direction LS1 First end surface LS2 Second end surface

Claims

1. A multilayer ceramic capacitor comprising: a plurality of stacked dielectric layers and a plurality of internal electrode layers disposed on the dielectric layers, wherein the laminate has a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction; and a pair of external electrodes disposed spaced apart from each other at each end of the laminate in the length direction, wherein the external electrodes comprise a base electrode layer containing a metal component, a conductive resin layer disposed on the base electrode layer containing filler powder and a resin component, and a plating layer disposed on the conductive resin layer, and at least a crack portion is disposed inside the conductive resin layer or in contact with the conductive resin layer.

2. The multilayer ceramic capacitor according to claim 1, wherein the crack portion is located at least on the first main surface side, inside the conductive resin layer, or in contact with the surface of the conductive resin layer.

3. The multilayer ceramic capacitor according to claim 2, wherein the crack portion is located at the interface between the laminate and the conductive resin layer.

4. The multilayer ceramic capacitor according to claim 2 or 3, wherein the crack portion is located inside the conductive resin layer.

5. The multilayer ceramic capacitor according to any one of claims 2 to 4, wherein the crack portion is located at the interface between the conductive resin layer and the plating layer.

6. The multilayer ceramic capacitor according to any one of claims 2 to 5, wherein the crack portion is located at the interface between the base electrode layer and the conductive resin layer.

7. The multilayer ceramic capacitor according to claim 2, wherein the crack portion comprises a first crack portion located at the interface between the laminate and the conductive resin layer, and a second crack portion located at the interface between the base electrode layer and the conductive resin layer, and the first crack portion and the second crack portion are in contact.

8. The multilayer ceramic capacitor according to claim 2, wherein the crack portion comprises a first crack portion located at the interface between the laminate and the conductive resin layer, and a second crack portion located at the interface between the base electrode layer and the conductive resin layer, and the first crack portion and the second crack portion are spaced apart.

9. The multilayer ceramic capacitor according to any one of claims 2 to 8, wherein the crack portion is formed to extend in the longitudinal direction.

10. When the external electrode is viewed from the height direction, the projected area Sc of the crack portion onto the interface between the laminate and the external electrode is 10% or more of the area Sm of the interface between the laminate and the external electrode, according to any one of claims 2 to 9.

11. The multilayer ceramic capacitor according to any one of claims 2 to 10, wherein the plurality of internal electrode layers each have a lead portion at one end that is drawn out to the first end face or the second end face and connected to the external electrode, and a facing portion connected to the lead portion and facing another internal electrode layer, wherein in a cross-sectional view perpendicular to the length and height directions, the end on the length direction of both ends of the crack portion that is on the length direction is positioned further outward in the length direction than the facing portion.

12. The multilayer ceramic capacitor according to any one of claims 2 to 10, wherein the plurality of internal electrode layers each have a lead-out portion at one end that is drawn out to the first end face or the second end face and connected to the external electrode, and a facing portion connected to the lead-out portion and facing another internal electrode layer, and in a cross-sectional view perpendicular to the length direction and the height direction, the end on the length direction of both ends of the crack portion that is on the length direction is positioned further outward in the length direction than the first end face or the second end face.

13. The multilayer ceramic capacitor according to any one of claims 2 to 12, wherein the multiple cracks are arranged to be aligned in the longitudinal direction.

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