Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor (1) which exhibits excellent solder wetting during mounting and which causes few soldering failures. This multilayer ceramic capacitor (1) comprises: a multilayer body (2) including a dielectric layer (20), a first internal electrode layer (31), and a second internal electrode layer (32); a first external electrode (41); and a second external electrode (42). The first external electrode (41) and the second external electrode (42) each have a Ni plating layer (63), and an Sn plating layer (66) positioned on the Ni plating layer (63). The number of Sn deposition particles 300 exposed from the surface of the Sn plating layer (66) is 1-10 inclusive, in a range of 30 μm within the surface.

Description

Multilayer ceramic capacitor

[0001] This invention relates to a multilayer ceramic capacitor.

[0002] In recent years, the increasing density of mounting has led to the miniaturization and multi-terminal development of electronic components. This has resulted in a problem of increased soldering defects.

[0003] In particular, for small chip-type electronic components (chips) with dimensions of 0.6 mm x 0.3 mm x 0.3 mm or less, the volume of the chip itself is small, which increases the number of chips processed in a batch of barrel plating during the plating process. As a result, variations in the thickness of the outermost plating layer of the external electrode increase.

[0004] Furthermore, when chip-type electronic components are multi-terminal, even if the number of chips processed in a batch is the same, variations in the film thickness of the outermost plating layer of the external electrodes within the same chip become large due to differences in terminal positions and conductivity / non-conductivity between terminals.

[0005] Large variations in the thickness of the outermost plating layer on the external electrodes can result in chips with thin plating layers. When the plating layer is thin, solder wetting during mounting becomes poor, leading to reduced solderability.

[0006] For example, if the plating layer consists of a Ni plating layer and a Sn plating layer, if the Ni plating layer becomes thin, solder erosion will occur during mounting. On the other hand, if the Sn plating layer becomes thin, a thick Ni-Sn alloy layer will form at the grain boundaries of the Sn plating layer during mounting. As a result, poor solder wetting will occur.

[0007] To solve these problems, Patent Document 1 discloses a technique for suppressing soldering defects by making the average particle size of the Sn plating layer, which is the outermost layer of the external electrode, larger than the film thickness, and setting the relative strength of the crystal orientation plane to 4% or more and 40% or less.

[0008] Japanese Patent Publication No. 2013-206898

[0009] However, when chip-type electronic components are small chips with dimensions of 0.6 mm x 0.3 mm x 0.3 mm or less, the deposited particles become smaller due to the plating process. As a result, the proportion of grain boundaries increases on the surface of the Sn plating layer. Oxidation is more likely to progress at grain boundaries, for example, in humid environments. Therefore, if there are many grain boundaries on the surface of the Sn plating layer, the oxidized area increases. As a result, solderability decreases.

[0010] Furthermore, it is difficult to control the oxidation state of grain boundaries on the surface of the Sn plating layer. As a result, variations occur in the oxidation state of grain boundaries on the Sn plating surface of the opposing external electrode. Consequently, mounting defects such as the tombstone phenomenon are more likely to occur.

[0011] Therefore, the present invention aims to provide a multilayer ceramic capacitor that exhibits good solder wetting during mounting and has fewer soldering defects.

[0012] The multilayer ceramic capacitor of the present invention comprises a laminate including a plurality of stacked dielectric layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, disposed on the plurality of dielectric layers and exposed on the first end surface, and a second internal electrode layer disposed on the plurality of dielectric layers and exposed on the second end surface, and a first external electrode connected to the first internal electrode layer and disposed on the first end surface, and a second external electrode connected to the second internal electrode layer and disposed on the second end surface, wherein the first external electrode and the second external electrode are Ni plated layers and Sn plated layers located on the Ni plated layers, and the number of Sn deposited particles exposed from the surface in a 30 μm range on the surface of the Sn plated layer is 1 to 10.

[0013] According to the present invention, it is possible to provide a multilayer ceramic capacitor that exhibits good solder wetting during mounting and has fewer soldering defects.

[0014] Figure 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 2 is a cross-sectional view taken along line 101-101 of Figure 1. Figure 3 is a cross-sectional view taken along line 102-102 of Figure 1. Figure 4 is a cross-sectional view taken along line 103-103 of Figure 1. Figure 5A is a diagram corresponding to the cross-sectional view taken along line 101-101 of Figure 1, showing an example of the arrangement of the floating internal electrode layer. Figure 5B is a diagram corresponding to the cross-sectional view taken along line 101-101 of Figure 1, showing another example of the arrangement of the floating internal electrode layer. Figure 5C is a diagram corresponding to the cross-sectional view taken along line 101-101 of Figure 1, showing another example of the arrangement of the floating internal electrode layer. Figure 6 is a cross-sectional view of the external electrode of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 7 is a cross-sectional view of the external electrode of another example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 8 is a cross-sectional view of the external electrode of another example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 9 is a view of the first main surface of the multilayer ceramic capacitor in the height direction. Figure 10 is a table showing the number of Sn deposited particles and the mounting defect rate.

[0015] (Multilayer Ceramic Capacitor) A multilayer ceramic capacitor 1 according to one embodiment of the present disclosure will be described with reference to the drawings. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 according to an embodiment of the present disclosure.

[0016] As shown in Figure 1, the shape of the multilayer ceramic capacitor 1 is approximately a rectangular parallelepiped. The multilayer ceramic capacitor 1 consists of a laminate 2 and an external electrode 40. The shape of the laminate 2 is approximately a rectangular parallelepiped.

[0017] The external electrode 40 consists of a first external electrode 41 and a second external electrode 42. The external electrodes 40 are positioned at opposite ends of the laminate 2, separated from each other. The external electrode 40 positioned at one end is the first external electrode 41. The external electrode 40 positioned at the other end is the second external electrode 42.

[0018] (Laminate) The laminate 2 will be described with reference to Figure 1, as well as Figures 2, 3, and 4. Figure 2 is a cross-sectional view taken along line 101-101 of Figure 1. Figure 3 is a cross-sectional view taken along line 102-102 of Figure 1. Figure 3 shows the first internal electrode layer 31. Figure 4 is a cross-sectional view taken along line 103-103 of Figure 1.

[0019] As shown in Figure 2, the laminate 2 is composed of dielectric layers 20 and internal electrode layers 30. Multiple dielectric layers 20 and multiple internal electrode layers 30 are stacked on top of each other. The internal electrode layer 30 is composed of a first internal electrode layer 31 and a second internal electrode layer 32.

[0020] The directions in the multilayer ceramic capacitor 1 and the laminate 2 are described below. As shown in Figure 2, the direction in which the dielectric layer 20 and the internal electrode layer 30 are stacked is defined as the height direction T. In the multilayer ceramic capacitor 1, the direction that intersects the height direction T and in which the first external electrode 41 and the second external electrode 42 face each other is defined as the length direction L. The direction that intersects both the height direction T and the length direction L is defined as the width direction W. Note that the height direction T is sometimes also called the stacking direction.

[0021] In this embodiment, the height direction T, the length direction L, and the width direction W are mutually orthogonal. The height direction T, the length direction L, and the width direction W are the same directions as described above in figures other than Figure 2.

[0022] Regarding the cross-section of the multilayer ceramic capacitor 1 or the laminate 2, the cross-section parallel to the length direction L and the height direction T is defined as the LT cross-section. Regarding the cross-section of the multilayer ceramic capacitor 1 or the laminate 2, the cross-section parallel to the length direction L and the width direction W is defined as the LW cross-section. Regarding the cross-section of the multilayer ceramic capacitor 1 or the laminate 2, the cross-section parallel to the width direction W and the height direction T is defined as the WT cross-section.

[0023] Figure 2 shows the LT cross-section of the multilayer ceramic capacitor 1. Figure 3 shows the LW cross-section of the multilayer ceramic capacitor 1. Figure 4 shows the WT cross-section of the multilayer ceramic capacitor 1.

[0024] Two surfaces of the laminate 2 facing each other in the height direction T are defined as the first main surface 3 and the second main surface 4. Two surfaces of the laminate 2 facing each other in the width direction W are defined as the first side surface 5 and the second side surface 6. Two surfaces of the laminate 2 facing each other in the length direction L are defined as the first end surface 7 and the second end surface 8.

[0025] The portions where two surfaces of the laminate 2 intersect are defined as edges. The portions where three surfaces of the laminate 2 intersect are defined as corners. It is preferable that the corners and edges are rounded. The rectangular parallelepiped shape of the laminate 2 includes the shape of a rectangular parallelepiped in which the edges and corners are rounded. Furthermore, the rectangular parallelepiped shape of the laminate 2 includes all members having a first main surface 3, a second main surface 4, a first side surface 5, a second side surface 6, a first end surface 7, and a second end surface 8. In addition, some or all of the main surfaces, side surfaces, and end surfaces may have irregularities or other features formed on them.

[0026] As shown in Figure 2, the central position of the laminated body 2 in the height direction T is defined as the height direction center 111. The central position of the laminated body 2 in the length direction L is defined as the length direction center 112. The central position of the laminated body 2 in the width direction W is defined as the width direction center 113.

[0027] (Dielectric layer) The total number of dielectric layers 20 included in the laminate 2 is preferably 15 to 700.

[0028] An example of a ceramic material included in the dielectric layer 20 is BaTiO ３ CaTiO ３ SrTiO ３ CaZrO ３ These are dielectric ceramics whose main components are these elements. The ceramic material may also have minor components such as Mg, Mn, Si, Ni, Fe, Cr, Co, or compounds containing these elements added to these main components.

[0029] The multilayer ceramic capacitor described in this embodiment is an example of a multilayer ceramic electronic component. When a piezoelectric ceramic is used in the multilayer structure, the multilayer ceramic electronic component functions as a ceramic piezoelectric element. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) based ceramic materials.

[0030] Furthermore, when semiconductor ceramics are used in the laminate, the multilayer ceramic electronic component functions as a thermistor element. Specific examples of semiconductor ceramic materials include spinel-based ceramic materials.

[0031] Furthermore, when magnetic ceramics are used in the laminate, the multilayer ceramic electronic component functions as an inductor element.

[0032] Furthermore, when multilayer ceramic electronic components function as inductors, the internal electrode layers become coil-shaped conductors. Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0033] The thickness of the dielectric layer 20 is preferably, for example, 0.5 μm or more and 10 μm or less.

[0034] The dimensions of the laminate 2 are not particularly limited. The length L of the laminate 2 can be, for example, 0.2 mm or more and 10 mm or less. The width W of the laminate 2 can be, for example, 0.1 mm or more and 10 mm or less. The height T of the laminate 2 can be, for example, 0.1 mm or more and 5 mm or less.

[0035] (Internal Electrode Layer) The internal electrode layer 30 will now be described. As mentioned above, the internal electrode layer 30 is composed of a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The internal electrode layer 30 exposed on the first end face 7 is defined as the first internal electrode layer 31. The internal electrode layer 30 exposed on the second end face 8 is defined as the second internal electrode layer 32.

[0036] The first internal electrode layer 31 is exposed on the first end face 7, but not on the first main surface 3, the second main surface 4, the first side surface 5, the second side surface 6, and the second end face 8. The second internal electrode layer 32 is exposed on the second end face 8, but not on the first main surface 3, the second main surface 4, the first side surface 5, the second side surface 6, and the first end face 7.

[0037] Furthermore, the ends of the first internal electrode layer 31 and the second internal electrode layer 32 may be positioned slightly recessed from the first end face 7 or the second end face 8.

[0038] Inside the laminate 2, a plurality of substantially rectangular first internal electrode layers 31 and second internal electrode layers 32 are alternately arranged at equal intervals along the height direction T. Each of the first internal electrode layer 31 and the second internal electrode layer 32 is substantially parallel to the first main surface 3 and the second main surface 4. The first internal electrode layer 31 and the second internal electrode layer 32 face each other via the dielectric layer 20 in the height direction T.

[0039] The first internal electrode layer 31 is composed of a first opposing portion 33 and a first lead-out portion 35. A portion of the first internal electrode layer 31 that faces the second internal electrode layer 32 is defined as the first opposing portion 33. A portion of the first internal electrode layer 31 that is drawn out from the first opposing portion 33 to the first end face 7 is defined as the first lead-out portion 35. Similarly, the second internal electrode layer 32 is composed of a second opposing portion 34 and a second lead-out portion 36. A portion of the second internal electrode layer 32 that faces the first internal electrode layer 31 is defined as the second opposing portion 34. A portion of the second internal electrode layer 32 that is drawn out from the second opposing portion 34 to the second end face 8 is defined as the second lead-out portion 36.

[0040] The shape of the first opposing portion 33 is not particularly limited. The shape of the first opposing portion 33 is preferably rectangular. The corner portion of the first opposing portion 33 can be formed in a rounded shape, and the corner portion of the first opposing portion 33 can be formed obliquely in a tapered shape. Similarly, the shape of the second opposing portion 34 is not particularly limited. The shape of the second opposing portion 34 is preferably rectangular. The corner portion of the second opposing portion 34 can be formed in a rounded shape, and the corner portion of the second opposing portion 34 can be formed obliquely in a tapered shape. The taper may have an inclination in thickness toward the end.

[0041] The shape of the first lead-out portion 35 is not particularly limited. The shape of the first lead-out portion 35 is preferably rectangular. The corner portion of the first lead-out portion 35 can be formed by rounding, and the corner portion of the first lead-out portion 35 can be formed obliquely in a tapered shape. Similarly, the shape of the second lead-out portion 36 is not particularly limited. The shape of the second lead-out portion 36 is preferably rectangular. The corner portion of the second lead-out portion 36 can be formed by rounding, and the corner portion of the second lead-out portion 36 can be formed obliquely in a tapered shape. The taper may have an inclination in thickness toward the end.

[0042] The corner portion refers to the portion located at the corner of the outer shape of the internal electrode layer 30 when the internal electrode layer 30 is viewed in a cross-section in the length direction L and the width direction W.

[0043] The width of the first opposing portion 33 in the width direction W and the width of the first lead-out portion 35 in the width direction W may be the same width, or either width may be narrower. The width of the second opposing portion 34 in the width direction W and the width of the second lead-out portion 36 in the width direction W may be the same width, or either width may be narrower.

[0044] The internal electrode layer 30 contains at least one of Ni, Cu, Ag, Pd, Ag-Pd alloy, and Au. The main component of the internal electrode layer 30 is preferably Ni.

[0045] The metal constituting the internal electrode layer 30 forms a compound with the metal contained in the external electrode 40 or the metal constituting the conductive filler contained in the external electrode 40.

[0046] The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 15 or more and 200 or less.

[0047] The thickness of the first internal electrode layer 31 and the thickness of the second internal electrode layer 32 are preferably, for example, 0.2 μm or more and 2.0 μm or less.

[0048] (Division in the height direction) The division of the laminate 2 in the height direction T will now be explained. As shown in Figures 2 and 4, the laminate 2 can be divided into an inner layer 10 and an outer layer 11 along the height direction T. The outer layer 11 consists of a first outer layer 12 and a second outer layer 13.

[0049] (Inner layer) In the height direction T, the portion of the laminate 2 located between the position of the internal electrode layer closest to the first main surface 3 and the position of the internal electrode layer closest to the second main surface 4 is defined as the inner layer 10.

[0050] More specifically, the inner layer 10 is a portion in which the first internal electrode layer 31 and the second internal electrode layer 32 and the dielectric layer 20 are alternately stacked, and refers to the portion from the first internal electrode layer 31 or the second internal electrode layer 32 closest to the first main surface 3 to the first internal electrode layer 31 or the second internal electrode layer 32 closest to the second main surface 4.

[0051] (Outer layer) In the height direction T, the portion of the laminate 2 located between the position of the inner electrode layer closest to the first main surface 3 and the first main surface 3 is defined as the first outer layer 12. The first outer layer 12 is the portion of the laminate 2 located between the inner layer 10 and the first main surface 3.

[0052] In the height direction T, the portion of the laminate 2 located between the position of the inner electrode layer closest to the second main surface 4 and the second main surface 4 is defined as the second outer layer portion 13. The second outer layer portion 13 is the portion of the laminate 2 located between the inner layer portion 10 and the second main surface 4.

[0053] In other words, the outer layer 11 is the portion that sandwiches the inner layer 10 in the height direction T. The dielectric layer 20 that constitutes the outer layer 11 is, in particular, made of BaTiO as the main material. ３ or CaZrO ３ It is preferable that it contains [a certain element], and it is also preferable that it contains Si, V, Mn, Mg, or Ni as an additive.

[0054] (Division in the width direction) The division of the laminate 2 in the width direction W will now be explained. As shown in Figures 3 and 4, the laminate 2 can be divided along the width direction W into a core portion 25 and a side gap 14. The side gap 14 consists of a first side gap 15 and a second side gap 16.

[0055] (Core portion) In the width direction W, the portion of the laminate 2 in which the internal electrode layer 30 is provided is defined as the core portion 25.

[0056] (Side gap) In the width direction W, the portion of the laminate 2 located between the core portion 25 and the first side surface 5 is defined as the first side gap 15. In the width direction W, the portion of the laminate 2 located between the core portion 25 and the second side surface 6 is defined as the second side gap 16. No internal electrode layer is provided in the side gap 14. Only the dielectric layer 20 is provided in the side gap 14. The side gap is also called a W gap or side gap.

[0057] (Sectionalization of the core) The sectionalization of the core 25 in the height direction T will now be explained. As shown in Figure 4, the core 25 can be divided into an effective section 26 and an ineffective section 27 along the height direction T. The ineffective section 27 consists of a first ineffective section 28 and a second ineffective section 29.

[0058] (Effective portion) In the height direction T, the portion of the core 25 in which the first internal electrode layer 31 or the second internal electrode layer 32 is arranged is defined as the effective portion 26. That is, the effective portion 26 refers to the portion of the core 25 from the internal electrode layer 30 closest to the first main surface 3 to the internal electrode layer 30 closest to the second main surface 4. The effective portion 26 in the multilayer ceramic capacitor 1 provided with the floating internal electrode layer 38, which will be described later, will be defined later.

[0059] (Inactive parts) In the height direction T, the portion of the core 25 located between the effective part 26 and the first main surface 3 is defined as the first inactive part 28. In the height direction T, the portion of the core 25 located between the effective part 26 and the second main surface 4 is defined as the second inactive part 29. The inactive part 27 does not have an internal electrode layer 30. The inactive part 27 is provided only with a dielectric layer 20.

[0060] (Opposite electrode portion) The portion where the first internal electrode layer 31 and the second internal electrode layer 32 overlap is defined as the opposite electrode portion 37. In the opposite electrode portion 37, the first opposing portion 33 and the second opposing portion 34 overlap. In the multilayer ceramic capacitor 1, capacitance is formed when the opposing portions of the internal electrode layers 30 face each other via the dielectric layer 20. That is, capacitance is formed in the opposite electrode portion 37. Capacitance is expressed in the multilayer ceramic capacitor 1 due to this capacitance.

[0061] (End Face Gap) The end face gap 17 will be described with reference to Figures 2 and 3. In the laminate 2, the portion located between the electrode facing portion 37 and the end face, and including the pull-out portion of either the first internal electrode layer 31 or the second internal electrode layer 32, is defined as the end face gap 17. The end face gap 17 is also called the L gap.

[0062] The end face gap 17 is composed of a first end face gap 18 and a second end face gap 19. The portion located between the electrode facing portion 37 and the first end face 7, including the first lead-out portion 35, is defined as the first end face gap 18. Similarly, the portion located between the electrode facing portion 37 and the second end face 8, including the second lead-out portion 36, is defined as the second end face gap 19.

[0063] (Floating Internal Electrode Layer) The floating internal electrode layer 38 will be described with reference to Figures 5A to 5C. Figures 5A to 5C correspond to the cross-sectional view along line 102-102 in Figure 1. However, the external electrode 40 is not shown in Figures 5A to 5C.

[0064] An internal electrode layer 30 that is not drawn out to either the first end face 7 or the second end face 8 is defined as a floating internal electrode layer 38. As shown in Figures 5A to 5C, a floating internal electrode layer 38 may be formed as the internal electrode layer 30 in the laminate 2.

[0065] (Floating electrode opposing portion) The floating electrode opposing portion 39 is defined as the portion where the floating internal electrode layers 38 face each other in the height direction T, the portion where the floating internal electrode layer 38 and the first internal electrode layer 31 face each other in the height direction T, and the portion where the floating internal electrode layer 38 and the second internal electrode layer 32 face each other in the height direction T.

[0066] In the example shown in Figures 5A to 5C, no electrode opposing portion 37 is formed where the first internal electrode layer 31 and the second internal electrode layer 32 face each other in the height direction T. However, in the example shown in Figures 5A to 5C, a floating electrode opposing portion 39 is formed. Multiple floating electrode opposing portions 39 may be formed in the length direction L. The formation of the floating electrode opposing portions 39 creates capacitance in the multilayer ceramic capacitor 1.

[0067] In the example shown in Figure 5A, the first internal electrode layer 31 and the second internal electrode layer 32 are formed in the same layer. A floating internal electrode layer 38 is formed between the layer in which the first internal electrode layer 31 and the second internal electrode layer 32 are formed and another layer in which the first internal electrode layer 31 and the second internal electrode layer 32 are formed.

[0068] In the example shown in Figure 5B, a floating internal electrode layer 38 is formed in both the layer where the first internal electrode layer 31 is formed and the layer where the second internal electrode layer 32 is formed.

[0069] In the example shown in Figure 5C, the first internal electrode layer 31 and the second internal electrode layer 32 are formed in the same layer. A floating internal electrode layer 38 is formed in the layer in which the first internal electrode layer 31 and the second internal electrode layer 32 are formed. In addition, a floating internal electrode layer 38 is formed between the layer in which the first internal electrode layer 31 and the second internal electrode layer 32 are formed and another layer in which the first internal electrode layer 31 and the second internal electrode layer 32 are formed. The floating internal electrode layer 38 is not limited to being formed in two consecutive rows in the same layer along the length L, as shown in Figure 5C. Needless to say, structures in which three, four, or five or more rows are formed are also possible.

[0070] As shown in Figures 5A to 5C, by forming a floating internal electrode layer 38, a structure can be realized in which the floating electrode opposing portion 39 is divided and arranged in multiple parts. This structure forms multiple capacitor components between the internal electrode layers 30 facing each other in the height direction T. The formed capacitor components are then connected in series. As a result, the voltage applied to each capacitor component becomes lower, and the voltage withstand capability of the multilayer ceramic capacitor 1 can be increased.

[0071] (Effective portion) The effective portion 26 in the multilayer ceramic capacitor 1 in which the floating internal electrode layer 38 is formed is as follows. Specifically, in the core portion 25, the effective portion 26 is defined as the portion in which the first internal electrode layers connected to the first external electrode are arranged facing each other in the height direction, the portion in which the second internal electrode layers connected to the second external electrode are arranged facing each other in the height direction, the portion in which the first internal electrode layer 31 or the second internal electrode layer 32 and the floating internal electrode layer 38 are arranged facing each other in the height direction T, and the portion in which the floating internal electrode layers 38 are arranged facing each other in the height direction T. In other words, the effective portion 26 refers to the portion in the core portion 25 from the internal electrode layer 30 closest to the first main surface 3 to the internal electrode layer 30 closest to the second main surface 4.

[0072] (External Electrode) The external electrode 40 consists of a first external electrode 41 and a second external electrode 42. The external electrode 40 that is positioned on the first end face 7 and connected to the first internal electrode layer 31 is defined as the first external electrode 41. In addition to the first end face 7, the first external electrode 41 may be positioned on a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6. In this embodiment, the first external electrode 41 is positioned to extend from the first end face 7 to a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6.

[0073] An external electrode 40 positioned on the second end face 8 and connected to the second internal electrode layer 32 is defined as the second external electrode 42. The second external electrode 42 may be positioned not only on the second end face 8, but also on a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6. In this embodiment, the second external electrode 42 is positioned to extend from the second end face 8 to a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6.

[0074] The external electrode 40 is composed of a base electrode layer 50 and a plating layer 60. The base electrode layer 50 constituting the first external electrode 41 is defined as the first base electrode layer 51. The base electrode layer 50 constituting the second external electrode 42 is defined as the second base electrode layer 52.

[0075] The plating layer 60 constituting the first external electrode 41 is defined as the first plating layer 61. The plating layer 60 constituting the second external electrode 42 is defined as the second plating layer 62.

[0076] The base electrode layer 50 may include at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0077] (Underlayment electrode layer) The following describes the case where the underlayment electrode layer 50 is a baked layer. The baked layer contains glass components and metals. The glass components include at least one element such as B, Si, Ba, Mg, Al, and Li. The metal components include at least one such element such as Cu, Ni, Ag, Pd, Ag-Pd alloy, and Au.

[0078] The baked layer may consist of multiple layers. The baked layer is formed by applying a conductive paste containing glass components and metal to the laminate 2 and baking it. The baking process can be performed simultaneously with the baking of the internal electrode layer 30 and the dielectric layer 20, or after their baking. When the baked layer is baked simultaneously with the baking of the internal electrode layer and the dielectric layer, it is preferable to add a dielectric material instead of glass components to form the baked layer.

[0079] The thickness in the length direction L at the center 111 in the height direction of the baked layer located at the first end face 7 and the second end face 8 is preferably, for example, 10 μm or more and 150 μm or less.

[0080] Furthermore, when a baking layer as a base electrode layer 50 is formed on a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6, the thickness in the height direction T at the central position in the length direction L of the base electrode layer 50 located on the first main surface 3, the second main surface 4, the first side surface 5, and the second side surface 6 is preferably, for example, 3 μm or more and 40 μm or less.

[0081] (Conductive resin layer) The base electrode layer 50 may be composed of a baked layer and a conductive resin layer. In this case, the base electrode layer 50 has a two-layer structure in which the baked layer and the conductive resin layer are laminated in order. The conductive resin layer is arranged, for example, to cover the base electrode layer 50.

[0082] Specifically, the conductive resin layer is placed on the base electrode layer 50 located on the first end face 7 and the second end face 8. Preferably, the conductive resin layer is placed so as to extend to the base electrode layer 50 located on the first main surface 3, the second main surface 4, the first side surface 5, and the second side surface 6. However, the conductive resin layer may be placed only on the base electrode layer 50 located on the first end face 7 and the second end face 8.

[0083] The conductive resin layer is more flexible than the baked-on layer because it contains resin and metal. The conductive resin layer functions as a buffer layer. Therefore, even if flexural stress is applied to the mounting substrate and a physical force is applied to the multilayer ceramic capacitor 1 due to this stress, cracks are less likely to occur in the multilayer ceramic capacitor 1.

[0084] Furthermore, even when forces caused by thermal cycling act on the multilayer ceramic capacitor 1, cracks are less likely to occur in the multilayer ceramic capacitor 1.

[0085] The resin contained in the conductive resin layer is preferably a thermosetting resin such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is one of the suitable resins because it has excellent heat resistance, moisture resistance, and adhesion. In addition, multiple types of resins, such as epoxy resin and phenolic resin, can be used in the conductive resin layer.

[0086] The conductive resin layer preferably contains a curing agent in addition to the resin. When epoxy resin is used as the resin, the curing agent is preferably a compound such as a phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, or amide-imide-based compound.

[0087] The conductive resin layer contains metal. The presence of metal in the conductive resin layer makes it electrically conductive. The metal contained in the conductive resin layer is included in the conductive resin layer as metal powder, i.e., conductive filler. The shape of the conductive filler is, for example, flattened. Contact between conductive fillers creates an electrical pathway within the conductive resin layer. This formed electrical pathway makes the conductive resin layer electrically conductive.

[0088] The metal contained in the conductive resin layer is preferably Ag, Cu, Ni, Sn, Bi, or an alloy containing these. The metal is particularly preferably Ag. The Ag may be pure Ag, or the Ag may be an alloy containing Ag. For example, the metal is preferably at least one of Ag, Ag-coated Cu, Ag-coated Ni, and Ag-coated alloy powder.

[0089] When using a material in which the surface of the metal powder is coated with Ag, it is preferable to use copper powder or Ni powder as the metal powder. Antioxidant treated Cu can also be used. The reason for using Ag-coated metal is that it allows for the use of an inexpensive metal as the base material while maintaining the properties of Ag.

[0090] The metal content in the conductive resin layer is preferably 35 vol% to 75 vol% relative to the total volume of the conductive resin layer. The shape of the conductive filler is not limited to the flattened shape described above, and may be spherical or other shapes. Furthermore, a mixture of spherical metal powder and flattened metal powder can be used. The average particle size of the conductive filler is also not particularly limited, but is preferably, for example, 0.3 μm to 10 μm.

[0091] The thickness of the conductive resin layer is preferably 10 μm or more and 200 μm or less.

[0092] Furthermore, the base electrode layer 50 may consist only of a conductive resin layer and not include a baking layer. In other words, it is also possible to form a conductive resin layer directly on the laminate 2 without forming a baking layer.

[0093] If the underlying electrode layer 50 is a thin film layer, the thin film layer can be formed by a thin film formation method such as sputtering or vapor deposition, and can be a layer of 1 μm or less in thickness on which metal particles are deposited.

[0094] (Plating layer) The first plating layer 61 is arranged to cover the first base electrode layer 51. The second plating layer 62 is arranged to cover the second base electrode layer 52.

[0095] The material of the plating layer 60 includes at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, and Au.

[0096] The plating layer 60 may be composed of multiple layers. In this embodiment, the first plating layer 61 and the second plating layer 62 are each composed of two plating layers. When the plating layer 60 is composed of two layers, preferably one layer is a Ni plating layer 63 and the other layer is a Sn plating layer 66.

[0097] The Ni plating layer 63 included in the first plating layer 61 is defined as the first Ni plating layer 64. The Ni plating layer 63 included in the second plating layer 62 is defined as the second Ni plating layer 65.

[0098] The Sn plating layer 66 included in the first plating layer 61 is defined as the first Sn plating layer 67. The Sn plating layer 66 included in the second plating layer 62 is defined as the second Sn plating layer 68.

[0099] The Ni plating layer 63 prevents the underlying electrode layer 50 from being eroded by the solder when mounting the multilayer ceramic capacitor 1.

[0100] The Sn plating layer 66 improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. The formation of the Sn plating layer 66 makes mounting easier.

[0101] Based on the above, it is preferable to have a Ni plating layer 63 and a Sn plating layer 66 in order from the plating layer 60 in contact with the base electrode layer 50. The plating layer 60 may consist of three or more layers. The main component of the plating layer 60 may be a metal species other than Ni and Sn.

[0102] The preferred thickness of each layer of the plating layer 60 is 1 μm or more and 10 μm or less.

[0103] The external electrode 40 may be formed using only the plating layer without providing the underlayer electrode layer 50. The following describes a structure in which the plating layer is provided without providing the underlayer electrode layer 50.

[0104] The first external electrode 41 and the second external electrode 42 may each have no underlying electrode layer 50, and the plating layer may be formed directly on the surface of the laminate 2. That is, the multilayer ceramic capacitor 1 may have a structure that includes a plating layer electrically connected to the first internal electrode layer 31 or the second internal electrode layer 32. In such a structure, the plating layer may be formed after a catalyst is placed on the surface of the laminate 2 as a pretreatment.

[0105] The plating layer preferably includes a lower plating electrode formed on the surface of the laminate 2 and an upper plating electrode formed on the surface of the lower plating electrode.

[0106] Preferably, the lower plated electrode and the upper plated electrode each contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such metal.

[0107] The lower layer plating electrode is preferably formed using Ni, which has solder barrier properties. Furthermore, the upper layer plating electrode is preferably formed using Sn or Au, which have good solder wettability.

[0108] Furthermore, for example, when the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni, it is preferable that the lower plated electrode be formed using Cu, which has good bonding properties with Ni. The upper plated electrode may be formed as needed, and the first external electrode 41 and the second external electrode 42 may each consist only of the lower plated electrode.

[0109] The plating layer may have the upper plating electrode as the outermost layer. Alternatively, other plating electrodes may be formed on the surface of the upper plating electrode within the plating layer.

[0110] The thickness of each plating layer, which is placed without an undercoat electrode layer, is preferably 1 μm or more and 15 μm or less.

[0111] The plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0112] (Dimensions of Multilayer Ceramic Capacitors) The dimensions of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes, will be described below. The dimension in the length direction L is defined as the L dimension. The L dimension of the multilayer ceramic capacitor 1 can be, for example, 0.2 mm or more and 10.0 mm or less. Preferably, the L dimension of the multilayer ceramic capacitor 1 is 3.0 mm or less, and more preferably 0.2 mm or less.

[0113] The dimension in the height direction T is defined as dimension T. The dimension T of the multilayer ceramic capacitor 1 can be, for example, 0.1 mm or more and 5.0 mm or less. Preferably, the dimension T of the multilayer ceramic capacitor 1 is 1.5 mm or less, and more preferably 0.1 mm or less.

[0114] The dimension in the width direction W is defined as the W dimension. The W dimension of the multilayer ceramic capacitor 1 can be, for example, 0.1 mm or more and 10.0 mm or less. Preferably, the W dimension of the multilayer ceramic capacitor 1 is 1.5 mm or less, and more preferably 0.1 mm or less.

[0115] The L dimension of the multilayer ceramic capacitor 1 can be made larger than the W and T dimensions of the multilayer ceramic capacitor 1.

[0116] (Precipitated Particles) In the multilayer ceramic capacitor 1 of this embodiment, the number of Sn precipitated particles on the surface of the Sn plating layer 66 is within a predetermined range. A region having a specific crystal orientation contained within the Sn plating layer 66 is defined as a precipitated particle. A precipitated particle is synonymous with a single crystalline region, i.e., a grain. This will be explained with reference to Figures 6 and 7. Figures 6 and 7 are cross-sectional views of the external electrode 40 of the multilayer ceramic capacitor 1 of the embodiment of the present invention, showing a cross section parallel to the length direction L and the height direction T, i.e., an LT cross section.

[0117] In this application, Sn precipitate particles in the Sn plating layer 66 are defined as Sn precipitate particles 300. The range for observing the external electrode 40 is defined as the observation range 260. In this embodiment, the Sn plating layer 66 on the external electrode 40 is observed in particular.

[0118] The length of the observation range 260 is defined as the observation range length 251. The observation range length 251 is the length of the observation range 260 in a direction perpendicular to the thickness direction of the external electrode 40. In the example shown in Figure 6, the observation range length 251 is the length of the observation range 260 in a direction parallel to the height direction T.

[0119] The number of Sn precipitate particles 300 observed within an observation range 260 with a predetermined observation range length 251 is defined as the number of Sn precipitate particles.

[0120] In the Sn plating layer 66, the surface on the side that does not come into contact with the Ni plating layer 63 is defined as the Sn plating layer surface 240.

[0121] In the following explanation, the observation range length 251 is assumed to be 30 μm. In the example shown in Figure 6, one Sn precipitate particle 300 is observed on the Sn plating layer surface 240 of the Sn plating layer 66 in the observation range 260 where the observation range length 251 is 30 μm. The observation of an Sn precipitate particle 300 on the Sn plating layer surface 240 means that an Sn precipitate particle 300 exposed from the Sn plating layer surface 240 is observed. In the example shown in Figure 6, there is one Sn precipitate particle.

[0122] Furthermore, as shown in Figure 2, the observation range 260 is located in the central part of the height direction T in the LT cross section. In other words, the observation range 260 is positioned and observed such that its center is located at the center 111 in the height direction in either the LT or WT cross section.

[0123] Furthermore, the observation of Sn precipitate particles 300 means that at least a portion of the Sn precipitate particles 300 are observed within the observation range 260. Even if only a portion of the Sn precipitate particles 300 are observed within the observation range 260, the Sn precipitate particles 300 are still considered to be observed. Sn precipitate particles 300 that are only partially observed are also included in the number of Sn precipitate particles.

[0124] In the example shown in Figure 7, similar to Figure 6, four Sn precipitate particles 300 are observed on the Sn plated layer surface 240 of the Sn plated layer 66 within an observation range with an observation range length 251 of 30 μm. The number of Sn precipitate particles in the example shown in Figure 7 is four.

[0125] In the multilayer ceramic capacitor 1 of this embodiment, the number of Sn deposited particles in a 30 μm range on the surface of the Sn plating layer 66 is between 1 and 10. As a result, the multilayer ceramic capacitor of this embodiment exhibits good solder wetting during mounting, and provides a multilayer ceramic capacitor 1 with fewer soldering defects.

[0126] (Particles and grain boundaries) The interface between adjacent Sn precipitate particles 300 is defined as an Sn grain boundary 301. An Sn grain boundary 301 refers to the interface between Sn precipitate particles 300.

[0127] The Sn plating layer 66 includes Sn precipitated particles 300 and Sn grain boundaries 301.

[0128] (Capacitor size and particle size) As the size of the multilayer ceramic capacitor 1 decreases, the particle size of the Sn precipitate particles 300 contained in the Sn plating layer 66 decreases due to the plating process. As the particle size of the Sn precipitate particles 300 decreases, the ratio of Sn grain boundaries 301 in the Sn plating layer 66 increases. The ratio of Sn grain boundaries 301 refers to the length of the Sn grain boundaries 301 contained within a predetermined range of the Sn plating layer 66 when viewing a cross-section of the Sn plating layer 66, as shown in Figure 6.

[0129] Regarding the size of the multilayer ceramic capacitor 1, a size where the L dimension × T dimension × W dimension is 0.6 mm × 0.3 mm × 0.3 mm or less is defined as a small size. In particular, in small-sized multilayer ceramic capacitors 1, the particle size of the Sn deposited particles 300 in the Sn plating layer 66 becomes smaller. As a result, the ratio of Sn grain boundaries 301 increases.

[0130] When the multilayer ceramic capacitor 1 is small in size, the self-plating effect between the multilayer ceramic capacitors 1 decreases during barrel plating. As a result, the growth of Sn precipitate particles 300 becomes more difficult during Sn plating. Consequently, the particle size of the Sn precipitate particles 300 decreases. When the particle size of the Sn precipitate particles 300 decreases, the proportion of Sn grain boundaries 301 increases.

[0131] (Installation defects) When the ratio of Sn grain boundaries 301 increases in the vicinity of the Sn plating layer 66, particularly the Sn plating layer surface 240, installation defects are more likely to occur.

[0132] (Solderability) As mentioned above, oxidation of Sn is particularly likely to occur at Sn grain boundaries 301 in humid environments. Therefore, if there are many Sn grain boundaries 301 near the surface 240 of the Sn plating layer, the area where Sn is oxidized increases. The area where Sn is oxidized has lower solder wettability than the area where Sn is not oxidized. Therefore, in the Sn plating layer 66 with many areas where Sn is oxidized, solderability decreases. As a result, mounting defects are more likely to occur. Note that in the following explanation, oxidation of Sn grain boundaries 301 may be referred to as grain boundary oxidation.

[0133] Regarding the size of the multilayer ceramic capacitor 1, a size where the L x T x W dimensions are 0.25 mm x 0.125 mm x 0.125 mm or less is defined as ultra-miniature size. The decrease in solderability is more likely to become apparent in ultra-miniature multilayer ceramic capacitors 1, even among small-sized multilayer ceramic capacitors 1. This is because as the size of the multilayer ceramic capacitor 1 becomes smaller, the proportion of Sn grain boundaries 301 tends to increase, and the region where Sn is oxidized expands further.

[0134] (Tombstone Phenomenon) Next, the tombstone phenomenon will be explained. The tombstone phenomenon that occurs when mounting the multilayer ceramic capacitor 1 is caused by the difference in the solder wetting start time between the two opposing external electrodes 40. The solder wetting start time is affected by the oxidation state of the Sn grain boundary 301 on the surface 240 of the Sn plating layer.

[0135] As the particle size of the Sn precipitated particles 300 decreases and the proportion of Sn grain boundaries 301 increases, the tombstone phenomenon is more likely to occur. When the proportion of Sn grain boundaries 301 increases, it becomes difficult to control the oxidation state of the Sn grain boundaries 301 near the Sn plating layer 66, especially near the surface 240 of the Sn plating layer.

[0136] When the proportion of Sn grain boundaries 301 near the Sn plating layer 66, particularly the Sn plating layer surface 240, increases, grain boundary oxidation is more likely to occur. As a result, variations in the degree of grain boundary oxidation are more likely to occur, and differences in the solder wetting start time of the two external electrodes 40 are more likely to occur.

[0137] As described above, when the particle size of the Sn precipitated particles 300 decreases, variations in the grain boundary oxidation state of the Sn plating layer surface 240 tend to occur between the first external electrode 41 and the second external electrode 42, and as a result, the tombstone phenomenon is more likely to occur.

[0138] Furthermore, the tombstone phenomenon, like solderability, is more likely to occur in small-sized multilayer ceramic capacitors 1, and is even more pronounced in ultra-small-sized multilayer ceramic capacitors 1.

[0139] The smaller the chip size, the more susceptible it becomes to the effects of solder tension during mounting. In particular, multilayer ceramic capacitors 1 with chip sizes smaller than small are more susceptible to the effects of solder tension. As a result, they become more susceptible to variations in the progression of grain boundary oxidation, and the difference in solder wetting start time between opposing external electrodes tends to increase. Consequently, defects such as the tombstone phenomenon and mounting misalignment are more likely to occur.

[0140] Furthermore, when the plating method is barrel plating, the smaller the chip size, the smaller the media used, which reduces friction between chips during plating. Reduced friction between chips during plating makes grain boundary fracture less likely to occur during the plating growth process, thus reducing grain growth.

[0141] Furthermore, as the chip size decreases, chip lifting and barrel jamming are more likely to occur during plating. As a result, grain growth becomes less likely.

[0142] Furthermore, if the plating method is centrifugal barrel plating rather than conventional barrel plating, the difficulty in grain growth becomes even more pronounced.

[0143] In the multilayer ceramic capacitor 1 of this embodiment, the decrease in solderability and the occurrence of the tombstone phenomenon described above can be suppressed. In the multilayer ceramic capacitor 1 of this embodiment, the number of Sn deposited particles in a 30 μm range on the surface 240 of the Sn plating layer 66 is between 1 and 10. This reduces the ratio of Sn grain boundaries 301 near the surface 240 of the Sn plating layer, and consequently suppresses oxidation of the surface 240 of the Sn plating layer.

[0144] As a result, the multilayer ceramic capacitor 1 of this embodiment provides a multilayer ceramic capacitor 1 equipped with a Sn plating layer 66 that exhibits good solder wetting and fewer soldering defects. Furthermore, it provides a multilayer ceramic capacitor 1 that is less prone to the tombstone phenomenon.

[0145] Furthermore, the multilayer ceramic capacitor 1 of this embodiment can suppress the occurrence of soldering defects and the tombstone phenomenon, even when the size is small or even ultra-small.

[0146] In the multilayer ceramic capacitor 1 of this embodiment, the increase in the region where Sn is oxidized can be suppressed, so even in the case of small chip sizes or even ultra-small sizes or smaller, soldering defects and the like can be suppressed.

[0147] Furthermore, in the multilayer ceramic capacitor 1 of this embodiment, it becomes easier to reduce the difference in the number of Sn deposited particles between the first Sn plating layer 67, which is the Sn plating layer 66 of the first external electrode 41, and the second Sn plating layer 68, which is the Sn plating layer 66 of the second external electrode 42. As a result, it becomes easier to reduce the difference in the oxidation state of the Sn grain boundary 301 between the first external electrode 41 and the second external electrode 42, and consequently, the difference in solder wettability. As a result, it becomes easier to suppress the occurrence of the tombstone phenomenon.

[0148] Here, it is preferable that the difference in the number of Sn precipitated particles between the first Sn plating layer 67 and the second Sn plating layer 68 is 9 or less.

[0149] (Modified Version) A modified version of the multilayer ceramic capacitor 1 will be described with reference to Figure 8. Figure 8 is a cross-sectional view of the external electrode 40 of another example of the multilayer ceramic capacitor 1 according to an embodiment of the present invention. The following description will mainly focus on the differences between the multilayer ceramic capacitor 1, and in particular the external electrode 40, shown in Figures 6 and 7. Matters not specifically described can be the same as those of the multilayer ceramic capacitor 1 shown in Figure 6 or 7.

[0150] The surface of the Ni plating layer 63 that is in contact with the Sn plating layer 66 is defined as the Ni plating layer surface 242. The direction from the Sn plating layer surface 240 toward the Ni plating layer surface 242 is defined as the Ni plating direction 270.

[0151] The modified multilayer ceramic capacitor 1 shown in Figure 8 differs from the multilayer ceramic capacitor 1 shown in Figures 6 and 7 in that the configuration of the Sn deposited particles 300 differs depending on the position in the Ni plating direction 270 of the Sn plating layer 66. Here, "configuration" refers to, for example, the particle size of the Sn deposited particles 300.

[0152] In the Sn plating layer 66, the region from the Sn plating layer surface 240 to 1 μm in the Ni plating direction 270 is defined as the first region 221. The surface at the end of the first region 221 on the Ni plating direction 270 side is defined as the region boundary surface 244. The region from the region boundary surface 244 to the Ni plating layer surface 242 in the Ni plating direction 270 is defined as the second region 222. The first region 221 includes the Sn plating layer surface 240. On the other hand, the second region 222 does not include the Sn plating layer surface 240.

[0153] The thickness of the first region 221 in the Ni plating direction 270 is defined as the first region thickness 225. The first region thickness is 1 μm.

[0154] In the first region 221, the number of Sn precipitated particles in the observation range 260 with an observation range length 251 of 30 μm is between 1 and 10.

[0155] Furthermore, the number of Sn precipitated particles in the observation range 260 of the second region 222 with an observation range length 251 of 30 μm is greater than the number of Sn precipitated particles in the observation range 260 of the first region 221 with an observation range length 251 of 30 μm.

[0156] In the example shown in Figure 8, the number of Sn precipitated particles in the observation range 260 of the first region 221, where the observation range length 251 is 30 μm, is 4. On the other hand, the number of Sn precipitated particles in the observation range 260 of the second region 222, where the observation range length 251 is 30 μm, is 13.

[0157] In the first region 221, the number of Sn precipitated particles in the predetermined range described above is between 1 and 10. On the other hand, in the second region 222, the number of Sn precipitated particles in the predetermined range described above is greater than the number of Sn precipitated particles in the first region 221.

[0158] In the modified multilayer ceramic capacitor 1 shown in Figure 8, soldering defects and the tombstone phenomenon are suppressed, similar to the multilayer ceramic capacitor 1 shown in Figures 6 and 7. This is because, on the surface 240 of the Sn plating layer, the number of Sn deposited particles is within a predetermined range, similar to the multilayer ceramic capacitor 1 shown in Figures 6 and 7.

[0159] In addition to suppressing soldering defects and the tombstone phenomenon, the modified multilayer ceramic capacitor 1 shown in Figure 8 can enhance the adhesion between the Sn plating layer 66 and the Ni plating layer 63. In the modified multilayer ceramic capacitor 1 shown in Figure 8, the number of Sn precipitated particles in the second region 222 is greater than the number of Sn precipitated particles in the first region 221.

[0160] Therefore, the adhesion force between the Sn plating layer 66 and the Ni plating layer 63 can be increased compared to the case where the second region 222 is not provided. This is because a large amount of Sn precipitated particles 300 are present at the interface between the Sn plating layer 66 and the Ni plating layer 63. The modified multilayer ceramic capacitor 1 shown in Figure 8 can suppress the occurrence of delamination between the Sn plating layer 66 and the Ni plating layer 63.

[0161] (Observation Method) Referring to Figure 9, the position of the observation range 260 when observing the Sn plating layer 66 will be explained. Figure 9 is a view of the first main surface 3 of the multilayer ceramic capacitor 1 along the height direction T, from the first main surface 3 towards the second main surface.

[0162] (External Electrode Contour) As shown in Figure 9, the outer contour of the external electrode 40 when viewed in a plane parallel to the length direction L and the width direction W is defined as the external electrode contour 401. Viewing the external electrode 40 in a plane parallel to the length direction L and the width direction W is the same as viewing the external electrode 40 along the height direction T. Furthermore, the outside of the external electrode 40 means, for the first external electrode 41, the side away from the second external electrode 42 in the length direction L, and for the second external electrode 42, the side away from the first external electrode 41 in the length direction L. Figure 9 shows the external electrode contour 401 of the first external electrode 41.

[0163] The external electrode contour 401 includes a straight portion 411, a first curved portion 421, and a second curved portion 422. The portion of the external electrode contour 401 that extends linearly parallel to the width direction W is defined as the straight portion 411. The portion of the external electrode contour 401 that extends curvedly continuously from one end of the straight portion 411 is defined as the curved portion. The curved portion extending from one end of the straight portion 411 on the first side surface 5 side is defined as the first curved portion 421. The curved portion extending from one end of the straight portion 411 on the second side surface 6 side is defined as the second curved portion 422.

[0164] The connection point between the straight section 411 and the first curved section 421 is defined as the first curved end 431. The first curved end 431 is also the end of the straight section 411 on the first side surface 5 side. Similarly, the connection point between the straight section 411 and the second curved section 422 is defined as the second curved end 432. The second curved end 432 is also the end of the straight section 411 on the second side surface 6 side.

[0165] A line passing through the first curved end 431 and parallel to the length direction L is defined as the first side reference line 201. Similarly, a line passing through the second curved end 432 and parallel to the length direction L is defined as the second side reference line 202.

[0166] The observation range 260 when observing the Sn plating layer 66 is a portion of the cross-section of the external electrode 40 parallel to the length direction L and the height direction T. The cross-section of the external electrode 40 is exposed by polishing the multilayer ceramic capacitor 1.

[0167] Figure 9 shows the polishing surface 206 when polishing the multilayer ceramic capacitor 1. The polishing surface 206 is parallel to the length direction L. The polishing surface 206 is also parallel to the first side reference line 201 and the second side reference line 202.

[0168] The range in the width direction W between the first side reference line 201 and the second side reference line 202 is defined as the polishing surface range 204. Observation of the Sn plating layer 66 can be performed by setting the polishing surface 206 at any position within the polishing surface range 204. In other words, the Sn plating layer 66 can be evaluated at the LT cross-section at any position within the polishing surface range 204.

[0169] As shown in Figure 9, when viewing the internal electrode layer 30 in an LW cross-section, the edge of the internal electrode layer 30 on the first side surface 5 side is defined as the first internal electrode layer edge 211. Similarly, the edge of the internal electrode layer 30 on the second side surface 6 side is defined as the second internal electrode layer edge 212. The first side surface reference line 201 is located at approximately the same position as the first internal electrode layer edge 211. The second side surface reference line 202 is located at approximately the same position as the second internal electrode layer edge 212. The polishing surface area 204 corresponds to the area in the width direction W where the internal electrode layer 30 is extended to the end face of the laminate 2.

[0170] "The number of Sn precipitated particles in a 30 μm range on the surface of the Sn plating layer 66 is 1 or more and 10 or less" means that the number of Sn precipitated particles is within that range in the LT cross-section at at least one position in the polished surface range 204.

[0171] Similarly, "When the region from the surface of the Sn plating layer 66 to the surface of the Ni plating layer is defined as the first region 221, and the region from the first region 221 to the surface of the Ni plating layer 63 is defined as the second region 222, the number of Sn precipitated particles in the 30 μm range of the first region 221 is between 1 and 10, and the number of Sn precipitated particles in the 30 μm range of the second region 222 is greater than the number of Sn precipitated particles in the 30 μm range of the first region 221" means that the number of Sn precipitated particles in the LT cross section at at least one position in the polished surface range 204 is within that range.

[0172] Note that the cross-sections shown in Figures 6 to 8 are those when the polished surface 206 is set to the center 113 in the width direction. In other words, the cross-sections shown in Figures 6 to 8 are the LT cross-sections of the external electrode 40 at the center position in the width direction W of the laminate 2.

[0173] Referring to Figure 2, the position of the observation range 260 in the height direction T will be explained. As shown in Figure 2, the observation range 260 is located at the center of the multilayer ceramic capacitor 1 in the height direction T.

[0174] The conditions for preparing a sample for observing the observation range 260 by polishing the multilayer ceramic capacitor 1 on the polished surface 206 are as follows: (1) Sample processing: Cross-sectional mirror surface processing. (2) Observation equipment, etc.: SEM image observation, observation at 2000x to 5000x magnification, observation of secondary electron image, counting of particle count. (3) Sample embedding: Epoxy resin hardening. (4) Rough polishing: Equipment Wingo / L-5000 (product name), polishing paper Refinetech P400, P2000 (product name). (5) Finishing polishing: Equipment Union polishing machine (product name), polishing paper #240 -> #600 -> #2000 -> 1 μm abrasive grain -> colloidal silica used in order.

[0175] In SEM image observation, the Sn precipitate particles 300 are observed as regions with a different brightness from other areas. Similarly, the Sn grain boundaries 301 are observed as lines with a different brightness from other areas. The Sn precipitate particles 300 can also be described as the area enclosed by the lines indicating the Sn grain boundaries 301. The Sn grain boundaries 301 are typically arranged along the surface 240 of the Sn plating layer, as schematically shown in Figure 7.

[0176] The relationship between the number of Sn precipitated particles and the mounting failure rate will be explained with reference to Figure 10. Figure 10 is a table showing the number of Sn precipitated particles and the mounting failure rate. The number of Sn precipitated particles is the number of Sn precipitated particles 300 observed in an observation range 260 with an observation range length 251 of 30 μm. The mounting failure rate indicates the occurrence rate of soldering defects when the multilayer ceramic capacitor 1 is mounted on a substrate. GR01 to GR04 represent groups of multilayer ceramic capacitors 1 extracted from different manufacturing lots.

[0177] As shown in Figure 10, when the number of Sn precipitated particles was between 1 and 10, the mounting defect rate was 0.00% in all groups from GR01 to GR04. In contrast, when the number of Sn precipitated particles was between 11 and 19, mounting defects occurred in GR01 and GR02. Furthermore, when the number of Sn precipitated particles was 20 or more, mounting defects occurred in GR01, GR02, and GR03.

[0178] (Method for Manufacturing Multilayer Ceramic Capacitors) The method for manufacturing the multilayer ceramic capacitor 1 will be described below. However, the method for manufacturing the multilayer ceramic capacitor 1 is not limited to the method described below.

[0179] Prepare a conductive paste for the dielectric sheet and internal electrode layer. The conductive paste for the dielectric sheet and internal electrode layer contains a binder and a solvent. Known binders and solvents can be used. The dielectric sheet is also called a ceramic green sheet.

[0180] A dielectric sheet with an internal electrode layer pattern is prepared. Specifically, a conductive paste for the internal electrode layer is printed onto the dielectric sheet in a predetermined pattern to prepare a dielectric sheet with a first internal electrode layer pattern and a dielectric sheet with a second internal electrode layer pattern. Printing is performed, for example, by screen printing or gravure printing.

[0181] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first outer layer. On top of this, dielectric sheets with printed first internal electrode layer patterns and dielectric sheets with printed second internal electrode layer patterns are sequentially stacked to form the inner layer. Furthermore, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of the inner layer to form the second outer layer. This completes the production of the laminated sheet.

[0182] Next, the prepared laminated sheets are pressed in the height direction using a hydrostatic press or similar method to create laminated blocks.

[0183] Laminated blocks are cut into individual pieces to produce laminated chips. Specifically, laminated blocks are cut with a cutting blade to create individual pieces, and a pre-firing laminate is produced.

[0184] The laminated chips are fired to create the laminated structure. Before firing, the corners and edges of the laminated chips may be rounded using barrel polishing or other methods. The firing temperature depends on the dielectric and internal electrode layer materials, but a temperature of 900°C to 1400°C is desirable. Barrel polishing and other methods can also be performed on the laminated structure after firing.

[0185] Next, the external electrodes are formed. First, a conductive paste, which will serve as the base electrode layer, is applied to both end faces of the laminate 2 to form the base electrode layer. In forming the baked layer as the base electrode layer, a conductive paste containing glass components and metal is applied by dipping or other means, and then baked. The baking temperature at this time is preferably 700°C to 900°C.

[0186] When forming the base electrode layer with a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may be formed directly on the laminate without forming a baked layer. As a method for forming the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to the baked layer or the laminate. Then, heat treatment is performed at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably a nitrogen gas atmosphere. In addition, in order to prevent the scattering of resin and to prevent oxidation of various metal components, it is preferable to keep the oxygen concentration below 100 ppm.

[0187] Furthermore, when forming the underlying electrode layer as a thin film layer, the underlying electrode layer can be formed by a thin film formation method such as sputtering or vapor deposition. The underlying electrode layer formed as a thin film layer can be a layer of 1 μm or less in thickness with metal particles deposited on it.

[0188] Furthermore, a plating layer may be provided on the exposed portion of the internal electrode of the laminate without providing a base electrode layer. In that case, the plating layer can be formed by the following method: Plating is applied to the first and second end faces of the laminate to form a base plating film on the exposed portion of the internal electrode layer. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferable. Barrel plating is preferred as the plating method. Also, if necessary, the upper plating electrode formed on the surface of the lower plating electrode may be formed in the same manner.

[0189] Thereafter, a plating layer is formed on the surface of the base electrode layer, the surface of the conductive resin layer or the surface of the base plating layer, or the surface of the upper plating layer. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the baking layer as the base electrode layer. The Ni plating layer and the Sn plating layer are sequentially formed, for example, by a barrel plating method.

[0190] A centrifugal plating apparatus is used as the plating apparatus.

[0191] (Heat treatment after plating) Heat treatment is performed after the Sn plating layer is formed. This heat treatment is preferably performed until the Sn plating layer melts.

[0192] Specifically, after Sn plating, heat treatment is performed in a reducing atmosphere of N ２ + H ２ The heat treatment is performed using a high-frequency induction heating furnace. Specifically, first, it is superheated at 220 ° C for 120 minutes. As a result, Sn grains grow. Thereafter, it is superheated at 238 ° C for 0.5 minutes. Thereby, the Sn film can be melted.

[0193] By the heat treatment as described above, grain growth can be performed while suppressing the oxidation of the Sn surface.

[0194] Note that the above superheating conditions are exemplary. As another superheating method, there is the following method. First, flux application is performed under predetermined conditions. Thereafter, heat treatment is performed in an N ２ atmosphere. The conditions for the heat treatment are 235 ° C for 0.5 minutes. Thereafter, solvent cleaning is performed as flux cleaning. Subsequently, pure water replacement is performed, and suction drying is performed. 4]

[0195] In this way, a multilayer ceramic capacitor including a Sn plating layer having a desired number of Sn deposited particles is obtained.

[0196] The embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various changes, modifications, and combinations are possible. For example, the multilayer ceramic capacitor is not limited to having two terminals, and can be a multilayer ceramic capacitor having three or more terminals.

[0197] Furthermore, multilayer ceramic capacitors are an example of multilayer ceramic electronic components. The technology described above can also be applied to other multilayer ceramic electronic components besides multilayer ceramic capacitors.

[0198] As described above, in the multilayer ceramic capacitor of this embodiment, by setting the number of deposited Sn particles to 1 to 10 within a 30 μm range on the surface of the Sn plating layer, the number of particles at the grain boundaries on the surface of the Sn plating layer is reduced, and oxidation of the surface of the Sn plating layer is suppressed, thereby providing a multilayer ceramic capacitor with a Sn plating layer that has good solder wetting and few soldering defects. In the multilayer ceramic capacitor of this embodiment, it is possible to provide a small and multi-terminal electronic component with a Sn plating layer that has good solder wetting during mounting and few soldering defects.

[0199] 1 Multilayer ceramic capacitor 2 Laminate 3 First main surface 4 Second main surface 5 First side surface 6 Second side surface 7 First end surface 8 Second end surface 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 32 Second internal electrode layer 40 External electrode 41 First external electrode 42 Second external electrode 50 Underlay electrode layer 51 First underlay electrode layer 52 Second underlay electrode layer 60 Plating layer 61 First plating layer 62 Second plating layer 63 Ni plating layer 64 First Ni plating layer 65 Second Ni plating layer 66 Sn plating layer 67 First Sn plating layer 68 Second Sn plating layer 111 Center in height direction 112 Center in length direction 113 Center in width direction 201 Reference line on the first side surface 202 204 Second side reference line Polishing surface range Polishing surface 206 Polishing surface 211 Edge of first internal electrode layer 212 Edge of second internal electrode layer 221 First region 222 Second region 225 Thickness of first region 240 Surface of Sn plating layer 242 Surface of Ni plating layer 244 Region boundary surface 251 Length of observation area 260 Observation area 270 Plating direction 300 Deposited particles 301 Grain boundary 401 Outer electrode contour 411 Straight section 421 First curved section 422 Second curved section 431 First curved end 432 Second curved end

Claims

1. A multilayer ceramic capacitor comprising a plurality of stacked dielectric layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, a first internal electrode layer disposed on the plurality of dielectric layers and exposed on the first end surface, and a second internal electrode layer disposed on the plurality of dielectric layers and exposed on the second end surface, a first external electrode connected to the first internal electrode layer and disposed on the first end surface, and a second external electrode connected to the second internal electrode layer and disposed on the second end surface, wherein the first external electrode and the second external electrode are Ni plated layers and Sn plated layers located on the Ni plated layers, wherein the number of Sn deposited particles exposed from the surface in a 30 μm range on the surface of the Sn plated layer is 1 to 10.

2. The multilayer ceramic capacitor according to claim 1, wherein the region from the surface of the Sn plating layer to the surface of the Ni plating layer is defined as a first region, and the region from the first region to the surface of the Ni plating layer is defined as a second region, the number of Sn deposited particles in the 30 μm range of the first region is 1 or more and 10 or less, and the number of Sn deposited particles in the 30 μm range of the second region is greater than the number of Sn deposited particles in the 30 μm range of the first region.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the dimensions of the multilayer ceramic capacitor are such that the length is 0.6 mm or less, the width is 0.3 mm or less, and the height is 0.3 mm or less.

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