Piezoelectric ceramic capacitor driving circuit
By combining a boost circuit and a full-bridge circuit, the applicability of piezoelectric ceramic capacitor drivers to large loads is solved, achieving efficient load driving and precise voltage control.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI SG MICRO CO LTD
- Filing Date
- 2025-06-13
- Publication Date
- 2026-06-30
AI Technical Summary
In the existing technology, the piezoelectric ceramic capacitor driver requires a high voltage power supply, which limits the size of the load that can be driven and makes it difficult to apply to large load driving scenarios.
The system employs a boost circuit, a full-bridge circuit, and a boost control circuit. The boost circuit boosts the power supply voltage to a higher boost voltage, and the full-bridge circuit amplifies the boost voltage to achieve efficient driving of the piezoelectric ceramic capacitor.
It achieves effective driving of large loads and improves driving accuracy.
Smart Images
Figure CN224438842U_ABST
Abstract
Description
Technical Field
[0001] The embodiments disclosed herein relate to the field of integrated circuit technology, and more particularly to piezoelectric ceramic capacitor drive circuits. Background Technology
[0002] In the design of touch electronic devices, piezoelectric ceramic capacitors are often used. Based on the inverse piezoelectric effect, when a valid press operation is detected, different driving waveforms are retrieved from the driver chip to drive the piezoelectric ceramic capacitor, thereby bringing different tactile sensations.
[0003] In the prior art, a high-voltage power supply is usually required for piezoelectric ceramic capacitor drivers. The piezoelectric ceramic capacitor drivers use the high-voltage power supply voltage as the working voltage to drive the load. However, the fixed high-voltage power supply voltage limits the size of the load that can be driven, making it difficult to apply to scenarios with large loads. Utility Model Content
[0004] This disclosure provides a piezoelectric ceramic capacitor driving circuit that can drive large loads and improve driving accuracy.
[0005] In a first aspect, this disclosure provides a piezoelectric ceramic capacitor driving circuit, including a boost circuit, a full-bridge circuit, and a boost control circuit. The full-bridge circuit has a positive voltage output terminal and an anti-phase voltage output terminal. The piezoelectric ceramic capacitor is connected across the positive voltage output terminal and the anti-phase voltage output terminal. The boost module has a voltage input terminal and a voltage output terminal. The voltage input terminal is connected to a voltage source, and the voltage output terminal is connected to the input terminal of the full-bridge circuit to output a boosted voltage.
[0006] The boost circuit includes an upper transistor, a lower transistor, and an inductor. The upper transistor and the lower transistor are connected in series between the voltage output terminal and the reference ground. The connection point of the upper transistor and the lower transistor is a switching node. The switching node is connected to the voltage input terminal through the inductor.
[0007] The boost control circuit includes a voltage sampling circuit, a lower MOSFET turn-on detection circuit, and a control circuit. The first input terminal of the voltage sampling circuit is connected to the positive voltage output terminal, the second input terminal of the voltage sampling circuit is connected to the inverting voltage output terminal, and the output terminal of the voltage sampling circuit is connected to the first input terminal of the lower MOSFET turn-on detection circuit to output a feedback voltage.
[0008] The second input terminal of the lower MOSFET turn-on detection circuit is connected to a reference voltage. The output terminal of the lower MOSFET turn-on detection circuit is connected to the first input terminal of the control circuit to output a lower MOSFET turn-on signal. The first output terminal of the control circuit is connected to the control terminal of the lower MOSFET. The second output terminal of the control circuit is connected to the control terminal of the upper MOSFET.
[0009] In some embodiments of this disclosure, the rectification includes a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the third transistor and a first terminal of the fourth transistor are connected to the voltage input terminal. A second terminal of the third transistor is connected to the inverting voltage output terminal and a first terminal of the second transistor. A second terminal of the fourth transistor is connected to the non-inverting voltage output terminal and a first terminal of the first transistor. The second terminals of the first transistor and the second terminals of the second transistor are connected to the voltage output terminal.
[0010] In some embodiments of this disclosure, the voltage sampling circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a chopper, and an operational amplifier. The lower transistor turn-on detection circuit includes a first comparator. The non-inverting voltage output terminal is connected to the first terminal of the chopper through the first resistor, the inverting voltage output terminal is connected to the second terminal of the chopper through the second resistor, the third terminal of the chopper is connected to the non-inverting input terminal of the operational amplifier and the first terminal of the third resistor, and the fourth terminal of the chopper is connected to the first terminal of the fourth resistor and the inverting input terminal of the operational amplifier.
[0011] The second end of the third resistor is connected to the common-mode voltage of the feedback voltage and the reference voltage. The second end of the fourth resistor is connected to the output of the operational amplifier and the non-inverting input of the first comparator. The inverting input of the first comparator is connected to the reference voltage. The output of the first comparator is connected to the first input of the control circuit to output the lower transistor turn-on signal when the feedback voltage is less than the reference voltage.
[0012] In some embodiments of this disclosure, the boost control circuit further includes a first current source, a second current source, and a lower MOSFET turn-off detection circuit. The output terminal of the first current source is connected to the first input terminal of the lower MOSFET turn-off detection circuit, the second current source is connected to the second input terminal of the lower MOSFET turn-off detection circuit, and the output terminal of the lower MOSFET turn-off detection circuit is connected to the second input terminal of the control unit to output a lower MOSFET turn-off signal.
[0013] In some embodiments of this disclosure, the lower transistor turn-off detection circuit includes a first capacitor, a fifth resistor, and a second comparator. The first plate of the first capacitor is connected to the output terminal of the first current source and the non-inverting input terminal of the second comparator. The first terminal of the fifth resistor is connected to the output terminal of the second current source and the inverting input terminal of the second comparator. The output terminal of the second comparator is connected to the second input terminal of the control circuit. The second plate of the first capacitor and the second terminal of the fifth resistor are connected to the reference ground.
[0014] In some embodiments of this disclosure, the boost control circuit further includes an upper MOSFET turn-on detection circuit. The input terminal of the upper MOSFET turn-on detection circuit is connected to the switching node, and the output terminal of the upper MOSFET turn-on detection circuit is connected to the third input terminal of the control circuit, so as to output an upper MOSFET turn-on signal when the sum of the switching node voltage and the clamping voltage is equal to the boost voltage.
[0015] In some embodiments of this disclosure, the upper transistor turn-on detection circuit includes a sixth resistor, a fifth transistor, a clamping transistor, a second capacitor, and a Schmitt trigger. The first terminal of the sixth resistor and the power supply terminal of the Schmitt trigger are connected to the voltage output terminal. The second terminal of the sixth resistor is connected to the first terminal of the fifth transistor and the input terminal of the Schmitt trigger. The second terminal of the fifth transistor is connected to the first terminal of the clamping transistor and the first plate of the second capacitor. The second terminal of the clamping transistor and the second plate of the second capacitor are connected to the switching node. The output terminal of the Schmitt trigger is connected to the third input terminal of the control circuit.
[0016] In some embodiments of this disclosure, the boost control circuit further includes a current sampling circuit and a zero-crossing detection circuit. The first input terminal of the current sampling circuit is connected to the positive voltage output terminal, the second input terminal of the current sampling circuit is connected to the inverted voltage output terminal, and the output terminal of the current sampling circuit is connected to the first input terminal of the zero-crossing detection circuit, so as to output the sampling current of the third transistor in the first cycle of the boost voltage and output the sampling current of the fourth transistor in the second cycle of the boost voltage.
[0017] The second input terminal of the zero-crossing detection circuit is connected to the voltage input terminal, and the output terminal of the zero-crossing detection circuit is connected to the fourth input terminal of the control circuit, so as to output a zero-crossing signal when the sampled current is equal to the reference current.
[0018] In some embodiments of this disclosure, the current sampling circuit includes a first sampling transistor and a second sampling transistor, and the zero-crossing detection circuit includes a third comparator. The control terminal of the first sampling transistor is connected to the control terminal of the third transistor, the control terminal of the second sampling transistor is connected to the control terminal of the fourth transistor, the first terminals of the first and second sampling transistors are connected to the inverting input terminal of the third comparator, the second terminal of the first sampling transistor is connected to the second terminal of the third transistor, the second terminal of the second sampling transistor is connected to the second terminal of the fourth transistor, the non-inverting input terminal of the third comparator is connected to the voltage input terminal, and the output terminal of the third comparator is connected to the fourth input terminal of the control circuit.
[0019] In some embodiments of this disclosure, the control circuit includes a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, a second inverter, a third inverter, a first SR latch, and a second SR latch.
[0020] The first input of the first AND gate is connected to a frequency limiting signal, the second input of the first AND gate is connected to an upper transistor turn-off control signal, the output of the first AND gate is connected to the first input of the second AND gate and the first input of the third AND gate, the second input of the second AND gate is connected to the lower transistor turn-on signal, the third input of the second AND gate is connected to a boost voltage rise signal, the output of the second AND gate is connected to the first input of the first NOR gate, the second input of the third AND gate is connected to an auxiliary turn-on signal; the third input of the third AND gate is connected to a boost voltage fall signal, and the output of the third AND gate is connected to the second input of the first NOR gate.
[0021] The first input of the fourth AND gate is connected to the boost voltage rise signal, the second input of the fourth AND gate is connected to the lower transistor turn-off signal, the output of the fourth AND gate is connected to the first input of the second NOR gate, the second input of the second NOR gate is connected to the first current limiting signal, the first input of the fifth AND gate is connected to the boost voltage fall signal, the second input of the fifth AND gate is connected to the second current limiting signal, and the output of the fifth AND gate is connected to the third input of the second NOR gate.
[0022] The first input of the sixth AND gate is connected to the boost voltage rise signal, the second input of the sixth AND gate is connected to the zero-crossing signal, the output of the sixth AND gate is connected to the first input of the third NOR gate, the first input of the seventh AND gate is connected to the boost voltage fall signal, the second input of the seventh AND gate is connected to the lower transistor turn-on signal, and the output of the seventh AND gate is connected to the second input of the third NOR gate.
[0023] The set terminal of the first SR latch is connected to the output terminal of the first NOR gate. The reset terminal of the first SR latch is connected to the output terminal of the second NOR gate and the set terminal of the second SR latch. The inverted output terminal of the first SR latch is connected to the control terminal of the lower transistor through the first inverter. The reset terminal of the second SR latch is connected to the output terminal of the third NOR gate. The inverted output terminal of the second SR latch is connected to the first input terminal of the eighth AND gate through the second inverter. The upper transistor enable signal is connected to the second input terminal of the eighth AND gate through the third inverter. The output terminal of the eighth AND gate is connected to the control terminal of the upper transistor.
[0024] In a second aspect, this disclosure provides a piezoelectric ceramic capacitor driving chip, including any of the piezoelectric ceramic capacitor driving circuits provided in the first aspect.
[0025] This disclosure provides a piezoelectric ceramic capacitor driving circuit, including a boost circuit, a full-bridge circuit, and a boost control circuit. The voltage input terminal of the boost circuit is connected to the power supply voltage, and the voltage output terminal of the boost circuit is connected to the input terminal of the full-bridge circuit to output a boosted voltage. The boost control circuit includes a voltage sampling circuit, a lower MOSFET turn-on detection circuit, and a control circuit. The first input terminal of the voltage sampling circuit is connected to the non-inverting voltage output terminal of the full-bridge circuit, and the second input terminal is connected to the inverting voltage output terminal of the full-bridge circuit. The output terminal of the voltage sampling circuit is connected to the first input terminal of the lower MOSFET turn-on detection circuit to output a feedback voltage. The second input terminal of the lower MOSFET turn-on detection circuit is connected to a reference voltage, and the output terminal of the lower MOSFET turn-on detection circuit is connected to the first input terminal of the control circuit to output a lower MOSFET turn-on signal. This circuit can boost a lower power supply voltage to a higher boosted voltage, and then amplify the boosted voltage to obtain a higher output voltage, thereby increasing the charge stored in the piezoelectric ceramic capacitor and enabling it to drive large loads. Furthermore, it can obtain a more accurate feedback voltage, thereby improving driving accuracy. Attached Figure Description
[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. It should be understood that the accompanying drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:
[0027] Figure 1 This is a schematic diagram of a piezoelectric ceramic capacitor driving circuit provided in an embodiment of the present disclosure.
[0028] Figure 2 This is a circuit diagram of a piezoelectric ceramic capacitor driving circuit provided in an embodiment of the present disclosure.
[0029] Figure 3 This is a schematic diagram of the voltage at each node of a piezoelectric ceramic capacitor driving circuit provided in an embodiment of this disclosure.
[0030] Figure 4 This is a circuit diagram of a boost control circuit provided in an embodiment of the present disclosure.
[0031] Figure 5 This is a schematic diagram of the inductor current of a boost circuit provided in an embodiment of this disclosure.
[0032] Figure 6 A circuit diagram of another boost control circuit provided in an embodiment of this disclosure.
[0033] Figure 7This is a circuit diagram of a first current source provided in an embodiment of the present disclosure.
[0034] Figure 8 This is a circuit diagram of a second current source provided in an embodiment of the present disclosure.
[0035] Figure 9 This is a circuit diagram of another boost control circuit provided in an embodiment of the present disclosure.
[0036] Figure 10 A circuit diagram of another piezoelectric ceramic capacitor driving circuit provided in an embodiment of this disclosure.
[0037] Figure 11 This is a circuit diagram of a control circuit provided in an embodiment of the present disclosure. Detailed Implementation
[0038] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.
[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the related art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement “connecting” two or more parts together shall mean that the parts are joined directly together or joined through one or more intermediate components.
[0040] In this disclosure, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.
[0041] Furthermore, the terms "first," "second," etc., in the specification, claims, or the accompanying drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.
[0042] In this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three possibilities: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0043] In the description of this disclosure, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).
[0044] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.
[0045] Figure 1 This is a schematic diagram of a piezoelectric ceramic capacitor driving circuit provided in an embodiment of the present disclosure, as shown below. Figure 1 As shown, the piezoelectric ceramic capacitor driving circuit 100 includes a boost circuit 110, a full-bridge circuit 120, and a boost control circuit 130.
[0046] The full-bridge circuit 120 has a positive voltage output terminal OUTP and an inverting voltage output terminal OUTN. The positive voltage output terminal OUTP is used to output the positive output voltage Voutp, and the inverting voltage output terminal OUTN is used to output the inverting output voltage Voutn. A piezoelectric ceramic capacitor Cload is connected between the positive voltage output terminal OUTP and the inverting voltage output terminal OUTN. The boost circuit 110 has a voltage input terminal and a voltage output terminal. The voltage input terminal is used to receive the power supply voltage Vin, and the voltage output terminal is connected to the input terminal of the full-bridge circuit 120 to output the boost voltage Vboost. The output voltage Vout of the piezoelectric ceramic capacitor drive circuit 100 is the positive output voltage Voutp minus the inverting output voltage Voutn, i.e., Vout = Voutp - Voutn.
[0047] The reference terminal of the boost control circuit 130 is connected to the reference voltage Vref, the output terminal of the boost control circuit 130 is connected to the control terminal of the boost circuit 110, the first input terminal of the full-bridge circuit 120 is connected to the voltage input terminal to receive the power supply voltage Vin, and the second input terminal of the full-bridge circuit 120 is connected to the voltage output terminal to receive the boost voltage Vboost.
[0048] The boost control circuit 130 is configured to control the boost module 110 to convert the power supply voltage Vin into a boost voltage Vboost, so that the boost voltage Vboost follows the periodic change of the reference voltage Vref.
[0049] The full-bridge circuit 120 is configured to output the boost voltage Vboost based on the positive voltage output terminal OUTP and the power supply voltage Vin based on the inverting voltage output terminal OUTN during the first cycle T1 of the boost voltage Vboost. During the second cycle T2 of the boost voltage Vboost, the power supply voltage Vin is output based on the positive voltage output terminal OUTP and the boost voltage Vboost is output based on the inverting voltage output terminal OUTN. The second cycle T1 is adjacent to the first cycle T2.
[0050] For example, Figure 2 This is a circuit diagram of a piezoelectric ceramic capacitor driving circuit provided in an embodiment of the present disclosure, as shown below. Figure 2 As shown, the full-bridge circuit 120 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The first terminals of the third transistor M3 and the fourth transistor M4 are connected to the voltage input terminals. The second terminal of the third transistor M3 is connected to the inverting voltage output terminal OUTN and the first terminal of the second transistor M2. The second terminal of the fourth transistor M4 is connected to the non-inverting voltage output terminal OUTP and the first terminal of the first transistor M1. The second terminals of the first transistor M1 and the second terminals of the second transistor M2 are connected to the voltage output terminals.
[0051] Figure 3 A schematic diagram of the node voltages of a piezoelectric ceramic capacitor driving circuit provided in an embodiment of this disclosure is shown below. Figure 3 As shown, during the first cycle T1, the first transistor M1 is in the on state, which connects the voltage output terminal to the non-inverting voltage output terminal OUTP, resulting in a non-inverting output voltage Voutp = Vboost. Simultaneously, the third transistor M3 is in the on state, which connects the voltage input terminal to the inverting voltage output terminal OUTN, resulting in an inverting output voltage Voutn = Vin. Therefore, the output voltage Vout = Voutp - Voutn = Vboost - Vin.
[0052] During the second cycle T2, which is adjacent to the first cycle T1, the second transistor M2 is in the on state, connecting the voltage output terminal to the inverting voltage output terminal OUTN. Therefore, the inverting output voltage Voutn = Vboost. Simultaneously, the fourth transistor M4 is in the on state, connecting the voltage input terminal to the non-inverting voltage output terminal OUTP. Therefore, the non-inverting output voltage Voutp = Vin. At this point, the output voltage Vout = Voutp - Voutn = Vin - Vboost.
[0053] Thus, the full-bridge circuit 120 can amplify the boost voltage Vboost provided by the boost circuit 110 to obtain the output voltage Vout.
[0054] See also Figure 2The boost circuit 110 includes an upper transistor MH, a lower transistor ML, and an inductor L. The upper transistor MH and the lower transistor ML are connected in series between the voltage output terminal and the reference ground. The connection point of the upper transistor MH and the lower transistor ML is the switching node SW. The switching node SW is connected to the voltage input terminal through the inductor L.
[0055] When the lower transistor ML is turned on and the upper transistor MH is turned off, the inductor L is in a charging state, and the inductor current IL increases linearly. When the lower transistor ML is turned off and the upper transistor MH is turned on, the inductor L is in a discharging state. At this time, the first transistor M1 and the third transistor M3 are turned on, or the second transistor M2 and the fourth transistor M4 are turned on, and the piezoelectric ceramic capacitor Cload is in a charging state.
[0056] Figure 4 A circuit diagram of a boost control circuit provided in an embodiment of this disclosure is shown below. Figure 4 As shown, the boost control circuit 130 includes a voltage sampling circuit 131, a lower transistor turn-on detection circuit 132, and a control circuit 133. The first input terminal of the voltage sampling circuit 131 is connected to the positive voltage output terminal OUTP, the second input terminal of the voltage sampling circuit 131 is connected to the inverted voltage output terminal OUTN, and the output terminal of the voltage sampling circuit 131 is connected to the first input terminal of the lower transistor turn-on detection circuit 132 to output a feedback voltage Vfb.
[0057] The second input terminal of the lower MOSFET turn-on detection circuit 132 is connected to the reference voltage Vref. The output terminal of the lower MOSFET turn-on detection circuit 132 is connected to the first input terminal of the control circuit 133 to output the lower MOSFET turn-on signal FB_L. The first output terminal of the control circuit 133 is connected to the control terminal of the lower MOSFET ML. The second output terminal of the control circuit 133 is connected to the control terminal of the upper MOSFET MH.
[0058] For example, such as Figure 4 As shown, the voltage sampling circuit 131 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a chopper 1311, and an operational amplifier OPA. The lower transistor turn-on detection circuit 132 includes a first comparator CMP1. The non-inverting voltage output terminal OUTP is connected to the first terminal of the chopper 1311 through the first resistor R1; the inverting voltage output terminal OUTN is connected to the second terminal of the chopper 1311 through the second resistor R2; the third terminal of the chopper 1311 is connected to the non-inverting input terminal of the operational amplifier OPA and the first terminal of the third resistor R3; and the fourth terminal of the chopper 1311 is connected to the first terminal of the fourth resistor R4 and the inverting input terminal of the operational amplifier OPA.
[0059] The second end of the third resistor R3 is connected to the common-mode voltage Vcm of the feedback voltage Vfb and the reference voltage Vref. The second end of the fourth resistor R4 is connected to the output of the operational amplifier OPA and the non-inverting input of the first comparator CMP1. The inverting input of the first comparator CMP1 is connected to the reference voltage Vref. The output of the first comparator CMP1 is connected to the second input of the control circuit 132.
[0060] During the first cycle T1, the first and third terminals of chopper 1311 are turned on, as are the second and fourth terminals. This allows chopper 1311 to connect the non-inverting voltage output terminal OUTP to the non-inverting input terminal of operational amplifier OPA, and the inverting voltage output terminal OUTN to the inverting input terminal of operational amplifier OPA. At this time, the non-inverting power supply voltage of operational amplifier OPA is Vboost, and the inverting power supply voltage is Vin. The feedback voltage output by operational amplifier OPA is Vfb = Vout / k + Vcm = (Vboost - Vin) / k + Vcm, where k = R2 / R4, where R2 is the resistance of the second resistor R2, and R4 is the resistance of the fourth resistor R4.
[0061] During the second cycle T2, the first and fourth terminals of chopper 1311 are turned on, and the second and third terminals of chopper 1311 are also turned on. Therefore, chopper 1311 can connect the non-inverting voltage output terminal OUTP to the inverting input terminal of operational amplifier OPA, and the inverting voltage output terminal OUTN to the non-inverting input terminal of operational amplifier OPA. At this time, the non-inverting power supply voltage of operational amplifier OPA is Vin, and the inverting power supply voltage of operational amplifier OPA is Vboost. The feedback voltage output by operational amplifier OPA is Vfb = Vout / k + Vcm = (Vin - Vboost) / k + Vcm.
[0062] Thus, the voltage sampling circuit 131 can determine the feedback voltage Vfb based on the differential voltage between the boost voltage Vboost and the power supply voltage Vin.
[0063] The first comparator CMP1 compares the reference voltage Vref and the feedback voltage Vfb, and generates a lower transistor turn-on signal FB_L when the feedback voltage Vfb is less than the reference voltage Vref. The control circuit 133 controls the switching of the upper transistor MH and the lower transistor ML according to the lower transistor turn-on signal FB_L, causing the inductor L in the boost module 110 to switch between charging and discharging states. Based on the switching of the charging and discharging states of the inductor L, the boost module 110 can boost the power supply voltage Vin to a boost voltage Vboost, and the boost voltage Vboost changes periodically with the reference voltage Vref.
[0064] Figure 5A schematic diagram of the inductor current of a boost circuit provided in an embodiment of this disclosure is shown below. Figure 5 As shown, the control circuit 133 can control the lower transistor ML to conduct during the rising phase of the boost voltage Vboost according to the lower transistor turn-on signal FB_L, causing the inductor current IL to increase linearly. During the falling phase of the boost voltage Vboost, the upper transistor MH is turned off according to the lower transistor turn-on signal FB_L, causing the inductor current IL to freewheel to zero.
[0065] In summary, the piezoelectric ceramic capacitor driving circuit provided in this embodiment includes a boost circuit, a full-bridge circuit, and a boost control circuit. The voltage input terminal of the boost circuit is connected to the power supply voltage, and the voltage output terminal of the boost circuit is connected to the input terminal of the full-bridge circuit to output a boosted voltage. The boost control circuit includes a voltage sampling circuit, a lower MOSFET turn-on detection circuit, and a control circuit. The first input terminal of the voltage sampling circuit is connected to the non-inverting voltage output terminal of the full-bridge circuit, and the second input terminal of the voltage sampling circuit is connected to the inverting voltage output terminal of the full-bridge circuit. The output terminal of the voltage sampling circuit is connected to the first input terminal of the lower MOSFET turn-on detection circuit to output a feedback voltage. The second input terminal of the lower MOSFET turn-on detection circuit is connected to a reference voltage, and the output terminal of the lower MOSFET turn-on detection circuit is connected to the first input terminal of the control circuit to output a lower MOSFET turn-on signal. This circuit can boost a lower power supply voltage to a higher boosted voltage, and then amplify the boosted voltage to obtain a higher output voltage, thereby increasing the amount of charge stored in the piezoelectric ceramic capacitor and enabling it to drive large loads. Furthermore, it can obtain a more accurate feedback voltage, thereby improving driving accuracy.
[0066] In some embodiments, Figure 6 A circuit diagram of another boost control circuit provided in this disclosure embodiment is shown in [the diagram]. Figure 4 Based on the embodiment shown, the boost control circuit 130 further includes a first current source IB1, a second current source IB2, and a lower transistor turn-off detection circuit 134.
[0067] The output of the first current source IB1 is connected to the first input of the lower transistor turn-off detection circuit 134, the second current source IB2 is connected to the second input of the lower transistor turn-off detection circuit 134, and the output of the lower transistor turn-off detection circuit 134 is connected to the second input of the control circuit 133.
[0068] The first current source IB1 is configured to generate a first variable current Ib1 based on a first fixed current I1, a second fixed current I2, and an error amplification voltage Veao. The second current source IB2 is configured to generate a second variable current Ib2 based on a third fixed current I3, a power supply voltage Vin, and a boost voltage Vboost.
[0069] The lower transistor turn-off detection circuit 134 is configured to convert the first variable current Ib1 into a first variable voltage Vb1, and the second variable current Ib2 into a second variable voltage Vb2, and generate a lower transistor turn-off signal MAIN TRIP based on the first variable voltage Vb1 and the second variable voltage Vb2. The control circuit 133 is further configured to control the lower transistor ML to turn off according to the lower transistor turn-off signal MAIN TRIP during the rising phase of the boost voltage Vboost.
[0070] For example, the boost control circuit 130 also includes an error amplifier EA, the non-inverting input of which is connected to the feedback voltage Vfb, and the inverting input of which is connected to the reference voltage Vref, and the error amplification voltage Veao of the feedback voltage Vfb and the reference voltage Vref can be calculated.
[0071] Figure 7 A circuit diagram of a first current source provided in an embodiment of this disclosure is shown below. Figure 7 As shown, the first current source IB1 includes a first fixed current source IB_c1, a second fixed current source IB_c2, a first operational amplifier OPA1, a fifth transistor M5, a sixth transistor M6, and a seventh resistor R7.
[0072] The non-inverting input of the first operational amplifier OPA1 is connected to the output of the error amplifier EA. The inverting input of the first operational amplifier OPA1 is connected to the first terminal of the fifth transistor M5 and the first terminal of the seventh resistor R7. The output of the first operational amplifier OPA1 is connected to the control terminal of the fifth transistor M5, and the second terminal of the seventh resistor R7 is grounded. The second terminal of the fifth transistor M5 is connected to the output of the first fixed current source IB_c1 and the first terminal of the sixth transistor M6. The control terminal of the sixth transistor M6 is connected to the first bias voltage Vb1. The output of the sixth transistor M6 and the output of the second fixed current source IB_c2 are connected to the output of the first current source IB1.
[0073] Wherein, the first fixed current source IB_c1 provides the first fixed current I1, the second fixed current source IB_c2 provides the second fixed current I2, and the transconductance of the first operational amplifier OPA1 is gm1. Then, the first variable current output by the first current source IB1 is Ib1 = I1 + I2 - gm1 * Veao.
[0074] Figure 8 A circuit diagram of a second current source provided in an embodiment of this disclosure is shown below. Figure 8 As shown, the second current source IB2 includes a third fixed current source IB_c3, a second operational amplifier OPA2, a third operational amplifier OPA3, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11.
[0075] The non-inverting input of the second op-amp OPA2 is connected to the reference voltage Vref. The inverting input of the second op-amp OPA2 is connected to the first terminal of the seventh transistor M7 and the first terminal of the eighth resistor R8. The output of the second op-amp OPA2 is connected to the control terminal of the seventh transistor M7. The second terminal of the eighth resistor R8 is grounded. The second terminal of the seventh transistor M7 is connected to the second terminal of the eighth transistor M8, the control terminal of the eighth transistor M8, and the control terminal of the ninth transistor M9. The first terminals of the eighth transistor M8 and the first terminals of the ninth transistor M9 are connected to the power supply voltage.
[0076] The second terminal of the ninth transistor M9 is connected to the first terminal of the tenth transistor M10 and the second terminal of the eleventh transistor M11. The control terminal of the tenth transistor M10 is connected to the second bias voltage Vb2. The second terminal of the tenth transistor M10 is also connected to the output terminal of the third fixed current source IB_c3 and the output terminal of the second current source IB2. The power supply voltage Vin is grounded sequentially through the ninth resistor R9 and the tenth resistor R10. The connection point of the ninth resistor R9 and the tenth resistor R10 is connected to the non-inverting input terminal of the third operational amplifier OPA3. The inverting input terminal of the third operational amplifier OPA3 is connected to the first terminal of the eleventh resistor R11 and the first terminal of the eleventh transistor M11. The output terminal of the third operational amplifier OPA3 is connected to the control terminal of the eleventh transistor M11. The second terminal of the eleventh resistor R11 is grounded.
[0077] Among them, the third fixed current source IB_c3 provides the third fixed current I3, the current flowing through the seventh transistor M7 is gm2*Vboost, gm2 is the transconductance of the circuit composed of the control circuit that controls the boost voltage Vboost according to the reference voltage Vref and the second operational amplifier OPA2, and the current flowing through the eleventh transistor M11 is Vin*gm3, gm3 is the transconductance of the circuit composed of the ninth resistor R9, the tenth resistor R10 and the third operational amplifier OPA3. Then the second variable current IB2 = I3 + gm2*Vboost - gm3*Vin.
[0078] For example, such as Figure 6 As shown, the lower transistor turn-off detection circuit 134 includes a first capacitor C1, a fifth resistor R5, and a second comparator CMP2. The first plate of the first capacitor C1 is connected to the output terminal of the first current source IB1 and the non-inverting input terminal of the second comparator CMP2. The first terminal of the fifth resistor R5 is connected to the output terminal of the second current source IB2 and the inverting input terminal of the second comparator CMP2. The output terminal of the second comparator CMP2 is connected to the third input terminal of the control circuit 133. The second plate of the first capacitor C1 and the second terminal of the fifth resistor R5 are grounded.
[0079] The first variable current Ib1 charges the first capacitor C1, generating a voltage drop across C1 to obtain the first variable voltage Vb1. The fifth resistor R5 converts the second variable current Ib2 into the second variable voltage Vb2. The second comparator CMP2 compares the magnitudes of the first variable voltage Vb1 and the second variable voltage Vb2, and generates a lower transistor turn-off signal MAIN TRIP when the first variable voltage Vb1 is greater than the second variable voltage Vb2. During the rising phase of the boost voltage Vboost, the control circuit 133 can control the lower transistor ML to turn off according to the lower transistor turn-off signal MAIN TRIP, and the inductor current IL begins to decrease. Figure 5 As shown.
[0080] In some embodiments, Figure 9 A circuit diagram of another boost control circuit provided in this disclosure embodiment is shown in the figure. Figure 4 Based on the embodiment shown, the boost control circuit 130 further includes an upper transistor turn-on detection circuit 135. The input terminal of the upper transistor turn-on detection circuit 135 is connected to the switch node SW, and the output terminal of the upper transistor turn-on detection circuit 135 is connected to the fourth input terminal of the control circuit 133.
[0081] The upper transistor turn-on detection circuit 135 is configured to generate an upper transistor turn-on signal when the sum of the switching node voltage Vsw and the clamping voltage Vclamp, Vsw + Vclamp, equals the boost voltage Vboost. The control circuit 133 is also configured to control the upper transistor MH to turn on based on the upper transistor turn-on signal.
[0082] For example, the upper transistor turn-on detection circuit 135 includes a sixth resistor R6, a fifth transistor M5, a clamping transistor D, a second capacitor C2, and a Schmitt trigger 1351. The first end of the sixth resistor R6 and the power supply terminal of the Schmitt trigger 1351 are connected to the voltage output terminal. The second end of the sixth resistor R6 is connected to the first end of the fifth transistor M5 and the input terminal of the Schmitt trigger 1351. The second end of the fifth transistor M5 is connected to the first end of the clamping transistor D and the first plate of the second capacitor C2. The second end of the clamping transistor D and the second plate of the second capacitor C2 are connected to the switching node SW. The output terminal of the Schmitt trigger 1351 is connected to the third input terminal of the control circuit 133.
[0083] For example, clamping transistor D is a Schottky diode, such as Figure 9 As shown, the negative terminal of the clamping transistor D is connected to the first plate of the second capacitor C2 and the second terminal of the fifth transistor M5, and the positive terminal of the clamping transistor D is connected to the switching node SW to receive the switching node voltage Vsw.
[0084] When the down transistor ML is turned on, the switching node voltage Vsw is zero, and the voltage output terminal outputs a boost voltage Vboost. The clamping transistor D is turned on in reverse, which can limit the voltage drop across the second capacitor C2 to the clamping voltage Vclamp. For example, the clamping voltage Vclamp is 5.5V.
[0085] When the lower transistor ML switches from the on state to the off state and the upper transistor MH remains in the off state, the inductor current IL charges the switching node SW, and the switching node voltage Vsw rises from zero. The voltage drop across the second capacitor C2 maintains the clamping voltage Vclamp, and the power supply voltage Vsw+Vclamp of the Schmitt trigger 1351 rises from Vclamp.
[0086] When Vsw + Vclamp rises from Vclamp to the boost voltage Vboost, the output signal of the Schmitt trigger 1351 flips to generate a turn-on signal for the upper transistor. Based on this turn-on signal, the control circuit 133 controls the upper transistor MH to switch from the off state to the on state, causing the inductor current IL to drop rapidly. Figure 5 As shown.
[0087] In this embodiment of the disclosure, when the sum of the switching node voltage Vsw and the clamping voltage Vclamp, Vsw+Vclamp, equals the boost voltage Vboost, an upper transistor turn-on signal is generated to turn on the upper transistor MH. This reduces the source-drain voltage of the upper transistor MH when it is turned on, protects the upper transistor MH, and also reduces the switching loss of the upper transistor MH, thereby improving efficiency and making it suitable for large-capacity piezoelectric ceramic capacitors.
[0088] In some embodiments, Figure 10 This is a circuit diagram of another piezoelectric ceramic capacitor driving circuit provided in an embodiment of this disclosure. Figure 4 Based on the embodiment shown, the boost control circuit 130 further includes a current sampling circuit 136 and a zero-crossing detection circuit 137.
[0089] The first input terminal of the current sampling circuit 136 is connected to the positive voltage output terminal OUTP, the second input terminal of the current sampling circuit 136 is connected to the inverted voltage output terminal OUTN, and the output terminal of the current sampling circuit 136 is connected to the first input terminal of the zero-crossing detection circuit 137. The second input terminal of the zero-crossing detection circuit 137 is connected to the voltage input terminal, and the output terminal of the zero-crossing detection circuit 137 is connected to the fourth input terminal of the control circuit 133.
[0090] The zero-crossing detection circuit 137 is configured to sample the current flowing through the third transistor M3 during the first cycle T1 to obtain the sampled current Isns, and to sample the current flowing through the fourth transistor M4 during the second cycle T2 to obtain the sampled current Isns; to generate a reference current based on the power supply voltage Vin, and to output a zero-crossing signal ZCD when the sampled current equals the reference current. The control circuit 133 is configured to control the upper transistor MH to turn off during the rising phase of the boost voltage Vboost based on the zero-crossing signal ZCD.
[0091] For example, such as Figure 10 As shown, the current sampling circuit 136 includes a first sampling transistor Msns1 and a second sampling transistor Msns2, and the zero-crossing detection circuit 137 includes a third comparator CMP3. The control terminal of the first sampling transistor Msns1 is connected to the control terminal of the third transistor M3, the control terminal of the second sampling transistor Msns2 is connected to the control terminal of the fourth transistor, and the first terminal of the first sampling transistor Msns1 and the first terminal of the second sampling transistor Msns2 are connected to the inverting input terminal of the third comparator CMP3.
[0092] The second terminal of the first sampling transistor Msns1 is connected to the second terminal of the third transistor M3, the second terminal of the second sampling transistor Msns2 is connected to the second terminal of the fourth transistor M4, the non-inverting input terminal of the third comparator CMP3 is connected to the voltage input terminal, and the output terminal of the third comparator CMP3 is connected to the fourth input terminal of the control circuit 133.
[0093] During the first cycle T1, the third transistor M3 is in the on state, and current flows through it. The first sampling transistor Msns1 samples the current flowing through the third transistor M3 to obtain the sampling current Isns. During the second cycle T2, the fourth transistor M4 is in the on state, and current flows through it. The second sampling transistor Msns2 samples the current flowing through the fourth transistor M4 to obtain the sampling current Isns.
[0094] The third comparator, CMP3, compares the sampled current Isns with the reference current. When the sampled current Isns equals the reference current, it indicates that the inductor current IL is zero, and the third comparator CMP3 generates a zero-crossing signal ZCD. During the rising phase of the boost voltage Vboost, the inductor current IL drops rapidly when the upper transistor MH is turned on. When the inductor current IL drops to zero, the upper transistor MH is turned off according to the zero-crossing signal ZCD. Figure 5 As shown. At this time, both the upper transistor MH and the lower transistor ML are in the off state, so the inductor current IL remains zero.
[0095] In some embodiments, see continue to see Figure 2 and Figure 10The boost module 110 also includes an output capacitor Chv, which is connected between the voltage output terminal and ground.
[0096] When the lower transistor ML is off and the upper transistor MH is on, the inductor L is in a discharging state. At this time, the first transistor M1 and the third transistor M3 are on, or the second transistor M2 and the fourth transistor M4 are on, and the output capacitor Chv is in a charging state. The capacitance of the output capacitor Chv is much smaller than the capacitance of the piezoelectric ceramic capacitor Cload. For example, the capacitance of the output capacitor Chv is at least one order of magnitude smaller than the capacitance of the piezoelectric ceramic capacitor Cload, so that the energy released by the inductor L is stored in the piezoelectric ceramic capacitor Cload as much as possible.
[0097] In the above embodiment, the current flowing through the third transistor M3 and the current flowing through the fourth transistor M4 sampled by the zero-crossing detection circuit 137 are actually the charging current of the piezoelectric ceramic capacitor Cload. However, the zero-crossing signal ZCD output by the zero-crossing detection circuit 137 needs to reflect whether the inductor current IL has crossed zero. The reference current can be adjusted by the output capacitor Chv, thereby improving the accuracy of zero-crossing detection and thus improving the driving accuracy.
[0098] In some embodiments, such as Figure 10 As shown, the current sampling circuit 136 also includes a third sampling transistor Msns3. The control terminal of the third sampling transistor Msns3 is connected to the control terminal of the lower transistor ML. The second terminal of the third sampling transistor Msns3 is connected to the second terminal of the lower transistor ML. The first terminal of the third sampling transistor Msns3 outputs the sampling current of the lower transistor.
[0099] During the rising phase of the boost voltage Vboost, the control circuit 133 determines whether the inductor current IL has reached the maximum peak inductor current based on the sampling current of the lower transistor. When the inductor current IL reaches the maximum peak inductor current, a first current limiting signal LIM is generated, and the lower transistor ML is controlled to turn off according to the first current limiting signal LIM to reduce the safety risks caused by excessive inductor current IL.
[0100] When the feedback voltage Vfb is less than the reference voltage Vref, the lower transistor turn-on detection circuit 132 generates an auxiliary turn-on signal FB_H. During the falling phase of the boost voltage Vboost, the control circuit 133 controls the lower transistor ML to turn on according to the auxiliary turn-on signal FB_H, and the inductor current IL increases linearly. Figure 5 As shown. The control circuit 133 also determines whether the inductor current IL has reached the minimum inductor peak current based on the sampling current of the lower transistor. When the inductor current IL reaches the minimum inductor peak current, a second current limiting signal NTRIP is generated, and the lower transistor ML is controlled to turn off according to the second current limiting signal NTRIP, so as to avoid the problem that the lower transistor ML is turned off as soon as it is turned on, which can improve the stability of the circuit.
[0101] At this time, both the upper transistor MH and the lower transistor ML are in the off state, and the inductor current IL charges the switching node SW to pull up the switching node voltage Vsw. When the sum of the switching node voltage Vsw and the clamping voltage Vclamp, Vsw + Vclamp, equals the boost voltage Vboost, the upper transistor turn-on detection circuit 135 generates an upper transistor turn-on signal, and the control circuit 133 controls the upper transistor MH to turn on according to the upper transistor turn-on signal.
[0102] In some embodiments, the control circuit 133 can determine whether the switching frequency of the boost circuit 110 has reached the maximum switching frequency, and when the switching frequency reaches the maximum switching frequency, it generates a frequency limiting signal CLK. The lower transistor ML is turned on according to the frequency limiting signal CLK, which can improve the problem of poor circuit stability caused by excessively high switching frequency.
[0103] In some embodiments, Figure 11 A circuit diagram of a control circuit provided in an embodiment of this disclosure is shown below. Figure 11 As shown, the control circuit 133 includes a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fourth AND gate AND4, a fifth AND gate AND5, a sixth AND gate AND6, a seventh AND gate AND7, an eighth AND gate AND8, a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, a first inverter INV1, a second inverter INV2, a third inverter INV3, a first SR latch Latch1, and a second SR latch Latch2.
[0104] The first input of the first AND gate AND1 is connected to the frequency limiting signal CLK. The second input of the first AND gate AND1 is connected to the upper transistor turn-off control signal HS_OFF. The output of the first AND gate AND1 is connected to the first input of the second AND gate AND2 and the first input of the third AND gate AND3. The second input of the second AND gate AND2 is connected to the lower transistor turn-on signal FB_L. The third input of the second AND gate AND2 is connected to the boost voltage rise signal RISE. The output of the second AND gate AND2 is connected to the first input of the first NOR gate NOR1. The second input of the third AND gate AND3 is connected to the auxiliary turn-on signal FB_H. The third input of the third AND gate AND3 is connected to the boost voltage fall signal FALL. The output of the third AND gate AND3 is connected to the second input of the first NOR gate NOR1.
[0105] The first input of the fourth AND gate AND4 is connected to the boost voltage rise signal RISE, the second input of the fourth AND gate AND4 is connected to the lower transistor turn-off signal MAIN TRIP, the output of the fourth AND gate AND4 is connected to the first input of the second NOR gate NOR2, the second input of the second NOR gate NOR2 is connected to the first current limiting signal LIM, the first input of the fifth AND gate AND5 is connected to the boost voltage fall signal FALL, the second input of the fifth AND gate AND5 is connected to the second current limiting signal NTRIP, and the output of the fifth AND gate AND5 is connected to the third input of the second NOR gate NOR2.
[0106] The first input of the sixth AND gate AND6 is connected to the boost voltage rise signal RISE, the second input of the sixth AND gate AND6 is connected to the zero-crossing signal ZCD, the output of the sixth AND gate AND6 is connected to the first input of the third NOR gate NOR3, the first input of the seventh AND gate AND7 is connected to the boost voltage fall signal FALL, the second input of the seventh AND gate AND7 is connected to the lower transistor turn-on signal FB_L, and the output of the seventh AND gate AND7 is connected to the second input of the third NOR gate NOR3.
[0107] The set input of the first SR latch Latch1 Connect the output of the first NOR gate (NOR1) to the reset terminal of the first SR latch (Latch1). Connect the output of the second NOR gate NOR2 and the set input of the second SR latch Latch2. The inverting output of the first SR latch, Latch1 The control terminal of the lower transistor LS is connected to the first inverter INV1, and the reset terminal of the second SR latch Latch2 is connected to it. Connect the output of the third NOR gate (NOR3) to the inverted output of the second SR latch (Latch2). The first input terminal of the eighth AND gate AND8 is connected through the second inverter INV2. The upper transistor turn-on signal is connected to the second input terminal of the eighth AND gate AND8 through the third inverter INV3. The output terminal of the eighth AND gate AND8 is connected to the control terminal of the upper transistor HS.
[0108] This disclosure also provides a piezoelectric ceramic capacitor driving chip, including the piezoelectric ceramic capacitor driving circuit 100 provided in any of the above embodiments.
[0109] The piezoelectric ceramic capacitor driving chip provided in this embodiment includes the piezoelectric ceramic capacitor driving circuit 100 provided in any of the above embodiments, and has the functional modules and beneficial effects of the piezoelectric ceramic capacitor driving circuit 100, which will not be repeated here.
[0110] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” are to be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” should be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, the “example” is merely exemplary and illustrative, and should not be considered exclusive or extensive.
[0111] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.
Claims
1. A piezoelectric ceramic capacitor drive circuit, characterized by comprising: Includes boost circuit, full-bridge circuit and boost control circuit; The full-bridge circuit has a positive voltage output terminal and an anti-phase voltage output terminal, and the piezoelectric ceramic capacitor is connected across the positive voltage output terminal and the anti-phase voltage output terminal; The boost circuit has a voltage input terminal and a voltage output terminal. The voltage input terminal is connected to the power supply voltage, and the voltage output terminal is connected to the input terminal of the full-bridge circuit to output a boosted voltage. The boost circuit includes an upper transistor, a lower transistor, and an inductor. The upper transistor and the lower transistor are connected in series between the voltage output terminal and the reference ground. The connection point of the upper transistor and the lower transistor is a switching node. The switching node is connected to the voltage input terminal through the inductor. The boost control circuit includes a voltage sampling circuit, a lower MOSFET turn-on detection circuit, and a control circuit. The first input terminal of the voltage sampling circuit is connected to the positive voltage output terminal, the second input terminal of the voltage sampling circuit is connected to the inverted voltage output terminal, and the output terminal of the voltage sampling circuit is connected to the first input terminal of the lower MOSFET turn-on detection circuit to output a feedback voltage. The second input terminal of the lower MOSFET turn-on detection circuit is connected to a reference voltage. The output terminal of the lower MOSFET turn-on detection circuit is connected to the first input terminal of the control circuit to output a lower MOSFET turn-on signal. The first output terminal of the control circuit is connected to the control terminal of the lower MOSFET. The second output terminal of the control circuit is connected to the control terminal of the upper MOSFET.
2. The piezoelectric ceramic capacitor driving circuit according to claim 1, wherein The full-bridge circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The first terminal of the third transistor and the first terminal of the fourth transistor are connected to the voltage input terminal. The second terminal of the third transistor is connected to the inverting voltage output terminal and the first terminal of the second transistor. The second terminal of the fourth transistor is connected to the non-inverting voltage output terminal and the first terminal of the first transistor. The second terminal of the first transistor and the second terminal of the second transistor are connected to the voltage output terminal.
3. The piezoelectric ceramic capacitor driving circuit according to claim 1, wherein The voltage sampling circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a chopper, and an operational amplifier; the lower transistor turn-on detection circuit includes a first comparator. The positive voltage output terminal is connected to the first terminal of the chopper through the first resistor, the negative voltage output terminal is connected to the second terminal of the chopper through the second resistor, the third terminal of the chopper is connected to the positive input terminal of the operational amplifier and the first terminal of the third resistor, and the fourth terminal of the chopper is connected to the first terminal of the fourth resistor and the negative input terminal of the operational amplifier. The second end of the third resistor is connected to the common-mode voltage of the feedback voltage and the reference voltage. The second end of the fourth resistor is connected to the output of the operational amplifier and the non-inverting input of the first comparator. The inverting input of the first comparator is connected to the reference voltage. The output of the first comparator is connected to the first input of the control circuit to output the lower transistor turn-on signal when the feedback voltage is less than the reference voltage.
4. The piezoelectric ceramic capacitor drive circuit according to claim 3, wherein The boost control circuit also includes a first current source, a second current source, and a lower transistor turn-off detection circuit; The output terminal of the first current source is connected to the first input terminal of the lower MOSFET turn-off detection circuit, the second current source is connected to the second input terminal of the lower MOSFET turn-off detection circuit, and the output terminal of the lower MOSFET turn-off detection circuit is connected to the second input terminal of the control circuit to output a lower MOSFET turn-off signal.
5. The piezoelectric ceramic capacitor drive circuit according to claim 4, wherein The lower transistor turn-off detection circuit includes a first capacitor, a fifth resistor, and a second comparator. The first plate of the first capacitor is connected to the output terminal of the first current source and the non-inverting input terminal of the second comparator. The first terminal of the fifth resistor is connected to the output terminal of the second current source and the inverting input terminal of the second comparator. The output terminal of the second comparator is connected to the second input terminal of the control circuit. The second plate of the first capacitor and the second terminal of the fifth resistor are connected to the reference ground.
6. The piezoelectric ceramic capacitor driving circuit according to claim 4, characterized in that, The boost control circuit also includes an upper tube activation detection circuit; The input terminal of the upper MOSFET turn-on detection circuit is connected to the switching node, and the output terminal of the upper MOSFET turn-on detection circuit is connected to the third input terminal of the control circuit, so as to output an upper MOSFET turn-on signal when the sum of the switching node voltage and the clamping voltage is equal to the boost voltage.
7. The piezoelectric ceramic capacitor drive circuit according to claim 6, wherein The upper transistor turn-on detection circuit includes a sixth resistor, a fifth transistor, a clamping transistor, a second capacitor, and a Schmitt trigger; The first end of the sixth resistor and the power supply terminal of the Schmitt trigger are connected to the voltage output terminal. The second end of the sixth resistor is connected to the first end of the fifth transistor and the input terminal of the Schmitt trigger. The second end of the fifth transistor is connected to the first end of the clamping transistor and the first plate of the second capacitor. The second end of the clamping transistor and the second plate of the second capacitor are connected to the switching node. The output terminal of the Schmitt trigger is connected to the third input terminal of the control circuit.
8. The piezoelectric ceramic capacitor drive circuit according to claim 2, wherein The boost control circuit also includes a current sampling circuit and a zero-crossing detection circuit; The first input terminal of the current sampling circuit is connected to the positive voltage output terminal, the second input terminal of the current sampling circuit is connected to the inverted voltage output terminal, and the output terminal of the current sampling circuit is connected to the first input terminal of the zero-crossing detection circuit, so as to output the sampling current of the third transistor in the first cycle of the boost voltage and output the sampling current of the fourth transistor in the second cycle of the boost voltage. The second input terminal of the zero-crossing detection circuit is connected to the voltage input terminal, and the output terminal of the zero-crossing detection circuit is connected to the fourth input terminal of the control circuit, so as to output a zero-crossing signal when the sampled current is equal to the reference current.
9. The piezoelectric ceramic capacitor drive circuit according to claim 8, characterized by, The current sampling circuit includes a first sampling transistor and a second sampling transistor, and the zero-crossing detection circuit includes a third comparator; The control terminal of the first sampling transistor is connected to the control terminal of the third transistor, the control terminal of the second sampling transistor is connected to the control terminal of the fourth transistor, the first terminal of the first sampling transistor and the first terminal of the second sampling transistor are connected to the inverting input terminal of the third comparator, the second terminal of the first sampling transistor is connected to the second terminal of the third transistor, the second terminal of the second sampling transistor is connected to the second terminal of the fourth transistor, the non-inverting input terminal of the third comparator is connected to the voltage input terminal, and the output terminal of the third comparator is connected to the fourth input terminal of the control circuit.
10. The piezoelectric ceramic capacitor drive circuit according to claim 6, wherein The control circuit includes a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, a second inverter, a third inverter, a first SR latch, and a second SR latch. The first input of the first AND gate is connected to a frequency limiting signal; the second input of the first AND gate is connected to a high-side transistor turn-off control signal; the output of the first AND gate is connected to the first input of the second AND gate and the first input of the third AND gate; the second input of the second AND gate is connected to a low-side transistor turn-on signal; the third input of the second AND gate is connected to a boost voltage rise signal; the output of the second AND gate is connected to the first input of the first NOR gate; the second input of the third AND gate is connected to an auxiliary turn-on signal; the third input of the third AND gate is connected to a boost voltage fall signal; and the output of the third AND gate is connected to the second input of the first NOR gate. The first input of the fourth AND gate is connected to the boost voltage rise signal, the second input of the fourth AND gate is connected to the lower transistor turn-off signal, the output of the fourth AND gate is connected to the first input of the second NOR gate, the second input of the second NOR gate is connected to the first current limiting signal, the first input of the fifth AND gate is connected to the boost voltage fall signal, the second input of the fifth AND gate is connected to the second current limiting signal, and the output of the fifth AND gate is connected to the third input of the second NOR gate. The first input of the sixth AND gate is connected to the boost voltage rise signal, the second input of the sixth AND gate is connected to the zero-crossing signal, the output of the sixth AND gate is connected to the first input of the third NOR gate, the first input of the seventh AND gate is connected to the boost voltage fall signal, the second input of the seventh AND gate is connected to the lower transistor turn-on signal, and the output of the seventh AND gate is connected to the second input of the third NOR gate. The set terminal of the first SR latch is connected to the output terminal of the first NOR gate. The reset terminal of the first SR latch is connected to the output terminal of the second NOR gate and the set terminal of the second SR latch. The inverted output terminal of the first SR latch is connected to the control terminal of the lower transistor through the first inverter. The reset terminal of the second SR latch is connected to the output terminal of the third NOR gate. The inverted output terminal of the second SR latch is connected to the first input terminal of the eighth AND gate through the second inverter. The upper transistor enable signal is connected to the second input terminal of the eighth AND gate through the third inverter. The output terminal of the eighth AND gate is connected to the control terminal of the upper transistor.