Program and method

Abstract

A program according to one embodiment of the present disclosure causes a computer to execute: a first input procedure for inputting a first nonterminal node and a second nonterminal node on a zero-suppressed binary decision diagram; a second input procedure for inputting at least designation of a first function representing a condition to be satisfied by a set pair of a set included in a set group represented by the first nonterminal node and a set included in a set group represented by the second nonterminal node; and a calculation procedure for executing a set group calculation of the set group represented by the first nonterminal node and the set group represented by the second nonterminal node, on the basis of the first nonterminal node, the second nonterminal node, the first function, and a template of an algorithm for achieving the set group calculation.

Description

Program and Method

[0001] This disclosure relates to programs and methods.

[0002] A data structure called a zero-suppressed binary decision graph (ZDD) is known as a technique that compresses a family of sets and allows operations to be performed on them while they remain compressed (Non-Patent Literature 1). In addition to basic operations such as union and intersection, advanced operations on ZDDs have been systematized as family algebra (Non-Patent Literature 2).

[0003] S. Minato. Zero-suppressed BDDs for set manipulation in combinatorial problems. In Proc. of the 30th ACM / IEEE Design Automation Conference (DAC 1993), pages 272-277, 1993.DE Knuth. The Art of Computer Programming: Vol. 4A. Combinatorial Algorithms, Part 1, volume 4A: Combinatorial Algorithms, Part I. Addison-Wesley Professional, 2011.

[0004] However, family algebra does not include any special operations, and there may be requests that cannot be fulfilled using only the operations included in family algebra.

[0005] This disclosure has been made in view of the above points and aims to provide a technology that can realize a desired set family operation.

[0006] A program according to one aspect of the present disclosure causes a computer to execute: a first input procedure for inputting a first non-terminal node and a second non-terminal node on a zero-suppressed binary decision graph; a second input procedure for inputting at least a specification of a first function that represents a condition that a pair of sets, one set in the family of sets represented by the first non-terminal node and the other set in the family of sets represented by the second non-terminal node, must satisfy; and an operation procedure for performing a family of sets operation between the family of sets represented by the first non-terminal node and the family of sets represented by the second non-terminal node, based on the first non-terminal node, the second non-terminal node, the first function, and a template of an algorithm for realizing a family of sets operation.

[0007] A technique is provided that enables the realization of a desired set-family operation.

[0008] This figure shows an example of an algorithm for implementing a Meet operation. This figure shows an example of the hardware configuration of the set family arithmetic device according to this embodiment. This figure shows an example of the functional configuration of the set family arithmetic device according to this embodiment. This flowchart shows an example of the operation of the set family arithmetic device according to this embodiment. This is a figure (1 / 2) showing an example of an algorithm template for implementing a general set family arithmetic. This is a figure (2 / 2) showing an example of an algorithm template for implementing a general set family arithmetic. This is a figure (1 / 2) showing an example of an algorithm template for implementing a set family arithmetic that includes ForAll as a condition. This is a figure (2 / 2) showing an example of an algorithm template for implementing a set family arithmetic that includes ForAll as a condition.

[0009] One embodiment of the present invention will be described in detail below with reference to the drawings.

[0010] <Background> A family of sets is a set whose elements are other sets. It is known that many practical concepts can be expressed as families of sets. There are many types of operations that generate new families of sets from existing families of sets (e.g., meet operations, non-subset operations, etc.).

[0011] The Meet Operation is an operation in which, given two families of sets F and G, the intersection of all possible pairs of sets in family F and family G is calculated, and a family of sets is created from these intersections. The Meet Operation is applied to real-world problems such as common factor extraction. Common factor extraction is the problem of determining how similar (or dissimilar) sets are to each other within a given family of sets. In this problem, by performing a Meet Operation between the given family of sets and itself, the intersection of all pairs of sets is calculated, and these intersections can be considered as similarity scores. Common factor extraction is used in fields such as data mining.

[0012] Non-subset operations are operations that, given two families of sets F and G, find sets that are included in family F but not included in any of the sets in family G. For example, in the case of extracting common factors, it is possible to find all sets of family F that have elements not common to any of the sets in family G, that is, all sets of family F that have a distance of 1 or more to all of the sets in family G.

[0013] As shown in the example above, families of sets and their operations are applied to a variety of real-world problems. However, since the size of a family of sets increases exponentially with the number of elements in the set, it is necessary to perform operations efficiently. In response to this, ZDD is known as a data structure that can compress and represent families of sets and perform operations on them while they remain compressed (Non-Patent Literature 1). ZDD is a data structure that represents families of sets using an undirected acyclic graph (DAG), and it supports various family of sets operations, including the MEAT operation.

[0014] Due to its high compression ratio and computational power, ZDD has been applied to various real-world problems. In addition to basic operations such as union and intersection, advanced operations on ZDD have been systematized as family algebra (Non-Patent Literature 2). Family algebra consists of well-known operations, but does not include special operations that may be necessary in specific situations.

[0015] <Challenge> While ZDD supports many operations, it still doesn't support a sufficient number of operations, and there are cases where requirements cannot be met using only existing combinations of operations. In such cases, creating an algorithm that can perform the operations that satisfy the requirements requires specialized knowledge of ZDD.

[0016] <Proposed Method> We propose an algorithm template for computation that extends family algebra on ZDD.

[0017] The following discussion will focus on operations within family algebra that can be formalized in the form shown in equation (1) below.

[0018]

[0019] Here, F and G are families of sets, ○ is an operation, and p and q are functions.

[0020] By specifying concrete entities for the operation ○ and functions p and q in equation (1) above, it is possible to realize specific set family operations, including, for example, the Meet operation.

[0021] Let U = {1, ..., σ} be the underlying set of families F and G, where σ is an integer greater than or equal to 1.

[0022] In this case, the operation ○ can be a set operation that satisfies the associative law, such as a union operation, intersection operation, exclusive union operation, or frequent union operation.

[0023] Furthermore, the function p can be a function that satisfies the constraints shown in equation (2) below.

[0024]

[0025] Here, c ０ is a variable c ∈ R that holds intermediate calculation results when recursively calculating set family operations, and is the initial value of ｄ it. Also, d is an integer greater than or equal to 0. When d = 0, c does not exist (therefore, naturally, c ０ also does not exist). Also, when d = 0, p(s, t) = true.

[0026] Also, as the function q, a function that satisfies the constraints shown in the following formula (3) can be specified.

[0027]

[0028] Here, both is a special value that means both true and false. That is, for example, for a certain element i, when the set generated from the set pair s, t necessarily contains the element i, q ｉ = true, when it necessarily does not contain it, q ｉ = false, and when it may or may not contain it, q ｉ = both.

[0029] Also, the following symbols represent set family operations defined by the following formula (4) for any set families F, G.

[0030]

[0031]

[0032] By making a small change to the operation shown in the above formula (1), an operation in the form shown in the following formula (5) can also be realized.

[0033]

[0034] Next, the family of set operations device 10 that implements the operation of the form shown in the above formula (1) (or the above formula (5)) will be described. According to the family of set operations device 10 according to the present embodiment, by specifying an operation ○ that satisfies the associative law and functions p and q that satisfy the constraints shown in the above formulas (2) and (3), any family of set operations of the form shown in the above formula (1) can be realized. Further, according to the family of set operations device 10 according to the present embodiment, by specifying a function p that satisfies the constraint shown in the above formula (2), any family of set operations of the form shown in the above formula (5) (that is, a family of set operations including the ForAll condition) can be realized.

[0035] Note that the function p represents "a function that determines the condition that a pair of sets should satisfy", and the function q represents "a function that generates a set from a pair of sets". As shown in the above formulas (2) and (3), these two functions are restricted to be decomposable into per-element sub-functions, which enables an operation that can be efficiently executed on ZDD.

[0036] <Preparation> Below, ZDD will be described as a preparation necessary for the description of the above family of set operations device 10. Also, as an example, an existing algorithm for implementing the meet operation on ZDD will be described.

[0037] <<ZDD>> Let the ZDD Z be represented by the following seven-tuple.

[0038]

[0039] Here, U = {1,..., σ} is the base set. V is the set of non-terminal nodes of the ZDD Z. The bottom symbol and the top symbol are the terminal nodes of the ZDD Z. Hereinafter, in the text of this specification, the top symbol will be substituted with the capital tau (Τ).

[0040] λ is a label function λ: V ∪ {⊥, Τ} → U ∪ {0} for extracting a label from a node. The label of each node v of the ZDD Z can be obtained by λ(v). The label of a non-terminal node is any element of the base set U, and the label of a terminal node is 0.

[0041] Each non-terminal node v has two children δ ０(v) and δ １ has (v), which are called 0 - child and 1 - child respectively. The edge from a non - terminal node to its 0 - child is called 0 - branch, and the edge to its 1 - child is called 1 - branch. For any non - terminal node v, λ(v) < λ(δ ０ (v)) and λ(v) < λ(δ １ (v)) hold. That is, it is guaranteed that any non - terminal node always has a label smaller than that of its children.

[0042] - The set family represented by ZDD Z represents the set family on the base set U as follows. The set family F(v) represented by each node v is recursively defined by the rules shown in (a1) and (a2) below. (a1) When the node v is a terminal node, if v = Τ, then F(v) = {φ}; if v = ⊥, then F(v) = φ. (a2) When the node v is a non - terminal node, F(v) = {λ(v)}×F(δ １ (v)) ∪ F(δ ０ (v)).

[0043] According to the above definition, a certain set s = {e １ , ···, e ｄ} corresponds to the following path on ZDD Z. That is, starting from a certain node v, at a non - terminal node with label e, if e ∈ s, extend the path to the 1 - branch; otherwise, extend the path to the 0 - branch. By repeating this procedure, finally, it reaches one of the terminal nodes. When the path reaches the terminal node Τ, it means s ∈ F(v); when the path reaches the terminal node ⊥, it means that the set s is not included in the set family F(v). Therefore, there are |F(v)| paths from the node v to the terminal node Τ. The number of paths from the node v to the terminal node Τ is called the density of the node v.

[0044] << Algorithm for realizing the meet operation >> Figure 1 is a diagram showing an example of an algorithm for realizing the meet operation. The algorithm shown in Figure 1 takes non - terminal nodes u, v ∈ V of ZDD Z as input and outputs a non - terminal node w representing the result F(w) of the meet operation between the set family F(u) and the set family F(v).

[0045] Here, GETNODE(i, u, v) means λ(w) = i, δ ０(w) = u, δ １ This function returns a pointer to node w if a node w satisfying (w) = v exists, and creates the node w otherwise. Furthermore, h is a key-value type hash table; h.insert(a, b) registers value b with a as the key, and h.find(a) returns a value with key a (however, it returns NULL if no value with key a is registered).

[0046] In Figure 1, (Meet, u, v) means calling the MEET function with u as the first argument and v as the second argument.

[0047] <Example of Hardware Configuration of the Set Family Arithmetic Unit 10> Figure 2 is a diagram showing an example of the hardware configuration of the set family arithmetic unit 10 according to this embodiment. As shown in Figure 2, the set family arithmetic unit 10 according to this embodiment includes an input device 101, a display device 102, an external I / F 103, a communication I / F 104, a RAM (Random Access Memory) 105, a ROM (Read Only Memory) 106, an auxiliary storage device 107, and a processor 108. Each of these hardware components is connected to each other so as to be able to communicate via a bus 109.

[0048] The input device 101 is, for example, a keyboard, mouse, touch panel, or physical button. The display device 102 is, for example, a display or display panel. The set-family arithmetic unit 10 does not necessarily have to have at least one of the input device 101 and the display device 102.

[0049] The external I / F 103 is an interface with external devices such as the recording medium 103a. Examples of recording media 103a include CDs (Compact Discs), DVDs (Digital Versatile Disks), SD memory cards (Secure Digital memory cards), and USB (Universal Serial Bus) memory cards.

[0050] The communication interface 104 is an interface for connecting to a communication network. The RAM 105 is a volatile semiconductor memory (storage device) that temporarily holds programs and data. The ROM 106 is a non-volatile semiconductor memory (storage device) that can retain programs and data even when the power is turned off. The auxiliary storage device 107 is a non-volatile storage device such as an HDD (Hard Disk Drive), SSD (Solid State Drive), or flash memory. The processor 108 is a computing device such as a CPU (Central Processing Unit) or GPU (Graphics Processing Unit).

[0051] Note that the hardware configuration shown in Figure 1 is just one example, and the hardware configuration of the set-family arithmetic unit 10 is not limited to this. For example, the set-family arithmetic unit 10 may have multiple auxiliary storage devices 107 or multiple processors 108, it may not have some of the hardware shown, or it may have various hardware other than the hardware shown.

[0052] <Example of Functional Configuration of the Set Family Arithmetic Unit 10> Figure 3 is a diagram showing an example of the functional configuration of the set family arithmetic unit 10 according to this embodiment. As shown in Figure 3, the set family arithmetic unit 10 according to this embodiment has an input unit 201, an arithmetic unit 202, and an output unit 203. Each of these units is realized by processing that one or more programs installed in the set family arithmetic unit 10 cause a processor 108 or the like to execute. The set family arithmetic unit 10 according to this embodiment also has a storage unit 204. The storage unit 204 is realized by a storage area such as an auxiliary storage device 107.

[0053] The input unit 201 receives ZDD Z and non-terminal nodes u, v ∈ V representing the family of sets to be subjected to the family of sets operation of the form shown in equation (1) or equation (5) above. The non-terminal nodes u, v ∈ V representing the family of sets to be subjected to the family of sets operation are specified, for example, by the user of the family of sets operation device 10.

[0054] Furthermore, when performing a family of sets operation of the form shown in equation (1) above, the input unit 201 receives input specifying an operation ○ that satisfies the associative law and functions p and q that satisfy the constraints shown in equations (2) and (3) above. On the other hand, when performing a family of sets operation of the form shown in equation (5) above, the input unit 201 receives input specifying a function p that satisfies the constraint shown in equation (2) above. These specifications are provided, for example, by the user of the family of sets operation device 10.

[0055] The arithmetic unit 202 implements the set family operation on two sets represented by u, v ∈ V, based on the specification input by the input unit 201 and a template of an algorithm that implements a set family operation of the form shown in equation (1) or equation (5) above. The arithmetic unit 202 can implement the set family operation by applying the specification to the template and then executing the algorithm.

[0056] The output unit 203 outputs the result of the set family operation performed by the calculation unit 202 to a predetermined output destination. Examples of such output destinations include a display device 102 such as a display, a program, or other devices or equipment connected via communication.

[0057] The memory unit 204 stores ZDD Z, which represents the family of sets that are the target of the family of sets operation.

[0058] <Example of operation of the set family arithmetic unit 10> Figure 4 is a flowchart showing an example of the operation of the set family arithmetic unit 10 according to this embodiment.

[0059] The input unit 201 receives ZDD Z and non-terminal nodes u, v∈V representing the family of sets to be subjected to the family of sets operation (step S101).

[0060] The input unit 201 inputs an operation ○ that satisfies the associative law and functions p and q that satisfy the constraints shown in equations (2) and (3) above when performing a family of set operations of the form shown in equation (1) above, and inputs a function p that satisfies the constraint shown in equation (2) above when performing a family of set operations of the form shown in equation (5) above (step S102). When specifying the function p, d is also specified, and if d ≠ 0, c ０ Please note that this will also be specified at the same time.

[0061] The arithmetic unit 202 implements the set family operation on the two sets represented by u, v ∈ V based on the specification input in step S102 and the template of the algorithm that implements the set family operation of the form shown in equation (1) or equation (5) above (step S103). That is, the arithmetic unit 202 implements the set family operation by applying the specification to the template and then executing the algorithm. Details of the template of the algorithm that implements the set family operation of the form shown in equation (1) or equation (5) above will be described later.

[0062] The output unit 203 outputs the result of the set family operation in step S103 to a predetermined output destination (step S104).

[0063] ≪Template for an algorithm that implements a family of sets operation of the form shown in equation (1) above≫ Figures 5A and 5B show an example of a template for an algorithm that implements a general family of sets operation. The operation ○ and functions p and q specified in step S101 above are applied to the algorithm template shown in Figures 5A and 5B, and then the algorithm is executed for u, v ∈ V input in step S101 above. This makes it possible to implement a family of sets operation of the form shown in equation (1) above. Note that when the function GENOPE(u, v, c) shown in Figures 5A and 5B is called for the first time, the non-terminal nodes u, v ∈ V input in step S101 above are specified as the first and second arguments, and if d ≠ 0, then c = c ０ This is specified as the third argument. Also, in Figures 5A and 5B, (Genope, u, v, c) means calling the GENOPE function with u as the first argument, v as the second argument, and c as the third argument.

[0064] For example, let's assume that d = 0, and that in step S102 above, 〇 = ∪, p(s, t) = true, and q(s, t) = {s∩t} are specified. In this case, the MIT operation can be realized by applying these specifications to the algorithm templates shown in Figures 5A and 5B. That is, the algorithms to which these specifications are applied in Figures 5A and 5B are equivalent to the algorithm shown in Figure 1.

[0065] Furthermore, the algorithm templates shown in Figures 5A and 5B can be described as algorithms that realize a family of sets operation of the form shown in equation (1) above, divided into a common part and an eigenpart, with the eigenpart being made variable by specifying the operation 〇 and functions p and q.

[0066] ≪Argument template for realizing the set family operation of the form shown in equation (5) above≫ Figures 6A and 6B show an example of an algorithm template for realizing a set family operation that includes ForAll as a condition. The function p specified in step S101 above is applied to the algorithm template shown in Figures 6A and 6B, and then the algorithm is executed for u, v∈V input in step S101 above. This makes it possible to realize the set family operation of the form shown in equation (5) above. Note that when the function GENOPEFA(u, v, c) shown in Figures 6A and 6B is called for the first time, the non-terminal nodes u, v∈V input in step S101 above are specified as the first and second arguments, and if d≠0, then c=c ０ This is specified as the third argument. Also, in Figures 6A and 6B, (GenopeFA, u, v, c) means calling the GENOPEFA function with u as the first argument, v as the second argument, and c as the third argument.

[0067] For example, if the following is specified for p in step S102 above, a non-subset operation can be realized.

[0068]

[0069] In other words, the algorithm to which the above specifications are applied in Figures 6A and 6B is equivalent to the algorithm that implements non-subset operations.

[0070] Furthermore, the algorithm templates shown in Figures 6A and 6B can be described as an algorithm that implements a family of sets operation of the form shown in equation (5) above, but with its intersection and eigenparts separated, and the eigenparts made variable by specifying the function p.

[0071] <Summary> As described above, the set family arithmetic unit 10 according to this embodiment can realize a desired set family arithmetic operation on ZDD by specifying the operation ○ and functions p and q. Therefore, with the set family arithmetic unit 10 according to this embodiment, even a person without specialized knowledge of ZDD can easily realize a desired set family arithmetic operation.

[0072] The present invention is not limited to the embodiments specifically disclosed above, and various modifications, changes, and combinations with known technologies are possible without departing from the spirit of the claims.

[0073] 10 Set family arithmetic unit 101 Input device 102 Display device 103 External I / F 103a Recording medium 104 Communication I / F 105 RAM 106 ROM 107 Auxiliary storage device 108 Processor 109 Bus 201 Input unit 202 Arithmetic unit 203 Output unit 204 Storage unit

Claims

1. A program that causes a computer to execute: a first input procedure for inputting a first non-terminal node and a second non-terminal node on a zero-suppressed binary decision graph; a second input procedure for inputting at least a specification of a first function that represents a condition that a pair of sets, one set in the family of sets represented by the first non-terminal node and the other set in the family of sets represented by the second non-terminal node, must satisfy; and an operation procedure for performing a family of sets operation on the family of sets represented by the first non-terminal node and the family of sets represented by the second non-terminal node, based on the first non-terminal node, the second non-terminal node, the first function, and a template of an algorithm that realizes a family of sets operation.

2. The program according to claim 1, wherein the second input procedure further inputs the specification of a second function for generating a new set from the pair of sets and a set operation that satisfies the associative law, and the operation procedure executes the set family operation based on the second function and the set operation.

3. The program according to claim 1 or 2, wherein the template includes a fixed portion and a variable portion of the algorithm, and the calculation procedure performs the set family operation by setting the information specified in the second input procedure for the variable portion and then executing the algorithm.

4. A method by which a computer executes: a first input procedure for inputting a first non-terminal node and a second non-terminal node on a zero-suppressed binary decision graph; a second input procedure for inputting at least a specification of a first function that represents a condition that a pair of sets, one set in the family of sets represented by the first non-terminal node and the other in the family of sets represented by the second non-terminal node, must satisfy; and an operation procedure for executing a family of sets operation between the family of sets represented by the first non-terminal node and the family of sets represented by the second non-terminal node, based on the first non-terminal node, the second non-terminal node, the first function, and a template of an algorithm that realizes a family of sets operation.

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