Display apparatus and electronic device

Abstract

One of the purposes of this disclosure is to provide a display apparatus with which it is possible to expand the dynamic range of a video signal, and an electronic device having the display apparatus.　This display apparatus includes a plurality of pixel circuits. Each of the pixel circuits includes a first transistor that controls an input current to a light emitting element that emits light with luminance that accords with the input current, a second transistor that controls writing of a pixel signal to a gate of the first transistor, and a first capacitor formed between the gate of the first transistor and a gate of the second transistor.

Description

Display device and electronic device

[0001] The present technology relates to a display device and an electronic device.

[0002] There is known a display device having a light-emitting element (so-called current-driven light-emitting element) whose emission luminance changes according to the current value of an input current. Patent Document 1 below discloses a technique for correcting the threshold voltage of a driving transistor that controls the current flowing through the light-emitting element. Along with this, a technique is disclosed in which the initialization voltage applied to the gate (control terminal) of the transistor is set to a lower value as the voltage value of the video signal (gradation voltage signal) is higher, thereby improving the dynamic range and contrast.

[0003] Japanese Patent Application Laid-Open No. 2015-55837

[0004] By the way, improvement in light-emitting efficiency is required for the light-emitting element used in the display device. However, as the light-emitting element becomes more efficient, there is a concern that the dynamic range of the video signal will be reduced and the gradation accuracy will deteriorate. Therefore, a technique for expanding the dynamic range of the video signal from a different perspective from Patent Document 1 is desired.

[0005] One of the objectives of the present technology is to provide, for example, a display device capable of expanding the dynamic range of a video signal, and an electronic device having the display device.

[0006] The present technology is, for example, a display device having a plurality of pixel circuits, wherein the pixel circuit includes a first transistor that controls the input current to a light-emitting element that emits light with luminance corresponding to the input current, a second transistor that controls writing of a pixel signal to the gate of the first transistor, and a first capacitor formed between the gate of the first transistor and the gate of the second transistor.

[0007] The present technology is, for example, an electronic device having the display device of the present technology.

[0008] Figure 1 is a diagram showing a schematic configuration example of a pixel circuit in a comparative example display device. Figure 2 is a graph illustrating the light emission characteristics according to the efficiency of the light-emitting element. Figure 3 is a block diagram showing a configuration example of a display device according to one embodiment of this technology. Figure 4 is a diagram showing a configuration example of a pixel circuit in a pixel section. Figure 5 is a timing chart showing an example of operation of a display device according to one embodiment. Figure 6A is a graph showing the relationship between the gate-source voltage of the drive transistor and the signal voltage during light emission, and Figure 6B is a graph showing the relationship between brightness and signal voltage during light emission. Figure 7 is a diagram showing a cross-sectional configuration example of a panel that can be used as a display device. Figure 8A is a diagram showing a cross-sectional configuration example when capacitors Cs and Cws are formed by MIM, and Figure 8B is a diagram showing a cross-sectional configuration example when capacitors Cs, Csub, and Cws are formed by MIM. Figure 9 is a diagram showing a planar configuration example when capacitors Cs, Csub, and Cws are all formed by MOM capacitors in the same layer. Figure 10 shows a planar configuration example when capacitors Cs and Cws are formed in the same layer using MOM capacitors. Figure 11 shows a planar configuration example when capacitor Cws is formed in a metal layer using MOM capacitors. Figure 12A shows a layout example according to a comparative example, and Figure 12B shows a layout configuration example when capacitor Cws is formed by parasitic capacitance between wirings. Figure 13 shows a layout configuration example when capacitor Cws is formed by parasitic capacitance between layers. Figure 14A shows a cross-sectional configuration example of a transistor forming capacitor Cws, and Figure 14B shows another cross-sectional configuration example of a transistor forming capacitor Cws. Figure 15A shows a planar configuration example of a transistor forming capacitor Cws, and Figure 15B shows another planar configuration example of a transistor forming capacitor Cws. Figure 16 is a diagram illustrating an example of a pixel circuit configuration in which this technology can be employed. Figure 17 shows one example of a pixel circuit configuration. Figure 18 shows one example of a pixel circuit configuration. Figure 19 shows an example of a pixel circuit configuration. Figure 20 shows an example of a pixel circuit configuration. Figure 21 shows an example of a pixel circuit configuration. Figure 22 shows an example of a pixel circuit configuration.Figure 23 is a diagram showing one example of a pixel circuit configuration. Figure 24 is a diagram showing one example of a pixel circuit configuration. Figure 25 is a perspective view showing one example of the appearance of a head-mounted display. Figure 26 is a perspective view showing one example of the appearance of another head-mounted display. Figure 27A is a front view showing one example of the appearance of a digital still camera. Figure 27B is a rear view showing one example of the appearance of a digital still camera. Figure 28 is a perspective view showing one example of the appearance of a television system. Figure 29 is a perspective view showing one example of the appearance of a smartphone. Figure 30A is a diagram showing one example of the interior of a vehicle from the rear to the front. Figure 30B is a diagram showing one example of the interior of a vehicle from the diagonal rear to the diagonal front.

[0009] The embodiments of this technology will be described below with reference to the drawings. The description will be given in the following order. In this specification and the drawings, components having substantially the same function or configuration will be denoted by the same reference numerals, and redundant explanations will be omitted as appropriate. In addition, the shape, size, positional relationship, etc. of the components shown in each drawing may be exaggerated depending on the content of the explanation, and reference numerals may be omitted to avoid complexity in the illustrations. The following description mainly concerns the parts related to this technology and does not exclude configurations or functions that are not shown or described. <1. One Embodiment of this Technology> 1-1. Overview of this Technology 1-2. Example of the Configuration of a Display Device According to This Embodiment 1-3. Example of Pixel Circuit Configuration 1-4. Example of Pixel Circuit Operation 1-5. Effects of this Embodiment <2. Specific Configuration Examples of Capacitor Cws> 2-1. Configuration Example 1 (Formation by MIM) 2-2. Configuration Example 2 (Formation by MO) 2-3. Configuration Example 3 (Formation by Parasitic Capacitance) 2-4. Configuration Example 4 (Formation by Transistor Internal Capacitance) <3. Other examples of pixel circuit configurations > <4. Modified versions> <5. Application examples>

[0010] <1. One Embodiment of the Technology> [1-1. Overview of the Technology] First, an overview of the technology will be described. Figure 1 is a diagram showing a schematic configuration example of a pixel circuit 11 in a comparative example display device 10. Although Figure 1 shows one pixel circuit 11 as a representative example, the display device 10 has a plurality of pixel circuits 11 arranged in a matrix. The pixel circuit 11 has a transistor 12 (WS Tr), a transistor 13 (Drv.Tr), a capacitor 14, and a light-emitting element 15. The transistors 12 and 13 are P-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The light-emitting element 15 changes its luminescence brightness according to the value of the input current (luminescence current Iel).

[0011] One end of capacitor 14 is connected to a high-potential power line. The cathode of light-emitting element 15 is connected to a low-potential power line. The gate of transistor 12 is connected to a control line (not shown here) to which a control signal is supplied, the source is connected to a signal line 17 to which the signal voltage Vsig of the video signal from driver IC 16 is supplied, and the drain is connected to the other end of capacitor 14 and the gate of transistor 13. The source of transistor 13 is connected to a high-potential power line, and the drain is connected to the anode of light-emitting element 15. The signal voltage Vsig represents the brightness level of light emission in the pixel circuit 11 with a predetermined number of gradations (for example, 256 gradations of 8 bits).

[0012] In this pixel circuit 11, the signal voltage Vsig is held in the capacitor 14 when the transistor 12 is turned on (conducting). Using this held signal voltage, the transistor 13 supplies a light-emitting current Iel to the light-emitting element 15 according to the gate-source voltage Vgs. As a result, the light-emitting element 15 emits light with a brightness corresponding to the signal voltage Vsig. Here, the light-emitting element 15 is being made more efficient from the viewpoint of reducing power consumption. However, as the efficiency of the light-emitting element 15 increases, there are concerns about deterioration of gradation accuracy and contrast.

[0013] Figure 2 is a graph illustrating the light emission characteristics according to the efficiency of the light-emitting element 15. The upper graph in Figure 2 shows the relationship between brightness (vertical axis) and signal voltage Vsig (horizontal axis) during light emission, while the lower graph shows the change in dynamic range according to the signal voltage Vsig (horizontal axis). For example, if the efficiency of the light-emitting element 15 is increased, even when emitting the same brightness, the dynamic range of the signal voltage Vsig becomes smaller compared to a low-efficiency element, and the width per gradation becomes smaller. Therefore, it is thought that achieving high accuracy becomes difficult as the efficiency of the light-emitting element 15 is increased. In addition, as shown in the upper graph in Figure 2, there is concern that the contrast may deteriorate due to the increased efficiency of the light-emitting element 15. Therefore, in one embodiment described below, a technique is proposed to improve gradation accuracy and contrast by expanding the dynamic range of the signal voltage Vsig.

[0014] [1-2. Example of the configuration of a display device according to one embodiment] Figure 3 is a block diagram showing an example of the configuration of a display device 1 according to one embodiment of the present technology. The display device 1 is a device that displays various information such as images using light-emitting elements. The light-emitting elements are, for example, LEDs (Light Emitting Diodes). LEDs include LEDs used in micro-LED displays and OLEDs (Organic Light Emitting Diodes) used in organic EL (Electro-Luminescence) displays. Hereinafter, the display device 1 will be described assuming that OLEDs are used as light-emitting elements. The display device 1 is, for example, a display mounted on an electronic device. Specific examples of electronic devices to which the display device 1 can be applied will be described later.

[0015] The display device 1 includes, as a circuit block, a pixel unit 2, a timing controller 3, a first drive unit 4, and a second drive unit 5. The display device 1 mounts all or part of these circuit blocks on a panel. The panel includes, for example, a semiconductor substrate such as silicon.

[0016] The pixel unit 2 has pixels (pixel circuits) PIX. Although Figure 3 shows one pixel PIX, the pixel unit 2 has multiple pixels PIX arranged in an m x n matrix (m and n are natural numbers), forming a display area. Note that the arrangement of the pixels PIX does not have to be a matrix; it is sufficient that the pixels PIX are arranged along a first direction and a second direction intersecting the first direction. Here, the first direction is assumed to be the column direction and the second direction is assumed to be the row direction.

[0017] The pixel section 2 is provided with pixels PIX representing the three primary colors, for example, R (red), G (green), and B (blue), to represent a color image. However, the number and arrangement of pixels PIX, and the color representation of the image are not limited to these; for example, a configuration with additional pixels PIX representing W (white) may be provided, or a monochrome (black and white) image may be represented.

[0018] Furthermore, the pixel unit 2 has control lines WSL, DSL, and AZSL that extend along the row direction of the pixel array, and signal lines SGL that extend along the column direction of the pixel array. The control lines WSL, DSL, and AZSL are provided for each pixel row, and the signal lines SGL are provided for each pixel column. The control lines WSL, DSL, and AZSL are connected to the output terminal of the corresponding row of the first drive unit 4 and to the pixel group of the corresponding row, respectively. The signal lines SGL are connected to the output terminal of the corresponding column of the second drive unit 5 and to the pixel group of the corresponding column, respectively. Specifically, the control line WSL (first control line) is supplied with a control signal that controls the writing of pixel signals to the pixel PIX, the control line DSL (second control line) is supplied with a control signal that controls the light emission state of the pixel PIX, the control line AZSL (third control line) is supplied with a control signal that initializes the pixel PIX as appropriate, and the signal line SGL is supplied with pixel signals such as the signal voltage Vsig. The control signal is a signal that performs control by switching the voltage level (for example, switching between low voltage and high voltage). The type and number (including the number of the same type) of control lines connected to the first drive unit 4 and signal lines connected to the second drive unit 5 are appropriately changed according to the configuration of the pixel PIX in the pixel unit 2. In this specification, "lines" such as control lines and power lines include not only linear wiring but also planar wiring.

[0019] The timing controller 3 controls the drive timing of the first drive unit 4 and the second drive unit 5. The timing controller 3 controls the operation of the first drive unit 4 and the second drive unit 5 based on, for example, an external input signal. The timing controller 3 is connected to the first drive unit 4 and outputs a control signal to the first drive unit 4 to control it. The timing controller 3 is also connected to the second drive unit 5 and outputs a control signal to the second drive unit 5 to control it.

[0020] The first drive unit 4 generates and outputs control signals to the control lines WSL, DSL, and AZSL based on the control signals input from the timing controller 3. The first drive unit 4 can be configured as a shift register type circuit, for example, having a shift register circuit in the signal input section. The first drive unit 4 is not limited to this, and may be configured as an address decoder type circuit, for example, having an address decoder in the signal input section.

[0021] The second drive unit 5, based on the control signal input from the timing controller 3, distributes the externally input image data to each signal line SGL, converts the distributed image data into a video signal for each pixel, and outputs it to the corresponding signal line SGL of the pixel unit 2. The second drive unit 5 can be configured as, for example, a RAMPDAC circuit that uses an analog signal of ramp waveform to generate pixel signals such as video signals output to the signal line SGL. The second drive unit 5 is not limited to this, and may be configured as, for example, a voltage follower circuit having a voltage follower circuit at the output section to the signal line SGL.

[0022] [1-3. Example of Pixel Circuit Configuration] Figure 4 shows an example of the configuration of a pixel PIX in the pixel unit 2. An appropriate body voltage is applied to the body (back gate) of the following transistors. This pixel PIX has capacitors C11 and C12, transistors MP12 to MP15, and light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to the control line WSL, one of its source and drain is connected to the signal line SGL, and the other of its source and drain is connected to the gate of transistor MP14 and the other end of capacitor C12. One end of capacitor C11 is connected to the high-potential power line VCCP (power supply potential Vccp), and the other end is connected to one end of capacitor C12, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14. The other end is connected to the other of the source and drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, one of its source and drain is connected to the power line VCCP, and the other of its source and drain is connected to one of the source and drain of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the other of the source and drain of transistor MP12 and the other end of capacitor C12. One of its source and drain is connected to the other of the source and drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12. The other of its source and drain is connected to the anode of the light-emitting element EL and one of the source and drain of transistor MP15.The gate of transistor MP15 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP14 and to the anode of the light-emitting element EL, and the other of its source and drain is connected to the low-potential power line VSS (power supply potential Vssp). The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP14 and to one of the source and drain of transistor MP15, and its cathode is connected to the low-potential power line Vcath.

[0023] Furthermore, in this embodiment, the pixel PIX is further provided with a capacitor Cws (first capacitor) between the gate of transistor MP12 and the gate of transistor MP14. Specifically, one end of capacitor Cws is connected to the gate of transistor MP12, and the other end is connected to the gate of transistor MP14. Here, each gate includes all wiring electrically connected to the gate, for example, not only the gate electrode but also all gate wiring electrically connected to the gate. This gate wiring also includes electrodes of other elements and interlayer connections. Therefore, there are four possible connections between the gates: when the gate electrode of one transistor MP12 and the gate electrode of the other transistor are connected; when the gate electrode of one transistor and the gate wiring of the other transistor are connected; when the gate wiring of one transistor and the gate electrode of the other transistor are connected; and when the gate wiring of one transistor and the gate wiring of the other transistor are connected.

[0024] In other words, the control line WSL is connected to the gate of transistor MP12 and one end of capacitor Cws, and the other end of the source and drain of transistor MP12 is connected to the other end of capacitor C12, the gate of transistor MP14 and the other end of capacitor Cws. In this configuration example, transistor MP14 is a drive transistor (first transistor: Drv.Tr) that controls the light-emitting current Iel flowing through the light-emitting element EL, and transistor MP12 is a write control transistor (second transistor: WS Tr) that controls the writing of the pixel signal to the gate of transistor MP14. Transistor MP13 is a light-emitting control transistor (third transistor: DS Tr) that controls the light-emitting state of the light-emitting element EL, and transistor MP15 is an initialization transistor (fourth transistor: AZ Tr) that controls the initialization of transistor MP14. Furthermore, capacitor C12 functions as a holding capacitance (second capacitor: Cs) that holds the signal voltage Vsig of the video signal, and capacitor C11 functions as an auxiliary capacitance (third capacitor: Csub) that assists in holding the signal.

[0025] In this configuration, in a pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal from control line DSL. Transistor MP14 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C12 while transistor MP13 is on. The light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal from control line AZSL. While transistor MP15 is on, the voltage at the anode of the light-emitting element EL is initialized by being set to the voltage of power line VSS.

[0026] Furthermore, transistors MP12 to MP15 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP12 and MP15 may be a transistor made of oxide semiconductor.

[0027] [1-4. Example of Pixel Circuit Operation] Figure 5 is a timing chart showing an example of the operation of the display device 1. Specifically, Figure 5 shows the changes in the potentials of the control signals DS, WS, and AZ of the control lines DSL, WSL, and AZSL, the potentials of the source and gate of transistor MP14, and the potential of the anode of the light-emitting element EL. Transistors MP12, MP13, and MP15 are P-channel type, and the low-level (low potential) state of the control signals WS, DS, and AZ of the corresponding control lines WSL, DSL, and AZSL connected to the gates of each transistor indicates conduction, while the high-level (high potential) state indicates non-conduction. The relative magnitudes of the potentials are power supply potential Vccp > potential Vofs > potential Vssp.

[0028] First, at a certain point in time t0, the control signals DS and WS become high levels, and transistors MP12 and MP13 are turned off. On the other hand, the control signal AZ becomes low level, and transistor MP15 is turned on. As a result, the anode potential of the light-emitting element EL becomes Vssp. Therefore, the light-emitting element EL becomes extinguished.

[0029] Next, at time t1, the control signal DS goes low, and transistor MP13 turns on. As a result, the source potential of transistor MP14 becomes Vccp. Then, at time t2, the control signal WS goes low, and transistor MP12 turns on. At this time t2, the pixel signal of signal line SGL is controlled to the threshold voltage correction potential Vofs of transistor MP14. As a result, the gate potential of transistor MP14 becomes Vofs, and transistor MP14 turns on. Subsequently, at time t3, the control signal WS goes high, and transistor MP12 turns off.

[0030] Next, at time t4, the control signal DS goes high, and transistor MP13 turns off. As a result, the gate-source voltage Vgs of transistor MP14 becomes the threshold voltage Vth, and it turns off. This threshold voltage Vth is held in capacitor C12. Then, at time t5, the control signal AZ goes high, and transistor MP15 turns off. Next, at time t6, the control signal WS goes low, and transistor MP12 turns on. At time t6, the pixel signal of signal line SGL is controlled to the signal voltage Vsig of the video signal. Subsequently, at time t7, the control signal AZ goes low, and transistor MP15 turns on. As a result, the light-emitting current Iel does not flow to the light-emitting element EL. Then, at time t8, the control signal WS goes high, and transistor MP12 turns off.

[0031] Next, light emission begins at time t9. Specifically, at time t9, the control signal DS becomes low level, and transistor MP13 turns on. This causes the source potential of transistor MP14 to become Vccp, and transistor MP14 turns on, causing a light emission current Iel corresponding to the signal voltage Vsig to flow from transistor MP14 to the light-emitting element EL. At this time, since the threshold voltage Vth of capacitor C12 is held, the variation in the threshold voltage Vth of transistor MP14 is corrected, and the light-emitting element EL emits light with brightness corresponding to the signal voltage Vsig. The display device 1 repeats the operation shown in Figure 5 every horizontal period, for example. The display device 1 forms a frame image every vertical period by sequentially scanning row by row, for example.

[0032] As described above, the pixel PIX has a capacitor Cws between the gate of transistor MP12 and the gate of transistor MP14. Therefore, as shown in Figure 5, the gate potential of transistor MP14 rises after the signal voltage Vsig is written by coupling with capacitor Cws, by an amount corresponding to the capacitance of capacitor Cws. As a result, the gate-source voltage Vgs of transistor MP14 at the time of light emission becomes smaller than that of the signal voltage Vsig. Light emission by transistor MP13 begins after this coupling rise has stabilized.

[0033] In other words, in this embodiment, since the pixel PIX has the capacitor Cws described above, the gate coupling of transistors MP12 and MP14 is used to raise the gate potential of transistor MP14 after the signal voltage Vsig is written. This makes it possible to compress the gate-source voltage Vgs (hereinafter abbreviated as Vgs as appropriate) of transistor MP14 with respect to the signal voltage Vsig. As a result, even when producing the same brightness, a larger value of the signal voltage Vsig can be used, and the dynamic range of the signal voltage Vsig can be expanded.

[0034] Figure 6 is an exemplary graph showing the relationship between the capacitance of capacitor Cws and the gate-source voltage Vgs and brightness of transistor MP14. Specifically, six types of capacitances A to F are shown as exemplary for capacitor Cws. The relationship between the capacitance values ​​is A < B < C < D < E < F. Figure 6A shows the relationship between Vgs (vertical axis) and signal voltage Vsig (SIG) at the time of light emission for each capacitance, and Figure 6B shows the relationship between brightness (vertical axis) and signal voltage Vsig at the time of light emission for each capacitance.

[0035] Figure 6A shows that when the same signal voltage Vsig is written, the larger the capacitance of capacitor Cws, the smaller the Vgs during light emission becomes, meaning the compression ratio increases. Also, Figure 6B shows that when the same signal voltage Vsig is written, the brightness becomes less pronounced. In other words, even if the light-emitting element (EL) is highly efficient, it is possible to move from the high-efficiency characteristics shown in Figure 2 to the low-efficiency characteristics.

[0036] [1-5. Effects of this Embodiment] As described above, the display device 1 of this embodiment has a plurality of pixels PIX. Each pixel PIX includes a transistor MP14 (first transistor) that controls the input current to a light-emitting element EL that emits light with brightness corresponding to the input current, a transistor MP12 (second transistor) that controls the writing of the pixel signal to the gate of transistor MP14, and a capacitor Cws (first capacitor) formed between the gate of transistor MP14 and the gate of transistor MP12.

[0037] This allows the coupling of the control signal WS of transistor MP12 to be intentionally introduced into the gate of transistor MP14 after the signal voltage Vsig has been written, causing the gate voltage of transistor MP14 to be higher than the signal voltage Vsig. Therefore, the gate-source voltage Vgs of transistor MP14 at the time of illumination is compressed relative to the written signal. As a result, the dynamic range of the signal voltage Vsig can be expanded, improving gradation accuracy. Furthermore, contrast can be improved. For example, when writing black (specifically, when the signal voltage Vsig = the power supply voltage of the power line VCCP), it becomes possible to write a higher voltage to the gate of transistor MP14, thereby improving contrast.

[0038] <2. Specific Configuration Examples of Capacitor Cws> [2-1. Configuration Example 1 (Formation by MIM)] Figure 7 shows a cross-sectional configuration example of a panel that can be used in the display device 1. The panel shown in Figure 7 has a structure in which metal layers are laminated on a silicon (Si) substrate. In the illustrated example, the first metal layer, second metal layer, third metal layer, fourth metal layer and top metal layer are sequentially laminated with an insulator in between, and the wirings of each metal layer are electrically connected as appropriate. MIM (Metal Insulator Metal) capacitors are formed in predetermined wirings of the second metal layer and the third metal layer, respectively. The capacitor Cws described above can be made of this MIM capacitor, for example.

[0039] Figure 8 shows a schematic cross-sectional configuration example of a panel when capacitor Cws is formed using MIM (Metal Injection Molding) capacitors. Figure 8A shows a cross-sectional configuration example when capacitor C12 (Cs) and capacitor Cws are formed using MIM, and Figure 8B shows a cross-sectional configuration example when capacitor C12 (Cs), capacitor C11 (Csub), and capacitor Cws are formed using MIM.

[0040] In the configuration example shown in Figure 8A, a capacitor Cws made of MIM (first MIM) is formed between the gate (WS.Gate) of transistor MP12 and the gate (Drv.Gate) of transistor MP14. Furthermore, a capacitor C12 (Cs) made of MIM (second MIM) is formed between the gate (Drv.Source) of transistor MP14. This allows for the effects of providing the aforementioned capacitor Cws to be achieved.

[0041] In the configuration example shown in Figure 8B, a capacitor Cws made of MIM (first MIM) is formed between the gate layers of transistor MP12 and transistor MP14. Furthermore, a capacitor C12 (Cs) made of MIM (second MIM) is formed between the gate and source layers of transistor MP14. Additionally, a capacitor C11 (Csub) made of MIM (third MIM) is formed between the source of transistor MP14 and the power line VCCP. This configuration allows for the effects of providing the aforementioned capacitor Cws.

[0042] Furthermore, the formation of capacitor Cws using MIM capacitors is not limited to the configuration described above; any configuration in which capacitor Cws is formed between the gates of transistor MP12 and transistor MP14 is acceptable. For example, the stacking order of the layers may be reversed, and wiring and electrodes may be formed on the same layer as much as possible. Alternatively, only capacitor Cws may be formed using MIM.

[0043] [2-2. Configuration Example 2 (Formation by MOM)] The capacitor Cws may be formed by a MOM (Metal Oxide Metal) capacitor. FIGS. 9 to 11 are diagrams showing schematic planar configurations of metal layers in the case where the capacitor Cws is formed by a MOM capacitor.

[0044] FIG. 9 shows a planar configuration example in the case where the capacitors C12 (Cs), C11 (Csub), and Cws are all formed by a MOM capacitor in the same layer. In the configuration example shown in FIG. 9, the power supply line VCCP and the source (Drv.S) of the transistor MP14 are made to run parallel, and a capacitor C11 formed by a MOM capacitor is formed between the power supply line VCCP and the source of the transistor MP14 by coupling in the parallel running portion. Also, the source of the transistor MP14 and the gate (Drv.G) of the transistor MP14 are made to run parallel, and a capacitor C12 formed by a MOM capacitor is formed between the source of the transistor MP14 and the gate of the transistor MP14 by coupling in the parallel running portion. Further, the gate of the transistor MP14 and the gate (WS G) of the transistor MP12 are made to run parallel, and a capacitor Cws formed by a MOM capacitor is formed between the gate of the transistor MP14 and the gate of the transistor MP12 by coupling in the parallel running portion. Thereby, the effect of providing the above-described capacitor Cws can be achieved.

[0045] Figure 10 shows a planar configuration example when capacitors C12 (Cs) and Cws are formed in the same layer using MOM capacitors. Capacitor C11 (Csub) is formed, for example, in a separate layer. In the configuration example shown in Figure 10, the source (Drv.S) and gate (Drv.G) of transistor MP14 are arranged in parallel, and a capacitor C12 made of MOM capacitor is formed between the source and gate of transistor MP14 by coupling in the parallel section. Also, the gate of transistor MP14 and the gate (WSG) of transistor MP12 are arranged in parallel, and a capacitor Cws made of MOM capacitor is formed between the gate of transistor MP14 and the gate of transistor MP12 by coupling in the parallel section. This makes it possible to achieve the effects of providing the capacitor Cws described above.

[0046] Figure 11 shows a planar configuration example when capacitor Cws is formed using a MOM capacitor in a metal layer. Capacitors C12 (Cs) and C11 (Csub) are formed, for example, in a separate layer. In the configuration example shown in Figure 11, the gate (Drv. G) of transistor MP14 and the gate (WS G) of transistor MP12 are arranged in parallel, and a capacitor Cws made of a MOM capacitor is formed between the gates of transistor MP14 and transistor MP12 by coupling in the parallel section. This makes it possible to achieve the effects of providing the capacitor Cws described above.

[0047] Note that the formation of the capacitor Cws by the MOM capacitor is not limited to the above-described configuration. As long as the capacitor Cws by the MOM capacitor is formed between the gates of the transistors MP12 and MP14 running in parallel in the same layer, it is acceptable. Here, the parallel running includes not only the case where a gap with a completely constant interval is provided, but also the case where, as a whole, it can be said that they are running in parallel even if there is a part that does not run in parallel. Further, for example, the power supply line VCCP, the source of the transistor MP14, the gate of the transistor MP14, and the gate of the transistor MP12 are not limited to the illustrated shapes, and the shapes can be appropriately changed according to the capacitance of the MOM capacitor to be formed. That is, as long as the capacitor Cws is formed by intentionally running the wirings of the gates of the transistors MP14 and MP12 in parallel, it is acceptable.

[0048] [2-3. Configuration Example 3 (Formation by Parasitic Capacitance)] The capacitor Cws may be formed by parasitic capacitance. FIGS. 12 and 13 are diagrams showing schematic configuration examples in the case where the capacitor Cws is formed by parasitic capacitance.

[0049] FIG. 12 is a diagram showing a layout configuration example in the case of forming by the parasitic capacitance between wirings in a certain metal layer. FIG. 12A shows a layout example of a comparative example, and FIG. 12B shows a layout example in the case where this configuration example is applied. In FIG. 12 (the same applies to FIG. 13), "Gate" indicates the gate of the transistor MP14, and "WS" indicates the gate of the transistor MP12.

[0050] When laying out the pixels PIX shown in Figure 4, the gate of transistor MP12 is usually not placed next to the gate of transistor MP14, as shown in Figure 12A. This is based on the idea that the gate potential of transistor MP14 should be as unaffected as possible by the gate signal (control signal WS) of transistor MP12. In contrast, when applying this configuration example, the gate of transistor MP12 is intentionally placed next to the gate of transistor MP14, as shown in Figure 12B. Since capacitor Cws (and similarly capacitor C11) does not require a large capacitance value compared to capacitor C12 (Cs), capacitor Cws can also be formed by the parasitic capacitance of the wiring achieved by this layout design. This makes it possible to achieve the effects of providing capacitor Cws as described above.

[0051] Figure 13 shows an example layout configuration when a capacitor Cws is formed by interlayer wiring parasitic capacitance. As shown in the figure, the gate of transistor MP14 is formed on one of two adjacent metal layers (nMT layer), and the gate of transistor MP12 is formed on the other ((n+1)MT layer). The gates of transistor MP14 and transistor MP12 are then positioned so that interlayer wiring parasitic capacitance is formed. Specifically, as shown in the figure, they are positioned so that they overlap in the interlayer space. This increases the capacitance of the formed capacitor Cws. Note that if the desired wiring parasitic capacitance is formed, it is not necessarily required that they overlap each other; they may be positioned flush or in close proximity in the interlayer space. In this layout example as well, the effects of providing the capacitor Cws described above can be achieved.

[0052] [2-4. Configuration Example 4 (Formation by Transistor Internal Capacitance)] Capacitor Cws may be formed by the internal capacitance of a transistor. Specifically, by modifying the structure of transistor MP12 so that the capacitance of capacitor Cws is larger, an internal capacitance Cgd is formed between the gate and drain of transistor MP12, and this formed internal capacitance Cgd is used as capacitor Cws.

[0053] Figures 14 and 15 show examples of the configuration of transistor MP12 that forms capacitor Cws. Figure 14 shows a cross-sectional example of transistor MP12, and Figure 15 shows a planar example of transistor MP12. Figures 14A and 15A show the first configuration example, and Figures 14B and 15B show the second configuration example. Note that in Figure 14, the silicide block is omitted from the drawing for the sake of illustration simplification. Figure 15 shows the structure of transistor MP12 as viewed from the gate formation layer side (upper side of Figure 14).

[0054] As shown in Figures 14A and 15A, the first configuration example has an asymmetrical structure when the source of transistor MP12 is on the left and the drain is on the right. Specifically, in transistor MP14 shown in Figures 14A and 15A, the gate and source are far apart when viewed in plan. Therefore, the gate and drain are made flush when viewed in plan, and the distance between them is shorter than the distance between the gate and source. This makes it possible to form an internal capacitance Cgd, i.e., a capacitor Cws.

[0055] As shown in Figures 14B and 15B, the second configuration example has an asymmetrical structure when the source of transistor MP12 is on the left and the drain is on the right. Specifically, in transistor MP14 shown in Figures 14B and 15B, the gate and source are flush when viewed in plan. Therefore, the gate and drain are made to overlap when viewed in plan, so that the distance is shorter than the gate-source distance. This makes it possible to form an internal capacitance Cgd, i.e., a capacitor Cws.

[0056] Thus, in this configuration example 4, the source side is configured as usual, and the drain is configured to be closer to the gate than the source, thereby forming an internal capacitance Cgd, and the formed internal capacitance Cgd is used as the capacitor Cws. This makes it possible to achieve the effects of providing the capacitor Cws as described above. Note that the configuration of the transistor MP12 is not limited to those shown in Figures 14 and 15, and as long as the desired capacitor Cws can be formed, the shape can be changed as appropriate.

[0057] <3. Other Pixel Circuit Configuration Examples> This technology is also applicable to other pixel circuits having a write control transistor. Specifically, as shown in Figure 16, it can be applied to a display device that uses a pixel PIX having a drive transistor (Drv.Tr) that controls the light-emitting current Iel flowing through the light-emitting element EL, and a write control transistor (WSTr) that controls the signal writing to the gate of the drive transistor. By forming a capacitor Cws between the gate of the write control transistor and the gate of the drive transistor, the same effect as the display device 1 of the above-described embodiment can be achieved. Other configuration examples of the pixel PIX will be described below. Note that the following configuration examples are merely illustrative and do not exclude other configurations.

[0058] (Configuration Example 1) Figure 17 shows another configuration example of a pixel PIX. The pixel PIX has a capacitor C01, transistors MN02 to MN03, and a light-emitting element EL. Transistors MN02 to MN03 are N-type MOSFETs. The gate of transistor MN02 is connected to the control line WSL, the other of its source and drain is connected to the signal line SGL, and one of its source and drain is connected to the gate of transistor MN03 and one end of capacitor C01. One end of capacitor C01 is connected to one of the source and drain of transistor MN02 and the gate of transistor MN03, and the other end is connected to one of the source and drain of transistor MN03 and the anode of the light-emitting element EL. The gate of transistor MN03 is connected to one of the source and drain of transistor MN02 and one end of capacitor C01, the other of its source and drain is connected to the power line VCCP, and one of its source and drain is connected to the other end of capacitor C01 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to one of the source and drain terminals of transistor MN03 and the other terminal of capacitor C01, while the cathode is connected to the power line Vcath. The voltage of the power line VCCP is switched as appropriate between a first voltage and a second voltage lower than the first voltage.

[0059] Furthermore, in this configuration example, the pixel PIX is further provided with a capacitor Cws between the gate of transistor MN02 and the gate of transistor MN03. Specifically, one end of capacitor Cws is connected to the gate of transistor MN02, and the other end is connected to the gate of transistor MN03. In other words, in this configuration example, transistor MN02 corresponds to the write control transistor, and transistor MN03 corresponds to the drive transistor.

[0060] In this configuration, when transistor MN02 is turned on in a pixel PIX, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During the period when the voltage of power line VCCP is the first voltage, transistor MN03 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C01. The light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. During the period when the voltage of power line VCCP is the second voltage, the light-emitting element EL is extinguished.

[0061] (Configuration Example 2) Figure 18 shows another configuration example of a pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to the control line WSL, the other of its source and drain is connected to the signal line SGL, and one of its source and drain is connected to the gate of transistor MN24 and one end of capacitor C21. One end of capacitor C21 is connected to one of the source and drain of transistor MN22 and the gate of transistor MN24, and the other end is connected to one of the source and drain of transistor MN24, the other of the source and drain of transistor MN25, and the anode of the light-emitting element EL. The gate of transistor MN23 is connected to the control line DSL, the other of its source and drain is connected to the power line VCCP, and one of its source and drain is connected to the other of the source and drain of transistor MN24. The gate of transistor MN24 is connected to one of the source and drain of transistor MN22 and one end of capacitor C21, the other source and drain is connected to one of the source and drain of transistor MN23, and one source and drain is connected to the other end of capacitor C21, the other source and drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN25 is connected to the control line AZSL, the other source and drain is connected to one of the source and drain of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and one source and drain is connected to the power line VSS. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN24, the other end of capacitor C21, and the other source and drain of transistor MN25, and its cathode is connected to the power line Vcath.

[0062] Furthermore, in this example configuration, the pixel PIX is further provided with a capacitor Cws between the gate of transistor MN22 and the gate of transistor MN24. Specifically, one end of capacitor Cws is connected to the gate of transistor MN22, and the other end is connected to the gate of transistor MN24. In other words, in this example configuration, transistor MN22 corresponds to the write control transistor, and transistor MN24 corresponds to the drive transistor.

[0063] In this configuration, in a pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal from control line DSL. Transistor MN24 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C21 while transistor MN23 is on. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal from control line AZSL. While transistor MN25 is on, the voltage at the anode of the light-emitting element EL is initialized by being set to the voltage of power line VSS.

[0064] Transistors MN22 to MN25 may be transistors made of low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MN22 and MN25 may be a transistor made of oxide semiconductor.

[0065] (Configuration Example 3) Figure 19 shows another configuration example of a pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to the control line WSL, one of its source and drain is connected to the signal line SGL, and the other of its source and drain is connected to the gate of transistor MP33, the other of its source and drain of transistor MP34, and the other end of capacitor C31. One end of capacitor C31 is connected to the power line VCCP, and the other end is connected to the other of its source and drain of transistor MP32, the gate of transistor MP33, and the other of its source and drain of transistor MP34. The gate of transistor MP33 is connected to the other source and drain of transistor MP32, the other source and drain of transistor MP34, and the other end of capacitor C31. One source and drain is connected to the power line VCCP, and the other source and drain is connected to one source and drain of transistor MP35 and one source and drain of transistor MP34. The gate of transistor MP34 is connected to the control line AZSL1, and one source and drain is connected to the other source and drain of transistor MP33 and one source and drain of transistor MP35. The other source and drain is connected to the other source and drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to the control line DSL, and one source and drain is connected to the other source and drain of transistor MP33 and one source and drain of transistor MP34. The other source and drain is connected to one source and drain of transistor MP36 and the anode of the light-emitting element EL.The gate of transistor MP36 is connected to the control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP35 and to the anode of the light-emitting element EL, and the other of its source and drain is connected to the power line VSS. The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP35 and to one of the source and drain of transistor MP36, and its cathode is connected to the power line Vcath.

[0066] Furthermore, in this configuration example, the pixel PIX is further provided with a capacitor Cws between the gates of transistor MP32 and transistor MP33. Specifically, one end of capacitor Cws is connected to the gate of transistor MP32, and the other end is connected to the gate of transistor MP33. In other words, in this configuration example, transistor MP32 corresponds to the write control transistor, and transistor MP33 corresponds to the drive transistor.

[0067] In this configuration, in a pixel PIX, when transistor MP32 is turned ON, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned ON or OFF based on the signal from control line DSL. Transistor MP33 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C31 while transistor MP35 is ON. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. Transistor MP34 is turned ON or OFF based on the signal from control line AZSL1. While transistor MP34 is ON, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned ON or OFF based on the signal from control line AZSL2. While transistor MP36 is ON, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of power line VSS.

[0068] Transistors MP32 to MP36 may be transistors made of low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MP32, MP34, and MP36 may be a transistor made of oxide semiconductor.

[0069] (Configuration Example 4) Figure 20 shows another configuration example of a pixel PIX. One end of capacitor C48 is connected to the signal line SGL1, and the other end is connected to the power line VSS. One end of capacitor C49 is connected to the signal line SGL1, and the other end is connected to the signal line SGL2. Transistor MP49 is a P-type MOSFET, with its gate connected to the control line WSL2, one of its source and drain connected to the signal line SGL1, and the other of its source and drain connected to the signal line SGL2.

[0070] Each pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to the control line WSL1, one of its source and drain is connected to the signal line SGL2, and the other of its source and drain is connected to the gate of transistor MP43 and the other end of capacitor C41. One end of capacitor 41 is connected to the power line VCCP, and the other end is connected to the other of its source and drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the other of its source and drain of transistor MP42 and the other end of capacitor C41, one of its source and drain is connected to the power line VCCP, and the other of its source and drain is connected to one of its source and drain of transistors MP44 and MP45. The gate of transistor MP44 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP43, and one of the source and drain of transistor MP45, and the other of its source and drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP43, and one of the source and drain of transistor MP44, and the other of its source and drain is connected to one of the source and drain of transistor MP46 and the anode of the light-emitting element EL. The gate of transistor MP46 is connected to control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP45 and the anode of the light-emitting element EL, and the other of its source and drain is connected to power line VSS. The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP45 and one of the source and drain of transistor MP46, and its cathode is connected to power line Vcath.The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP124, and to one of the source and drain of transistor MP125, while the cathode is connected to the power line Vcath.

[0071] Furthermore, in this configuration example, the pixel PIX is further provided with a capacitor Cws between the gates of transistor MP42 and transistor MP43. Specifically, one end of capacitor Cws is connected to the gate of transistor MP42, and the other end is connected to the gate of transistor MP43. In other words, in this configuration example, transistor MP42 corresponds to the write control transistor, and transistor MP43 corresponds to the drive transistor.

[0072] In this configuration, in a pixel PIX, when transistor MP42 is turned ON, the voltage across capacitor C41 is set based on the pixel signal supplied to signal line SGL1. Transistor MP45 is turned ON or OFF based on the signal on control line DSL. Transistor MP43 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C41 while transistor MP45 is ON. The light-emitting element EL emits light based on the current supplied by transistor MP43. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. Transistor MP44 is turned ON or OFF based on the signal on control line AZSL1. While transistor MP44 is ON, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned ON or OFF based on the signal on control line AZSL2. While transistor MP46 is ON, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line VSS.

[0073] Furthermore, transistors MP42 to MP46 and MP49 may be transistors using low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP42, MP46, and MP49 may be a transistor using an oxide semiconductor.

[0074] (Configuration Example 5) Figure 21 shows another configuration example of a pixel PIX. Multiple pixels PIX are arranged in a matrix in the display area 100, and the display area 100 is located between the first control unit 91 and the second control unit 92.

[0075] The first control unit 91 includes transmission gates TG45 and TG46, transistors MP50 and MP51, and capacitor C50. Transistors MP50 and MP51 are P-type MOSFETs. A pixel signal is supplied to one end of transmission gate TG45, and the other end of transmission gate TG45 is connected to signal line 93a. One end of transmission gate TG46 is connected to signal line 93b, and the other end of transmission gate TG46 is connected to power line Vorst. One end of capacitor C50 is connected to signal line 93a, and the other end is connected to power line VSS1. The gate of transistor MP50 is connected to control line INIL, one of its source and drain is connected to power line Vini, and the other of its source and drain is connected to signal line 93b. The gate of transistor MP51 is connected to control line ELL, one of its source and drain is connected to power line Vel, and the other of its source and drain is connected to signal line 93b.

[0076] The second control unit 92 includes a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. One end of the transmission gate TG72 is connected to the signal line 93a, and the other end is connected to the other of the source and drain of the transistor MP73, and to one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, one of the source and drain is connected to the power line Vref, and the other of the source and drain is connected to the other end of the transmission gate TG72 and to one end of the capacitor C82. One end of the capacitor C82 is connected to the other end of the transmission gate TG72 and the other of the source and drain of the transistor MP73, and the other end is connected to the signal line 93b.

[0077] Each pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. Transistors MP121 to MP125 are P-type MOSFETs. The gate of transistor MP122 is connected to the control line WSL, one of its source and drain is connected to the signal line 93b, and the other of its source and drain is connected to the gate of transistor MP121 and the other end of capacitor C132. One end of capacitor C132 is connected to the power line Vel, and the other end is connected to the other of its source and drain of transistor MP122 and the gate of transistor MP121. The gate of transistor MP121 is connected to the other of its source and drain of transistor MP122 and the other end of capacitor C132, one of its source and drain is connected to the power line Vel, and the other of its source and drain is connected to one of its source and drain of transistors MP123 and MP124. The gate of transistor MP123 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP121, and one of the source and drain of transistor MP124, and the other of its source and drain is connected to the signal line 93b. The gate of transistor MP124 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP121, and one of the source and drain of transistor MP123, and the other of its source and drain is connected to one of the source and drain of transistor MP125 and the anode of the light-emitting element EL. The gate of transistor MP125 is connected to the control line AZSL, the other of its source and drain is connected to the power line Vorst, and one of its source and drain is connected to the other of the source and drain of transistor MP124 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP124 and one of the source and drain of transistor MP125, and its cathode is connected to the power line Vcath.

[0078] Furthermore, in this configuration example, the pixel PIX is further provided with a capacitor Cws between the gates of transistor MP122 and transistor MP121. Specifically, one end of capacitor Cws is connected to the gate of transistor MP122, and the other end is connected to the gate of transistor MP121. In other words, in this configuration example, transistor MP122 corresponds to the write control transistor, and transistor MP121 corresponds to the drive transistor.

[0079] In this configuration, in a pixel PIX, when transistor MP122 is turned ON, the voltage across capacitor C132 is set based on the pixel signal supplied to one end of transmission gate TG45. Transistor MP124 is turned ON or OFF based on the signal on control line DSL. Transistor MP121 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C132 during the period when transistor MP124 is ON. The light-emitting element EL emits light based on the current supplied by transistor MP121. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. Transistors MP123 and MP125 are turned ON or OFF based on the signal on control line AZSL. During the period when transistor MP123 is ON, the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124 are connected to signal line 93b. During the period when transistor MP125 is ON, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line Vorst. Furthermore, transistor MP50 is switched on and off based on the signal of control line INIL, transistor MP51 is switched on and off based on the signal of control line ELL, and transistor MP73 is switched on and off based on the signal of control line REFL. When transistor MP50 is turned on, signal line 93b is set to the voltage of power line Vini, and when transistor MP51 is turned on, signal line 93b is set to the voltage of power line Vel. When transistor MP73 is turned on, one end of capacitor C82 is initialized by being set to the voltage of power line Vref.

[0080] Furthermore, transistors MP121 to MP125, MP50, and MP51 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP122 and MP125 may be a transistor made of oxide semiconductor.

[0081] (Configuration Example 6) Figure 22 shows another configuration example of a pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to the control line WSL, one of its source and drain is connected to the signal line SGL, and the other of its source and drain is connected to the other of its source and drain of transistor MP53 and one of its source and drain of transistor MP54. The gate of transistor MP53 is connected to the control line DSL, one of its source and drain is connected to the power line VCCP, and the other of its source and drain is connected to the other of its source and drain of transistor MP52 and one of its source and drain of transistor MP54. The gate of transistor MP54 is connected to one of the source and drain of transistor MP55, the other of the source and drain of transistor MP57, and the other end of capacitor C51. One of the source and drain is connected to the other of the source and drain of transistors MP52 and MP53, and the other of the source and drain is connected to one of the source and drain of transistors MP58 and MP59. One end of capacitor C51 is connected to the power line VCCP, and the other end is connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other of the source and drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel with each other. The gate of transistor MP55 is connected to the control line AZSL1, one of the source and drain is connected to the gate of transistor MP54, the other of the source and drain of transistor MP57, and the other end of capacitor C51, and the other of the source and drain is connected to one of the source and drain of transistor MP56. The gate of transistor MP56 is connected to control line AZSL1, one of its source and drain is connected to the other of its source and drain of transistor MP55, and the other of its source and drain is connected to power line VSS.The gate of transistor MP57 is connected to the control line WSL, the other of its source and drain is connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other end of capacitor C51, and one of its source and drain is connected to the other of its source and drain of transistor MP58. The gate of transistor MP58 is connected to the control line WSL, the other of its source and drain is connected to one of the source and drain of transistor MP57, the other of its source and drain is connected to the other of its source and drain of transistor MP54, and one of its source and drain is connected to one of its source and drain of transistor MP59. The gate of transistor 59 is connected to the control line DSL, the other of its source and drain is connected to the other of its source and drain of transistor MP54, and one of its source and drain is connected to one of its source and drain of transistor MP58, and the other of its source and drain is connected to one of its source and drain of transistor MP60, and the anode of the light-emitting element EL. The gate of transistor MP60 is connected to the control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP59 and to the anode of the light-emitting element EL, and the other of its source and drain is connected to the power line VSS. The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP59 and to one of the source and drain of transistor MP60, and its cathode is connected to the power line Vcath.

[0082] Furthermore, in this configuration example, the pixel PIX is further provided with a capacitor Cws between the gates of transistors MP57 and MP58 and the gate of transistor MP54. Specifically, one end of capacitor Cws is connected to the gates of transistors MP57 and MP58, and the other end is connected to the gate of transistor MP54. Note that capacitor Cws may also be provided between the gates of transistor MP52 and transistor MP54, or between the gates of transistor MP52 and transistors MP57 and MP58 and the gate of transistor MP54. In this configuration example, transistors MP52, MP57, and MP58 correspond to write control transistors, and transistor MP54 corresponds to a drive transistor.

[0083] In this configuration, in the pixel PIX, the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL when transistors MP52, MP54, MP58, and MP57 are turned ON. Transistors MP53 and MP59 are turned ON and OFF based on the signal from control line DSL. Transistor MP54 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C51 while transistors MP53 and MP59 are ON. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistors MP55 and MP56 are turned ON and OFF based on the signal from control line AZSL1. While transistors MP55 and MP56 are ON, the gate voltage of transistor MP54 is initialized by being set to the voltage of power line VSS. Transistor MP60 is turned ON and OFF based on the signal from control line AZSL2. During the period when transistor MP60 is ON, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of the power line VSS.

[0084] Transistors MP52 to MP60 may be transistors using low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0085] (Configuration Example 7) Figure 23 shows another configuration example of a pixel PIX. The signals of control line WSNL and control line WSPL are inverted signals of each other.

[0086] Each pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, MN65-MN67, and light-emitting element EL. Transistors MN63, MN65-MN67 are N-type MOSFETs, and transistor MP64 is a P-type MOSFET. The gate of transistor MN63 is connected to the control line WSNL, and the other of its source and drain is connected to the signal line SGL and one of the source and drain of transistor MP64. The other of its source and drain is connected to the other of the source and drain of transistor MP64, one end of capacitors C61 and C62, and the gate of transistor MN65. The gate of transistor MP64 is connected to the control line WSPL, and the other of its source and drain is connected to the signal line SGL and the other of the source and drain of transistor MN63. The other of its source and drain is connected to one of the source and drain of transistor MN63, one end of capacitors C61 and C62, and the gate of transistor MN65. Capacitor C61 is constructed using, for example, a MOM (Metal Oxide Metal) capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C62, and the gate of transistor MN65, and the other end connected to the power line VSS2. Capacitor C61 may also be constructed using, for example, a MOS capacitor or a MIM (Metal Insulator Metal) capacitor. Capacitor C62 is constructed using, for example, a MOS capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power line VSS2. Capacitor C62 may also be constructed using, for example, a MOM capacitor or a MIM capacitor. The other end of capacitor C62 may also be connected to the power line VSS3 (not shown).The gate of transistor MN65 is connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, and one end of capacitors C61 and C62. The other of the source and drain is connected to the power line VCCP, and the other of the source and drain is connected to the other of the source and drain of transistors MN66 and MN67. The gate of transistor MN66 is connected to the control line AZL, and the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN67, and the other of the source and drain is connected to the power line VSS1. The gate of transistor MN67 is connected to the control line DSL, and the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN66, and the other of the source and drain is connected to the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to one of the source and drain of transistor MN67, and its cathode is connected to the power line Vcath. Alternatively, the transistor MN67 and the control line DSL may be omitted, and one of the source and drain of transistor MN65 may be connected to the other of the source and drain of transistor MN66, and to the anode of the light-emitting element EL.

[0087] Furthermore, in this example configuration, the pixel PIX is further provided with a capacitor Cws between the gates of transistor MN63 and transistor MN65. Specifically, one end of capacitor Cws is connected to the gate of transistor MN63, and the other end is connected to the gate of transistor MN65. Note that capacitor Cws may also be provided between the gates of transistor MP64 and transistor MN65, or between the gates of transistor MP64 and transistor MN63 and the gate of transistor MN65, respectively. In this example configuration, transistors MN63 and MP64 correspond to write control transistors, and transistor MN65 corresponds to a drive transistor.

[0088] In this configuration, at least one of transistors MN63 and MP64 is turned on in the pixel PIX, setting the voltage across capacitors C61 and C62 based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal from control line DSL. Transistor MN65 supplies a current to the light-emitting element EL corresponding to the voltage across capacitors C61 and C62 during the period when transistor MN67 is on. The light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal from control line AZL. Transistor MN66 may also function as a resistive element having a resistance value corresponding to the signal from control line AZL. In this case, transistors MN65 and MN66 constitute a so-called source follower circuit.

[0089] Furthermore, transistors MN63, MP64, and MN65-MN67 may be transistors using low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0090] (Configuration Example 8) Figure 24 shows another configuration example of a pixel PIX. This pixel PIX has a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are N-type MOSFETs. The gate of transistor MN72 is connected to the control line WSL, the other of its source and drain is connected to the signal line SGL, and one of its source and drain is connected to one of the source and drain of transistor MN74 and the other of the source and drain of transistor MN75. One end of capacitor C71 is connected to the gate of transistor MN74 and one of the source and drain of transistor MN76, and the other end is connected to the other of the source and drain of transistor MN77, one of the source and drain of transistor MN75, and the anode of the light-emitting element EL. The gate of transistor MN73 is connected to control line DSL1, the other of its source and drain is connected to power line VCCP, and one of its source and drain is connected to the other of its source and drain of transistor MN74 and the other of its source and drain of transistor MN76. The gate of transistor MN74 is connected to one of its source and drain of transistor MN76 and one end of capacitor C71, the other of its source and drain is connected to one of its source and drain of transistor 73 and the other of its source and drain of transistor MN76, and one of its source and drain is connected to one of its source and drain of transistor MN72 and the other of its source and drain of transistor MN75. The gate of transistor MN75 is connected to control line DSL2, the other of its source and drain is connected to one of its source and drain of transistor MN72 and the other of its source and drain of transistor MN74, and one of its source and drain is connected to the other end of capacitor C71, the other of its source and drain of transistor MN77 and the anode of light-emitting element EL.The gate of transistor MN76 is connected to the control line AZSL, and the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN74, with one of its source and drain connected to the gate of transistor MN74 and one end of capacitor C71. The gate of transistor MN77 is connected to the control line AZSL, and the other of its source and drain is connected to the other end of capacitor C71, one of the source and drain of transistor MN75 and the anode of light-emitting element EL, with one of its source and drain connected to the power line VSS. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN75, the other of the source and drain of transistor MN77 and the other end of capacitor C71, and its cathode is connected to the power line Vcath.

[0091] Furthermore, in this example configuration, the pixel PIX is further provided with a capacitor Cws between the gates of transistor MN72 and transistor MN74. Specifically, one end of capacitor Cws is connected to the gate of transistor MN72, and the other end is connected to the gate of transistor MN74. In other words, in this example configuration, transistor MN72 corresponds to the write control transistor, and transistor MN74 corresponds to the drive transistor.

[0092] In this configuration, in the pixel PIX, the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL when transistors MN72, MN74, and MN76 are turned on. Transistor MN73 is turned on and off based on the signal from control line DSL1, and transistor MN75 is turned on and off based on the signal from control line DSL2. Transistor MN74 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C71 while transistors MN73 and MN75 are turned on. The light-emitting element EL emits light based on the current supplied from transistor MN74. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistor MN77 is turned on and off based on the signal from control line AZSL. While transistor MN77 is turned on, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of power line VSS.

[0093] Transistors MN72 to MN77 may be transistors made of low-temperature polycrystalline silicon (LTPS). Transistor MN76 may be a transistor made of oxide semiconductor.

[0094] <4. Modifications> Although embodiments of this technology have been described in detail above, the content of this technology is not limited to the embodiments described above, and various modifications are possible based on the technical concept of this technology. For example, the configurations, methods, processes, materials, shapes, and numerical values ​​of the embodiments described above can be combined or replaced with each other, as long as they do not deviate from the spirit of this technology. It is also possible to divide one thing into two or more, and to omit parts of it. Furthermore, if this technology is applicable, each of the above-described configurations may be deleted, changed, or replaced with other configurations as appropriate, or replaced with alternative configurations. In addition, this technology may be a combination of the technologies described in each of the embodiments described above, to the extent possible.

[0095] For example, although the capacitor Cws described above was formed using MIM, MOM, wiring parasitic capacitance, or the internal capacitance Cgd of transistor MP12, these may be combined. Other capacitors such as capacitor C12 (Cs) and C11 (Csub) can be appropriately selected from among them according to the required capacitance value. By forming them in the same way as capacitor Cws, the manufacturing process can be simplified. Furthermore, the signals input to control lines WSL, DSL, and AZSL, and the signals supplied to signal line SGL may be other than those described above, as long as they can perform the same operation as described above.

[0096] For example, this technology can be applied to various displays. This technology can be applied to display panels such as SXRD (Silicon X-tal Reflective Display: registered trademark) used in projectors, and to phase-modulated panels using SLM (Spatial Light Modulator) for hologram display. Furthermore, this technology can be applied to panels such as LCOS (Liquid Crystal on Silicon, LCoS is a trademark) and HTPS (High Temperature Poly-Silicon).

[0097] For example, in the embodiment described above, the second drive unit 5 is shown to output a pixel signal representing brightness using voltage to the pixel unit 2. However, the second drive unit 5 may also output a pixel signal representing brightness using current. In this case, the second drive unit 5 becomes a current source (a voltage source in the embodiment described above) when generating the pixel signal.

[0098] <5. Application Examples> Next, application examples of the display device 1 described in the above embodiments and modified examples will be explained.

[0099] (Application Example 1) Figure 25 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, a glasses-shaped display unit 111 and ear hooks 112 on both sides for attachment to the user's head. The technology according to the above embodiment can be applied to such a head-mounted display 110.

[0100] (Application Example 2) Figure 26 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a transmissive head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. This display unit emits image light of the displayed image. The arm 122 connects the main body 121 and the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 towards the user's eyes through the lenses 129 of the eyeglasses 128. The technology according to the above embodiment can be applied to such a head-mounted display 120.

[0101] This head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this; for example, it may be a so-called birdbath type head-mounted display. This birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0102] (Application Example 3) Figures 27A and 27B show an example of the external appearance of a digital still camera 130, with Figure 27A showing a front view and Figure 27B showing a rear view. This digital still camera 130 is a single-lens reflex type camera with interchangeable lenses and has a camera body 131, a shooting lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The shooting lens unit 132 is an interchangeable lens unit and is located near the center of the front of the camera body 131. The grip 133 is located on the left side of the front of the camera body 131, and the photographer holds this grip 133. The monitor 134 is located to the left of the center of the rear of the camera body 131. The electronic viewfinder 135 is located on the rear of the camera body 131, above the monitor 134. The photographer can look through the electronic viewfinder 135 to see the light image of the subject guided by the shooting lens unit 132 and determine the composition. The technology according to the above embodiment can be applied to the electronic viewfinder 135.

[0103] (Application Example 4) Figure 28 shows an example of the appearance of a television device 140. The television device 140 has an image display screen section 141 including a front panel 142 and a filter glass 143. The technology according to the above embodiments can be applied to this image display screen section 141.

[0104] (Application Example 5) Figure 29 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept user input. The technology according to the above embodiment can be applied to this display unit 151.

[0105] (Application Example 6) Figures 30A and 30B show an example of a vehicle configuration to which the technology of this disclosure is applied. Figure 30A shows an example of the interior of the vehicle as seen from the rear of the vehicle 200, and Figure 30B shows an example of the interior of the vehicle as seen from the left rear of the vehicle 200.

[0106] The vehicle in Figures 30A and 30B has a center display 201, a console display 202, a head-up display 203, a digital rear mirror 204, a steering wheel display 205, and a rear entertainment display 206.

[0107] The center display 201 is located on the dashboard 261, facing the driver's seat 262 and the passenger seat 263. Figure 30A shows an example of a horizontally elongated center display 201 extending from the driver's seat 262 to the passenger seat 263, but the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display images captured by an image sensor, distance images to obstacles in front of and to the side of the vehicle measured by a ToF sensor, and the body temperature of occupants detected by an infrared sensor. The center display 201 can be used to display at least one of the following: safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information.

[0108] Safety-related information includes data based on sensor detection results, such as drowsiness detection, distraction detection, detection of mischief by passengers, seatbelt usage status, and detection of unattended occupants. Operation-related information includes information on occupant gestures detected using sensors. Gestures may include operation of various in-vehicle equipment, such as air conditioning, navigation systems, AV (Audio Visual) systems, and lighting systems. Lifelogs include the lifelogs of all occupants. For example, lifelogs include records of each occupant's actions. By acquiring and saving lifelogs, it is possible to check the condition of occupants in the event of an accident. Health-related information includes the occupant's body temperature detected using temperature sensors, and information on the occupant's health status inferred from the detected body temperature. Alternatively, information on the occupant's health status may be inferred based on the occupant's face captured by an image sensor. Furthermore, information on the occupant's health status may be inferred based on the occupant's responses obtained by conversing with the occupant using automated voice. Authentication / identification-related information includes information such as keyless entry functions that use sensors for facial recognition and functions that automatically adjust seat height and position based on facial recognition. Entertainment-related information includes information on AV equipment operation by occupants detected by sensors, and information on content to be displayed that is appropriate for occupants detected and recognized by sensors.

[0109] The console display 202 can be used, for example, to display life log information. The console display 202 is located near the shift lever 265 in the center console 264 between the driver's seat 262 and the passenger seat 263. The console display 202 can also display information detected by various sensors. In addition, the console display 202 may display images of the area around the vehicle captured by an image sensor, or it may display distance images to obstacles around the vehicle.

[0110] The head-up display 203 is virtually displayed behind the windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 203 is often virtually positioned in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as vehicle speed, fuel level, and battery level.

[0111] The digital rearview mirror 204 can not only display the area behind the vehicle, but also show the condition of the rear-seat passengers. Therefore, it can be used, for example, to display life log information of rear-seat passengers.

[0112] The steering wheel display 205 is positioned near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of the following: safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, or information related to the operation of AV equipment, air conditioning equipment, etc.

[0113] The rear entertainment display 206 is mounted on the back of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear-seat passengers. The rear entertainment display 206 can be used to display at least one of the following: safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the rear entertainment display 206 is in front of the rear-seat passengers, it displays information relevant to the rear-seat passengers. For example, the rear entertainment display 206 may display information related to the operation of AV equipment or air conditioning equipment, or it may display the results of temperature sensor measurements of the rear-seat passengers' body temperature, etc.

[0114] The technologies described in the above embodiments can be applied to these center displays 201, console displays 202, head-up displays 203, digital rear mirrors 204, steering wheel displays 205, and rear entertainment displays 206.

[0115] Furthermore, this technology can also adopt the following configurations: (1) A display device having a plurality of pixel circuits, the pixel circuit having a first transistor that controls the input current to a light-emitting element that emits light with brightness corresponding to the input current, a second transistor that controls the writing of a pixel signal to the gate of the first transistor, and a first capacitor formed between the gate of the first transistor and the gate of the second transistor. (2) The display device according to (1), wherein after the writing of the pixel signal by the control of the second transistor, coupling is performed between the gate of the first transistor and the second transistor by the first capacitor, and after the gate potential of the first transistor is stabilized by the coupling, the light-emitting element starts to emit light. (3) The display device according to (1) or (2), wherein the first capacitor is formed of a MOM (Metal Oxide Metal) capacitor. (4) The display device according to any one of (1) to (3), wherein the first capacitor is formed by the parasitic capacitance between the gate of the first transistor and the gate of the second transistor. (5) The display device according to (4), wherein the parasitic capacitance is the parasitic capacitance between wirings of the same layer. (6) The parasitic capacitance is the parasitic capacitance between adjacent layers, as in (4) or (5). (7) The parasitic capacitance is caused by the layout in which the gate of the first transistor and the gate of the second transistor run parallel, as in the display device according to any one of (4) to (6). (8) The first capacitor is made of a MIM (Metal Insulator Metal) capacitor, as in the display device according to any one of (1) to (7). (9) The first capacitor is formed by the internal capacitance of the second transistor, as in the display device according to any one of (1) to (8).(10) The pixel circuit comprises a second capacitor, a third capacitor, a third transistor, a fourth transistor, and the light-emitting element, one end of the third capacitor is connected to a high-potential power line, the cathode of the light-emitting element is connected to a low-potential power line, the gate of the second transistor is connected to a first control line to which a control signal for controlling the writing of the pixel signal is supplied, and to one end of the first capacitor, one of its source and drain is connected to a signal line to which the pixel signal is supplied, and the other of its source and drain is connected to the other end of the second capacitor, the gate of the first transistor, and the other end of the first capacitor, the gate of the third transistor is connected to a second control line to which a control signal for controlling the light-emitting state of the light-emitting element is supplied, one of its source and drain is connected to a high-potential power line, the other of its source and drain is connected to the other end of the third capacitor, one end of the second capacitor, and one of the source and drain of the first transistor, the other of the source and drain of the first transistor is connected to one of the source and drain of the fourth transistor, and to the anode of the light-emitting element, The display device according to any one of (1) to (9), wherein the gate of the fourth transistor is connected to a third control line to which a control signal for controlling the initialization of the first transistor is supplied, and the other of the source and drain is connected to a power line on the low potential side. (11) The display device according to (10), wherein the second capacitor and the third capacitor are made of MIM (Metal Insulator Metal) capacitors or MOM (Metal Oxide Metal) capacitors. (12) Electronic equipment having the display device according to any one of (1) to (11).

[0116] 1...Display device, 2...Pixel unit, 4...First drive unit, 5...Second drive unit, Csw...Capacitor, PIX...Pixel, MP12...Transistor (WS Tr), MP14...Transistor (Drv.Tr)

Claims

It has multiple pixel circuits, The aforementioned pixel circuit is A first transistor controls the input current to a light-emitting element that emits light with a brightness corresponding to the input current, A second transistor controls the writing of a pixel signal to the gate of the first transistor, A first capacitor formed between the gate of the first transistor and the gate of the second transistor and has Display device. 　 After the pixel signal is written by controlling the second transistor, coupling is performed between the gate of the first transistor and the second transistor by the first capacitor. The light-emitting element starts emitting light after the gate potential of the first transistor has been stabilized by the coupling described above. The display device according to claim 1. 　 The first capacitor is formed of a MOM (Metal Oxide Metal) capacitor. The display device according to claim 1. 　 The first capacitor is formed by the parasitic capacitance between the gate of the first transistor and the gate of the second transistor. The display device according to claim 1. 　 The aforementioned parasitic capacitance is the parasitic capacitance between wiring within the same layer. The display device according to claim 4. 　 The aforementioned parasitic capacity is the parasitic capacity between adjacent layers. The display device according to claim 4. 　 The aforementioned parasitic capacitance arises from the layout in which the gates of the first transistor and the gates of the second transistor run parallel to each other. The display device according to claim 4. 　 The first capacitor is composed of a MIM (Metal Insulator Metal) capacitor. The display device according to claim 1. 　 The first capacitor is formed by the internal capacitance of the second transistor. The display device according to claim 1. 　 The pixel circuit includes a second capacitor, a third capacitor, a third transistor, a fourth transistor, and the light-emitting element. One end of the third capacitor is connected to the high-potential power line. The cathode of the light-emitting element is connected to the low-potential power line. The gate of the second transistor is connected to a first control line to which a control signal for controlling the writing of the pixel signal is supplied, and to one end of the first capacitor; one of the source and drain is connected to a signal line to which the pixel signal is supplied; and the other of the source and drain is connected to the other end of the second capacitor, the gate of the first transistor, and the other end of the first capacitor. The gate of the third transistor is connected to a second control line to which a control signal is supplied to control the light-emitting state of the light-emitting element; one of the source and drain is connected to a high-potential power line; and the other of the source and drain is connected to the other end of the third capacitor, one end of the second capacitor, and one of the source and drain of the first transistor. The source and drain of the first transistor, the other of which is connected to the source and drain of the fourth transistor, and the anode of the light-emitting element. The gate of the fourth transistor is connected to a third control line to which a control signal for controlling the initialization of the first transistor is supplied, and the other of the source and drain is connected to a low-potential power line. The display device according to claim 1. 　 The second and third capacitors are composed of MIM (Metal Insulator Metal) capacitors or MOM (Metal Oxide Metal) capacitors. The display device according to claim 10. 　 An electronic device having the display device described in claim 1.

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