IGO material layer having high mobility and high reliability, method for manufacturing same, and transistor and NAND flash memory using same

Abstract

Provided is a method for manufacturing an IGO material layer. The method for manufacturing an IGO material layer comprises the steps of: preparing a substrate; providing reactants including an indium (In) precursor, a gallium (Ga) precursor, and oxygen on the substrate to form an IGO material layer; and heat-treating the IGO material layer, wherein the method may comprise improving the electrical properties of the IGO material layer by controlling at least one among the cationic ratio of indium to gallium in the IGO material layer, the process temperature for forming the IGO material layer, and the temperature for heat-treating the IGO material layer.

Description

IGO material film having high mobility and high reliability, method for manufacturing the same, and transistor and NAND flash memory applying the same

[0001] The present invention relates to an IGO material film having high mobility and high reliability, a method for manufacturing the same, and a transistor and a NAND flash memory to which the same is applied.

[0002] Oxide semiconductors are materials used in various fields due to their high electric field mobility, low leakage current, and ease of 3D processing. In particular, recently, there has been extensive research aimed at using oxide semiconductors as transistor channel materials for semiconductor memory due to their characteristics, such as the ability to reduce power consumption through low leakage current and ease of application in complex 3D structures. However, oxide semiconductor materials have the disadvantage of poor high-temperature stability and a trade-off relationship between mobility and reliability. To overcome these drawbacks, a technology has been reported in which hydrogen is doped into InO channel materials to suppress initial nucleation and increase the final grain size, thereby enabling excellent electrical characteristics without reliability degradation.

[0003] However, the method of increasing the grain size of InO through hydrogen doping has the problem that hydrogen within the InO material film is easily desorbed, leading to deterioration of the electrical characteristics of the device or changes in the properties of the thin film due to hydrogen diffusion issues that occur during the high-temperature heat treatment process. Accordingly, the method described above is unsuitable for application to 3D structured devices, and additionally, it has the disadvantage that the high-temperature stability of the InO material itself is poor. Furthermore, the currently 주목받는 IGZO material also has the disadvantage of poor high-temperature stability.

[0004] The technical problem that the present invention aims to solve is to provide an IGO material film having high-temperature stability and a method for manufacturing the same.

[0005] Another technical problem that the present invention aims to solve is to provide an IGO material film having high mobility and a method for manufacturing the same.

[0006] Another technical problem that the present invention aims to solve is to provide a highly reliable IGO material film and a method for manufacturing the same.

[0007] Another technical problem that the present invention aims to solve is to provide a transistor with an IGO material film applied thereto.

[0008] Another technical problem that the present invention aims to solve is to provide a NAND flash memory with an IGO material film applied.

[0009] The technical problems that the present invention aims to solve are not limited to those described above.

[0010] To solve the technical problems described above, the present invention provides a method for manufacturing an IGO material film.

[0011] According to one embodiment, the method for manufacturing the IGO material film comprises the steps of preparing a substrate, providing a reaction material comprising an indium (In) precursor, a gallium (Ga) precursor, and oxygen on the substrate to form an IGO material film, and heat-treating the IGO material film, wherein at least one of the indium:gallium cation ratio in the IGO material film, the process temperature for forming the IGO material film, and the temperature for heat-treating the IGO material film is controlled to improve the electrical properties of the IGO material film.

[0012] According to one embodiment, the ratio of indium to gallium cations in the IGO material film may be controlled to be greater than 2:1 at% and less than 7:1 at%.

[0013] According to one embodiment, the process temperature for forming the IGO material film may be controlled to be greater than 200°C and less than 300°C.

[0014] According to one embodiment, the temperature at which the IGO material film is heat-treated may be controlled to 400°C or higher.

[0015] According to one embodiment, as at least one of the indium:gallium cation ratio in the IGO material film, the process temperature for forming the IGO material film, and the temperature for heat-treating the IGO material film is controlled, the grain size of the IGO material film increases, and as the grain size of the IGO material film increases, the hydrogen desorption rate in the IGO material film decreases, thereby improving the electrical properties of the IGO material film.

[0016] According to one embodiment, the IGO material film may be formed by atomic layer deposition.

[0017] According to one embodiment, the step of forming the IGO material film may include the step of providing the indium precursor on the substrate, the step of providing the reaction material on the substrate provided with the indium precursor, the step of providing the gallium precursor on the substrate, and the step of providing the reaction material on the substrate provided with the gallium precursor.

[0018]

[0019] To solve the technical problems described above, the present invention provides an IGO material film.

[0020] According to one embodiment, in an IGO (InGaO) material film comprising indium, gallium, and oxygen, the IGO material film may have crystallinity oriented in the C-axis direction.

[0021] According to one embodiment, the IGO material film may include having an average grain size of 88 nm or more at a thickness of 10 nm.

[0022] According to one embodiment, the IGO material film may include a Hall mobility measured at a temperature of 800°C.

[0023]

[0024] To solve the technical problems described above, the present invention provides a transistor.

[0025] According to one embodiment, the transistor may include a gate electrode, a gate insulating film disposed on the gate electrode, an IGO material film according to the embodiment disposed on the gate insulating film, a source electrode disposed on the gate insulating film so as to be in contact with one side of the IGO material film, and a drain electrode disposed on the gate insulating film so as to be in contact with the other side of the IGO material film.

[0026] According to one embodiment, the transistor is 100 cm 2 It may include having mobility greater than / Vs.

[0027]

[0028] To solve the technical problems described above, the present invention provides a NAND flash memory.

[0029] According to one embodiment, the NAND flash memory comprises a gate electrode, an ONO (Oxide-Nitride-Oxide) layer disposed on the gate electrode, a channel layer disposed on the ONO layer, and a source electrode and a drain electrode disposed on one side and the other side, respectively, on the channel layer, wherein the channel layer may comprise a first channel layer comprising silicon (Si) and a second channel layer comprising IGO having crystallinity oriented in the C-axis direction.

[0030] According to one embodiment, the first channel layer may be arranged adjacent to the ONO layer, and the source electrode and the drain electrode may be arranged to be in contact with one side and the other side of the second channel layer, respectively.

[0031] The present invention forms an IGO material film by atomic layer deposition and then heat-treats the IGO material film, wherein the ratio of indium to gallium cations in the IGO material film is controlled to be greater than 2:1 at% and less than 7:1 at%, the process temperature for forming the IGO material film is controlled to be greater than 200°C and less than 300°C, and the temperature for heat-treating the IGO material film can be controlled to be 400°C or higher.

[0032] The IGO material film formed under the conditions described above may have an average grain size of 88 nm or more at a thickness of 10 nm and crystallinity oriented in the C-axis direction. As a result, the IGO material film may have high high-temperature durability, high reliability, and high mobility characteristics.

[0033] FIG. 1 is a flowchart illustrating a method for manufacturing an IGO material film according to an embodiment of the present invention.

[0034] FIG. 2 is a diagram illustrating precursors used in the manufacturing process of an IGO material film according to an embodiment of the present invention.

[0035] FIG. 3 is a diagram illustrating a transistor to which an IGO material film according to an embodiment of the present invention is applied.

[0036] FIG. 4 is a drawing for explaining an example of a NAND flash memory to which an IGO material film according to an embodiment of the present invention is applied.

[0037] FIG. 5 is a diagram illustrating another example of a NAND flash memory to which an IGO material film according to an embodiment of the present invention is applied.

[0038] FIG. 6 is a drawing illustrating another example of a NAND flash memory to which an IGO material film according to an embodiment of the present invention is applied.

[0039] Figure 7 is a drawing for specifically explaining area A of Figure 6.

[0040] FIG. 8 is a diagram illustrating the TDS analysis results for H2 in material films according to Experimental Example 1 of the present invention.

[0041] FIG. 9 is a diagram illustrating the TDS analysis results for OH in material films according to Experimental Example 1 of the present invention.

[0042] FIG. 10 is a diagram illustrating the TDS analysis results for H2O in material films according to Experimental Example 1 of the present invention.

[0043] FIG. 11 is a diagram illustrating the TOF-SIMS analysis results of an InO material film according to Experimental Example 1 of the present invention.

[0044] FIG. 12 is a diagram illustrating the TOF-SIMS analysis results of an IGO material film according to Experimental Example 1 of the present invention.

[0045] FIG. 13 is a diagram illustrating the TOF-SIMS analysis results of an IGZO material film according to Experimental Example 1 of the present invention.

[0046] FIG. 14 is a diagram for comparing the TOF-SIMS analysis results of material films according to Experimental Example 1 of the present invention.

[0047] FIG. 15 is a diagram for more specifically explaining the TOF-SIMS analysis results of an InO material film according to Experimental Example 1 of the present invention.

[0048] FIG. 16 is a diagram for more specifically explaining the TOF-SIMS analysis results of an IGO material film according to Experimental Example 1 of the present invention.

[0049] FIG. 17 is a diagram for more specifically explaining the TOF-SIMS analysis results of an IGZO material film according to Experimental Example 1 of the present invention.

[0050] FIG. 18 is a diagram illustrating the high-temperature stability of an IGO material film according to Experimental Example 2 of the present invention.

[0051] FIG. 19 is a diagram illustrating the high-temperature stability of an InO material film according to Experimental Example 2 of the present invention.

[0052] FIG. 20 is a diagram illustrating the high-temperature stability of an IGZO material film according to Experimental Example 2 of the present invention.

[0053] FIG. 21 is a diagram illustrating the EBSD measurement results and preferred crystal orientation mapping results of an InO material film according to Experimental Example 3 of the present invention.

[0054] FIG. 22 is a diagram for comparing the grain size according to the deposition temperature of the InO material film according to Experimental Example 3 of the present invention and the grain size according to the cation composition ratio of indium:gallium in the IGO material film.

[0055] FIG. 23 is a diagram for comparing XRD analysis results according to the cation composition ratio of the IGO material film according to Experimental Example 3 of the present invention.

[0056] Figure 24 is a diagram for comparing XRD analysis results according to the deposition temperature of an IGO material film according to Experimental Example 3 of the present invention.

[0057] FIG. 25 is a diagram for comparing XRD analysis results according to the heat treatment temperature of an IGO material film according to Experimental Example 3 of the present invention.

[0058] FIG. 26 is a diagram for comparing the average grain size extracted from the results of FIG. 23 to FIG. 25.

[0059] Figure 27 is an HR-TEM image of an IGO material film according to Experimental Example 3 of the present invention.

[0060] FIG. 28 is a diagram illustrating the GIWAXS analysis results for an IGO material film according to Experimental Example 3 of the present invention.

[0061] FIG. 29 is a diagram illustrating the transfer characteristics of a transistor according to experimental examples 4-1 to 4-3 of the present invention.

[0062] FIG. 30 is a diagram illustrating the results of measuring the reliability of a transistor according to Experimental Example 4-3 of the present invention.

[0063] FIG. 31 is a diagram illustrating the transfer characteristics of a NAND flash memory according to experimental examples 5-1 and 5-2 of the present invention.

[0064] FIG. 32 is a diagram illustrating the cumulative probability of electrical characteristics measured from a NAND flash memory according to experimental examples 5-1 and 5-2 of the present invention.

[0065] FIGS. 33 and 34 are drawings for explaining the operation results of a NAND flash memory according to Experimental Example 5-1 of the present invention.

[0066] FIGS. 35 and 36 are drawings for explaining the operation results of a NAND flash memory according to Experimental Example 5-2 of the present invention.

[0067] FIG. 37 is an image of a NAND flash memory according to Experimental Example 6-2 of the present invention.

[0068] FIG. 38 is a diagram illustrating the transfer characteristics of a NAND flash memory according to experimental examples 6-1 and 6-2 of the present invention.

[0069] FIG. 39 is a diagram illustrating the cumulative probability of electrical characteristics measured from a NAND flash memory according to experimental examples 6-1 and 6-2 of the present invention.

[0070] FIGS. 40 and FIGS. 41 are drawings for explaining the operation results of a NAND flash memory according to Experimental Example 6-1 of the present invention.

[0071] FIGS. 42 and FIGS. 43 are drawings for explaining the operation results of a NAND flash memory according to Experimental Example 6-2 of the present invention.

[0072] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed content is thorough and complete and to ensure that the concept of the present invention is sufficiently conveyed to those skilled in the art.

[0073] In this specification, when a component is described as being on another component, it means that it may be formed directly on the other component or that a third component may be interposed between them. Additionally, in the drawings, the thicknesses of the films and regions are exaggerated for the effective description of the technical content.

[0074] Additionally, although terms such as first, second, third, etc., have been used to describe various components in the various embodiments of this specification, these components should not be limited by such terms. These terms are used merely to distinguish one component from another. Accordingly, what is referred to as the first component in one embodiment may be referred to as the second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. Furthermore, in this specification, "and / or" is used to mean including at least one of the components listed before and after it.

[0075] In the specification, singular expressions include plural expressions unless the context clearly indicates otherwise. Furthermore, terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, components, or combinations thereof described in the specification, and should not be understood as excluding the existence or addition of one or more other features, numbers, steps, components, or combinations thereof. Additionally, in this specification, "connection" is used to include both indirectly connecting multiple components and directly connecting them.

[0076] In addition, in describing the present invention below, if it is determined that a detailed description of related known functions or configurations could unnecessarily obscure the essence of the invention, such detailed description will be omitted.

[0077]

[0078] FIG. 1 is a flowchart for explaining a method for manufacturing an IGO material film according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining precursors used in the process of manufacturing an IGO material film according to an embodiment of the present invention.

[0079] Referring to FIGS. 1 and FIGS. 2, a substrate may be prepared (S110). According to one embodiment, the substrate may be a silicon semiconductor substrate. Alternatively, according to another embodiment, the substrate may be any one of a compound semiconductor substrate, a glass substrate, or a plastic substrate. The type of substrate is not limited.

[0080] An IGO material film can be formed by providing a reaction material containing an indium (In) precursor, a gallium (Ga) precursor, and oxygen on the substrate (S120). Subsequently, the IGO material film can be heat-treated (S130). According to one embodiment, the IGO material film can be formed by atomic layer deposition (ALD) using ozone (O3) as the reaction material.

[0081] For example, the indium precursor may include DBADMIn((N,N'-di-tert-butylacetimidamido)-dimethylindium) which is represented by the chemical formula shown in Figure 2(a). For example, the above indium precursors are DADI((3-Dimethylaminopropyl)dimethylindium), TMI(Trimethyl indium), TEI(Triethyl indium), InCA-1(Bis(trimethysilyl)amidodiethyl Indium), CpIn(Cyclopentadienylindium), In(tmhd)3((Tris(2,2,6,6-tetramethyl-3,5-heptandionato)indium(III)), In(acac)3((Indium (III) acetylacetonate), DATI((dimethylbutylamino)trimethylindium), Me2In(EDPA)(dimethyl(Nethoxy-2,2-dimethylpropanamido)indium), InEtCp(ethylcyclopentadienyl indium), TMION(Trimethyl[N-(2-methoxyethyl)-2-methylpropan-2-amine]indium), DMION(Dimethyl[N-(tert-butyl)-2-methoxy-2-methylpropan-1-amine]indium), DMITN(Dimethyl[N1-(tert-butyl)-N2,N2-dimethylethane-1,2-diamine]indium), [In[(i Pr)2CNEt2]3](tris-(N,N'-diisopropyl-2-diethylamido-guanidinato)-indium(III)), [In[(i Pr)2CNMe2]3](tris-(N,N'-diisopropyl-2-dimethylamidoguanidinato)-indium(III)),It may include any one of Et2InN(SiMe3)2(diethyl[bis(trimethylsilyl)amido]indium), In(dmamp)3(tris(1-dimethylamino-2-methyl-2-propoxy)indium), and tris((N,N'-diisopropylacetamidinato) indium(III)).

[0082] For example, the gallium (Ga) precursor may include TMGa (trimethylgallium) represented by the chemical formula shown in Fig. 2 (b). In contrast, for other examples, the gallium precursors include TEGa(Triethyl gallium), Ga(acac)3(Gallium acetylacetonate), [(CH3)2GaNH2]3(dimethylgallium amide), Ga2(NMe2)6(hexakis(dimethylamido)digallium), Me2GaOiPr(dimethylgallium isopropoxide), Ga(OiPr)3(gallium tri-isopropoxide), [Ga(TMHD)3]([tris (2,2,6,6-tetramethyl-3,5-heptanedionato) gallium(III)]), GaCp (pentamethylcyclopentadienyl gallium), [Ga(thd)3](gallium 2,2,6,6-tetramethyl-3,5-heptanedionate), TMGON (Trimethyl[N-(2-methoxyethyl)-2-methylpropan-2-amine]gallium), It may include either DMGON (Dimethyl[N-(tert-butyl)-2-methoxy-2-methylpropan-1-amine]gallium) and DMGTN (Dimethyl[N1-(tert-butyl)-N2,N2-dimethylethane-1,2-diamine]gallium).

[0083] According to one embodiment, the step of forming the IGO material film (S120) may include a step of providing the indium precursor on the substrate (S121a), a purging step (S122a), a step of providing the reaction material on the substrate provided with the indium precursor (S123a), a purging step (S124a), a step of providing the gallium precursor on the substrate (S125a), a purging step (S126a), a step of providing the reaction material on the substrate provided with the gallium precursor (S127a), and a purging step (S128a). In this case, the steps S121a-S122a-S123a-S124a are defined as a first unit process, and the steps S125a-S126a-S127a-S128a are defined as a second unit process, and the first unit process and the second unit process may each be repeated multiple times. Accordingly, the thickness and composition of the IGO material film can be controlled.

[0084] According to one embodiment, by controlling at least one of the indium:gallium cation ratio in the IGO material film, the process temperature for forming the IGO material film, and the temperature for heat-treating the IGO material film, the high-temperature durability, reliability, and electrical properties (e.g., mobility) of the IGO material film can be improved.

[0085] As described above, when at least one of the indium:gallium cation ratio in the IGO material film, the process temperature for forming the IGO material film, and the temperature for heat-treating the IGO material film is controlled, the grain size of the IGO material film increases, and as the grain size of the IGO material film increases, the hydrogen desorption rate in the IGO material film decreases, so the high-temperature durability, reliability, and electrical properties (e.g., mobility) of the IGO material film can be improved.

[0086] More specifically, the ratio of indium to gallium cations in the IGO material film can be controlled to be greater than 2:1 at% and less than 7:1 at%. Conversely, if the ratio of indium to gallium cations in the IGO material film is controlled to be 2:1 at% or less, the IGO material film may have an amorphous structure, or even if it has a crystalline structure, the grain size may be formed small, which may result in a decrease in the high-temperature durability, reliability, and electrical properties (e.g., mobility) of the IGO material film. Additionally, if the ratio of indium to gallium cations in the IGO material film is controlled to be 7:1 at% or more, initial nucleation growth inhibition is not easily achieved, which may result in a problem where the grain size of the IGO material film is formed small.

[0087] The process temperature for forming the IGO material film can be controlled to be greater than 200°C and less than 300°C. When the process temperature for forming the IGO material film is controlled to be 200°C or lower or 300°C or higher, the crystal grain size of the IGO material film is formed relatively smaller compared to when it is controlled to be greater than 200°C and less than 300°C, so problems may arise in which the high-temperature durability, reliability, and electrical properties (e.g., mobility) of the IGO material film are degraded.

[0088] The temperature at which the IGO material film is heat-treated can be controlled to 400°C or higher. When the IGO material film is heat-treated at a temperature of 400°C or higher, the IGO material film may have larger grain sizes and crystallinity oriented in the C-axis direction. Accordingly, the IGO material film may have improved high-temperature durability, reliability, and electrical properties (e.g., mobility).

[0089] That is, the present invention forms an IGO material film by atomic layer deposition and then heat-treats it, wherein the indium:gallium cation ratio in the IGO material film is controlled to be greater than 2:1 at% and less than 7:1 at%, the process temperature for forming the IGO material film is controlled to be greater than 200°C and less than 300°C, and the temperature for heat-treating the IGO material film can be controlled to be 400°C or higher. The IGO material film formed under the conditions described above may have an average grain size of 88 nm or more at a thickness of 10 nm and crystallinity oriented in the C-axis direction. As a result, the IGO material film may have high high-temperature durability, high reliability, and high mobility characteristics.

[0090]

[0091] The above describes an IGO material film and a method for manufacturing the same according to an embodiment of the present invention. Below, a transistor and a NAND flash memory to which an IGO material film according to an embodiment of the present invention is applied are described.

[0092] FIG. 3 is a diagram illustrating a transistor to which an IGO material film according to an embodiment of the present invention is applied.

[0093] Referring to FIG. 3, the transistor having the IGO material film applied thereto may include a gate electrode (110), a gate insulating film (120) disposed on the gate electrode (110), an IGO material film (130) disposed on the gate insulating film (120), a source electrode (140) disposed on the gate insulating film (120) so as to be in contact with one side of the IGO material film (130), and a drain electrode (150) disposed on the gate insulating film (120) so as to be in contact with the other side of the IGO material film (130).

[0094] According to one embodiment, the IGO material film (130) may be the same as the IGO material film described with reference to FIGS. 1 and 2 as the channel of the transistor. According to one embodiment, the gate electrode (110) is p-doped silicon (p ++ It may include Si). According to one embodiment, the gate insulating film (120) may include aluminum oxide (Al2O3). According to one embodiment, the source electrode (140) and the drain electrode (150) may include Indium-Tin-Oxide (ITO).

[0095] A transistor having the structure described above is a Field Effect Transistor (FET), and 100 cm 2 It can have high electric field effect mobility of / Vs or higher.

[0096] FIG. 4 is a drawing for explaining an example of a NAND flash memory to which an IGO material film according to an embodiment of the present invention is applied.

[0097] Referring to FIG. 4, a NAND flash memory according to a first embodiment is provided in which the IGO material film described with reference to FIG. 1 and FIG. 2 is applied as a channel layer. The NAND flash memory according to the first embodiment may have a two-dimensional structure comprising a gate electrode (210), an ONO layer (220) disposed on the gate electrode (210), a channel layer (230) disposed on the ONO layer (220), a source electrode (240) disposed on one side of the channel layer (230), and a drain electrode (250) disposed on the other side of the channel layer (230).

[0098] The gate electrode (210) is p-doped silicon (p ++ It may include Si) and can be used as a substrate to support the above-described configurations.

[0099] The ONO layer (220) may include a first oxide layer (221), a nitride layer (222), and a second oxide layer (223). According to one embodiment, the first oxide layer (221) may be disposed on the gate electrode (210), the nitride layer (222) may be disposed on the first oxide layer (221), and the second oxide layer (223) may be disposed on the nitride layer (222). That is, the first oxide layer (221), the nitride layer (222), and the second oxide layer (223) may be disposed sequentially on the gate electrode (210).

[0100] The first oxide layer (221) may include silicon oxide (SiO2) as a block oxide layer. According to one embodiment, the first oxide layer (221) may be formed to a thickness of 7 nm via a Low Pressure Chemical Vapor Deposition (LPCVD) method. Alternatively, the nitride layer (222) may include silicon nitride (Si3N4) as a charge trap layer. According to one embodiment, the nitride layer (222) may be formed to a thickness of 7 nm via an LPCVD method. The second oxide layer (223) may include silicon oxide (SiO2) as a tunnel oxide layer. According to one embodiment, the second oxide layer (223) may be formed to a thickness of 7 nm via an LPCVD method.

[0101] The channel layer (230) may be disposed on the second oxide layer (223). According to one embodiment, the channel layer (230) may include an IGO material film as described with reference to FIGS. 1 and FIGS. 2.

[0102] The source electrode (240) and the drain electrode (250) may comprise Indium-Tin-Oxide (ITO). According to one embodiment, the source electrode (240) and the drain electrode (250) may be formed to a thickness of 100 nm through a sputtering method.

[0103] FIG. 5 is a diagram illustrating another example of a NAND flash memory to which an IGO material film according to an embodiment of the present invention is applied.

[0104] Referring to FIG. 5, a NAND flash memory according to a second embodiment is provided in which the IGO material film described with reference to FIG. 1 and FIG. 2 is applied as a channel layer. The NAND flash memory according to the second embodiment may have a two-dimensional structure comprising a gate electrode (210), an ONO layer (220) disposed on the gate electrode (210), a first channel layer (235) disposed on the ONO layer (220), a second channel layer (230) disposed on the first channel layer (235), a source electrode (240) disposed on one side of the second channel layer (230), and a drain electrode (250) disposed on the other side of the second channel layer (230).

[0105] The gate electrode (210), the ONO layer (220), the source electrode (240), and the drain electrode (250) included in the NAND flash memory according to the second embodiment may be identical to the gate electrode (210), the ONO layer (220), the source electrode (240), and the drain electrode (250) included in the NAND flash memory according to the first embodiment. Accordingly, a detailed description is omitted.

[0106] The first channel layer (235) may include polycrystalline silicon (Poly-Si). According to one embodiment, the first channel layer (235) may be formed to have a thickness of 10 nm through an LPCVD method. Alternatively, the second channel layer (230) may include an IGO material film as described with reference to FIGS. 1 and 2. That is, the NAND flash memory according to the second embodiment is the same as the NAND flash memory according to the first embodiment, but a channel of a hybrid structure in which a polycrystalline silicon (Poly-Si) material film and an IGO material film are stacked may be used as the channel.

[0107] FIG. 6 is a drawing for explaining another example of a NAND flash memory to which an IGO material film according to an embodiment of the present invention is applied, and FIG. 7 is a drawing for specifically explaining region A of FIG. 6.

[0108] Referring to FIGS. 6 and 7, a NAND flash memory according to a third embodiment is provided in which the IGO material film described with reference to FIGS. 1 and 2 is applied as a channel layer. The NAND flash memory according to the third embodiment may have a three-dimensional structure comprising a substrate (S), a gate stack (310) disposed on the substrate (S), an ONO layer (320) disposed on the substrate (S) to be in contact with one side of the gate stack (310), a channel layer (330) disposed on the substrate (S) to cover the ONO layer (320), and a plurality of electrodes (340) disposed to be in contact with the gate stack (310) and the channel layer (330).

[0109] The above substrate (S) is p-doped silicon (p ++It may include Si). The gate stack (310) can be formed by alternately depositing spacers (311a, 312a, 313a, 314a) and gates (311b, 312b, 323). More specifically, the gate stack (310) can be formed by sequentially stacking a first spacer (311a), a first gate (311b), a second spacer (312a), a second gate (312b), a third spacer (313a), a third gate (313b), and a fourth spacer (314a) on the substrate (S). After the gate stack (310) is formed, a dry etch process may be performed for trench patterning and gate opening.

[0110] According to one embodiment, the first to fourth spacers (311a, 312a, 313a, 314a) all comprise silicon oxide (SiO2) and can be formed to have a thickness of 50 nm through an LPCVD method. Additionally, the first to fourth spacers (311a, 312a, 313a, 314a) are ion implanted (1E20 cm -3 Conductivity can be imparted through the ) process and the RTP (Rapid Thermal Processing, 930°C, 30 min) process.

[0111] According to one embodiment, the first to third gates (311b, 312b, 313b) all comprise polycrystalline silicon (Poly-Si) and can be formed to have a thickness of 100 nm through an LPCVD method. According to one embodiment, the first gate (311b) can be used as a gate for a ground select line (GSL), the second gate (312b) can be used as a gate for a cell, and the third gate (313b) can be used as a gate for a string select line (SSL).

[0112] The ONO layer (320) may be formed on the substrate (S) to be in contact with one side and one upper region of the gate stack (310). According to one embodiment, the ONO layer (320) may be formed to be in contact with one side of the first to fourth spacers (311a, 312a, 313a, 314a) and one side of the first to third gates (311b, 312b, 313b), and to be in contact with one upper region of the fourth spacer (314a).

[0113] The ONO layer (320) may include a first oxide layer (321), a nitride layer (322), and a second oxide layer (323). According to one embodiment, the first oxide layer (321) may be arranged to be in contact with one side of the gate stack (310), the nitride layer (322) may be arranged on the first oxide layer (321), and the second oxide layer (323) may be arranged on the nitride layer (322). That is, the first oxide layer (321), the nitride layer (322), and the second oxide layer (323) may be arranged sequentially in the direction of one side of the gate stack (310).

[0114] The first oxide layer (321) may include silicon oxide (SiO2) as a block oxide layer. According to one embodiment, the first oxide layer (321) may be formed to a thickness of 6 nm via a Low Pressure Chemical Vapor Deposition (LPCVD) method. Alternatively, the nitride layer (322) may include silicon nitride (Si3N4) as a charge trap layer. According to one embodiment, the nitride layer (322) may be formed to a thickness of 4 nm via an LPCVD method. The second oxide layer (323) may include silicon oxide (SiO2) as a tunnel oxide layer. According to one embodiment, the second oxide layer (323) may be formed to a thickness of 3 nm via an LPCVD method.

[0115] The channel layer (330) may be formed on the substrate (S) to cover the ONO layer (320). More specifically, the channel layer (330) may be formed to cover the exposed side and top surfaces of the ONO layer (320) and to be in contact with an upper portion of the fourth spacer (314a).

[0116] The above channel layer (330) may include a first channel layer (331) and a second channel layer (332). According to one embodiment, the first channel layer (331) may be arranged to be in contact with the second oxide layer (323), and the second channel layer (332) may be arranged on the first channel layer (331). That is, the first channel layer (331) and the second channel layer (332) may be arranged sequentially in one direction of the ONO layer (320).

[0117] The first channel layer (331) may comprise polycrystalline silicon (Poly-Si). According to one embodiment, the first channel layer (331) may be formed to have a thickness of 10 nm through an LPCVD method. Additionally, the first channel layer (331) may be polycrystalline through a Rapid Thermal Processing (RTP, 950°C, 20 min) process. Alternatively, the second channel layer (332) may comprise an IGO material film as described with reference to FIGS. 1 and 2.

[0118] The plurality of electrodes (340) may be formed to contact the first to third gates (311b, 312b, 313b) of the gate stack (310) exposed by a dry etching process, and the channel layer (330). According to one embodiment, an electrode (340) formed to contact one side of the channel layer (330) may be defined as a source electrode, and an electrode (340) formed to contact the other side of the channel layer (330) may be defined as a drain electrode. According to one embodiment, the plurality of electrodes (340) may include Indium-Tin-Oxide (ITO) and may be formed to have a thickness of 100 nm through a sputtering process.

[0119]

[0120] Above, a transistor and a NAND flash memory to which an IGO material film according to an embodiment of the present invention are applied have been described. Below, specific experimental examples and characteristic evaluation results for the IGO material film, transistor, and NAND flash memory according to an embodiment of the present invention are described.

[0121] Experimental Example 1: Comparison of Hydrogen Desorption Rates According to Material Film Type

[0122] After preparing InO material films, IGO material films, and IGZO material films, each was heat-treated at a temperature of 0 to 800°C, and TDS (Thermal desorption spectroscopy) analysis and TOF-SIMS (Time-of-flight secondary-ion mass spectrometry) analysis were performed on the heat-treated material films.

[0123] FIG. 8 is a diagram illustrating the TDS analysis results for H2 in material films according to Experimental Example 1 of the present invention, FIG. 9 is a diagram illustrating the TDS analysis results for OH in material films according to Experimental Example 1 of the present invention, and FIG. 10 is a diagram illustrating the TDS analysis results for H2O in material films according to Experimental Example 1 of the present invention.

[0124] As can be seen in Figures 8 to 10, in the case of the InO material film, hydrogen is desorbed in the form of H2 molecules at a heat treatment temperature of 400°C or higher, and in the case of the IGZO material film, hydrogen is desorbed in the form of OH and H2O molecules at a temperature of 400°C or lower. On the other hand, in the case of the IGO material film, it can be seen that hydrogen is not desorbed regardless of the heat treatment temperature.

[0125] FIG. 11 is a diagram illustrating the TOF-SIMS analysis results of an InO material film according to Experimental Example 1 of the present invention, FIG. 12 is a diagram illustrating the TOF-SIMS analysis results of an IGO material film according to Experimental Example 1 of the present invention, FIG. 13 is a diagram illustrating the TOF-SIMS analysis results of an IGZO material film according to Experimental Example 1 of the present invention, and FIG. 14 is a diagram for comparing the TOF-SIMS analysis results of the material films according to Experimental Example 1 of the present invention.

[0126] As can be seen in Figures 11 to 14, the amount of hydrogen desorption due to heat treatment is relatively high for InO material films and IGZO material films (34.3% and 49.5% at 800°C, respectively), whereas the amount of hydrogen desorption due to heat treatment is relatively low for IGO material films (20.9% at 800°C).

[0127] FIG. 15 is a drawing to explain in more detail the TOF-SIMS analysis results of an InO material film according to Experimental Example 1 of the present invention, FIG. 16 is a drawing to explain in more detail the TOF-SIMS analysis results of an IGO material film according to Experimental Example 1 of the present invention, and FIG. 17 is a drawing to explain in more detail the TOF-SIMS analysis results of an IGZO material film according to Experimental Example 1 of the present invention.

[0128] Figures 15 to 17 (a) shows the analysis results for the state before heat treatment, Figures 15 to 17 (b) shows the analysis results for the state after heat treatment at a temperature of 400°C, and Figures 15 to 17 (c) shows the analysis results for the state after heat treatment at a temperature of 800°C.

[0129] As can be seen in Figures 15 to 17, even though high heat treatment of 800°C is performed, elements such as indium (In), gallium (Ga), and zinc (Zn), excluding hydrogen, do not diffuse into adjacent thin films.

[0130]

[0131] Experimental Example 2: Comparison of High-Temperature Stability According to Material Film Type

[0132] After preparing InO, IGO, and IGZO material films, each was heat-treated at temperatures of 400°C and 800°C, and for the heat-treated material films, the carrier concentration (C10) -3 ), Hall mobility (cm 2 / Vs), and resistivity (Ω*cm) were measured.

[0133] FIG. 18 is a diagram illustrating the high-temperature stability of an IGO material film according to Experimental Example 2 of the present invention, FIG. 19 is a diagram illustrating the high-temperature stability of an InO material film according to Experimental Example 2 of the present invention, and FIG. 20 is a diagram illustrating the high-temperature stability of an IGZO material film according to Experimental Example 2 of the present invention.

[0134] As can be seen in FIGS. 18 to 20, when high-temperature heat treatment at 800°C is performed, it can be confirmed that the characteristics of the InO material film and the IGZO material film cannot be measured due to degradation. On the other hand, in the case of the IGO material film, carrier concentration, hole mobility, and resistivity were all measured despite high-temperature heat treatment at 800°C, and in particular, it can be confirmed that hole mobility significantly improves as the heat treatment temperature increases. Consequently, it can be seen that the IGO material film has significantly higher high-temperature (above 800°C) stability compared to the InO material film and the IGZO material film.

[0135]

[0136] Experimental Example 3: Verification of Structural Changes in InO and IGO Films According to Process Conditions

[0137] An IGO film was formed by atomic layer deposition using an indium precursor, a gallium precursor, and a reactant, and an InO film was formed by atomic layer deposition using an indium precursor and a reactant, and then these were heat-treated. DBADMIn ((N,N'-di-tert-butylacetimidamido)-dimethylindium) was used as the indium precursor, TMGa (trimethylgallium) was used as the gallium precursor, and ozone (O3) was used as the reactant.

[0138] In addition, various samples were prepared by controlling process conditions, and then EBSD (Electron Back Scattered Diffraction), XRD (X-Ray Diffraction), HR-TEM (High Resolution-Transmission Electron Microscopy), and GIWAXS (Grazing Incidence Wide Angle X-ray Scattering) analyses were performed on the prepared samples to confirm structural changes in IGO and InO material films according to process conditions.

[0139] More specifically, various samples were prepared such that the indium:gallium cation composition ratio in the IGO material film was 1:1 at%, 2:1 at%, 4:1 at%, and 7:1 at%, various samples were prepared at various deposition temperatures (atomic layer deposition process temperatures) of 200°C, 250°C, 300°C, and 350°C, and samples were prepared by heat treatment at temperatures of 400°C and 800°C.

[0140] FIG. 21 is a diagram illustrating the EBSD measurement results and preferred crystal orientation mapping results of an InO material film according to Experimental Example 3 of the present invention.

[0141] Figure 21 (a) shows the measurement results of an InO material film formed at a deposition temperature of 200°C, Figure 21 (b) shows the measurement results of an InO material film formed at a deposition temperature of 250°C, and Figure 21 (c) shows the measurement results of an InO material film formed at a deposition temperature of 300°C.

[0142] As can be seen in FIG. 21, the InO material film formed at a deposition temperature of 250°C has a very large average grain size of 63.8 nm at a thickness of 10 nm, and at the same time, it can be seen that there is a large amount of crystallinity oriented in the C-axis direction (111) (blue).

[0143] FIG. 22 is a diagram for comparing the grain size according to the deposition temperature of the InO material film according to Experimental Example 3 of the present invention and the grain size according to the cation composition ratio of indium:gallium in the IGO material film.

[0144] Referring to FIG. 22, the average grain size (nm) for InO film formed at different deposition temperatures (200°C, 250°C, 300°C) and IGO film having different indium:gallium cation composition ratios (1:1, 2:1, 4:1, 7:1 at%) is shown. The measurement results of FIG. 22 are summarized in Table 1 below.

[0145] Classification Condition Average Grain Size InO 200℃ 30.8 nm InO 250℃ 63.8 nm InO 300℃ 49.0 nm IGO 1:1 at %N / A (amorphous) IGO 2:1 at %30.6 nm IGO 4:1 at %88.2 nm IGO 7:1 at %54.4 nm

[0146] As can be seen in Fig. 22, in the case of the InO material film, the average grain size increases significantly as the deposition temperature increases from 200°C to 250°C, but decreases when the temperature increases from 250°C to 300°C. In other words, it can be seen that in order to manufacture an InO material film or an IGO material film with a large grain size, the process temperature of the atomic layer deposition process must be controlled to be greater than 200°C and less than 300°C.

[0147] In addition, for IGO film, it can be observed that the average grain size increases significantly as the indium:gallium cation composition ratio increases from 2:1 at% to 4:1 at%, but decreases when the ratio increases from 4:1 at% to 7:1 at%. In other words, it can be seen that in order to manufacture an IGO film with a large grain size, the indium:gallium cation composition ratio must be controlled to be greater than 2:1 at% and less than 7:1 at%. In particular, it can be seen that an IGO film manufactured with a cation composition ratio of 4:1 at% has a large average grain size of 88 nm or more at a thickness of 10 nm.

[0148] More specifically, the largest grain size was achieved at a cation composition ratio of 4:1 at%. In particular, at ratios of 1:1 at% and 2:1 at%, amorphous or very small crystal sizes were observed; this is because a high proportion of amorphous GaO introduced into the crystalline phase InO actually hinders overall crystal growth. In contrast, at a ratio of 4:1 at%, the grain size increased in IGO compared to InO, which is because the effect of increasing the average grain size due to the initial nucleation inhibition effect through hydrogen doping occurred in the same way. Finally, in the case of 7:1 at%, the crystal size was similar to that of InO, which is because the GaO doping ratio was too low to exert the initial nucleation inhibition effect.

[0149] FIG. 23 is a diagram for comparing XRD analysis results according to the cation composition ratio of an IGO material film according to Experimental Example 3 of the present invention, FIG. 24 is a diagram for comparing XRD analysis results according to the deposition temperature of an IGO material film according to Experimental Example 3 of the present invention, FIG. 25 is a diagram for comparing XRD analysis results according to the heat treatment temperature of an IGO material film according to Experimental Example 3 of the present invention, and FIG. 26 is a diagram for comparing the average grain size extracted from the results of FIG. 23 to FIG. 25.

[0150] As can be seen in FIGS. 23 to 26, the largest grain size is observed in the IGO material film in which the deposition temperature is controlled to 250°C, the indium:gallium cation composition ratio is controlled to 4:1 at%, and the heat treatment temperature is controlled to 800°C.

[0151] In addition, the C-axis orientation can be quantified as a ratio of C(222) / C(046) in FIGS. 23 to 25. More specifically, Ground was calculated as the intensity at 2theta 15 degrees, where there appears to be no InOx crystal peak, and Ground can be set differently depending on the measurement method, conditions, or situation, and the ratio of C(222) / C(046) was calculated through the following <Equation 1>.

[0152] <Mathematical Formula 1>

[0153] C(222)-{theta=15 o} / C(046)-{2theta=15 o}

[0154] The calculated values ​​can be summarized as shown in below. In the case of N / A shown in , it indicates an amorphous state or a state lacking crystallinity with an average grain size of 35 nm or less. Additionally, the values ​​in Fig. 26 can be summarized as shown in below.

[0155] Classification In:Ga Ratio (at%) Deposition Temperature Heat Treatment Temperature C(222) / C(400) IGO1: 1250℃ 800℃ N / AIGO2: 1250℃ 800℃ N / AIGO4: 1250℃ 800℃ 20.45 nm IGO7: 1250℃ 800℃ 8.50 nm IGO4: 1200℃ 800℃ 8.36 nm IGO4: 1300℃ 800℃ 7.65 nm IGO4: 1350℃ 800℃ 5.55 nm IGO4: 1250℃ As-dep N / AIGO4: 1250℃ 400℃ 11.87 nm

[0156] Classification In:Ga Ratio (at%) Deposition Temperature Heat Treatment Temperature Average Grain Size IGO1:1250℃800℃N / A (amorphous)IGO2:1250℃800℃30.6 nm IGO4:1250℃800℃88.2 nm IGO7:1250℃800℃54.4 nm IGO4:1200℃800℃85.5 nm IGO4:1300℃800℃80.4 nm IGO4:1350℃800℃80.4 nm IGO4:1250℃As-depN / A (amorphous)IGO4:1250℃400℃69.8 nm

[0157] FIG. 27 is an HR-TEM image of an IGO material film according to Experimental Example 3 of the present invention, and FIG. 28 is a diagram illustrating the GIWAXS analysis results of an IGO material film according to Experimental Example 3 of the present invention.

[0158] Referring to Fig. 27(a), an HR-TEM image of the IGO material film according to Experimental Example 3 before heat treatment is shown, and referring to Fig. 27(b), an HR-TEM image of the IGO material film according to Experimental Example 3 after heat treatment at a temperature of 800°C is shown.

[0159] As can be seen in Figures 27 and 28, the material has an amorphous state before heat treatment, whereas crystals are formed after heat treatment, indicating that the initial nucleation growth inhibition effect through Ga doping occurred, resulting in an increase in the grain size after heat treatment. In addition, just as the InO material film deposited at a temperature of 250°C had crystallinity oriented in the C-axis direction, it can be confirmed that the IGO material film also has crystallinity oriented in the C-axis direction.

[0160]

[0161] Experimental Example 4: Verification of Characteristics of a Transistor with an IGO Material Film

[0162] After preparing the transistor described with reference to Fig. 3, various characteristics were measured. More specifically, a transistor according to Experimental Example 4-1 (Ex 4-1) in which an unheat-treated IGO material film was used as the channel, a transistor according to Experimental Example 4-2 (Ex 4-2) in which an IGO material film heat-treated at a temperature of 400°C was used as the channel, and a transistor according to Experimental Example 4-3 (Ex 4-3) in which an IGO material film heat-treated at a temperature of 800°C was used as the channel were prepared, and various characteristics were measured for each.

[0163] FIG. 29 is a diagram illustrating the transfer characteristics of a transistor according to experimental examples 4-1 to 4-3 of the present invention, and FIG. 30 is a diagram illustrating the reliability measurement results of a transistor according to experimental example 4-3 of the present invention.

[0164] Referring to FIG. 29, the transfer characteristic measurement results for each of the transistors (Ex 4-1, Ex 4-2, Ex 4-3) according to Experimental Examples 4-1 to 4-3 above are shown. The results measured through FIG. 29 are summarized in below.

[0165] Classification Ex 4-1 Ex 4-2 Ex 4-3 V th [V]N / A-0.42±0.18-0.94±0.08μ FE [cm 2 / Vs]N / A80.57±3.26103.66±0.25Hysteresis [V]N / A0.01±0.010.01±0.01SS [mV / dec]N / A81±296±12I on / I off N / A6.67x10 7 1.35x10 8

[0166] As can be seen in Fig. 29 and Table 4, in the case of the transistor (Ex 4-3) where an IGO material film heat-treated at a temperature of 800°C is applied as a channel, 100 cm 2 It can be confirmed that it possesses high mobility characteristics greater than / Vs.

[0167] Referring to FIG. 30, the results of reliability measurements performed on the transistor (Ex 4-3) according to Experimental Example 4-3 under harsh stress conditions of 100°C and 3 MV / cm are shown. As can be seen in FIG. 30, excellent reliability characteristics are exhibited, with the threshold voltage shifting by only about +0.07 V over 10,000 seconds even under harsh conditions. This is confirmed to be the result of minimizing hydrogen desorption effects and grain boundary scattering and trapping effects by increasing the average grain size and expressing crystallinity oriented in the C-axis direction through the optimization of the manufacturing process of the IGO material film.

[0168]

[0169] Experimental Example 5: Verification of Characteristics of 2D Structured NAND Flash Memory with IGO Material Film

[0170] After preparing the two-dimensional NAND flash memory described with reference to Fig. 4 and the NAND flash memory described with reference to Fig. 5, various characteristics were measured for each. The two-dimensional NAND flash memory described with reference to Fig. 4 (single application of IGO material film) is defined as the NAND flash memory according to Experimental Example 5-1 (Ex 5-1), and the two-dimensional NAND flash memory described with reference to Fig. 5 (application of Poly-Si material film / IGO material film hybrid structure) is defined as the NAND flash memory according to Experimental Example 5-2 (Ex 5-2). In addition, the channel layers of each NAND flash memory were heat-treated at a temperature of 800°C.

[0171] FIG. 31 is a diagram illustrating the transfer characteristics of a NAND flash memory according to experimental examples 5-1 and 5-2 of the present invention, and FIG. 32 is a diagram illustrating the cumulative probability of electrical characteristics measured from a NAND flash memory according to experimental examples 5-1 and 5-2 of the present invention.

[0172] Referring to FIG. 31, the transfer characteristics (I) for each of the NAND flash memory (OS channel) according to Experimental Example 5-1 and the NAND flash memory (Hybrid channel) according to Experimental Example 5-2 are D -V GS It represents ) and electric field-effect mobility.

[0173] Referring to FIG. 32, the measured threshold voltage (V) for each of the NAND flash memory (OS FET) according to Experimental Example 5-1 and the NAND flash memory (Hybrid FET) according to Experimental Example 5-2 is th Cumulative probability of ) (a), cumulative probability of sub-threshold swing value (SS) (b), on-current (I on Cumulative probability (c) of ), and field-effect mobility (μ FE Represents the cumulative probability (d) of ).

[0174] In addition, various electrical characteristics measured from the NAND flash memory according to Experimental Example 5-1 (Ex 5-1) and the NAND flash memory according to Experimental Example 5-2 (Ex 5-2) are summarized in below.

[0175] Distinction V th [V]SS [mV / dec]I on [μA / μm]μ FE [cm 2 / Vs]Ex 5-1-2.48 ± 0.06116.69 ± 10.863.04 ± 0.92105.92 ± 23.62Ex 5-2-1.85 ± 0.45175.65 ± 25.814.73 ± 0.61116.08 ± 18.10

[0176] As can be seen in FIGS. 31 and 32 and Table 5, the hybrid channel device (Ex 5-2) exhibits higher field-effect mobility and sub-threshold swing values ​​than the single channel device (Ex 5-1). This may be a result of the formation of SiO due to the oxidation of Si at the poly-Si / IGO interface during the heat treatment process of the channel, and the increase in the amount of oxygen vacancies due to the reduction of IGO.

[0177] Meanwhile, regarding threshold voltage (Vth) and subthreshold swing value (SS), the single-channel device (Ex 5-1) exhibits superior distribution characteristics compared to the hybrid-channel device (Ex 5-2), whereas regarding on-current (Ion) and field-effect mobility, both the single-channel device (Ex 5-1) and the hybrid-channel device (Ex 5-2) exhibit similar distribution characteristics. Accordingly, it can be seen that pol-Si can affect the subthreshold swing value characteristics, even though the main channel layer is composed of IGO.

[0178] FIGS. 33 and 34 are drawings for explaining the operation results of a NAND flash memory according to Experimental Example 5-1 of the present invention.

[0179] Referring to FIG. 33, the transfer curve recorded after the erase and program voltage biases are applied to the NAND flash memory (OS channel NAND) according to Experimental Example 5-1 is shown, and referring to FIG. 34, the threshold voltage (Vth) value and voltage value after operation are shown.

[0180] As can be seen in FIGS. 33 and 34, the memory window appears wide at approximately 2.98 V, and the threshold voltage (V) during the erase operation thIt can be confirmed that no change occurs. This indicates that the bandgap of the IGO single channel is wide, so the GIDL (Gate-Induced Drain Leakage) erasure operation could not be easily performed.

[0181] FIGS. 35 and 36 are drawings for explaining the operation results of a NAND flash memory according to Experimental Example 5-2 of the present invention.

[0182] Referring to FIG. 35, the transfer curve recorded after the erase and program voltage biases are applied to the NAND flash memory (HC NAND) according to Experimental Example 5-2 is shown, and referring to FIG. 36, the threshold voltage (Vth) value and voltage value after operation are shown.

[0183] As can be seen in FIGS. 35 and 36, the program operation was successfully performed, and the threshold voltage (V) at the program voltage th It can be seen that the change is similar to the NAND flash memory according to Experimental Example 5-1 above. However, unlike the NAND flash memory according to Experimental Example 5-1 above, it can be confirmed that the NAND flash memory according to Experimental Example 5-2 above allows for easy GIDL (Gate-Induced Drain Leakage) erasure operation. More specifically, while the generation of GIDL current was confirmed at a drain voltage of 10 V or higher in the NAND flash memory according to Experimental Example 5-2 above, the GIDL current in the NAND flash memory according to Experimental Example 5-1 above was measured to be close to 0 until the drain voltage reached 15 V.

[0184] As a result, the erase operation was successfully implemented using the GIDL current generated by inter-band tunneling of the Poly-Si channel, and it can be seen that the memory window of the NAND flash memory with the hybrid channel (Poly-Si / IGO) applied increases up to 3.59 V.

[0185]

[0186] Experimental Example 6: Verification of Characteristics of 3D Structured NAND Flash Memory with IGO Material Film

[0187] A NAND flash memory with a three-dimensional structure, as described with reference to FIGS. 6 and 7, was prepared, and a NAND flash memory with a single-channel structure of an IGO material film and a NAND flash memory with a hybrid-channel structure in which a Poly-Si material film and an IGO material film are stacked were prepared, and various characteristics were measured for each. The NAND flash memory with a single-channel structure of an IGO material film is defined as the NAND flash memory according to Experimental Example 6-1 (Ex 6-1), and the NAND flash memory with a hybrid-channel structure is defined as the NAND flash memory according to Experimental Example 6-2 (Ex 6-2). In addition, the channels of each NAND flash memory were heat-treated at a temperature of 800°C.

[0188] FIG. 37 is an image of a NAND flash memory according to Experimental Example 6-2 of the present invention.

[0189] Referring to FIG. 37(a), a High Revolution-Transmission Electron Microscopy (HR-TEM) image of the NAND flash memory (Ex 6-2) according to Experimental Example 6-2 is shown, and referring to FIG. 37(b) and (c), phase mapping results obtained using TEM-ASTAR for the channel region of the NAND flash memory (Ex 6-2) according to Experimental Example 6-2 are shown. More specifically, FIG. 37(b) shows the results for the state before heat treatment, FIG. 37(c) shows the results for the state after heat treatment, and in FIG. 37(a), SSL refers to the string select line and GSL refers to the ground select line.

[0190] As can be seen in Fig. 37 (a), it can be confirmed that the formation of a gate stack in which spacers and gates are sequentially stacked was successfully achieved. As can be seen in Figs. 37 (b) and (c), it can be confirmed that the IGO channel has an amorphous state before heat treatment but crystallizes upon heat treatment. In addition, it can be confirmed that the Si channel maintains a polycrystalline state regardless of heat treatment. Furthermore, it can be confirmed that SiO is formed at the interface between the Poly-Si channel and the IGO channel due to the oxidation of Si caused by heat treatment.

[0191] FIG. 38 is a diagram illustrating the transfer characteristics of a NAND flash memory according to experimental examples 6-1 and 6-2 of the present invention, and FIG. 39 is a diagram illustrating the cumulative probability of electrical characteristics measured from a NAND flash memory according to experimental examples 6-1 and 6-2 of the present invention.

[0192] Referring to FIG. 38, the transfer characteristics (I) for each of the NAND flash memory (OS Vertical-channel) according to Experimental Example 6-1 and the NAND flash memory (Hybrid Vertical-channel) according to Experimental Example 6-2 are D -V GS It represents ) and electric field-effect mobility.

[0193] Referring to FIG. 39, the measured threshold voltage (V) for the NAND flash memory (OS V-FET) according to Experimental Example 6-1 and the NAND flash memory (Hybrid V-FET) according to Experimental Example 6-2, respectively th Cumulative probability of ) (a), cumulative probability of sub-threshold swing value (SS) (b), on-current (I on Cumulative probability (c) of ), and field-effect mobility (μ FE Represents the cumulative probability (d) of ).

[0194] In addition, various electrical characteristics measured from the NAND flash memory according to Experimental Example 6-1 (Ex 6-1) and the NAND flash memory according to Experimental Example 6-2 (Ex 6-2) are summarized in below.

[0195] Distinction V th [V]SS [mV / dec]I on [μA / μm]μ FE [cm 2 / Vs]Ex 6-1-1.88 ± 0.13109.35 ± 7.471.36 ± 0.05121.39 ± 12.31Ex 6-2-1.14 ± 0.84136.41 ± 16.041.59 ± 0.19134.70 ± 28.27

[0196] FIGS. 40 and FIGS. 41 are drawings for explaining the operation results of a NAND flash memory according to Experimental Example 6-1 of the present invention.

[0197] Referring to FIG. 40, the transfer curve recorded after the erase and program voltage biases are applied to the NAND flash memory (OS channel 3D NAND) according to Experimental Example 6-1 is shown, and referring to FIG. 41, the threshold voltage (Vth) value and voltage value after operation are shown.

[0198] FIGS. 42 and FIGS. 43 are drawings for explaining the operation results of a NAND flash memory according to Experimental Example 6-2 of the present invention.

[0199] Referring to FIG. 42, the transfer curve recorded after the erase and program voltage biases are applied to the NAND flash memory (HC V-NAND) according to Experimental Example 6-2 is shown, and referring to FIG. 43, the threshold voltage (Vth) value and voltage value after operation are shown.

[0200] As can be seen in FIGS. 38 to 43, the operation results and memory window of a three-dimensional NAND flash memory are similar to the operation results and memory window of a two-dimensional NAND flash memory.

[0201]

[0202] Although the present invention has been described in detail using preferred embodiments, the scope of the invention is not limited to specific embodiments and should be interpreted by the appended claims. Furthermore, those skilled in the art will understand that many modifications and variations are possible without departing from the scope of the invention.

[0203] The present invention can be used in the semiconductor industry.

Claims

1. Step of preparing the substrate; A step of forming an IGO material film by providing a reaction material comprising an indium (In) precursor, a gallium (Ga) precursor, and oxygen on the substrate; and The method includes the step of heat-treating the above IGO material film, A method for manufacturing an IGO material film, comprising controlling at least one of the indium:gallium cation ratio in the IGO material film, the process temperature for forming the IGO material film, and the temperature for heat-treating the IGO material film to improve the electrical properties of the IGO material film.

2. In Paragraph 1, A method for manufacturing an IGO material film comprising controlling the indium:gallium cation ratio in the IGO material film to be greater than 2:1 at% and less than 7:1 at%.

3. In Paragraph 1, A method for manufacturing an IGO material film, comprising controlling the process temperature for forming the IGO material film to be greater than 200℃ and less than 300℃.

4. In Paragraph 1, A method for manufacturing an IGO material film, comprising controlling the temperature at which the IGO material film is heat-treated to 400℃ or higher.

5. In Paragraph 1, As at least one of the indium:gallium cation ratio in the IGO material film, the process temperature for forming the IGO material film, and the temperature for heat-treating the IGO material film is controlled, the grain size of the IGO material film increases, and A method for manufacturing an IGO material film, comprising reducing the hydrogen desorption rate within the IGO material film as the crystal grain size of the IGO material film increases, thereby improving the electrical properties of the IGO material film.

6. In Paragraph 1, A method for manufacturing an IGO material film, comprising forming the above IGO material film by atomic layer deposition.

7. In Paragraph 1, The step of forming the above IGO material film is, A step of providing the indium precursor on the substrate; A step of providing the reaction material on the substrate provided with the indium precursor; The step of providing the gallium precursor on the substrate; and A method for manufacturing an IGO material film comprising the step of providing the reaction material on the substrate provided with the gallium precursor.

8. In an IGO(InGaO) material film comprising indium, gallium, and oxygen, The above IGO material film comprises an IGO material film having crystallinity oriented in the C-axis direction.

9. In Paragraph 8, An IGO material film having an average grain size of 88 nm or more at a thickness of 10 nm.

10. In Paragraph 8, An IGO material film in which hall mobility is measured at a temperature of 800°C.

11. Gate electrode; A gate insulating film disposed on the gate electrode; An IGO material film according to claim 8 disposed on the gate insulating film above; A source electrode disposed on the gate insulating film so as to be in contact with one side of the IGO material film; and A transistor comprising a drain electrode disposed on the gate insulating film so as to be in contact with the other side of the IGO material film.

12. In Paragraph 11, 100 cm 2 A transistor having a mobility greater than or equal to / Vs.

13. Gate electrode; An ONO (Oxide-Nitride-Oxide) layer disposed on the gate electrode; A channel layer disposed on the above ONO layer; and A source electrode and a drain electrode disposed respectively on one side and the other side of the channel layer, wherein The above channel layer is a NAND flash memory comprising a first channel layer comprising silicon (Si) and a second channel layer comprising IGO having crystallinity oriented in the C-axis direction.

14. In Paragraph 13, A NAND flash memory comprising the first channel layer being arranged adjacent to the ONO layer, and the source electrode and the drain electrode being arranged to contact one side and the other side of the second channel layer, respectively.

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