A layout joint structure design method for improving a metal stripping process of an indium gallium arsenide detector

Abstract

This invention belongs to the field of semiconductor device manufacturing and layout design technology. It provides a layout connection structure design method to improve the metal stripping process of indium gallium arsenide (IGaAs) detectors. The method employs an inverted trapezoidal stepped electrode edge optimization, forming a gradual slope along the direction perpendicular to the substrate. Rounded transitions are used at the corners of the electrode pattern. Small closed patterns to be stripped are connected to surrounding large patterns via connecting strips. The inverted trapezoidal slope of the connecting strips matches the electrode pattern. The connecting strips avoid the effective area of ​​the detector, with a minimum distance of ≥4µm from the effective electrode. The number of connecting strips is set according to the minimum area pattern distribution density, with one connecting strip shared by every 2-5 small closed patterns. This reduces contaminant generation by more than 98%, fundamentally lowering the risk of electrode contamination and scrapping. It is directly compatible with existing Ti / Pt / Au multilayer metal stripping processes. The connecting strip parameters can be flexibly adjusted according to different electrode sizes, making it suitable for detector production in various fields such as optical communication and spectral detection.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing and layout design technology, specifically relating to a layout connection structure design method for improving the metal stripping process of indium gallium arsenide detectors, and optimizing the metal evaporation stripping process in the production of indium gallium arsenide infrared detectors. Specifically, it is a layout drawing method that improves the integrity of metal layer stripping and reduces the residual rate through layout structure design. Background Technology

[0002] Indium gallium arsenide (IGaAs) infrared detectors, as core optoelectronic devices in the near-infrared and short-wave infrared bands, have irreplaceable application value in fields such as optical communication, spectral detection, security monitoring, lidar, and night vision imaging. The fabrication quality of their metal electrodes directly determines the detector's response speed, quantum efficiency, and reliability. The lift-off process is a crucial step in the fabrication of IGaAs infrared detector metal electrodes. It involves defining the electrode region using photoresist patterning, followed by metal deposition and removal of the photoresist and excess surface metal to ultimately form the target electrode structure. Layout design, as a core pre-processing step, directly affects the photoresist morphology, metal layer adhesion, and lift-off integrity.

[0003] In traditional photolithography layout design, the layout includes not only detector electrode patterns, test patterns, and linewidth test patterns, but also smaller, closed overlay patterns. During the stripping process after metal evaporation, acetone dissolves the photoresist beneath the metal layer, removing undefined areas. In this stripping process, closed patterns with large areas of photoresist beneath the metal layer are easier to remove, leaving no metal residue. However, closed patterns with small areas of photoresist beneath the metal layer are difficult to remove, often floating in the acetone after stripping and randomly settling onto the chip during subsequent cleaning, transfer, and drying steps, making them difficult to remove in later processes. Because the electrodes in the layout design of indium gallium arsenide (IGaAs) detectors are arranged in a large, dense area with small pattern spacing, small areas of residual metal film suspended in acetone, once they settle on the effective photosensitive area or critical electrodes of the detector chip, will form an unavoidable short circuit or optical blockage, directly causing the functional failure and scrapping of a single detector chip. This random failure mode caused by suspended contaminants severely damages process stability and product yield, posing a significant risk in mass production. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies such as insufficient adaptability of metal vapor deposition stripping processes for indium gallium arsenide (IGaAs) infrared detectors and the tendency for small-area stripping residues to cause electrode contamination, this invention provides a layout connection structure design method to improve the metal stripping process for IGaAs detectors. This invention addresses the layout drawing method by optimizing the graphic structure of the layout, integrating residue control design, and small-area pattern connectivity design. This reduces contaminant generation at the source, solving problems such as metal residue, incomplete stripping, and electrode contamination and scrapping caused by traditional layouts. The goal is to improve the integrity of metal layer stripping, reduce residue contamination rate, increase device yield, and optimize photoelectric performance consistency.

[0005] This invention is achieved by the following technical solution: a layout connection structure design method for improving the metal stripping process of indium gallium arsenide detectors, comprising the following steps: Electrode pattern structure optimization: The electrode edge is optimized by adopting an inverted trapezoidal step-type shape. The ratio of the top width to the bottom width of the electrode pattern is 1:1.2-1.5, forming a gradual slope along the direction perpendicular to the base. The corners of the electrode pattern are rounded. Small-area pattern connectivity design: Small-area closed patterns to be peeled off in the layout are connected to the surrounding large-area patterns to be peeled off by connecting strips with a width of 2-5µm. The inverted trapezoidal slope of the connecting strip is consistent with the electrode pattern, with a top:bottom ratio of 1:1.4. The connecting strip avoids the effective area of ​​the detector, and the minimum distance between it and the effective electrode is ≥4µm. The number of connecting strips is set according to the distribution density of the smallest area pattern, with every 2-5 small-area closed patterns sharing one connecting strip.

[0006] The line width tolerance of the connecting strip is ≤ ±0.5um, and the minimum spacing of the pattern is 5um.

[0007] The specific method includes the following steps: (1) Layout design: Draw a mask template and design the connecting strip between the small closed graphic to be peeled and the large graphic to be peeled: design the connecting strip in the center of the two rows of overlay marks. The connecting strip connects the five small closed graphic to be peeled, namely the overlay marks and the digital plate number, with the outer large area to be peeled. (2) Fabrication and trial production: The mask is remade according to the layout design and the wafer is produced without changing other production process conditions such as photolithography process parameters, vapor deposition process parameters, and stripping process parameters.

[0008] The width of the connecting strip is 4µm.

[0009] This invention employs an inverted trapezoidal stepped electrode edge optimization, with the top width to bottom width ratio of the electrode pattern being 1:1.2-1.5, forming a gradual slope along the direction perpendicular to the substrate. This adapts to the ideal development morphology of the photoresist, which is "smaller at the top and larger at the bottom," thus blocking the penetration path of metal atoms along the sidewalls of the resist layer. The corners of the electrode pattern are rounded to avoid cracking caused by stress concentration in the photoresist at sharp angles.

[0010] The small closed patterns to be peeled off in the layout are connected to the surrounding large patterns to be peeled off by connecting strips with a width of 2-5µm. The inverted trapezoidal slope of the connecting strips is consistent with the electrode pattern. The connecting strips avoid the effective area of ​​the detector, and the minimum distance between them and the effective electrodes is ≥4µm. The number of connecting strips is set according to the distribution density of the smallest area patterns. Every 2-5 small closed patterns share one connecting strip to avoid the connecting strips occupying too much chip area.

[0011] Compared with the prior art, the present invention has the following significant effects: Reduce small-area contaminants at the source: Connecting strips allow small-area closed patterns to peel off synchronously with large-area patterns, preventing small metal blocks from falling off and suspending in acetone. This reduces the amount of contaminants generated by more than 98%, fundamentally reducing the risk of electrode contamination and scrapping.

[0012] Strong process adaptability and compatibility: No need to adjust existing production equipment parameters or add extra cleaning processes. The design of the connecting strip does not affect the performance of the effective area of ​​the indium gallium arsenide detector and can be directly adapted to the existing Ti / Pt / Au multilayer metal stripping process.

[0013] Wide applicability: The parameters of the connecting strips can be flexibly adjusted according to the electrode size (micrometer to submicrometer) and small area pattern distribution of different specifications of indium gallium arsenide detectors, making it suitable for the production of detectors in multiple fields such as optical communication and spectral detection. Attached Figure Description

[0014] Figure 1 This is a design drawing for overlaying alignment marks on a traditional lithography pattern. In the drawing: 1-Clear area is the area where photoresist remains after photolithography (negative photoresist), used for overlaying the alignment mark of the previous photolithography layer; 2-Dark area is the part where the photoresist is developed away after photolithography (negative photoresist); 3-Clear area is the area where photoresist remains after photolithography (negative photoresist), used for overlaying the alignment mark of the first photolithography layer. Figure 2 This is a design diagram of the overlay marking in the layout of the present invention. In the diagram: 2-1 and 2-3 are clear areas, which are the areas where photoresist is left after photolithography (negative photoresist), used to overlay the alignment marks of the previous and first photolithography steps; 2-2 is a dark area, which is the part where the photoresist is developed away after photolithography (negative photoresist); 2-4 is the design of the connecting strip in the present invention. Figure 3 The image shows a magnified view of the connecting strip. In the image: 3-1 is the Clear region, which is the area where photoresist remains after photolithography (negative resist); 3-2 is the Dark region, which is the part where the photoresist is developed away after photolithography (negative resist); 3-3 is the connecting strip, with a width of 4µm. Figure 4 This is a mirror image of the overlay marks in the photomask; in the image: 4-1 is the Clear region, which is the area where photoresist remains after photolithography (negative photoresist); used for overlaying the alignment marks of the previous photolithography layer; 4-2 is the Dark region, which is the part where the photoresist is developed away after photolithography (negative photoresist); 4-3 is the Clear region, which is the area where photoresist remains after photolithography (negative photoresist), used for overlaying the alignment marks of the first photolithography layer; Figure 5 The diagram shows the fabrication results of a traditional layout without connecting strips; in the diagram: 5-1 is the normal detector P electrode; 5-2 is the SiN region; 5-3 is the abnormal detector P electrode that was removed by the markings during the metal stripping process; Figure 6 The diagram shows the fabrication results of the layout design for this invention. In the diagram: 6-1 is the normal detector P electrode; 6-2 is the SiN region. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains, and all materials publicly cited herein and cited by them are incorporated herein by reference.

[0017] Equivalent technologies of the specific embodiments described herein that are apparent to those skilled in the art through routine experimentation are included in this application.

[0018] Unless otherwise specified, the experimental methods used in the following examples are conventional methods. Unless otherwise specified, the instruments and equipment used in the following examples are all standard laboratory instruments and equipment; unless otherwise specified, the experimental materials used in the following examples were all purchased from regular biochemical reagent stores.

[0019] The layout design of this invention will be described using an overlay mark (a small closed pattern) as an example.

[0020] Traditional map overlay design, such as Figure 1 As shown, the graphic area is defined as Dark Area 2. Negative photoresist is used in the photolithography process, meaning the graphic area is the part that dissolves in the developer, while the blank areas, namely Clear Areas 1 and 3, are the parts where photoresist remains after development. It can be seen that in traditional layout design, each part of the overlay is an independent, small-area closed pattern, such as... Figure 6 As shown, a large number of small-area suspended contaminants are formed during the stripping process after metal evaporation. These small-area suspended contaminants will randomly fall and adhere to the chip surface during the subsequent transfer, cleaning and drying processes, which is an important source of electrode contamination.

[0021] The overlay marking design of the layout in this invention is as follows: Figure 2 As shown, the independent closed small-area patterns are connected together by connecting strips 2-4 to form new overlay marks. Similarly, the graphic area in the layout is defined as Dark area 2-2. Negative photoresist is used in the photolithography process, meaning the graphic area is the part dissolved in the developer, while the blank areas, namely Clear areas 2-1 and 2-3, are the parts where photoresist remains after development. In the layout design of this invention, the photoresist under the overlay marks and the surrounding large-area photoresist form a connected pattern. In the stripping process after metal evaporation, the photoresist at the bottom of the metal is dissolved by acetone. The small-area overlay marks are stripped off along with the surrounding large-area metal film due to the pull of the connecting strips. The acetone solution only contains the successfully stripped large-area metal film, and there are no more small-area metal suspended contaminants. This solves the problem of contaminant generation at its source and eliminates the possibility of electrode contamination by small-area metal suspended matter.

[0022] Dimensional tolerances and process adaptation design: Based on the micro / nano electrode requirements of the indium gallium arsenide infrared detector, the linewidth tolerance of the layout pattern (connecting strips) is controlled within ±0.5µm. Combined with the 1µm photolithography resolution of the metal lift-off process, the minimum pattern spacing is designed to be 5µm. To address the stress characteristics of the Ti / Pt / Au multilayer metal film, periodic stress relief notches are set along the long axis of the electrode pattern.

[0023] Layout verification and correction process: After the layout is drawn, the wafer fabrication verification is carried out. The stripping effect after metal evaporation is observed by microscopic inspection. If the metal residue rate exceeds 1%, the stripping integrity is less than 98%, or the residual electrode adhesion probability exceeds 0.5%, the inverted trapezoid slope ratio and the width of the connecting strip are adjusted until the process requirements are met.

[0024] The specific embodiments of this invention are not limited to the following parameters, and can be flexibly adjusted according to different specifications of indium gallium arsenide infrared detectors. This invention will take the metal stripping process of a 640×512 indium gallium arsenide infrared detector as an example, focusing on small-area overlay markings. The specific method is as follows: (1) Layout design: Use software to draw a mask, and design the connecting strips between the small closed area pattern to be peeled off and the large area pattern to be peeled off without affecting the performance of the detector's effective area and the overlay function. For example Figure 2 As shown, a connecting strip 3-3 is designed in the center of the two rows of nested marks, as follows. Figure 3 As shown, the width of the connecting strip is 4µm, and the connecting strip connects the five small closed patterns to be peeled off (with markings and digital version numbers) with the large surrounding area to be peeled off.

[0025] (2) Plate making and test film production: Remake the mask according to the layout design drawing, and make the markings in the mask as follows: Figure 4 As shown, the wafer fabrication process was carried out without changing other production process conditions such as photolithography parameters, vapor deposition parameters, and stripping parameters.

[0026] Comparison of metal stripping effects: In traditional layout design and production with no connecting strips for overlay markings, after metal evaporation and stripping, a large number of small closed patterns are randomly attached to various areas of the chip. Because the size of the overlay markings is much larger than the single pixel size of the indium gallium arsenide infrared detector, if the overlay markings in the stripping solution fall into the effective electrode area of ​​the detector, it will inevitably cause the detector to be scrapped. Figure 5 As shown, the scrapping of individual detectors due to incomplete removal of small-area closed patterns is too common in production, and no specific images of scrapped images were taken. This image shows the result of multiple attempts to remove the overlay metal film using physical methods after defects were caused by contamination from small-area closed patterns. Although the overlay metal film attached to the detector surface was eventually removed, the metal on top of the pixels in the attached area was also removed. This further demonstrates the significant harm that residue from the removal of small-area closed patterns can cause to detector performance.

[0027] In this invention, the overlay markings in the layout design include connecting strips. During metal stripping, the small-area overlay marking pattern to be stripped is connected to the larger-area pattern to be stripped on the outside by the connecting strips. No small, independent, closed stripping debris is generated in the solution during the stripping process. When the large-sized stripping debris detaches from the substrate, a localized stress field is generated due to interface separation, and its larger surface area creates a stronger surface tension gradient. Because of their small mass and weak adhesion to the substrate, the small-sized stripping debris is carried away along with the connecting strips by the adhesive drag and surface tension pull of the larger-sized stripping debris, achieving zero stripping debris residue on the chip surface. Figure 6 As shown, the detector chip designed using the layout of this invention exhibits a highly effective stripping effect, with no stripping residue remaining on the substrate. This achieves clean stripping of the chip's metal layers, photoresist, and other structures, significantly improving the production yield and stability of the indium gallium arsenide infrared detector chip.

[0028] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A layout connection structure design method for improving the metal lift-off process of indium gallium arsenide detectors, characterized in that: Electrode pattern structure optimization: The electrode edge is optimized by adopting an inverted trapezoidal step-type shape. The ratio of the top width to the bottom width of the electrode pattern is 1:1.2-1.5, forming a gradual slope along the direction perpendicular to the base. The corners of the electrode pattern are rounded. Small-area pattern connectivity design: Small-area closed patterns to be peeled off in the layout are connected to the surrounding large-area patterns to be peeled off by connecting strips with a width of 2-5µm. The inverted trapezoidal slope of the connecting strip is consistent with the electrode pattern, with a top:bottom ratio of 1:1.

4. The connecting strip avoids the effective area of ​​the detector, and the minimum distance between it and the effective electrode is ≥4µm. The number of connecting strips is set according to the distribution density of the smallest area pattern, with every 2-5 small-area closed patterns sharing one connecting strip.

2. The design method according to claim 1, characterized in that: The line width tolerance of the connecting strip is ≤ ±0.5um, and the minimum spacing of the pattern is 5um.

3. The design method according to claim 1, characterized in that: The specific method includes the following steps: (1) Layout design: Draw a mask template and design the connecting strip between the small closed graphic to be peeled and the large graphic to be peeled: design the connecting strip in the center of the two rows of overlay marks. The connecting strip connects the five small closed graphic to be peeled, namely the overlay marks and the digital plate number, with the outer large area to be peeled. (2) Fabrication and trial production: The mask is remade according to the layout design and the wafer is produced without changing other production process conditions such as photolithography process parameters, vapor deposition process parameters, and stripping process parameters.

4. The design method according to claim 3, characterized in that: The width of the connecting strip is 4µm.

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