Integrated passive device and manufacturing method therefor

Abstract

Provided in the present disclosure are an integrated passive device and a manufacturing method therefor. The integrated passive device comprises: a base substrate provided with a first via hole and a second via hole; a first electrically conductive post and a second electrically conductive post located in the first via hole and the second via hole, respectively; a first electrically conductive layer located on one side of the base substrate; a second electrically conductive layer located on the side of the base substrate opposite the first electrically conductive layer, wherein the second electrically conductive layer comprises a first electrically conductive portion and a second electrically conductive portion that are separated from each other, the first electrically conductive portion is electrically connected to the first electrically conductive layer by means of the first electrically conductive post, and the second electrically conductive portion is electrically connected to the first electrically conductive layer by means of the second electrically conductive post; a dielectric layer located on the side of the first electrically conductive portion away from the base substrate; and a third electrically conductive layer located on the side of the dielectric layer away from the base substrate, wherein the first electrically conductive layer comprises a first metal material, at least one of the first electrically conductive portion and the third electrically conductive layer comprises a main body layer and an adhesive layer stacked together, and the main body layer comprises a second metal material different from the first metal material.

Description

Integrated passive devices and their manufacturing methods Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an integrated passive device and a method for manufacturing the same. Background Technology

[0002] The current market demand for miniaturization in electronic products, particularly in end-products such as mobile phones, tablets, and wearable devices, is placing increasingly higher demands on the miniaturization of passive components. Currently, passive components such as capacitors, inductors, and resistors account for approximately 70% of the PCB area. Integrated passive device (IPD) technology can reduce the area of ​​passive components by more than 80%, indicating a promising market prospect. How to enable passive components to meet the ever-increasing demand for miniaturization has become a pressing issue that needs to be addressed. Summary of the Invention

[0003] According to one aspect of this disclosure, an integrated passive device is provided, comprising: a substrate having a first via and a second via disposed therein; a first conductive post and a second conductive post located in the first via and the second via, respectively; a first conductive layer located on one side of the substrate; a second conductive layer located on the side of the substrate opposite to the first conductive layer, the second conductive layer comprising a first conductive portion and a second conductive portion separated from each other, the first conductive portion being electrically connected to the first conductive layer via the first conductive post, and the second conductive portion being electrically connected to the first conductive layer via the second conductive post; a dielectric layer located on the side of the first conductive portion away from the substrate; and a third conductive layer located on the side of the dielectric layer away from the substrate; wherein the first conductive layer comprises a first metal material, and at least one of the first conductive portion and the third conductive layer comprises a stacked body layer and an adhesive layer, the body layer comprising a second metal material different from the first metal material.

[0004] In some embodiments, the integrated passive device further includes a third conductive portion located on the side of the first conductive portion away from the substrate and electrically connected to the first conductive portion.

[0005] The third conductive part includes a first metallic material;

[0006] The projection of the third conductive layer onto the substrate does not overlap with the projections of the dielectric layer and the third conductive layer onto the substrate.

[0007] In some embodiments, the first conductive part is provided with a third through hole, and the third conductive part is electrically connected to the first conductive post through the third through hole in the first conductive part.

[0008] In some embodiments, the second conductive portion comprises a first metallic material.

[0009] In some embodiments, the second conductive portion includes a stacked body layer and an adhesive layer, wherein the body layer of the second conductive portion includes a second metallic material.

[0010] In some embodiments, the integrated passive device further includes a fourth conductive portion, which is located on the side of the second conductive portion away from the substrate and is electrically connected to the second conductive portion.

[0011] The fourth conductive part includes the first metallic material.

[0012] In some embodiments, the second conductive part is provided with a fourth through hole, and the fourth conductive part is electrically connected to the first conductive post through the fourth through hole in the second conductive part.

[0013] In some embodiments, the thickness of the first metal material in the first conductive layer is greater than the thickness of the second metal material in the first conductive portion of the second conductive layer.

[0014] In some embodiments, the second metal material is Al, and the material of the adhesion layer is Ti, TiN, Ta, or TaN.

[0015] In some embodiments, the adhesive layer superimposed on the host layer includes a first adhesive layer and a second adhesive layer, with the host layer located between the first adhesive layer and the second adhesive layer.

[0016] In some embodiments, the main body layer is located in the enclosed space formed by the first adhesive layer and the second adhesive layer.

[0017] In some embodiments, the thickness of the main body layer of the first conductive portion is in the range of 1 μm to 3 μm.

[0018] In some embodiments, the thickness of the adhesive layer of the first conductive portion is in the range of 0.03 μm to 0.05 μm.

[0019] In some embodiments, the second conductive layer further includes a first metallic material.

[0020] In some embodiments, the distance between the projection of the dielectric layer on the substrate and the projection of the first conductor post on the substrate in a direction parallel to the substrate is greater than 5 μm.

[0021] In some embodiments, the integrated passive device further includes a fourth conductive layer, which includes a fifth conductive portion and a sixth conductive portion that are separated from each other. The fifth conductive portion is located on the side of the third conductive layer away from the substrate and is electrically connected to the third conductive layer. The sixth conductive portion is located on the side of the second conductive portion of the second conductive layer away from the substrate and is electrically connected to the second conductive portion.

[0022] In some embodiments, the integrated passive device further includes: a first insulating layer located on the side of the first conductive layer away from the substrate and covering the first conductive layer; and a second insulating layer located between the fourth conductive layer and the second and third conductive layers, wherein the fourth conductive layer penetrates the second insulating layer and is electrically connected to the second and third conductive layers.

[0023] In some embodiments, the integrated passive device further includes: a first conductive bump located on the side of the fifth conductive portion away from the substrate and electrically connected to the fifth conductive portion; and a second conductive bump located on the side of the sixth conductive portion away from the substrate and electrically connected to the fourth conductive portion.

[0024] In some embodiments, the integrated passive device further includes: a third insulating layer located on the side of the fourth conductor layer away from the substrate and covering the fourth conductor layer, wherein the first conductive bump and the second conductive bump penetrate the third insulating layer and are electrically connected to the fifth conductor portion and the sixth conductor portion, respectively.

[0025] In some embodiments, the first metal material is Cu, and the thickness of the first metal material is greater than 2 μm.

[0026] In some embodiments, the integrated passive device further includes a Cu seed layer disposed on the side of the first metal material facing the substrate and a Ti layer disposed on the side of the Cu seed layer facing the substrate.

[0027] In some embodiments, the second conductive layer includes a plurality of second conductive portions separated from each other, the first conductive layer includes a plurality of conductive connection units separated from each other, and the substrate includes a plurality of second vias; the plurality of second conductive portions are electrically connected to the plurality of conductive connection units through the plurality of second vias to form a zigzag winding, and one end of the zigzag winding is electrically connected to the first conductive portion.

[0028] According to another aspect of this disclosure, a method for manufacturing an integrated passive device as described above is also provided, comprising: forming a first blind via and a second blind via on a first side of an initial substrate; filling the first blind via and the second blind via with a conductive material to obtain a first initial conductive post located in the first blind via and a second initial conductive post located in the second blind via; forming a second conductive layer on the first side of the initial substrate, the second conductive layer including a first conductive portion and a second conductive portion electrically connected to the first initial conductive post and the second initial conductive post, respectively; forming a dielectric layer on the side of the first conductive portion away from the initial substrate; forming a third conductive layer on the side of the dielectric layer away from the initial substrate; thinning the initial substrate on a second side of the initial substrate opposite to the first side, such that the conductive material in the first blind via and the second blind via is exposed, to obtain a substrate having a first via and a second via, and a first conductive post and a second conductive post located in the first via and the second via, respectively; forming a first conductive layer comprising a first metal material on a second side of the substrate, such that the first conductive portion is electrically connected to the first conductive layer through the first conductive post, and the second conductive portion is electrically connected to the first conductive layer through the second conductive post.

[0029] In some embodiments, forming the second conductive layer includes: forming a stack of an adhesion material and a second metal material on an initial substrate; and patterning the stack to obtain a first conductive portion and a second conductive portion of the second conductive layer.

[0030] In some embodiments, the method further includes forming a third conductive portion and a fourth conductive portion on the side of the second conductive layer away from the initial substrate, wherein the third conductive portion is electrically connected to the first conductive portion, the fourth conductive portion is electrically connected to the second conductive portion, and the projection of the third conductive portion on the initial substrate does not overlap with the projections of the dielectric layer and the third conductive layer on the initial substrate.

[0031] In some embodiments, the method further includes: forming a third via in the first conductive portion and a fourth via in the second conductive portion before forming the third conductive portion and the fourth conductive portion, wherein the third conductive portion is electrically connected to the first initial conductive post through the third via in the first conductive portion, and the fourth conductive portion is electrically connected to the second conductive post through the fourth via in the second conductive portion.

[0032] In some embodiments, the integrated passive device further includes a third conductive portion, and forming the second conductive layer includes: forming a stack of an adhesion material and a second metal material on an initial substrate; patterning the stack to obtain a first conductive portion of the second conductive layer; depositing a first metal material on one side of the initial substrate where the first conductive portion is provided and patterning the first metal material to obtain a second conductive portion and a third conductive portion of the second conductive layer.

[0033] According to another aspect of this disclosure, an integrated passive device is also provided, comprising an inductor and a capacitor connected in series. The inductor has a first end and a second end, and the capacitor has a first pole and a second pole. The first end of the inductor is connected to the first pole of the capacitor. The inductor includes a portion of a first conductive layer and a second conductive layer, and the capacitor includes another portion of a second conductive layer, a dielectric layer, and a third conductive layer. The integrated passive device further includes a substrate, with the first conductive layer located on one side of the substrate and the second conductive layer located on the side of the substrate opposite to the first conductive layer. The second conductive layer includes a first conductive portion and a second conductive portion separated from each other. The first conductive portion serves as the first pole of the capacitor, the second conductive portion serves as a portion of the inductor, and the third conductive layer serves as the second pole of the capacitor. The first conductive layer includes a first metallic material, and the first pole of the capacitor includes a stacked body layer and an adhesive layer. The body layer includes a second metallic material different from the first metallic material.

[0034] In some embodiments, the integrated passive device further includes a third conductive portion located on the side of the first conductive portion away from the substrate and electrically connected to the first conductive portion, the third conductive portion comprising a first metallic material.

[0035] In some embodiments, the inductor further includes a fourth conductive portion located on the side of the second conductive portion away from the substrate and electrically connected to the second conductive portion, the fourth conductive portion comprising a first metallic material.

[0036] In some embodiments, the integrated passive device further includes a fourth conductive layer located on the side of the second and third conductive layers away from the substrate and electrically connected to the second and third conductive layers; wherein the fourth conductive layer includes a fifth conductive portion and a sixth conductive portion separated from each other, the fifth conductive portion being electrically connected to the second conductive portion of the second conductive layer as part of an inductor, and the sixth conductive portion being electrically connected to the third conductive layer.

[0037] In some embodiments, the integrated passive device further includes: a first pin located on the side of the fifth conductive portion away from the substrate, electrically connected to the second pole of the capacitor via the fifth conductive portion; and a second pin located on the side of the sixth conductive portion away from the substrate, electrically connected to the second terminal of the inductor via the sixth conductive portion. Attached Figure Description

[0038] Figure 1 shows a cross-sectional view of an integrated passive device;

[0039] Figure 2 shows a cross-sectional view of an integrated passive device according to an embodiment of the present disclosure;

[0040] Figures 3A to 3E show cross-sectional views of several examples of a first-layer structure according to embodiments of the present disclosure;

[0041] Figure 4 shows a cross-sectional view of the second layer structure according to an embodiment of the present disclosure;

[0042] Figure 5 shows an equivalent circuit diagram of an integrated passive device according to an embodiment of the present disclosure;

[0043] Figure 6 shows a cross-sectional view of an integrated passive device according to another embodiment of the present disclosure;

[0044] Figure 7 shows a cross-sectional view of an integrated passive device according to another embodiment of the present disclosure;

[0045] Figure 8 shows a cross-sectional view of an integrated passive device according to another embodiment of the present disclosure;

[0046] Figure 9 shows a planar layout diagram of the integrated passive device according to an embodiment of the present disclosure;

[0047] Figures 10A to 10L illustrate the manufacturing process of the integrated passive device of Figure 2;

[0048] Figures 11A to 11M illustrate the manufacturing process of the integrated passive device shown in Figure 6;

[0049] Figures 12A to 12D illustrate the manufacturing process of the integrated passive device in Figure 7;

[0050] Figures 13A to 13D illustrate the manufacturing process of the integrated passive device of 8. Detailed Implementation

[0051] While this disclosure will be fully described with reference to the accompanying drawings containing preferred embodiments, it should be understood before this description that those skilled in the art can modify the disclosure described herein to obtain the technical effects of this disclosure. Therefore, it should be understood that the above description is a broad disclosure to those skilled in the art and is not intended to limit the exemplary embodiments described herein.

[0052] Furthermore, in the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments disclosed herein. However, it will be apparent that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and apparatuses are illustrated to simplify the figures.

[0053] Based on different substrates, integrated passive device technologies can be categorized into silicon-based, LTCC-based, and glass-based technologies. With the development of communication technology, the frequencies used in mobile communication are increasing, from several hundred megahertz in 2G technology to 3.5 GHz and millimeter waves in 5G technology. As a major power-consuming component in electronic products, the radio frequency front-end requires significantly reduced electromagnetic losses. Due to the inherent material advantages of glass substrates, glass-based integrated passive devices have gradually become the mainstream approach.

[0054] Taking a second-order LC filter as an example, the key parameters are the cutoff frequency f and the quality factor Q. The capacitance C and inductance L of the device determine its operating frequency. The Q factor of an ideal series RLC circuit is:

[0055] R, L, and C represent the circuit's resistance, inductance, and capacitance, respectively. The larger the resistance value, the smaller the Q factor and the wider the operating bandwidth, making it unsuitable for 5G-related bands.

[0056] LTCC (Low Temperature Co-fired Ceramic) passive devices use laminated green ceramic tape to form the dielectric layer, which is a thick-film process. The process often requires high-temperature sintering below 1000℃. Due to the shrinkage issues during high-temperature sintering, the requirements for ceramic materials and sintering processes are extremely stringent. The traces are formed using printed metal paste, with conventional linewidths exceeding 75μm, making finer lines impossible. The ceramic layer serves as the capacitor dielectric layer, with a thickness ranging from 10μm to 100μm. Based on the capacitance calculation formula, taking a relative permittivity of 7 for ceramic and a thickness of 10μm as an example, to achieve a capacitance of 1nF, a total electrode area of ​​160mm² is required. 2 To achieve a small size, it is often necessary to stack multiple capacitor layers, which leads to an increase in device thickness and size.

[0057] Fabrication of 3D glass-based integrated LC filters utilizes thin-film technology. Photolithography can achieve linewidths exceeding 3μm, while the thickness of each film layer is significantly thinner than that of LTCC devices. Taking SiNx as the capacitor dielectric layer, with a thickness of 120nm and a relative permittivity of 7, as an example, forming a 1nF capacitor requires only a 2mm² area. 2 Compared to LTCC, it is easier to miniaturize the device. At the same time, due to the reduction in the number of film layers, the alignment accuracy between the layers of the glass-based IPD is higher, resulting in higher precision in its use.

[0058] Figure 1 shows a cross-sectional view of an integrated passive device.

[0059] As shown in Figure 1, the integrated passive device includes an inductor L and a capacitor C. The inductor includes multiple conductive layers M located on both sides of a glass substrate 110, and the conductive layers are connected by vias. The capacitor C includes a first electrode P1, a second electrode P2 located on one side of the glass substrate 110, and a dielectric layer located between the first electrode P1 and the second electrode P2. The inductor L and the capacitor C are electrically connected through vias in the glass substrate 110. In the example of Figure 1, Cu is used as the conductive body for each conductive layer M and the electrode of the capacitor C. When this 3D integrated passive device (IPD) with Cu as the capacitor electrode operates in a high-power, high-temperature environment, the Cu thin film is subjected to compressive stress from the substrate due to the difference in thermal expansion coefficients between the glass substrate and Cu. Under the action of compressive stress, Cu grains on the surface of the thin film will bulge out. At the same time, the high temperature of the process and the operating environment will cause the Cu grain size to increase. The protrusion of larger Cu grains will cause the dielectric layer E of the capacitor C to crack, resulting in a short circuit in the capacitor C, thereby causing device failure.

[0060] Figure 2 shows a cross-sectional view of an integrated passive device according to another embodiment of the present disclosure.

[0061] As shown in Figure 2, the integrated passive device includes a substrate, a first conductive pillar, a second conductive pillar, a first conductive layer, a second conductive layer, a dielectric layer, and a third conductive layer.

[0062] As shown in Figure 2, the substrate 110 has multiple vias, such as a first via Va and a second via Vb, and multiple conductive pillars 130 are respectively located in each via, for example, the first conductive pillar 130_a and the second conductive pillar 130_b are respectively located in the first via Va and the second via Vb. According to an embodiment of this disclosure, the substrate 110 can be a glass substrate, and the first via Va and the second via Vb can be through-glass vias (TGV).

[0063] The first conductive layer 120 is located on one side of the substrate 110, and the second conductive layer 140 is located on the side of the substrate 110 opposite to the first conductive layer 120.

[0064] The second conductive layer 140 includes a first conductive portion 140_a and a second conductive portion 140_b that are separated from each other. The first conductive portion 140_a is electrically connected to the first conductive layer 120 through a first conductive post 130_a, and the second conductive portion 140_b is electrically connected to the first conductive layer 120 through a second conductive post 130_b.

[0065] The dielectric layer 150 is located on the side of the first conductive portion 140_a away from the substrate 110. The material of the dielectric layer 150 includes, but is not limited to, SiN. XThe thickness of the dielectric layer 150 can be in the range of 100 nm to 120 nm. In some embodiments, as shown in FIG2, the distance D between the projection of the dielectric layer 150 on the substrate 110 and the projection of the first conductor pillar on the substrate 110 in a direction parallel to the substrate 110 is greater than 5 μm. In this way, the coupling between the 3D inductor L and the planar capacitor C (especially the second electrode 160 of the capacitor) can be reduced.

[0066] The third conductive layer 160 is located on the side of the dielectric layer 150 away from the substrate 110.

[0067] According to embodiments of this disclosure, the integrated passive device can be an integrated LC device, including an inductor L and a capacitor C fabricated on a substrate 110. The inductor can be a 3D wire-wound structure formed by multiple conductive layers, and the capacitor can adopt a MIM (Metal-Insulator-Metal) structure, including upper and lower metal electrodes and an intermediate dielectric layer 150. According to embodiments of this disclosure, the inductor L may include a first conductive layer 120, a portion of a second conductive layer 140 (e.g., a second conductive portion 140_b), and a second conductive post 130_b, and the capacitor C may include another portion of the second conductive layer 140 (e.g., a first conductive portion 140_a), a dielectric layer 150, and a third conductive layer 160. As an example, the second conductive portion 140_b of the second conductive layer 140 serves as the first electrode of the capacitor, and the third conductive layer 160 serves as the second electrode of the capacitor.

[0068] According to embodiments of this disclosure, the first conductive layer 120 includes a first metal material, and at least one of the first conductive portion 140_a and the third conductive layer 160 includes a stacked main layer and an adhesive layer. The main layer includes a second metal material different from the first metal material. For example, the first metal material may be Cu, the second metal material may be Al, and the material of the adhesive layer may be Ti, TiN, Ta, or TaN. In some embodiments, the thickness of the first metal material in the first conductive layer 120 is greater than the thickness of the second metal material in the second conductive layer 140. For example, the thickness of the first metal material in the first conductive layer 120 may be in the range of 2 μm to 4 μm, and the thickness of the second metal material in the second conductive layer 140 may be in the range of 1 μm to 3 μm.

[0069] In some embodiments, at least one of the first conductive portion 140_a and the third conductive layer 160 adopts a first layer structure, and the first conductor layer adopts a second layer structure different from the first layer structure. The first layer structure will be described below with reference to FIGS. 3A to 3E, and the second layer structure will be described with reference to FIG. 4.

[0070] In Figure 3A, the first layer structure includes a main layer M1 and an adhesive layer T1, with the adhesive layer T1 located on the side of the main layer M1 closest to the substrate 110. However, the embodiments of this disclosure are not limited to this, and the adhesive layer T1 may also be located on the side of the main layer M1 furthest from the substrate 110. The material of the main layer M1 may be Al, and the material of the adhesive layer may be Ti, TiN, Ta, or TaN.

[0071] In Figure 3B, similar to Figure 3A, the first layer structure also includes a main layer M1 and an adhesive layer. Unlike Figure 3A, the adhesive layer includes a first adhesive layer T1 and a second adhesive layer T2, with the main layer located between the first adhesive layer T1 and the second adhesive layer T2. The material of the main layer M1 can be Al, and the materials of the first adhesive layer T1 and the second adhesive layer T2 can be Ti, TiN, Ta, or TaN.

[0072] In Figure 3C, similar to Figure 3B, the first layer structure also includes a first adhesion layer T1, a second adhesion layer T2, and a main layer M1 located between the first and second adhesion layers. Unlike Figure 3B, the main layer M1 is located within the enclosed space formed by the first and second adhesion layers T1 and T2. As shown in Figure 3C, the main layer M1 is located on the side of the first adhesion layer T1 away from the substrate 110 (top in the figure), and the second adhesion layer T2 completely covers the main layer M1. At the edge of the main layer M1, the second adhesion layer T2 forms a stepped structure. Similarly, the material of the main layer M1 can be Al, and the materials of the first adhesion layer T1 and the second adhesion layer T2 can be Ti, TiN, Ta, or TaN. Due to the different etching rates of different metals, the sidewalls of each layer can easily shrink to varying degrees, causing protrusions or depressions on the sidewalls of the stacked layers, affecting the critical dimension (CD) of the device, also known as CD accuracy. The embodiments of this disclosure employ an adhesive layer design, as shown in FIG3C, to surround the main body layer with one of the second conductive portion 140_b and the third conductive layer 160. This design causes the main body layer to be recessed relative to the adhesive layers on both sides, and the edges of the main body layer are wrapped with upper and lower adhesive layer materials. This achieves control over the CD tolerance of the capacitor's electrodes (e.g., the upper second electrode, also called the upper electrode), thereby improving capacitor uniformity.

[0073] According to embodiments of this disclosure, at least one of the first electrode (second conductive portion 140_b) and the second electrode (third conductive layer 160) of capacitor C can be implemented as an X / M / X (Figures 3B and 3C) or X / M (Figure 3A) structure, where M represents the material of the main layer, i.e., the second metal material, and M can be Al; X represents the material of the adhesion layer, and X can be Ti, TiN, Ta, TaN, etc. As an example, the second conductive portion 140_b can be implemented as an X / Al / X or X / Al structure, and the third conductive layer 160 can be implemented as an X / Cu or X / Cu / X structure, i.e., the main layer is Cu, and the adhesion layer is X. The X / Al / X or X / Al structure can be fabricated by dry etching, wherein the X / Al structure can prevent the intermediate Al layer from shrinking during the etching process, further improving the CD accuracy of the upper electrode of the capacitor, thereby improving the consistency of device performance. The X / Cu or X / Cu / X structure can be fabricated by wet etching, and the CD accuracy is lower than that of the X / Al / X or X / Al structure.

[0074] In some embodiments, the first layer structure may include a first metal material in addition to a second metal material. For example, there may be multiple main body layers, and each main body layer may be made of a first metal material and a second metal material. As shown in FIG3D, unlike FIG3A to FIG3C, the main body layer includes a first main body layer M1_1, a first main body layer M1_2, and a first main body layer M1_3. The first main body layer M1_3 is located between the first main body layer M1_1 and the first main body layer M1_2, the first adhesive layer T1 is located between the first main body layer M1_1 and the first main body layer M1_3, and the second adhesive layer T2 is located between the first main body layer M1_2 and the first main body layer M1_3. The first main body layer M1_1 may be made of a first metal material (e.g., Cu), and the first main body layers M1_2 and M1_3 may be made of a second metal material (e.g., Al). In this way, the first layer structure can be realized as a stacked structure of a first metal material and a second metal material. Taking the second conductive layer as an example, the first conductive part 140_a of the second conductive layer can adopt the structure described above with reference to FIG3D, which includes both the first metal material and the second metal material.

[0075] Figure 3E is similar to Figure 3D, except that the first material's main layer is surrounded by the second material's main layer. As shown in Figure 3E, the first main layer M1_3 and its two sides, the first adhesive layer T1 and the second adhesive layer T2, are located in the closed space formed by the first main layer M1_1 and the first main layer M1_2. In the example of Figure 3E, the stacked structure of the first adhesive layer T1, the first main layer M1_3, and the second adhesive layer T2 is located on one side of the first main layer M1_1 and is covered by the first main layer M1_2.

[0076] Referring back to FIG2, the first layer structure of any embodiment described above with reference to FIGS. 3A to 3E is also applicable to the second conductive portion 140_b. In some embodiments, the second conductive portion 140_b and the first conductive portion 140_a may employ the same layer structure, so that they can be formed in a single process. For example, an adhesive material and a second metal material and / or a first metal material are formed into a stack, and then the stack is patterned to obtain the first conductive portion 140_a and the second conductive portion 140_b.

[0077] In the various embodiments described above with reference to Figures 3A to 3E, the thicknesses of the main layer and the adhesive layer are set as needed. For example, when the second conductive layer 140 adopts the first layer structure described above, the thickness of the second metal material (e.g., Al) serving as the main layer M1 is in the range of 1 μm to 3 μm, and the thicknesses of the first adhesive layer T1 and the second adhesive layer T2 are in the range of 0.03 μm to 0.05 μm. When the third conductive layer 160 adopts the first layer structure described above, the thickness of the main layer M1 of the third conductive layer 160 can be in the range of 0.2 μm to 0.5 μm, the thickness of the first adhesive layer T1 located below the main layer M1 is in the range of 0.03 μm to 0.05 μm, and the thickness of the second adhesive layer T2 located above the main layer M1 can be in the range of 0.02 μm to 0.05 μm.

[0078] The second layer structure will now be described with reference to FIG. 4. As shown in FIG. 4, the second layer structure may include a first metal material layer M2. The first metal material may be Cu. In some embodiments, the second layer structure may further include a third adhesion layer T3 and a seed layer Sd. The seed layer Sd is disposed on the side of the first metal material layer M2 facing the substrate 110, and the third adhesion layer T3 is disposed on the side of the seed layer Sd facing the substrate 110. The seed layer may be Cu. The material of the adhesion layer may be Ti. In some embodiments, the first conductive pillar 130_a and the second conductive pillar 130_b may also adopt the above-described second layer structure, and the thickness of the conductive pillar layer M2 may be determined by the height of the conductive pillar.

[0079] Referring back to FIG2, in some embodiments, the integrated passive device may further include a fourth conductive layer 170. The fourth conductive layer 170 includes a fifth conductive portion 170_a and a sixth conductive portion 170_b, which are separated from each other. The fifth conductive portion 170_a is located on the side of the third conductive layer 160 away from the substrate 110 and is electrically connected to the third conductive layer 160. The sixth conductive portion 170_b is located on the side of the second conductive portion 140_b of the second conductive layer 140 away from the substrate 110 and is electrically connected to the second conductive portion 140_b. In some embodiments, the fourth conductive layer 170 may also have a second layer structure. In this case, the inductor L may include the sixth conductive portion 170_b in the fourth conductive layer 170, in addition to the first conductive layer 120, the second conductive portion 140_b in the second conductive layer 140, and the second conductive post 130_b.

[0080] Similarly, in the second layer structure described above with reference to FIG4, the thickness of each layer can be set as needed. For example, the thickness of the first metal material layer M2 in the first conductive layer 120 can be greater than 5 μm, the thickness of the first metal material layer M2 in the third conductor portion and the fourth conductor portion can be in the range of 2 μm to 4 μm, and the thickness of the first metal material layer M2 in the fourth conductive layer 170 can be 5 μm to 10 μm.

[0081] In some embodiments, the integrated passive device may further include at least one of a first insulating layer 181 and a second insulating layer 182. As shown in FIG2, the first insulating layer 181 is located on the side of the first conductive layer 120 away from the substrate 110 and covers the first conductive layer 120. The second insulating layer 182 is located between the fourth conductive layer 170 and the second conductive layer 140 and the third conductive layer 160, and the fourth conductive layer 170 penetrates the second insulating layer 182 and is electrically connected to the second conductive layer 140 and the third conductive layer 160.

[0082] In some embodiments, the integrated passive device may further include a first conductive bump Bm1 and a second conductive bump Bm2. The first conductive bump Bm1 is located on the side of the fifth conductive portion 170_a away from the substrate 110 and is electrically connected to the fifth conductive portion 170_a. The second conductive bump Bm2 is located on the side of the sixth conductive portion 170_b away from the substrate 110 and is electrically connected to the fourth conductive portion. The first conductive bump Bm1 and the second conductive bump Bm2 may include a connection layer S1 and a solder layer S2. The connection layer S1 is electrically connected to the underlying fourth conductive layer 170, and the solder layer S2 is located on the side of the connection layer S1 away from the substrate 110. The connection layer S1 may adopt the second layer structure described above. The solder layer S2 may be implemented in the form of a solder ball. The first conductive bump Bm1 and the second conductive bump Bm2 are exposed from the integrated passive device, thereby serving as pins of the integrated passive device for connection with other components. In some embodiments, the first conductive bump Bm1 and the second conductive bump Bm2 may respectively serve as the first pin and the second pin of the integrated passive device. The second electrode (third conductive layer 160) of capacitor C is led out through the first conductive bump Bm1, and the second end (sixth conductive part 170_b) of inductor L is led out through the second pin Bm2.

[0083] In some embodiments, the integrated passive device may further include a third insulating layer 183. The third insulating layer 183 is located on the side of the fourth conductive layer 170 away from the substrate 110 and covers the fourth conductive layer 170. The first conductive bump Bm1 and the second conductive bump Bm2 penetrate the third insulating layer 183 and are electrically connected to the fifth conductive portion 170_a and the sixth conductive portion 170_b, respectively.

[0084] In embodiments of this disclosure, by including a first conductive layer 120 as a first metal material, and at least one of the first conductive portion 140_a and the third conductive layer 160 as a stacked host layer and an adhesive layer, wherein the host layer includes a second metal material different from the first metal material, the breakdown characteristics and high-temperature reliability of the capacitor can be improved, and the metal expansion effect can be mitigated. Embodiments of this disclosure use Al as the second metal material. Compared to conventional metal materials such as Cu grains (approximately 10 μm), Al grains are smaller (<1 μm) and more stable at high temperatures. Furthermore, using Ti, TiN, Ta, or TaN, which have higher hardness, as the adhesive layer further restricts the metal grain expansion effect.

[0085] Figure 5 shows an equivalent circuit diagram of an integrated passive device according to an embodiment of the present disclosure. The equivalent circuit of Figure 5 is applicable to integrated passive devices in any embodiment of the present disclosure. For ease of description, the integrated passive device of Figure 2 will be used as an example for illustration below.

[0086] As shown in Figure 5, the integrated passive device includes an inductor L and a capacitor C connected in series. The inductor L has a first end and a second end, and the capacitor C has a first pole and a second pole. The first end of the inductor L and the first pole of the capacitor C are connected at node N.

[0087] Referring to Figures 2 and 5, the inductor L includes a first conductive layer 120 and a portion of a second conductive layer 140, and the capacitor C includes another portion of the second conductive layer 140, a dielectric layer 150, and a third conductive layer 160. The first conductive layer 120 is located on one side of the substrate 110, and the second conductive layer 140 is located on the side of the substrate 110 opposite to the first conductive layer 120. The second conductive layer 140 includes a first conductive portion 140_a and a second conductive portion 140_b, which are separated from each other. The first conductive portion 140_a serves as the first electrode of the capacitor C, the second conductive portion 140_b serves as a portion of the inductor L, and the third conductive layer 160 serves as the second electrode of the capacitor C.

[0088] The first conductive layer 120 may adopt a first layer structure, as described above with reference to FIG4, and may include a first metal material. At least one of the first electrode (first conductive portion 140_a) and the second electrode (third conductive layer 160) of the capacitor C may adopt a second layer structure, as described above with reference to FIGS. 3A to 3E, including a stacked main body layer and an adhesive layer, wherein the main body layer includes a second metal material different from the first metal material.

[0089] As shown in Figure 5, the integrated passive device may also include a first pin Pin1 and a second pin Pin2. The second terminal of capacitor C is connected to the first pin Pin1 of the integrated passive device, and the second terminal of inductor C is connected to the second pin Pin2 of the integrated passive device. Referring to Figure 2, the first pin Pin1 can be implemented as the first conductive bump Bm1 mentioned above, and the second pin Pin2 can be implemented as the second conductive bump Bm2 mentioned above.

[0090] In some embodiments, referring to Figures 2 and 5, the integrated passive device may further include a fourth conductive layer 170. The fourth conductive layer 170 is located on the side of the second conductive layer 140 and the third conductive layer 160 away from the substrate 110, and is electrically connected to the second conductive layer 140 and the third conductive layer 160. The fourth conductive layer 170 includes a fifth conductive portion 170_a and a sixth conductive portion 170_b separated from each other. The fifth conductive portion 170_a is electrically connected to the second conductive portion 140_b of the second conductive layer 140 as part of an inductor, and the sixth conductive portion 170_b is electrically connected to the third conductive layer 160. A first pin (first conductive bump Bm1) is located on the side of the fifth conductive portion 170_a away from the substrate 110, and is electrically connected to the second terminal (140_b) of the capacitor via the fifth conductive portion 170_a. A second pin (second conductive bump Bm2) is located on the side of the sixth conductive portion 170_b away from the substrate 110, and is electrically connected to the second end (140_b) of the inductor L via the sixth conductive portion 170_b.

[0091] Figure 6 shows a cross-sectional view of an integrated passive device according to another embodiment of the present disclosure. The integrated passive device of Figure 6 is similar to that of Figure 2, except that the integrated passive device further includes a third conductive portion and a fourth conductive portion. For the sake of simplicity, the differences will be described in detail below, mainly focusing on the differences.

[0092] As shown in Figure 6, in addition to the substrate 110, the first conductive post 130_a, the second conductive post 130_b, the first conductive layer 120, the second conductive layer 140, and the third conductive layer 160, the integrated passive device may also include at least one of the third conductive portion 190_a and the fourth conductive portion 190_b.

[0093] The third conductive portion 190_a is located on the side of the first conductive portion 140_a away from the substrate 110, and is electrically connected to the first conductive portion 140_a. The projection of the third conductive portion 190_a on the substrate 110 does not overlap with the projections of the dielectric layer 150 and the third conductive layer 160 on the substrate 110.

[0094] The fourth conductive part 190_b is located on the side of the second conductive part 140_b away from the substrate 110, and is electrically connected to the second conductive part 140_b.

[0095] The third conductive portion 190_a, the fourth conductive portion 190_b, and the third conductive layer 160 are covered by the second insulating layer 182. The fourth conductive layer 170 is electrically connected to the fourth conductive portion 190_a and the third conductive layer 160 through a via in the second insulating layer 182.

[0096] The third conductive part 190_a and the fourth conductive part 190_b can adopt the second layer structure mentioned above, that is, including the first metal material. For a description of the second layer structure, please refer to the above, and it will not be repeated here.

[0097] Because the resistivity of Al (2.7 × 10⁻⁸ Ω·m) is greater than that of Cu (1.7 × 10⁻⁸ Ω·m), when one of the second conductive portion 140_b and the third conductive layer 160 adopts an X / Al / X or X / Al structure, Al will generate more device losses compared to Cu. Embodiments of this disclosure provide at least one of the third conductive portion 190_a and the fourth conductive portion 190_b, enabling a stacked structure of a first metal material, a second metal material, and an adhesive material, such as an Al / X / Cu composite film, in the non-capacitive region. This improves the conductivity of the traces and reduces device losses. This structural arrangement enhances device reliability, reduces Cu bulging, and keeps device losses at an acceptable level.

[0098] Figure 7 shows a cross-sectional view of an integrated passive device according to another embodiment of the present disclosure. The integrated passive device of Figure 7 is similar to that of Figure 6, except that at least one via is provided in both the first conductive portion 140'_a and the second conductive portion 140'_b. For the sake of simplicity, the differences will be described in detail below.

[0099] As shown in Figure 7, similar to Figure 6, the integrated passive device also includes a substrate 110, a first conductive layer 120, a second conductive layer 140, a third conductive layer 160, and a third conductive portion 190'_a and a fourth conductive portion 190'_b. Unlike Figure 6, the first conductive portion 140'_a has a third via Via3, and the second conductive portion 140'_b has a fourth via Via4. The third conductive portion 190'_a is electrically connected to the first conductive post 130_a through the third via Via3 in the first conductive portion 140'_a, and the fourth conductive portion 190'_b is electrically connected to the first conductive post 130_a through the fourth via Via4 in the second conductive portion 140'_b. In some embodiments, the diameters of the third via Via3 and the fourth via Via4 can be larger than the diameters of the first via Va and the second via Vb in the substrate 110.

[0100] By providing vias Via3 and Via4 in the first conductive portion 140'_a and the second conductive portion 140'_b, the third conductive portion 190'_a and the fourth conductive portion 190'_b can contact the conductive posts 130_a and 130_b below through the vias, thereby reducing the interface resistance between the third conductive portion 190'_a and the fourth conductive portion 190'_b and the conductive posts 130_a and 130_b, enhancing the conductivity between them, and reducing device losses.

[0101] Figure 8 shows a cross-sectional view of an integrated passive device according to another embodiment of the present disclosure. The integrated passive device of Figure 7 is similar to that of Figure 6, except that it lacks a third conductive portion, and the second conductive portion 140”_b adopts a different structure. For the sake of simplicity, the differences will be described in detail below.

[0102] As shown in Figure 8, similar to Figure 6, the integrated passive device also includes a substrate 110, a first conductive layer 120, a second conductive layer 140, a third conductive layer 160, and a fourth conductive portion. Unlike Figure 6, the second conductive portion 140"_b in Figure 6 is replaced by the third conductive portion 190_b. As shown in Figure 8, the second conductive portion 140"_b can adopt the second layer structure described above with reference to Figure 4, instead of the first layer structure. Referring to Figure 4, the second conductive portion 140"_b may include a layer M1 of a first metal material, such as Cu. In some embodiments, the second conductive portion 140"_b may further include a seed layer Sd and an adhesion layer T3 disposed on the side of the first metal material layer M1 facing the substrate 110.

[0103] As mentioned above, since Al has a higher resistivity than Cu, when one of the second conductive portion and the third conductive layer adopts an X / Al / X or X / Al structure, Al will generate more device losses compared to Cu. The embodiments of this disclosure replace the stack of the first-layer structure's second conductive portion and the second-layer structure's third conductive portion with a second conductive portion 140"_b having a second-layer structure in the inductor region, and use a stack of the first conductive portion 140_a and the third conductive portion 190_a in the inductor-capacitor connection region. This allows the inductor traces to use a single second-layer structure design (e.g., Cu), while the inductor-capacitor connection region uses a composite film design of the second-layer structure (e.g., Cu) and the first-layer structure (e.g., X / Al / X or X / Al). In this way, it is also possible to improve metal bulging in the capacitor region while ensuring that device losses are not reduced.

[0104] In some embodiments, the second conductive layer may include a plurality of second conductive portions that are separated from each other, and the first conductive layer may include a plurality of conductive connection units that are separated from each other. The plurality of second conductive portions are electrically connected to the plurality of conductive connection units to form an inductor, which will be described in detail below with reference to Figures 9A to 9E.

[0105] Figures 9A to 9E show planar layout diagrams of integrated passive devices according to embodiments of the present disclosure. Figures 9A to 9D show planar layout diagrams of each layer of the integrated passive device, and Figure 9E shows a planar layout diagram after the layers are stacked. The planar layouts shown in Figures 9A to 9E are applicable to any of the embodiments described above with reference to Figures 2 to 8, and the cross-sectional views of Figures 2 to 8 may be taken along the dashed line shown in Figure 9E. For ease of description, the planar layouts shown in Figures 9A to 9E will be illustrated using the structure of Figure 2 as an example.

[0106] As shown in Figures 9A to 9E, the second conductive layer 140 may include a first conductive portion 140_a and a plurality of second conductive portions 140_b1, 140_b2, and 140_b3 that are separated from each other. The first conductive layer 120 includes a plurality of conductive connection units 120_1, 120_2, and 120_3 that are separated from each other. The substrate 110 includes a first via Va and a plurality of second vias Vb11, Vb12, Vb21, Vb22, and Vb3.

[0107] Multiple second conductive parts 140_b1, 140_b2, and 140_b3 are electrically connected to multiple conductive connection units 120_1, 120_2, and 120_3 through multiple second vias Vb11, Vb12, Vb21, Vb22, and Vb3, forming a zigzag-shaped winding. As shown in Figures 9A to 9E, conductive connection unit 120_1 electrically connects the first conductive part 140_a and the second conductive part 140_b1 through the first via Va and the second via Vb11; conductive connection unit 120_2 electrically connects the second conductive parts 140_b1 and 140_b2 through the second vias Vb12 and Vb21; and conductive connection unit 120_3 electrically connects the second conductive parts 140_b2 and 140_b3 through the second vias Vb22 and Vb3. Thus, the second conductive portions 140_b1, 140_b2, and 140_b3 of the second conductive layer and the conductive connection units 120_1, 120_2, and 120_3 of the first conductive layer form a zigzag 3D winding structure as shown in Figure 9E, thereby realizing inductor winding. One end of the zigzag winding is electrically connected to the first conductive portion 140_a, thereby realizing the connection between the inductor and the capacitor. The first conductive portion 140_a is electrically connected to the first conductive bump Bm1, and the second conductive connection portion 140_b3 at the end of the winding is electrically connected to the second conductive bump Bm2, thereby leading out the second terminal of the capacitor and the second end of the inductor through a lead in the form of a conductive bump.

[0108] In the examples shown in Figures 9A to 9E, the first conductive portion 140_a and the second conductive portions 140_b1, 140_b2, and 140_b3 of the second conductive layer extend along a first direction, and the conductive connecting units 120_1, 120_2, and 120_3 of the first conductive layer extend along a second direction different from the first direction, thereby forming a zigzag-shaped winding structure. However, the embodiments of this disclosure are not limited to this; the second conductive layer and the first conductive layer can adopt other planar layouts as needed, as long as they can be connected to form an inductor winding structure.

[0109] In some embodiments, the integrated passive device may further include a fourth conductive layer 170, the planar layout of which is similar to that of the second conductive layer 140, as shown in Figures 9A to 9E. The fourth conductive layer may include a fifth conductive portion 170_a and a plurality of sixth conductive portions 190_b1, 190_b2, and 190_b3, which have substantially the same planar layout as the first conductive portion 140_a and the plurality of separate second conductive portions 140_b1, 140_b2, and 140_b3. Unlike the second conductive layer, the size of the fifth conductive connection portion 170_a in the fourth conductive layer is smaller than the size of the first conductive portion 140_a in the second conductive layer, which makes the projection of the fifth connection portion 170_a onto the substrate substantially located within the projection of the first conductive portion 140_a onto the substrate.

[0110] It should be noted that the cross-sectional views in Figures 2 to 8 can be spliced ​​views of two cross-sections taken along the dashed line shown in Figure 9E. The conductive posts 130_a and 130_b on both sides of the first conductive layer 120 in Figures 2 to 8 are only for illustrating that the first conductive part 140_a and the second conductive part 140_b are electrically connected through the first conductive layer 120. According to the planar layout shown in Figures 9A to 9E, the connection between the first conductive part 140_a and its adjacent second conductive part 140_b1 is achieved through a conductive connection unit 120_1 in the first conductive layer 120, and this adjacent second conductive part 140_b1 does not have a second conductive bump Bm2.

[0111] The embodiments of this disclosure also provide a method for manufacturing an integrated passive device, applicable to the integrated passive devices of any of the above embodiments. The method includes: forming a first blind via and a second blind via on a first side of an initial substrate; filling the first blind via and the second blind via with a conductive material to obtain a first initial conductive post located in the first blind via and a second initial conductive post located in the second blind via; forming a second conductive layer on the first side of the initial substrate, the second conductive layer including a first conductive portion and a second conductive portion electrically connected to the first initial conductive post and the second initial conductive post, respectively; forming a dielectric layer on the side of the first conductive portion away from the substrate; forming a third conductive layer on the side of the dielectric layer away from the substrate; thinning the initial substrate on a second side of the initial substrate opposite to the first side, exposing the conductive material in the first blind via and the second blind via, to obtain a substrate having a first via and a second via, and a first conductive post and a second conductive post located in the first via and the second via, respectively; forming a first conductive layer including a first metal material on the second side of the substrate, such that the first conductive portion is electrically connected to the first conductive layer through the first conductive post, and the second conductive portion is electrically connected to the first conductive layer 120 through the second conductive post.

[0112] Figures 10A to 10L illustrate the manufacturing process of the integrated passive device of Figure 2.

[0113] A first blind via Ha and a second blind via Hb are formed on the first side of the initial substrate 1100, as shown in Figure 1A. For example, a glass substrate with a thickness of 0.5 mm to 0.7 mm can be selected for small-size products. Blind vias are fabricated on the substrate 110 using laser-induced etching, with a via diameter of 50 μm to 80 μm. Traditional drilling methods involve laser ablation. However, the thermal effect of the laser results in a large roughness on the inner wall of the cylindrical via, which affects the deposition of the inner film layer and its bonding with the via wall, hindering the formation of a dense adhesion layer (Ti, Ta, W, TiN, TaN) and a Cu seed layer. The next-generation TGV drilling method uses laser-induced etching. This method uses laser irradiation to modify the molecular bonds at specific locations on the glass substrate, followed by etching with an etching solution. The etching rate of the laser-modified glass increases, forming blind vias. The smooth inner wall of the via obtained using laser-induced etching facilitates the bonding of the adhesion layer and seed layer with the via sidewall, enhancing reliability.

[0114] Next, as shown in Figure 1B, the first blind via Ha and the second blind via Hb are filled with conductive material to obtain the first initial conductive pillar 1300a in the first blind via Ha and the second initial conductive pillar 1300b in the second blind via Hb. For example, the through-holes in the glass substrate can be metallized to fill the glass blind vias. The conductive material can be Cu. The metallization of the conductive material in the blind vias can be performed by bottom-up electroplating. First, a Ti adhesion layer and a Cu seed layer are sputtered into the blind vias. For example, a continuous, fully covered Ti adhesion layer with a thickness of 10 nm to 300 nm and a Cu seed layer with a thickness of 30 nm to 1000 nm can be sputtered into the blind vias. Then, Cu electroplating is performed to fill the blind vias in a bottom-up manner. After electroplating, chemical mechanical polishing (CMP) is used to remove excess electroplated copper from the surface to ensure proper fabrication of subsequent film layers.

[0115] Next, as shown in FIG10C, a second conductive layer is formed on a first side of the initial substrate 1100. The second conductive layer includes a first conductive portion 140_a and a second conductive portion 140_b that are electrically connected to the first initial conductive post 1300a and the second initial conductive post 1300b, respectively. In some embodiments, forming the second conductive layer may include: forming a stack of an adhesive material and a second metal material on the initial substrate 1100; and patterning the stack to obtain the first conductive portion 140_a and the second conductive portion 140_b of the second conductive layer. A stack of a first adhesive material, a second adhesive material, and a second metal material and / or a first metal material may be formed on the initial substrate 1100, and the stack may be patterned to obtain the layer structure described above with reference to FIGS. 3A to 3E. For example, a first adhesive material (e.g., Ti, TiN, Ta, TaN, etc.) with a thickness of 0.03 μm to 0.05 μm can be deposited on the entire first side (front) of the substrate 110. A second metal material (e.g., Al) with a thickness of 1 μm to 3 μm is then formed on the first adhesive material, followed by the deposition of another second adhesive material (e.g., Ti, TiN, Ta, TaN, etc.) with a thickness of 0.03 μm to 0.05 μm. Next, photoresist is spin-coated, and the mask corresponding to the second conductive layer 140 is exposed. The photoresist irradiated with ultraviolet light undergoes denaturation, followed by development to remove the denatured photoresist. The pattern of the photoresist is then transferred to the second metal material using dry etching, completing the patterning of the second conductive layer 140. The second conductive layer 140 plays two roles in the entire device: part of it acts as the first electrode of a capacitor, and part of the winding of an inductor; therefore, high flatness is required.

[0116] Next, as shown in FIG10D, a dielectric layer 150 is formed on the side of the first conductive portion 140_a away from the initial substrate 1100. For example, the material of the dielectric layer 150 includes, but is not limited to, SiNx. Then, a highly flat SiNx film with a thickness of 100nm to 120nm can be deposited using a standard process such as plasma-enhanced chemical vapor deposition (PECVD) to serve as the dielectric layer material of the capacitor, thereby ensuring the uniformity of the capacitor. Then, the deposited SiNx is patterned, and a portion of the SiNx is removed by dry etching, leaving the remaining SiNx as the dielectric layer 150 of the capacitor.

[0117] Next, as shown in FIG10E, a third conductive layer 160 is formed on the side of the dielectric layer 150 away from the initial substrate 1100. For example, a stack of an adhesive material and a second metal material can be formed on the third conductive layer 160. As an example, a first adhesive material (e.g., Ti, TiN, Ta, TaN, etc.) with a thickness of 0.03 μm to 0.05 μm, a second metal material (e.g., Al) with a thickness of 0.2 μm to 0.5 μm, and a second adhesive material (e.g., Ti, TiN, Ta, TaN, etc.) with a thickness of 0.02 μm to 0.05 μm can be sequentially deposited on the dielectric layer 150 by magnetron sputtering. Then, the X / Al / X stack (X is Ti, TiN, Ta, TaN, etc.) is patterned to form the third conductive layer 160, which serves as the second electrode of the capacitor (the upper electrode in the figure).

[0118] Next, as shown in Figure 10F, a second insulating layer 182 is formed. For example, an insulating material with a thickness of 3 μm to 5 μm, such as PI (polyimide), can be spin-coated over the entire surface. The insulating material is then exposed and developed to obtain the second insulating layer 182. The second insulating layer 182 is used to electrically isolate the third conductive layer 160, the second conductive layer 140, and the fourth conductive layer 170 to be formed subsequently.

[0119] Next, as shown in Figure 10G, a fourth conductive layer 170 is formed. The fourth conductive layer 170 can adopt the second layer structure mentioned above. For example, first, a Ti layer with a thickness of 0.03 μm to 0.05 μm is deposited, and then a Cu layer with a thickness of 0.2 μm to 0.5 μm is deposited on top as a seed layer. Then, Cu is electroplated using an addition method as the first metal material, with a thickness of 5 μm to 10 μm, adjusted according to the design value. This results in a stack of Ti, seed, and Cu layers. Next, the stack is patterned to obtain the fourth conductive layer 170. For example, photoresist can be spin-coated onto the stack, and exposure can be performed using a mask corresponding to the fourth conductive layer 170. The photoresist irradiated with ultraviolet light undergoes denaturation, followed by development to remove the denatured photoresist. An etchant is then used to etch away the areas in the stack not protected by the photoresist (e.g., using a copper etchant to etch copper, and a Ti etchant to etch Ti), completing the patterning of the fourth conductive layer 170.

[0120] Next, as shown in Figure 10H, a third insulating layer 183 is formed. For example, an insulating material with a thickness of 5µm to 10µm can be spin-coated over the entire surface. The material is a photosensitive organic material, including but not limited to polyimide, to facilitate subsequent patterning and exposure of openings after device completion. The insulating material is then patterned (e.g., exposed and developed) to obtain the third insulating layer 183183 with vias. The vias in the third insulating layer 183183 expose the I / O area of ​​the device for subsequent I / O pin formation.

[0121] Next, as shown in FIG10I, the initial substrate 1100 is thinned on the second side opposite to the first side. For example, a glass substrate or silicon substrate with a thickness of 0.5 mm to 0.7 mm can be used as a bonding carrier to bond the front side (first side) of the structure shown in FIG10H, and mechanically grind the back side (second side) of the structure to thin the initial substrate 1100 to a specified thickness, such as 200 μm to 300 μm. By thinning the initial substrate 1100, the conductive material in the first blind via Ha and the second blind via Hb is exposed, resulting in a substrate 110 having a first via Va and a second via Vb, and a first conductive post 130_a and a second conductive post 130_b located in the first via Va and the second via Vb, respectively.

[0122] Next, as shown in Figure 10J, a first conductive layer 120 comprising a first metal material is formed on the second side of the substrate 110, such that the first conductive portion 140_a is electrically connected to the first conductive layer 120 through the first conductive post 130_a, and the second conductive portion 140_b is electrically connected to the first conductive layer 120 through the second conductive post 130_b. For example, the first conductive layer 120 is obtained by depositing and patterning the first metal material on the second side of the substrate 110. The first conductive layer 120 is part of the winding of the three-dimensional inductor and serves to connect the TGV via. It can be fabricated using subtractive or additive methods. Taking the subtractive process as an example, a Cu seed layer is first sputtered, then a thick Cu layer is electroplated across the entire surface, typically with a thickness greater than 5 μm, and then patterning is performed.

[0123] Next, as shown in Figure 10K, a first insulating layer 181 is formed. For example, an insulating material, such as polyimide or acrylic, can be spin-coated onto the entire surface to protect the traces on the lower surface of the device.

[0124] Next, as shown in Figure 10L, a first conductive bump Bm1 and a second conductive bump Bm2 are formed. For example, the substrate can be debonded to remove the bonding substrate on the front side. Solder balls are then implanted into the vias of the third insulating layer 183 in the structure shown in Figure 10K (i.e., the exposed area on the upper surface of the fourth conductive layer 170). This completes the fabrication of the integrated passive device.

[0125] Figures 11A to 11M illustrate the manufacturing process of the integrated passive device shown in Figure 6.

[0126] First, perform the process shown in Figures 11A to 11E, which is the same as that in Figures 10A to 10E, and will not be described again here.

[0127] Next, as shown in FIG11F, a third conductive portion 190_a and a fourth conductive portion 190_b are formed on the side of the second conductive layer 140 away from the initial substrate 1100. The third conductive portion 190_a is electrically connected to the first conductive portion 140_a, and the fourth conductive portion 190_b is electrically connected to the second conductive portion 140_b. The projection of the third conductive portion 190_a onto the initial substrate 1100 does not overlap with the projections of the dielectric layer 150 and the third conductive layer 160 onto the initial substrate 1100. For example, a first adhesion layer with a thickness of 0.03 μm to 0.05 μm and a Cu seed layer with a thickness of 0.3 μm to 0.5 μm can be deposited over the entire surface first, and then a copper layer with a thickness of 2 μm to 4 μm can be electroplated to obtain a stacked structure. Next, photoresist is spin-coated onto the stacked structure, and exposed with a mask. The photoresist irradiated with ultraviolet light undergoes denaturation. Then, development is performed to remove the denatured photoresist. An etchant is used to etch away the areas of the stacked structure that are not protected by the photoresist, thus completing the patterning and obtaining the third conductive part 190_a and the fourth conductive part 190_b.

[0128] Next, perform the process shown in Figures 11G to 11M, which is the same as that shown in Figures 10F to 10L, and will not be described again here.

[0129] Figures 12A to 12D illustrate the manufacturing process of the integrated passive device of Figure 7. This process is similar to that shown in Figures 11A to 11M, with the difference being at least that vias are formed in the first and second conductive portions before the formation of the third and fourth conductive portions. For simplicity, the differences will be described in detail below.

[0130] First, perform the processes shown in Figures 11A to 11C to obtain the structure shown in Figure 11C.

[0131] Next, as shown in FIG12A, vias are formed in the first conductive portion 140_a and the second conductive portion 140_b of FIG11C to obtain the first conductive portion 140'_a with the third via Via3 and the second conductive portion 140'_b with the fourth via Via4.

[0132] Next, as shown in Figures 12B and 12C, a dielectric layer 150 and a third conductive layer 160 are sequentially formed on the first conductive portion 140'_a. The methods for forming the dielectric layer 150 and the third conductive layer 160 are described in any of the above embodiments and will not be repeated here.

[0133] Next, a third conductive portion 190'_a and a fourth conductive portion 190'_b are formed on the structure shown in Figure 2C. As shown in Figure 2D, since the first conductive portion 140'_a and the second conductive portion 140'_b are provided with vias, the third conductive portion 190'_a is electrically connected to the first initial conductive post 1300a through the third via Via3 in the first conductive portion 140'_a, and the fourth conductive portion 190'_b is electrically connected to the second initial conductive post 1300b through the fourth via in the second conductive portion 140'_b.

[0134] Next, the process described in Figures 11G to 11M is performed to obtain the integrated passive device of Figure 7.

[0135] Figures 13A to 13D illustrate the manufacturing process of the integrated passive device 8. This process is similar to that shown in Figures 11A to 11M, with the difference being at least in the structure of the second conductive portion 140_b. For simplicity, the differences will be described in detail below.

[0136] First, the process shown in Figures 11A to 11B is executed to obtain an initial substrate 1100 having a first blind hole Ha and a second blind hole Hb, and a first initial conductive pillar 1300a and a second initial conductive pillar 1300b located in the first blind hole Ha and the second blind hole Hb.

[0137] Next, as shown in FIG13A, a first conductive portion 140_a of the second conductive layer 140 is formed on one side of the initial substrate 1100 where the first initial conductive pillar 1300a and the second initial conductive pillar 1300b are provided. For example, a stack of adhesion material and second metal material can be deposited on the initial substrate 1100, and then the stack can be patterned to obtain the first conductive portion 140_a of the second conductive layer 140. The first conductive portion 140_a formed in this way can have the first layer structure of any of the examples described above with reference to FIGS. 3A to 3E.

[0138] Next, as shown in Figures 13B and 13E, a dielectric layer 150 and a third conductive layer 160 are formed on the first conductive portion 140_a. The methods for forming the dielectric layer 150 and the third conductive layer 160 are described in any of the above embodiments and will not be repeated here.

[0139] Next, as shown in FIG13D, a second conductive portion 140”_b and a third conductive portion 190_b having the above-described second layer structure are formed on one side of the initial substrate 1100 where the first conductive portion 140_a is provided. For example, a first metal material can be deposited and patterned to obtain 140”_b and the third conductive portion 190_b.

[0140] Next, the process shown in Figures 11G to 11M is performed to obtain the integrated passive device shown in Figure 8.

[0141] This disclosure provides an integrated passive device and its fabrication method. The LC filter in the example includes a glass substrate, a three-dimensional spiral inductor structure, a planar thin-film capacitor structure, metal pads, and solder balls. The manufacturing process includes glass drilling, metal via filling, planar patterning, and double-sided patterning. The capacitor in the device adopts a MIM (Metal-Insulator-Metal) structure, consisting of upper and lower metal electrodes and a middle dielectric layer. The lower electrode material uses Al and the adhesion layer material X (Ti, TiN, Ta, TaN, etc.) to improve the capacitor's breakdown resistance and high-temperature reliability. The use of an Al / X / Cu composite film in non-capacitor areas can improve the conductivity of the traces and reduce device losses.

[0142] Those skilled in the art will understand that the embodiments described above are exemplary and can be improved upon. The structures described in the various embodiments can be freely combined without causing any conflict in structure or principle.

[0143] After a detailed description of the preferred embodiments of this disclosure, those skilled in the art will clearly understand that various changes and modifications can be made without departing from the scope and spirit of the appended claims, and that this disclosure is not limited to the implementation of the exemplary embodiments described in the specification.

Claims

1. An integrated passive device, comprising: A substrate, wherein a first via and a second via are provided in the substrate; The first conductive post and the second conductive post are located in the first via and the second via, respectively; The first conductive layer is located on one side of the substrate. The second conductive layer is located on the side of the substrate opposite to the first conductive layer. The second conductive layer includes a first conductive portion and a second conductive portion that are separated from each other. The first conductive portion is electrically connected to the first conductive layer through the first conductive post, and the second conductive portion is electrically connected to the first conductive layer through the second conductive post. A dielectric layer is located on the side of the first conductive portion away from the substrate. The third conductive layer is located on the side of the dielectric layer that is away from the substrate. Wherein, the first conductive layer includes a first metallic material, and at least one of the first conductive portion and the third conductive layer includes a stacked main body layer and an adhesive layer, wherein the main body layer includes a second metallic material different from the first metallic material.

2. The integrated passive device according to claim 1 further includes a third conductive portion, the third conductive portion being located on the side of the first conductive portion away from the substrate and electrically connected to the first conductive portion. The third conductive part includes a first metallic material; The projection of the third conductive portion onto the substrate does not overlap with the projections of the dielectric layer and the third conductive layer onto the substrate.

3. The integrated passive device according to claim 2, wherein, The first conductive part is provided with a third through hole, and the third conductive part is electrically connected to the first conductive post through the third through hole in the first conductive part.

4. The integrated passive device according to any one of claims 1 to 3, wherein, The second conductive part includes a first metallic material.

5. The integrated passive device according to any one of claims 1 to 3, wherein, The second conductive portion includes a stacked main body layer and an adhesive layer, and the main body layer of the second conductive portion includes the second metal material.

6. The integrated passive device according to claim 5 further includes a fourth conductive portion, the fourth conductive portion being located on the side of the second conductive portion away from the substrate and being electrically connected to the second conductive portion; The fourth conductive part includes the first metallic material.

7. The integrated passive device according to claim 6, wherein, The second conductive part is provided with a fourth through hole, and the fourth conductive part is electrically connected to the first conductive post through the fourth through hole in the second conductive part.

8. The integrated passive device according to any one of claims 1 to 7, wherein, The thickness of the first metal material in the first conductive layer is greater than the thickness of the second metal material in the first conductive portion of the second conductive layer.

9. The integrated passive device according to any one of claims 1 to 8, wherein, The second metal material is Al, and the material of the adhesion layer is Ti, TiN, Ta, or TaN.

10. The integrated passive device according to any one of claims 1 to 9, wherein, The adhesive layer superimposed on the main body layer includes a first adhesive layer and a second adhesive layer, with the main body layer located between the first adhesive layer and the second adhesive layer.

11. The integrated passive device according to claim 9, wherein, The main body layer is located in the enclosed space formed by the first adhesive layer and the second adhesive layer.

12. The integrated passive device according to any one of claims 1 to 11, wherein, The thickness of the main body layer of the first conductive part is in the range of 1 μm to 3 μm.

13. The integrated passive device according to any one of claims 1 to 12, wherein, The thickness of the adhesive layer of the first conductive part is in the range of 0.03 μm to 0.05 μm.

14. The integrated passive device according to any one of claims 1 to 13, wherein, The second conductive layer also includes a first metallic material.

15. The integrated passive device according to any one of claims 1 to 14, wherein, The distance between the projection of the dielectric layer on the substrate and the projection of the first conductor post on the substrate in a direction parallel to the substrate is greater than 5 μm.

16. The integrated passive device according to any one of claims 1 to 15, further comprising a fourth conductive layer, the fourth conductive layer comprising a fifth conductive portion and a sixth conductive portion separated from each other, the fifth conductive portion being located on the side of the third conductive layer away from the substrate and electrically connected to the third conductive layer, and the sixth conductive portion being located on the side of the second conductive portion of the second conductive layer away from the substrate and electrically connected to the second conductive portion.

17. The integrated passive device according to claim 16, further comprising: A first insulating layer is located on the side of the first conductive layer away from the substrate and covers the first conductive layer; The second insulating layer is located between the fourth conductive layer and the second and third conductive layers, and the fourth conductive layer penetrates the second insulating layer and is electrically connected to the second and third conductive layers.

18. The integrated passive device according to claim 16 or 17, further comprising: The first conductive bump is located on the side of the fifth conductive portion away from the substrate and is electrically connected to the fifth conductive portion; The second conductive bump is located on the side of the sixth conductive portion away from the substrate and is electrically connected to the fourth conductive portion.

19. The integrated passive device according to claim 18, further comprising: A third insulating layer is located on the side of the fourth conductor layer away from the substrate and covers the fourth conductor layer. The first conductive bump and the second conductive bump penetrate the third insulating layer and are electrically connected to the fifth conductor portion and the sixth conductor portion, respectively.

20. The integrated passive device according to any one of claims 1 to 19, wherein, The first metal material is Cu, and the thickness of the first metal material is greater than 2 μm.

21. The integrated passive device according to any one of claims 1 to 20, further comprising a Cu seed layer disposed on the side of the first metal material facing the substrate and a Ti layer disposed on the side of the Cu seed layer facing the substrate.

22. The integrated passive device according to any one of claims 1 to 21, wherein, The second conductive layer includes a plurality of second conductive portions separated from each other, the first conductive layer includes a plurality of conductive connection units separated from each other, and the substrate includes a plurality of second vias; The plurality of second conductive parts are electrically connected to the plurality of conductive connection units through the plurality of second vias to form a zigzag winding, one end of which is electrically connected to the first conductive part.

23. A method for manufacturing an integrated passive device according to claims 1 to 22, comprising: A first blind via and a second blind via are formed on a first side of the initial substrate. The first blind hole and the second blind hole are filled with conductive material to obtain a first initial conductive post located in the first blind hole and a second initial conductive post located in the second blind hole; A second conductive layer is formed on a first side of an initial substrate. The second conductive layer includes a first conductive portion and a second conductive portion that are electrically connected to the first initial conductive pillar and the second initial conductive pillar, respectively. A dielectric layer is formed on the side of the first conductive portion away from the initial substrate. A third conductive layer is formed on the side of the dielectric layer away from the initial substrate. The initial substrate is thinned on the second side opposite to the first side, so that the conductive material in the first blind hole and the second blind hole is exposed, resulting in a substrate having a first via and a second via, and a first conductive pillar and a second conductive pillar located in the first via and the second via, respectively. A first conductive layer comprising a first metallic material is formed on the second side of a substrate, such that a first conductive portion is electrically connected to the first conductive layer through a first conductive post, and a second conductive portion is electrically connected to the first conductive layer through a second conductive post.

24. The method according to claim 23, wherein, Forming the second conductive layer includes: A stack of an adhesion material and a second metal material is formed on an initial substrate. The stacked layers are patterned to obtain the first conductive portion and the second conductive portion of the second conductive layer.

25. The method of claim 24, further comprising: A third conductive portion and a fourth conductive portion are formed on the side of the second conductive layer away from the initial substrate. The third conductive portion is electrically connected to the first conductive portion, and the fourth conductive portion is electrically connected to the second conductive portion. The projection of the third conductive portion onto the initial substrate does not overlap with the projections of the dielectric layer and the third conductive layer onto the initial substrate.

26. The method of claim 25, further comprising: Before forming the third conductive portion and the fourth conductive portion, a third via is formed in the first conductive portion and a fourth via is formed in the second conductive portion, wherein the third conductive portion is electrically connected to the first initial conductive post through the third via in the first conductive portion, and the fourth conductive portion is electrically connected to the second conductive post through the fourth via in the second conductive portion.

27. The method according to claim 23, wherein, The integrated passive device further includes a third conductive portion, and the formation of the second conductive layer includes: A stack of an adhesion material and a second metal material is formed on an initial substrate. The stacked layers are patterned to obtain the first conductive portion of the second conductive layer; A first metal material is deposited on one side of the initial substrate where the first conductive portion is provided, and the first metal material is patterned to obtain the second conductive portion and the third conductive portion of the second conductive layer.

28. An integrated passive device comprising an inductor and a capacitor connected in series, the inductor having a first terminal and a second terminal, the capacitor having a first pole and a second pole, the first terminal of the inductor being connected to the first pole of the capacitor; in: The inductor includes a first conductive layer and a portion of the second conductive layer, and the capacitor includes another portion of the second conductive layer, a dielectric layer, and a third conductive layer; The integrated passive device further includes a substrate, the first conductive layer is located on one side of the substrate, and the second conductive layer is located on the side of the substrate opposite to the first conductive layer. The second conductive layer includes a first conductive portion and a second conductive portion separated from each other. The first conductive portion serves as the first electrode of the capacitor, the second conductive portion serves as part of the inductor, and the third conductive layer serves as the second electrode of the capacitor. The first conductive layer includes a first metallic material, and the first electrode of the capacitor includes a stacked main body layer and an adhesive layer, wherein the main body layer includes a second metallic material different from the first metallic material.

29. The integrated passive device of claim 28 further includes a third conductive portion located on the side of the first conductive portion away from the substrate and electrically connected to the first conductive portion, the third conductive portion comprising a first metallic material.

30. The integrated passive device according to claim 28, wherein, The inductor further includes a fourth conductive portion located on the side of the second conductive portion away from the substrate and electrically connected to the second conductive portion, the fourth conductive portion comprising a first metallic material.

31. The integrated passive device according to any one of claims 28 to 30, further comprising a fourth conductive layer, the fourth conductive layer being located on the side of the second conductive layer and the third conductive layer away from the substrate, and being electrically connected to the second conductive layer and the third conductive layer; The fourth conductive layer includes a fifth conductive portion and a sixth conductive portion that are separate from each other. The fifth conductive portion is electrically connected to the second conductive portion of the second conductive layer as part of the inductor, and the sixth conductive portion is electrically connected to the third conductive layer.

32. The integrated passive device according to claim 31, further comprising: The first pin is located on the side of the fifth conductive part away from the substrate, and is electrically connected to the second electrode of the capacitor via the fifth conductive part; The second pin, on the side of the sixth conductive part away from the substrate, is electrically connected to the second end of the inductor via the sixth conductive part.

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