Backplane and display apparatus

Abstract

Provided are a backplane and a display apparatus. The backplane comprises: a first transistor (M1), which comprises a first active layer, a first gate electrode, and a first insulating layer that is located between the first active layer and the first gate electrode and is in contact with the first active layer; and a second transistor (M2), which comprises a second active layer, a second gate electrode, and a second insulating layer that is located between the second active layer and the second gate electrode and is in contact with the second active layer. The first active layer comprises an oxide semiconductor material, the second active layer comprises an oxide semiconductor material, the mobility of the first active layer is different from that of the second active layer, and the first insulating layer and the second insulating layer are different layers.

Description

Back panel and display device Technical Field

[0001] Embodiments of this disclosure relate to a back panel and a display device. Background Technology

[0002] In the backplane of an organic light-emitting diode display device, there may be a backplane with transistors whose channels are made of all oxides. All oxide backplanes are increasingly used because of their superior performance. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a back panel and a display device.

[0004] At least one embodiment of this disclosure provides a backplane, comprising: a first transistor including a first active layer, a first gate, and a first insulating layer located between the first active layer and the first gate and in contact with the first active layer; and a second transistor including a second active layer, a second gate, and a second insulating layer located between the second active layer and the second gate and in contact with the second active layer, wherein the first active layer comprises an oxide semiconductor material, the second active layer comprises an oxide semiconductor material, the mobility of the first active layer is different from the mobility of the second active layer, and the first insulating layer and the second insulating layer are different layers.

[0005] For example, the oxygen content of the first insulating layer is different from that of the second insulating layer.

[0006] For example, the mobility of the first active layer is less than that of the second active layer, and the oxygen content of the first insulating layer is less than that of the second insulating layer.

[0007] For example, the channel length of the first transistor is greater than or equal to the channel length of the second transistor.

[0008] For example, the backplane also includes a substrate on which the first transistor and the second transistor are located.

[0009] For example, the first active layer is closer to the substrate than the second active layer.

[0010] For example, the second active layer is closer to the substrate than the first active layer.

[0011] For example, the backplane also includes an extension layer, which is located on the same layer as the first active layer, and the extension layer is located on the second gate to protect the second gate.

[0012] For example, the extended layer covers the sidewalls of the second gate and the surface away from the substrate.

[0013] For example, the second insulating layer is also located between the first active layer and the first gate, and the first insulating layer is closer to the first active layer than the second insulating layer. The portions of the first insulating layer and the second insulating layer located between the first active layer and the first gate constitute the gate insulating layer of the first transistor.

[0014] For example, the backplane also includes an interlayer insulating layer, the second transistor includes a source and a drain, the interlayer insulating layer is located between the second active layer and the source and drain of the second transistor, the interlayer insulating layer is also located between the first insulating layer and the first gate, and the first insulating layer and the interlayer insulating layer constitute the gate insulating layer of the first transistor.

[0015] For example, the thickness of the gate insulating layer of the first transistor is less than or equal to 2500 angstroms.

[0016] For example, the maximum thickness of the first insulating layer is less than the maximum thickness of the second insulating layer.

[0017] For example, the first transistor and the second transistor have different structures.

[0018] For example, one of the first transistor and the second transistor is a top-gate bottom contact, and the other of the first transistor and the second transistor is a top-gate top contact.

[0019] For example, in the transistor with the top gate bottom contact, the source or drain is located at the bottom.

[0020] For example, the backplane also includes a capacitor, which includes a first plate, a second plate, and a third plate. The first plate and the third plate are connected. The first plate is on the same layer as the first active layer or on the same layer as the lower source or drain. The second plate is on the same layer as the first gate, and the third plate is on the same layer as the second gate.

[0021] For example, the backplate also includes a light-emitting element, the first electrode of which is connected to the first transistor or the second transistor.

[0022] For example, the first transistor is a driving transistor, and the second transistor is a switching transistor.

[0023] Embodiments of this disclosure also provide a display device including any of the aforementioned back panels. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0025] Figure 1 is a cross-sectional schematic diagram of a backplate provided in an embodiment of the present disclosure.

[0026] Figure 2 is a cross-sectional schematic diagram of another backplate provided in another embodiment of this disclosure.

[0027] Figure 3 is a cross-sectional schematic diagram of another backplate provided in another embodiment of this disclosure.

[0028] Figure 4 is a cross-sectional schematic diagram of a conductive pattern layer LY1, an active layer LYa, a first insulating film, an active layer LYb, and a second insulating film formed on a substrate according to an embodiment of the present disclosure.

[0029] Figure 5 is a cross-sectional schematic diagram of a back plate provided in an embodiment of the present disclosure.

[0030] Figure 6 is a cross-sectional schematic diagram of a conductive pattern layer LY1, a buffer layer, an active layer AT1, an insulating film GI10, an active layer AT2, and an insulating layer GI2 formed on a substrate according to an embodiment of the present disclosure.

[0031] Figure 7 is a cross-sectional schematic diagram of a conductive pattern layer LY1, an active layer AT1, an insulating layer GI1, an active layer AT2, an insulating layer GI2, and a conductive pattern layer LY2 formed on a substrate according to an embodiment of the present disclosure.

[0032] Figure 8 is a cross-sectional schematic diagram of another backplate provided in another embodiment of this disclosure.

[0033] Figure 9 is a cross-sectional schematic diagram of another backplate provided in another embodiment of this disclosure. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0035] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0036] Currently, top-gate oxide backplanes are fabricated using a method where the gate and source / drain metals are on the same layer. The method of placing the data lines as the first layer of the backplane is used in large-size organic light-emitting diode (OLED) displays. Compared to conventional top-gate transistors, this structure saves on mask space and reduces costs, leading to its widespread application. However, for small-to-medium-sized OLED products, the larger number of transistors and the higher requirement for oxide mobility make achieving long-to-short channel compatibility more difficult. For example, a transistor with a channel length of 3 has a threshold voltage of 0V, but a transistor with a channel length of 10 or more has a threshold voltage greater than 3V. This makes transistor stability difficult to control. Furthermore, the longer size of the driving transistors significantly impacts design space, making it impossible to achieve high pixel density (Pixels Per Inch, PPI) products. Additionally, in circuits using all-oxide transistors across all channels, the larger area occupied by capacitors also significantly hinders the achievement of high PPI.

[0037] The fabrication of ultra-high mobility oxide devices for all-oxide backplane driving OLEDs is currently the main focus of notebook (NB) products. Due to the sensitivity of high mobility oxide materials to elements such as hydrogen / oxygen (H / O), the compatibility of transistors with different channel lengths becomes more difficult. To ensure high PPI, switching transistors are usually fabricated with ultra-short channels. At the same time, since the driving transistors need to meet the requirements of low grayscale expansion, the current needs to be reduced or the subthreshold swing of the device needs to be increased. The conventional approach is to lengthen the channel of the driving transistor. Under the same conditions, when the output current of the low aspect ratio transistor is lower, the rate of change with voltage is also lower, which can achieve perfect low grayscale expansion. However, this sacrifices backplane design space. The increase in the channel length of the transistor occupies a larger pixel area, making it difficult to improve PPI.

[0038] Because the gate insulating layer has a significant impact on oxide transistors, it is difficult to make the fabrication processes of gate insulating layers compatible with oxides of different mobilities. Typically, optimization is achieved by using the same gate insulating layer with different oxide materials as channels, which can easily lead to infeasibility. The backplane provided in this disclosure uses a non-shared gate insulating layer to enable transistors with different mobilities to perform different functions in the circuit.

[0039] Figure 1 is a cross-sectional schematic diagram of a backplane provided in an embodiment of the present disclosure. As shown in Figure 1, the backplane provided in the embodiment of the present disclosure includes: transistor M1 and transistor M2; transistor M2 includes an active layer AT1, a gate GT1, and an insulating layer GI1 located between the active layer AT1 and the gate GT1 and in contact with the active layer AT1; transistor M1 includes an active layer AT2, a gate GT2, and an interlayer insulating layer ILD located between the active layer AT2 and the gate GT2 and in contact with the active layer AT2; the active layer AT1 includes an oxide semiconductor material, the active layer AT2 includes an oxide semiconductor material, the mobility of the active layer AT1 is different from the mobility of the active layer AT2, and the insulating layer GI1 and the interlayer insulating layer ILD are different layers. Transistor M1 is a driving transistor, and transistor M2 is a switching transistor.

[0040] The driving transistor has a lower channel mobility, while the switching transistor has a higher channel mobility. The driving and switching transistors use different gate insulating layers (they do not share a common gate insulating layer). Therefore, the gate insulating layers in the driving and switching transistors can have different oxygen contents, which helps improve transistor performance. As shown in Figure 1, the gate insulating layer of transistor M1 is an interlayer insulating layer (ILD), and the gate insulating layer of transistor M2 is an insulating layer (GI1).

[0041] The backplane provided in the embodiments of this disclosure has transistors using an all-oxide channel, which can be used to fabricate small-to-medium-sized OLED products. It can reduce the channel size of the driving transistor (e.g., transistor M1 as shown in FIG. 1), ensuring transistor performance, improving the performance of oxide devices, and significantly increasing aperture ratio and PPI. Because the channel size of the driving transistor (e.g., transistor M1 as shown in FIG. 1) can be reduced, the difference between the channel sizes of the driving transistor (e.g., transistor M1 as shown in FIG. 1) and the switching transistor (e.g., transistor M2 as shown in FIG. 1) is reduced, becoming negligible, which is beneficial for improving PPI.

[0042] For example, as shown in Figure 1, the oxygen content of insulating layer GI1 is different from that of interlayer insulating layer ILD. For example, the mobility of active layer AT1 is greater than that of active layer AT2, and the oxygen content of insulating layer GI1 is greater than that of interlayer insulating layer ILD.

[0043] For example, as shown in Figure 1, the backplane also includes a substrate BS, and transistors M1 and M2 are located on the substrate BS.

[0044] For example, as shown in FIG1, active layer AT1 is closer to the substrate BS than active layer AT2. Of course, the embodiments of this disclosure are not limited to this; in the embodiment shown in FIG1, transistors M1 and M2 can also be interchanged in the Z-direction, thereby making active layer AT2 closer to the substrate BS than active layer AT1. That is, in some embodiments, active layer AT2 is closer to the substrate BS than active layer AT1.

[0045] Figure 1 also shows a conductive patterned layer LY1, which includes a light-shielding pattern LSD.

[0046] As shown in Figure 1, a buffer layer BF is disposed on the conductive pattern layer LY1. An active pattern layer LYa is disposed on the buffer layer BF. An insulating layer GI1 is disposed on the active pattern layer LYa. A conductive pattern layer LY2 is disposed on the insulating layer GI1. An interlayer insulating layer ILD is disposed on the conductive pattern layer LY2. A conductive pattern layer LY3 is disposed on the interlayer insulating layer ILD. A passivation layer PVX is disposed on the conductive pattern layer LY3. A planarization layer PLN is disposed on the passivation layer PVX. A first electrode E1 is disposed on the planarization layer PLN. A pixel defining layer PDL is disposed on the first electrode E1. The pixel defining layer PDL has a pixel opening OPN. A light-emitting functional layer EML is disposed in at least the pixel opening OPN. A second electrode E2 is disposed on the light-emitting functional layer EML.

[0047] As shown in Figure 1, the first electrode E1, the light-emitting functional layer EML, and the second electrode E2 constitute the light-emitting element EM. The first electrode E1 of the light-emitting element EM is connected to either transistor M1 or transistor M2.

[0048] For example, as shown in Figure 1, the backplane also includes a capacitor C0, which includes a first plate CE1, a second plate CE2, and a third plate CE3. The first plate CE1 and the third plate CE3 are connected (not shown in Figure 1, but connected elsewhere through vias penetrating the buffer layer BF and the interlayer insulating layer ILD). The first plate CE1 is on the same layer as the lower source or drain (light-shielding pattern LSD), the second plate CE2 is on the same layer as the gate GT1 or the active layer AT1, and the third plate CE3 is on the same layer as the gate GT2. The capacitor C0 employs a multi-layer structure, which significantly reduces the lateral area and substantially improves the PPI of small and medium-sized display devices.

[0049] The backplate shown in Figure 1 can be fabricated using the following method. First, a conductive pattern layer LY1 is formed on a substrate, such as a glass substrate. This layer can be made of a metal material, such as copper (Cu). Simultaneously, based on the bottom-mounted source or drain structure of the top-gate transistor, a bottom-mounted source or drain (light-shielding pattern LSD) is formed. While forming the light-shielding pattern LSD, a pattern (first electrode CE1) is formed as one electrode of the multilayer capacitor. Then, a buffer layer BF is formed on the conductive pattern layer LY1. This buffer layer can be made of an inorganic insulating material, such as a single-layer or composite film of SiNx and SiOx, with a thickness generally greater than 0.3 μm. Next, a first active thin film is formed and patterned to form an active pattern layer LYa. The active pattern layer LYa includes an active layer AT1, which uses a high-mobility oxide with a mobility greater than or equal to 20. A second electrode CE2 is formed simultaneously with the active layer AT1. Finally, a first insulating thin film is formed, typically using... The SiOx thin film is not patterned at this stage. A first gate film is formed on the first insulating film and patterned to form the gate GT1 and wiring of the thin-film transistor (switching transistor) M2. Subsequently, a second active film is formed and patterned to form a channel at another thin-film transistor (driving transistor) M1. A self-alignment process is performed without removing the photoresist. The first insulating film is etched away, and a conductorization process, for example, using helium (He) plasma, is used to conduct the active layer of the switching transistor into a conductive region. In this process, the gate GT1 of the switching transistor is also synchronously self-aligned above the channel region, thus forming a distinction between the channel and non-channel regions. Simultaneously, the portion of the active pattern LYa located in the capacitor region is also made conductive to form the second electrode CE2. Subsequently, a second insulating film is formed, and an aperture process is performed to form the interlayer insulating layer (ILD). For the switching transistor, the aperture reaches the conductive region of the active pattern layer LYa; for the driving transistor, the aperture simultaneously reaches the active pattern layer LYb and the conductive pattern layer LY1. Next, a conductive film is formed, for example, using a Cu-series metal. For the switching transistor, source and drain electrodes (electrodes Ea and Eb) are formed; for the driving transistor, gate GT2 and electrode Ec (formed in the drain region) are formed. This electrode Ec is connected to the light-shielding pattern LSD and the active layer AT2, respectively. Simultaneously, a third electrode CE3 is formed in the capacitor region. At this point, a doping process is used to make the conductive region of the active layer AT2 conductive (forming electrode Ed), thus forming the driving transistor. Next, the passivation layer PVX, the planarization layer PLN, the first electrode E1, and the pixel definition layer PDL are formed to complete the fabrication of the backplane.

[0050] Compared to the backplate provided in the embodiment shown in Figure 1, the backplate provided in the embodiment shown in Figure 2 further includes a fourth electrode plate CE4, which is located on the insulating layer GI1. An interlayer insulating layer ILD is provided between the fourth electrode plate CE4 and the third electrode plate CE3. The structure of the light-emitting element in Figure 2 can be referenced to that shown in Figure 1, or other suitable structures can be used.

[0051] For example, as shown in Figure 3, the backplane also includes an extension layer ATc. The extension layer ATc and the active layer AT2 are located in the same layer, that is, in the active patterning layer LYb. The extension layer ATc is located on the gate GT1 to protect the gate GT1 and to reduce the lateral size of the gate GT1, thereby improving the aperture ratio. The extension layer ATc is a conductor, that is, a conductor formed by an oxide semiconductor through a conductor-forming process.

[0052] For example, as shown in Figure 3, the extended layer ATc covers the side surface of the gate GT1 and the surface away from the substrate BS. That is, the extended layer ATc covers the gate GT1.

[0053] Compared to the backplane shown in Figure 2, the backplane shown in Figure 3 has an extended layer ATc above the gate GT1 of the switching transistor. This extended layer protects the gate GT1 during self-aligned etching after the active pattern layer LYb is patterned, preventing the gate GT1 from being etched. Simultaneously, it forms the pattern of the capacitor plate (fourth plate CE4) in the capacitor region. In the backplane shown in Figure 3, transistor M2 is the switching transistor, and transistor M1 is the driving transistor.

[0054] In embodiments of this disclosure, an extension layer can be provided for short-channel switching transistors to improve their performance.

[0055] As shown in Figures 4 and 5, an embodiment of this disclosure provides a backplane, including transistor M1 and transistor M2. Transistor M1 includes an active layer AT1, a gate GT1, and an insulating layer GI1 located between the active layer AT1 and the gate GT1 and in contact with the active layer AT1. Transistor M2 includes an active layer AT2, a gate GT2, and an insulating layer GI2 located between the active layer AT2 and the gate GT2 and in contact with the active layer AT2; the active layer AT1 includes an oxide semiconductor material, the active layer AT2 includes an oxide semiconductor material, the mobility of the active layer AT1 is different from that of the active layer AT2, and the insulating layers GI1 and GI2 are different layers.

[0056] As shown in Figures 4 and 5, the backplane also adopts the method that the driving transistor and the switching transistor do not share the same gate insulating layer.

[0057] As shown in Figure 5, an insulating layer GI2 is also provided between the active layer AT1 and the gate GT1. Insulating layers GI1 and GI2 constitute the gate insulating layer GI of transistor M1. As shown in Figure 5, the gate insulating layer GI of transistor M1 includes two sub-layers with different oxygen contents. For example, the sub-layer closer to the active layer AT1 has a lower oxygen content. That is, the oxygen content of insulating layer GI1 is lower than that of insulating layer GI2. In the backplane shown in Figure 5, transistor M1 is a driving transistor, and transistor M2 is a switching transistor.

[0058] As shown in Figures 4 and 5, after forming the active layer AT1, a gate insulating film GI10 is first fabricated without patterning. Then, the active layer AT2 is formed on the gate insulating film. The active layer AT1 uses a low-mobility oxide material, and the corresponding transistors formed thereon serve as driving transistors. The active layer AT2 uses a high-mobility oxide material, and the corresponding transistors serve as switching transistors. Subsequently, another gate insulating film is formed. Above this gate insulating film, vias are used to expose the electrodes of the driving transistors (revealing the light-shielding pattern LSD). Then, a conductive pattern layer LY2 is formed and patterned to form the gate GT1. The gate GT2 and electrode GTa are conductively fabricated using a self-aligned process. The gate insulating layer (insulating layer L1) of the driving transistor is insulating layer GI1 and insulating layer GI2, and the gate insulating layer of the switching transistor is insulating layer GI2. Since the active layer AT2 is a high-mobility material, insulating layer GI2 can be a high-oxygen-content insulating layer, such as a high-oxygen-content SiOx thin film. However, for devices using low-mobility materials as driving transistors, insulating layer GI1 is in direct contact with the active layer AT1, which can reduce the oxygen content in insulating layer GI1, such as the SiOx thin film, to stabilize device performance. Subsequently, a conductive pattern layer LY3 is formed. The conductive pattern layer LY3 includes the source and drain electrodes (electrodes Ea and Eb) of the switching transistor. Since the driving transistor uses the light-shielding pattern LSD in the conductive pattern layer LY1 as the transistor electrode (drain), the other end can be either the active layer AT1 or a component in the conductive pattern layer LY3 as the electrode (not shown in the figure), depending on the specific pixel circuit. Subsequent film layers follow conventional design and will not be described further here.

[0059] For example, as shown in Figures 4 and 5, insulating layer GI2 is also located between active layer AT1 and gate GT1. Insulating layer GI1 is closer to active layer AT1 than insulating layer GI2. The portions of insulating layer GI1 and insulating layer GI2 located between active layer AT1 and gate GT1 constitute the gate insulating layer GI of transistor M1.

[0060] As shown in Figure 4, a conductive pattern layer LY1 (including a light-shielding pattern LSD) is formed on a substrate BS. A buffer layer BF is formed on the conductive pattern layer LY1. An active pattern layer LYa (including an active layer AT1) is formed on the buffer layer BF. An active thin film GI10 is formed on the active pattern layer LYa. An active pattern layer LYb (including an active layer AT2) is formed on the active thin film GI10. An active thin film GI20 is formed on the active pattern layer LYb. The active thin films GI10 and GI20 are etched to form insulating layers GI1 and GI2. Then, a conductive pattern layer LY2 is formed, which includes electrodes GTa, gate GT1, and gate GT2. An interlayer insulating film is formed on the conductive pattern layer LY2. The interlayer insulating film is etched to form an interlayer insulating layer ILD. A conductive pattern layer LY3 is formed on the interlayer insulating layer ILD. The conductive pattern layer LY3 includes electrodes Ea and Eb.

[0061] Based on the structure of the backplate shown in Figure 5, the first electrode E1 of the light-emitting element can be connected to the driving transistor or the switching transistor through a via through the interlayer insulating layer ILD.

[0062] As shown in Figures 6 to 8, the backplane provided in this embodiment also employs a method where high and low mobility devices do not share a gate insulating layer. After the insulating thin film GI10 is fabricated, the active pattern layer LYb and the insulating layer GI2 are fabricated as continuous thin films and patterned simultaneously to form the same pattern. The insulating layer GI2 can be made of SiOx and can be formed using a dry etching method, while the active pattern layer LYb can be formed using a wet etching method, as shown in Figure 6. As shown in Figure 7, vias are then formed to form the insulating layer GI1, which is used for the left-side transistor to connect downwards to the signal line (light-shielding pattern LSD). Subsequently, the conductive pattern layer LY2 is formed, as shown in Figure 7. For the left-side transistor, the source / drain electrodes (the conductive portion of the electrodes GTa and the other end of the active layer AT1) and the gate GT1 are formed in the same layer. As shown in Figure 8, the conductive pattern layer LY3 is formed, and for the right-side transistor, the source / drain electrodes (electrodes Ea and Eb) are formed. In this embodiment, the gate insulating layers of the two transistors with different mobilities are completely independent. Therefore, the transistors on the left and right can be paired in different ways. Specifically, the left transistor can be a low-mobility transistor and the right transistor a high-mobility transistor, or vice versa. This can be flexibly selected based on the actual panel design and the function of the transistors. Subsequently, an interlayer insulating film is fabricated, and vias are formed within it to form the interlayer insulating layer (ILD). Then, a conductive pattern layer (LY3) is formed. The conductive pattern layer LY3 includes the electrode Ec connected to the electrode GTa of the left transistor and serves as the source and drain electrodes (electrodes Ea and Eb) of the right transistor. Similarly, subsequent film layers can refer to the previous or typical design and will not be described further here.

[0063] That is, in the backplane shown in Figure 8, in some embodiments, transistor M1 is a driving transistor and transistor M2 is a switching transistor. In other embodiments, transistor M1 may be a switching transistor and transistor M2 may be a driving transistor.

[0064] For example, as shown in Figure 9, the backplane also includes an interlayer insulating layer ILD. Transistor M2 includes a source Ea and a drain Eb. The interlayer insulating layer ILD is located between the active layer AT2 and the source-drain layers (source Ea and drain Eb, i.e., conductive pattern layer LY3) of transistor M2. The interlayer insulating layer ILD is also located between the insulating layer GI1 and the gate GT1. The insulating layer GI1 and the interlayer insulating layer ILD constitute the gate insulating layer GI of transistor M1.

[0065] For example, as shown in Figure 9, the sum of the thicknesses of the insulating layer GI1 and the interlayer insulating layer ILD (the gate insulating layer GI of transistor M1) is less than or equal to 2500 angstroms.

[0066] For example, as shown in Figure 9, the thickness of the portion of insulating layer GI1 at transistor M1 is less than the thickness of the portion of insulating layer GI1 at transistor M2.

[0067] The backplane shown in Figure 9 also shows transistors with high and low mobility channels using a non-shared gate insulating layer. As shown in Figure 9, after forming the thin film for forming the insulating layer GI1, an active patterned thin film for forming the active layer AT2 is fabricated. After patterning the active patterned thin film, the insulating layer GI2 and the conductive patterned layer LY2 are formed using a self-aligned patterning method. At this time, the transistor on the right side forms the channel and conductive region, while the portion of the insulating layer GI2 located above the transistor on the left side is completely etched. Since etching always involves a certain amount of over-etching, the insulating layer GI1 needs to be thickened by a certain amount based on the over-etching amount, such as changing it from 1500 angstroms to 2000 angstroms. Subsequently, the interlayer insulating layer ILD is fabricated. For the transistor on the right side, vias are formed to realize the electrical connection between the source / drain and the active layer AT2 (electrodes Ea and Eb are respectively connected to the active layer AT2). For the transistor on the left side, vias are formed to the light-shielding pattern LSD for... An electrical connection is formed between the source or drain and the active layer AT1. Subsequently, a conductive pattern layer LY3 is formed, which includes electrode Ec, gate GT1, electrode Ea, and electrode Eb. For the transistor on the right, a complete top-gate device is formed, and for the transistor on the left, a top-gate bottom-contact device is formed, i.e., a light-shielding pattern LSD is used to transmit signals. At the same time, gate GT1 is also formed in the same layer as the source and drain (electrodes Ea and Eb). At this time, doping can be performed under self-alignment to form active pattern layers LYa and LYb. The conductive region of active pattern AT1 is conductiveized, or conductiveization is performed by dry etching. However, the interlayer insulating layer ILD in the non-source and drain regions of the transistor on the right will also be etched (not shown in the figure). Finally, the subsequent film structure is fabricated, which will not be described in detail here. It is important to emphasize that if the active layer AT2 is a high-mobility material, the oxygen content margin in the interlayer insulating layer (ILD, which can be SiOx) has a wider margin and will not affect the transistor's device performance. Meanwhile, for a low-mobility device, the oxygen content of the insulating layer GI1 can be adjusted accordingly to achieve a lower oxygen content. Conversely, if the active layer AT2 is also a low-mobility material, the oxygen content of the interlayer insulating layer (ILD) needs to be lower to ensure the conductivity resistance of the transistor on the right side. In this case, for a high-mobility device with active layer AT1, the oxygen content of the insulating layer GI1 needs to be increased to ensure the transistor's performance. Otherwise, the transistor's threshold voltage (Vth) may become negatively biased. Therefore, the oxygen content of the insulating layer GI can be adjusted based on the active layer AT1, and the oxygen content of the interlayer insulating layer (ILD) can be adjusted based on the active layer AT2. Low-mobility devices correspond to insulating layers with lower oxygen content, while high-mobility devices correspond to insulating layers with higher oxygen content.

[0068] For example, as shown in Figure 9, the maximum thickness of insulating layer GI1 is less than the maximum thickness of insulating layer GI2. Insulating layer GI1 serves a protective function and does not need to be too thick. For the portion of insulating layer GI1 corresponding to transistor M1 in Figure 9, its thickness needs to be greater than 0 after etching to provide protection. The maximum thickness of insulating layer GI1 is the thickness of insulating layer GI1 at transistor M2, and the maximum thickness of insulating layer GI2 is the thickness of insulating layer GI2 at transistor M2.

[0069] For example, as shown in Figure 9, at transistor M1, the sum of the thickness of insulating layer GI1 and the thickness of interlayer insulating layer ILD can be equal to or approximately equal to the thickness of insulating layer GI2.

[0070] For example, transistor M1 and transistor M2 have different structures.

[0071] For example, one of transistors M1 and M2 is a top-gate bottom contact, and the other of transistors M1 and M2 is a top-gate top contact.

[0072] For example, in a transistor with a top-gate bottom contact, the source or drain is located below the active layer. This allows the source or drain to share the same film layer with other components, which helps reduce parasitic capacitance and power consumption. In the embodiments of this disclosure, "source or drain below the active layer" means that the source or drain in the transistor is located below the active layer.

[0073] For example, in the embodiments of this disclosure, transistor M1 is used as the driving transistor and transistor M2 is used as the switching transistor, but the method is not limited thereto.

[0074] Taking transistors M1 and M2 as examples, as shown in Figures 1 to 3, the active layer AT1 of transistor M2 is closer to the substrate BS than the active layer AT2 of transistor M1.

[0075] Taking transistors M1 and M2 as examples, as shown in Figures 5, 8 and 9, the active layer AT1 of transistor M1 is closer to the substrate BS than the active layer AT2 of transistor M2.

[0076] For example, in the backplane provided in the embodiments of this disclosure, direction Z is perpendicular to the main surface of the substrate BS. The main surface of the substrate BS is the surface used to fabricate various components.

[0077] For example, in the backplane provided in the embodiments of this disclosure, the substrate can be a flexible substrate or a rigid substrate.

[0078] For example, in the backplane provided in the embodiments of this disclosure, at least one of the conductive pattern layer LY1, conductive pattern layer LY2, and conductive pattern layer LY3 may be made of a conductive material such as metal.

[0079] For example, in the backplane provided in the embodiments of this disclosure, at least one of the buffer layer BF, insulating layer GI1, insulating layer GI2, interlayer insulating layer ILD, and passivation layer PVX can be made of inorganic insulating material.

[0080] For example, in the backplane provided in the embodiments of this disclosure, at least one of the planarization layer PLN and the pixel defining layer PDL can be made of an organic insulating material.

[0081] For example, in embodiments of this disclosure, low-mobility oxide materials include indium gallium zinc oxide (IGZO), and high-mobility oxide materials include indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or related materials doped with rare earth elements, as well as oxide materials with high indium (In) content. Embodiments of this disclosure include, but are not limited to, these.

[0082] In the embodiments shown in Figures 1 to 3, transistor M1 is a driving transistor and transistor M2 is a switching transistor, that is, the left side is the switching transistor and the right side is the driving transistor. The interlayer insulating layer ILD is the gate insulating layer (first insulating layer L1) of transistor M1, and the insulating layer GI1 and the interlayer insulating layer ILD are the gate insulating layers (second insulating layer L2) of transistor M2.

[0083] In embodiments other than those shown in Figures 1 to 3, transistor M1 is a driving transistor and transistor M2 is a switching transistor; that is, the left side is the driving transistor and the right side is the switching transistor. As shown in Figure 5, insulating layers GI1 and GI2 are the gate insulating layers (first insulating layer L1) of transistor M1, and insulating layer GI2 is the gate insulating layer (second insulating layer L2) of transistor M2. As shown in Figure 8, insulating layer GI1 is the gate insulating layer (first insulating layer L1) of transistor M1, and insulating layer GI2 is the gate insulating layer (second insulating layer L2) of transistor M2. Of course, for the embodiment shown in Figure 8, the transistor on the left can also be the switching transistor (transistor M2), and the transistor on the right can be the driving transistor (transistor M1). In this case, insulating layer GI2 is the gate insulating layer (first insulating layer L1) of transistor M1, and insulating layer GI2 is the gate insulating layer (second insulating layer L2) of transistor M2. As shown in Figure 9, insulating layer GI1 and interlayer insulating layer ILD are the gate insulating layer (first insulating layer L1) of transistor M1, and insulating layer GI2 is the gate insulating layer (second insulating layer L2) of transistor M2. Alternatively, in the embodiment shown in Figure 9, the transistor on the left can be a switching transistor (transistor M2), and the transistor on the right can be a driving transistor (transistor M1). In this case, insulating layer GI1 and interlayer insulating layer ILD are the gate insulating layer (second insulating layer L2) of transistor M2, and insulating layer GI2 is the gate insulating layer (first insulating layer L1) of transistor M1.

[0084] In embodiments of this disclosure, transistor M1 may be referred to as the first transistor, and transistor M2 may be referred to as the second transistor.

[0085] In embodiments of this disclosure, the transistor may be a thin-film transistor, but is not limited thereto.

[0086] Embodiments of this disclosure provide a display device including any of the aforementioned back panels.

[0087] For example, the display device provided in the embodiments of this disclosure can be an organic light-emitting diode display device or other display device, as well as any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator that includes the display device. The embodiments of this disclosure include, but are not limited to, these.

[0088] Embodiments of this disclosure provide a backplane that can achieve at least one of the following effects.

[0089] (1) The driving transistor and the switching transistor use different gate insulating layers (do not share a gate insulating layer), so that the gate insulating layers in the driving transistor and the switching transistor can have different oxygen contents, which is beneficial to improving the performance of the transistor.

[0090] (2) By using channel materials with different mobilities to fabricate different transistors, the channel length of the driving transistor can be reduced. For example, the channel length of the driving transistor can be greater than the channel length of the switching transistor, or the channel length of the driving transistor can be equal to or approximately equal to the channel length of the switching transistor. That is, the channel length of the driving transistor can be greater than or equal to the channel length of the switching transistor. The channel lengths of the driving transistor and the switching transistor can be made to be equal or approximately equal by adjusting the mobility of the active layer and the gate insulating layer of the transistor.

[0091] (3) By using a conductor-conductive double active layer and two conductive pattern layers to achieve multi-layered capacitance, the lateral area is greatly reduced, significantly improving the PPI of small and medium-sized OLEDs.

[0092] (4) Different structures are used for transistors with different functions to achieve compatibility between the top gate bottom contact and the backplane of conventional top gate transistors, and to achieve the sharing of conductive pattern layers, thereby minimizing the number of masks for the backplane of transistors with two mobility materials.

[0093] The following points need to be explained:

[0094] (1) Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0095] (2) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0096] (3) For clarity, the thickness of layers or regions is magnified in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0097] (4) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other.

[0098] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A back panel, comprising: The first transistor includes a first active layer, a first gate, and a first insulating layer located between the first active layer and the first gate and in contact with the first active layer. as well as The second transistor includes a second active layer, a second gate, and a second insulating layer located between the second active layer and the second gate and in contact with the second active layer. The first active layer comprises an oxide semiconductor material, the second active layer comprises an oxide semiconductor material, the mobility of the first active layer is different from that of the second active layer, and the first insulating layer and the second insulating layer are different layers.

2. The backplate according to claim 1, wherein, The oxygen content of the first insulating layer is different from that of the second insulating layer.

3. The backplate according to claim 1 or 2, wherein, The mobility of the first active layer is less than that of the second active layer, and the oxygen content of the first insulating layer is less than that of the second insulating layer.

4. The backplate according to claim 3, wherein, The channel length of the first transistor is greater than or equal to the channel length of the second transistor.

5. The backplate according to any one of claims 1-4, further comprising a substrate, wherein, The first transistor and the second transistor are located on the substrate.

6. The backplate according to claim 5, wherein, The first active layer is closer to the substrate than the second active layer.

7. The backplate according to claim 5, wherein, The second active layer is closer to the substrate than the first active layer.

8. The back sheet according to claim 7, further comprising an extension layer, wherein, The extended layer and the first active layer are located on the same layer, and the extended layer is located on the second gate to protect the second gate.

9. The backplate according to claim 8, wherein, The extended layer covers the sidewalls of the second gate and the surface away from the substrate.

10. The backplate according to any one of claims 1-6, wherein, The second insulating layer is also located between the first active layer and the first gate. The first insulating layer is closer to the first active layer than the second insulating layer. The portions of the first insulating layer and the second insulating layer located between the first active layer and the first gate constitute the gate insulating layer of the first transistor.

11. The back sheet according to any one of claims 1-6, further comprising an interlayer insulating layer, wherein, The second transistor includes a source and a drain. The interlayer insulating layer is located between the second active layer and the source and drain of the second transistor. The interlayer insulating layer is also located between the first insulating layer and the first gate. The first insulating layer and the interlayer insulating layer constitute the gate insulating layer of the first transistor.

12. The backplate according to claim 11, wherein, The thickness of the gate insulating layer of the first transistor is less than or equal to 2500 angstroms.

13. The backplate according to claim 11 or 12, wherein, The maximum thickness of the first insulating layer is less than the maximum thickness of the second insulating layer.

14. The backplate according to any one of claims 1-13, wherein, The first transistor and the second transistor have different structures.

15. The backplate according to claim 14, wherein, One of the first transistor and the second transistor is a top-gate bottom contact, and the other of the first transistor and the second transistor is a top-gate top contact.

16. The backplate according to claim 14 or 15, wherein, In the transistor with top-gate bottom contact, the source or drain is located at the bottom.

17. The backplane according to claim 15 or 16, further comprising a capacitor, wherein, The capacitor includes a first plate, a second plate, and a third plate. The first plate and the third plate are connected. The first plate is on the same layer as the first active layer or on the same layer as the lower source or drain. The second plate is on the same layer as the first gate, and the third plate is on the same layer as the second gate.

18. The backplate according to any one of claims 1-17, further comprising a light-emitting element, wherein, The first electrode of the light-emitting element is connected to either the first transistor or the second transistor.

19. The backplate according to any one of claims 1-18, wherein, The first transistor is a driving transistor, and the second transistor is a switching transistor.

20. A display device comprising a back panel as described in any one of claims 1-19.

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