Backplane and display apparatus

Abstract

Provided are a backplane and a display apparatus. The backplane comprises: a base substrate (BS); a transistor (M1) located on the base substrate (BS) and comprising an active layer (AT) and a gate electrode (GT / GT2), the active layer (AT) being closer to the base substrate (BS) than the gate electrode (GT / GT2); a first insulating layer (GI / GI1) located between the active layer (AT) and the gate electrode (GT / GT2); and a functional layer (L0) connected to the gate electrode (GT / GT2) of the transistor (M1). A channel extension layer (L0) is arranged to facilitate reducing the size of the gate electrode connected to the channel extension layer (L0) and improving the PPI.

Description

Back panel and display device Technical Field

[0001] Embodiments of this disclosure relate to a back panel and a display device. Background Technology

[0002] In the backplane of an organic light-emitting diode display device, there may be a backplane with transistors whose channels are made of all oxides. All oxide backplanes are increasingly used because of their superior performance. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a back panel and a display device.

[0004] At least one embodiment of this disclosure provides a backplane comprising: a substrate; a transistor located on the substrate and including an active layer and a gate, the active layer being closer to the substrate than the gate; a first insulating layer located between the active layer and the gate; and a functional layer connected to the gate of the transistor.

[0005] For example, the functional layer is located on the side of the gate opposite to the substrate.

[0006] For example, the functional layer covers the side of the gate and the surface of the gate facing away from the substrate.

[0007] For example, the functional layer is in contact with the gate.

[0008] For example, the functional layer and the gate of the transistor are electrically connected.

[0009] For example, the transistor further includes a source and a drain, which are respectively connected to the active layer.

[0010] For example, at least one of the source and the drain is located in the same layer as the functional layer and is made of the same material.

[0011] For example, the functional layer, the source, and the drain are located in different layers.

[0012] For example, at least one of the source and the drain is on the same layer as the gate.

[0013] For example, in a direction parallel to the substrate and from the source to the drain, the size of the functional layer is larger than the size of the gate.

[0014] For example, the source and drain are made of transparent conductive materials.

[0015] For example, the source and the drain are located on the side of the active layer closer to the substrate.

[0016] For example, the backplate also includes pixel electrodes and connection electrodes, which are located in the same layer and are made of the same material.

[0017] For example, the drain electrode is connected to the active layer via the connection electrode, and the pixel electrode and the source electrode are integrally structured.

[0018] For example, the backplane also includes a first conductive element, the source electrode and the first conductive element are connected to the active layer through a first via and a second via, respectively, and the source electrode and the first conductive element include a transparent conductive material.

[0019] For example, the backplate also includes a second conductive element that is electrically connected to the drain electrode, and the second conductive element comprises a transparent conductive material.

[0020] For example, the second conductive element is in contact with the drain electrode.

[0021] For example, the backplate also includes a reflective layer located on the side of the source and drain electrodes closer to the substrate.

[0022] For example, the material of the gate is different from the material of the functional layer.

[0023] For example, the functional layer is a channel extension layer.

[0024] For example, the backsheet also includes a second insulating layer that covers the functional layer.

[0025] For example, the oxygen content of the second insulating layer is different from that of the functional layer.

[0026] For example, the oxygen content of the second insulating layer is less than the oxygen content of the functional layer.

[0027] For example, the active layer is in contact with the functional layer.

[0028] For example, the length of one side of the portion of the active layer that contacts the functional layer is less than or equal to 1 μm.

[0029] For example, the gate is conductive, while the functional layer is not conductive.

[0030] For example, the functional layer is a diffusion barrier layer.

[0031] This disclosure also provides a display device including any of the aforementioned back panels. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0033] Figure 1 is a schematic diagram of a backplate.

[0034] Figure 2 is a cross-sectional view of the dashed box K1 in Figure 1.

[0035] Figure 3 is a cross-sectional view of a backplate.

[0036] Figure 4 is a cross-sectional view of a back panel (display panel) provided in an embodiment of the present disclosure.

[0037] Figure 5 shows the etching process in which the active layer is partially conductiveized in the via during the etching process to form a via.

[0038] Figure 6 is a cross-sectional view of a backplate provided in an embodiment of this disclosure.

[0039] Figure 7 is a cross-sectional view of a backplate provided in an embodiment of this disclosure.

[0040] Figure 8 is a cross-sectional view of a backplate provided in an embodiment of this disclosure.

[0041] Figure 9 is a cross-sectional view of another backplate provided in another embodiment of this disclosure.

[0042] Figure 10 is a cross-sectional view of another backplate provided in another embodiment of this disclosure.

[0043] Figure 11 is a cross-sectional view of another backplate provided in another embodiment of this disclosure. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0045] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0046] The top-gate oxide backplane technology has developed rapidly in recent years. Efforts are continuously improving the mobility of oxide materials to meet the demands of high-value-added products, with the hope that it can eventually replace Low Temperature Poly-Silicon (LTPS) technology, allowing all display products to be manufactured using an all-oxide process. However, the biggest challenge currently facing high-mobility oxides is the device capability of transistors, such as thin-film transistors (TFTs), including ultra-short channel characteristics and stability. This is especially true in Organic Light-Emitting Diode (OLED) displays, where driving transistors currently require long-channel designs. To increase pixel density (Pixels Per Inch, PPI), other transistors in the pixel circuit need to achieve short-channel designs as much as possible. Achieving compatibility between long and short-channel transistor characteristics is quite difficult.

[0047] Figure 1 is a schematic diagram of a backplane. Figure 2 is a cross-sectional view of the dashed box K1 in Figure 1. Figures 1 and 2 show the substrate BS, gate GT, active layer AT, connector GTa, and data line DL (light-shielding pattern LSD). Figure 1 also shows the gate line GL, which is an integral structure with the gate GT. Figure 2 also shows the buffer layer BF, gate insulating layer GI, and passivation layer PVX.

[0048] As shown in Figure 1, current top-gate oxide backplanes use a method where the gate (GT) and source / drain electrodes are fabricated on the same layer to form transistors, and the data line (DL, light-shielding pattern, LSD) is placed underneath as the first conductive layer of the backplane, which is widely used. This structure, when applied to OLED products, offers advantages such as reduced mask count and lower cost. When applied to Liquid Crystal Display (LCD) products, this structure can improve aperture ratio and reduce power consumption. However, this structure requires special design when forming the vias of the gate insulating layer. Additionally, the connector GTa (drain) on the same layer as the gate (GT) needs to overlap downwards in the source / drain region. This design is not conducive to obtaining high PPI products because the active layer AT at the contact hole (via H0) needs to be partially exposed; otherwise, according to the self-alignment process, there will be a section of unconductable semiconductor material in the non-channel region, resulting in a significant decrease in current and making it unusable. Furthermore, sufficient space needs to be left for the downward overlap of the connector GTa on the same layer as the gate (GT).

[0049] The reason why the active layer AT needs to be partially exposed at the via H0 is as follows: Before the gate GT and the connector GTa are formed, the via H0 is formed. During the formation of the via H0, the semiconductor material in the via H0 is made conductive. The semiconductor material in the via H0 needs to have an exposed part to avoid having a non-conductive part.

[0050] Figure 3 is a cross-sectional view of a backplane. To reduce the design area occupied by the source or drain-under-mounted transistors shown in Figures 1 and 2 and improve product resolution, a backplane structure as shown in Figure 3 is currently being considered. As shown in Figure 3, the backplane includes a substrate BS, electrodes Ee, a light-shielding pattern LSD, a buffer layer BF, an active layer AT, a gate insulating layer GI, a gate GT, a passivation layer PVX1, a planarization layer PLN, a passivation layer PVX2, a common electrode CM, and a pixel electrode PX. The active layer (semiconductor layer) AT can be an oxide semiconductor such as indium gallium zinc oxide (IGZO).

[0051] As shown in Figure 3, the active layer (semiconductor layer) AT is connected downward to the electrode Ee through via H1. Via H1 penetrates the buffer layer BF. However, the conductorization process has the following difficulties for such a structure: (1) The active layer AT is relatively thin at the bevel angle of via H1, resulting in poor conductorization resistance and low transistor on-state current (Ion), which cannot meet the driving requirements. (2) When using a structure with self-aligned etching of the gate insulating layer, the conductorization of the semiconductor material needs to be achieved by bombardment such as dry etching and helium plasma (He Plasma). At this time, the part of the active pattern located at the via is easily damaged by over-etching, resulting in poor overlap.

[0052] In typical structures, via designs are complex, and changing complex designs brings the disadvantage of high process difficulty. The backplane and display device provided by the embodiments of this disclosure have at least one of the following effects: (1) For high PPI products, it solves the problem of easy negative bias of ultra-short channel TFTs, and can realize the beneficial effects of high PPI all-oxide bottom-emission / top-emission OLEDs and high aperture ratio liquid crystal displays (LCDs); (2) By combining the fabrication of opaque conductive materials with transparent conductive materials such as indium tin oxide (ITO), transparent design and process at the vias are realized.

[0053] Figure 4 is a cross-sectional view of a backplane (display panel) provided in an embodiment of this disclosure. Figure 5 is an etching process in which the active layer is partially conductiveized in the via during the etching process of forming a via.

[0054] As shown in Figure 4, a light-emitting film layer EML and a second electrode E2 are formed on the backplate to form a display panel. The first electrode E1, the light-emitting film layer EML, and the second electrode E2 constitute the light-emitting element EM. In the embodiments of this disclosure, the light-emitting element EM can be an organic light-emitting diode (OLED). The backplate shown in Figure 4 is a bottom-emitting structure.

[0055] For example, the light-emitting film layer (EML) can be configured as needed. For example, the light-emitting film layer (EML) may include a light-emitting layer, and may also include at least one of the following films: a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, a hole blocking layer, etc.

[0056] An embodiment of this disclosure provides a backplane, as shown in FIG4. The backplane includes: a substrate BS, a transistor M1, a gate insulating layer GI, and a channel extension layer L0. The transistor M1 is located on the substrate BS and includes an active layer AT and a gate GT. The active layer AT is closer to the substrate BS than the gate GT. The gate insulating layer GI is located between the active layer AT and the gate GT. The channel extension layer L0 is connected to the gate GT of the transistor M1.

[0057] Embodiments of this disclosure provide a backplane in which a channel extension layer L0 is connected to the gate GT of a transistor M1. The channel extension layer L0 is provided to reduce the size of the gate GT connected to the channel extension layer L0, thereby improving the PPI.

[0058] The grid insulating layer GI in the backplane shown in Figure 4 can be called the first insulating layer Lm.

[0059] For example, as shown in Figure 4, the channel extension layer L0 is located on the side of the gate GT facing away from the substrate BS. As shown in Figure 4, the gate GT is formed first, and then the channel extension layer L0 is formed, with the channel extension layer L0 located above the gate GT.

[0060] For example, as shown in Figure 4, in order to facilitate the channel expansion, the channel expansion layer L0 covers the side of the gate GT and the surface of the gate GT away from the substrate BS.

[0061] For example, as shown in Figure 4, to facilitate connection and fabrication, the channel extension layer L0 is in contact with the gate GT. The channel extension layer L0 is conductive, the gate GT is conductive, and both the channel extension layer L0 and the gate GT are made of conductive materials. For example, the channel extension layer L0 is electrically connected to the gate GT of transistor M1. For example, the material of the gate GT includes a metal, and the material of the channel extension layer L0 includes a conductive metal oxide. Of course, the embodiments of this disclosure are not limited to this. In other embodiments, the channel extension layer L0 may also be made of an insulating material.

[0062] For example, as shown in Figure 4, transistor M1 also includes a source Ea and a drain Eb, which are connected to the active layer AT respectively.

[0063] For example, as shown in Figure 4, the backplate also includes a first conductive element CC1. The source electrode Ea and the first conductive element CC1 are connected to the active layer AT through the first via V1 and the second via V2, respectively. The source electrode Ea and the first conductive element CC1 include transparent conductive materials to improve the aperture ratio.

[0064] For example, as shown in Figure 4, the backplate also includes a second conductive element CC2, which is electrically connected to the drain Eb. The second conductive element CC2 includes a transparent conductive material to improve the aperture ratio.

[0065] For large-size OLED display products, the mainstream mass-produced products are still bottom-emission OLEDs. The most important thing to improve when manufacturing bottom-emission OLEDs is the aperture ratio. In the embodiments disclosed herein, all transparent parts are set in the aperture display area, which can improve the aperture ratio or PPI and improve the display effect of the display product.

[0066] For example, to facilitate connection and fabrication, the second conductive element CC2 is in contact with the drain Eb.

[0067] As shown in Figure 4, the drain Eb is located at the bottom. In embodiments of this disclosure, the bottom-mounted source or drain can share the same film layer with other components, such as the light-shielding pattern LSD, which helps to reduce parasitic capacitance and power consumption. In embodiments of this disclosure, bottom-mounted source or drain means that the source or drain of the transistor is located below the active layer. In some embodiments, the drain Eb can be integrated with the light-shielding pattern LSD, but is not limited thereto.

[0068] As shown in Figure 4, a conductive pattern layer LY1 is provided on the substrate BS, and a drain electrode Eb / light-shielding pattern LSD is located on the conductive pattern layer LY1; a conductive pattern layer LY2 is provided on the conductive pattern layer LY1, and the conductive pattern layer LY2 includes a second conductive element CC2; a buffer layer BF is provided on the conductive pattern layer LY2; an active layer AT is provided on the buffer layer BF; a gate insulating layer GI is provided on the active layer AT; a conductive pattern layer LY3 is formed on the gate insulating layer GI, and the conductive pattern layer LY3 includes a gate GT; a conductive pattern layer LY4 is formed on the conductive pattern layer LY3, and the conductive pattern layer LY4 includes a source electrode Ea, a channel extension layer L0, a first conductive element CC1, and a third conductive element CC3; a passivation layer PVX is formed on the conductive pattern layer LY4; a color filter layer CF is formed on the passivation layer PVX; a planarization layer PLN is formed on the color filter layer CF; a pixel definition layer PDL is formed on the planarization layer PLN; a light-emitting layer EML is formed on the pixel definition layer PDL; and a second electrode E2 is formed on the light-emitting layer EML.

[0069] In one embodiment, as shown in FIG4, a conductive pattern layer LY1 is first formed on a substrate BS, such as a glass substrate. For example, a metal wire can be fabricated using conventional metal wire materials such as copper (Cu). Simultaneously, based on the structural characteristics of the top-gate transistor with its source and drain positioned below each other, a drain electrode Eb (light-shielding pattern LSD) is formed. Subsequently, a conductive pattern layer LY2 is formed on this drain electrode Eb (light-shielding pattern LSD). The conductive pattern layer LY2 includes a second conductive element CC2. The conductive pattern layer LY2 can leave patterns at the locations where contact with the upper surface is required and at the locations of transparent capacitors, respectively. Next, a buffer layer (BF) is formed. The buffer layer (BF) can be an inorganic thin film, typically a single-layer or composite film of SiNx and SiOx, with a thickness generally greater than 0.3 μm. Then, the active film is fabricated and patterned. The active film uses a high-mobility oxide with a mobility greater than or equal to 20. Next, a gate insulating film is formed, typically a SiOx film. At this point, vias are formed in the gate insulating film to form the gate insulating layer (GI). Vias are simultaneously fabricated at locations where they need to connect to the drain electrode (Eb) (light-shielding pattern LSD) and at locations only connected to the active layer. Due to the conductive pattern layer LY4... The active layer AT and the second conductive element CC2 are both transparent layers, so they do not affect light emission in the pixel display area. Next, a conductive pattern layer LY3 is fabricated. LY3 includes a gate GT and can be a Cu metal-based thin film, ensuring that the exposed portions of the active pattern at the vias are not etched away. Then, a conductive pattern layer LY4 is formed on the conductive pattern layer LY3. The first conductive element CC1 is connected to the second conductive element CC2 via a via where it needs to be connected to the data signal (drain Eb). The source Ea of the transistor is connected to the active layer AT. At this point, [further details are needed]. The etching of the gate insulating layer and the conductor fabrication of the semiconductor layer can be achieved using a self-aligned process between the conductive pattern layer LY4 and the gate insulating film. The portion of the gate insulating film located in the non-via area of ​​the conductive pattern layer LY4 is retained to form the gate insulating layer GI. This is the semiconductor material conductor fabrication process used in large-size products. Especially above the gate GT, the channel extension layer L0, which overlaps the gate GT, is larger than the gate GT itself. The actual channel length of the transistor is the length of the channel extension layer L0. This allows the opaque gate GT to be shorter, maximizing the use of transparent space to improve the aperture ratio. The channel extension layer L0 can block diffusion without affecting light emission. It should be noted that for small-to-medium-sized products requiring bottom emission, we can form vias in the gate insulating film and then perform an ion implantation process, as shown in Figure 5. In this case, the semiconductor material conductor fabrication process can still be achieved. After the channel extension layer L0 above the gate GT is fabricated, the passivation layer PVX, color filter layer CF, planarization layer PLN, and first electrode E1 can be fabricated. Finally, the pixel boundary layer PDL is fabricated to form the backplane. A light-emitting film layer EML and a second electrode E2 are formed on the back plate to form a display panel.

[0070] The color filter layer (CF) is located on the array substrate, which is the backplane or display panel that forms the structure of the color filter on array (COA).

[0071] For example, as shown in Figure 4, the first electrode E1 is the anode and the second electrode E2 is the cathode.

[0072] Figure 4 also shows the pixel opening OPN of the pixel boundary layer PDL, where the pixel opening OPN is the light-emitting area of ​​the sub-pixel.

[0073] For example, to facilitate fabrication, at least one of the source electrode Ea and the drain electrode Eb is located in the same layer as the channel extension layer L0 and is made of the same material. As shown in Figure 4, the source electrode Ea is located in the same layer as the channel extension layer L0 and is made of the same material. In other embodiments, both the source electrode Ea and the drain electrode Eb may be located in the same layer as the channel extension layer L0 and are made of the same material.

[0074] Figure 6 is a cross-sectional view of a backplate provided in an embodiment of the present disclosure. Compared with the backplate shown in Figure 4, the backplate shown in Figure 6 is a top-emitting structure.

[0075] Compared to the backplate shown in Figure 4, the drain electrode Eb (light-shielding pattern LSD) in the backplate shown in Figure 6 serves as a reflective layer to reflect the light emitted by the first electrode E1, thereby improving the light efficiency and achieving the effect of high PPI and high aperture ratio for top emission. That is, the drain electrode Eb (light-shielding pattern LSD) is shared as the reflective layer of the first electrode E1.

[0076] It should be noted that in the conventional backplane fabrication of top-emitting diodes, the first electrode E1 (anode) uses an opaque aluminum (Al) or silver (Ag) sublayer that has a reflective effect, which is then combined with an indium tin oxide (ITO) sublayer that contacts the light-emitting film layer EML. In the backplane shown in Figure 6, the first electrode E1 (anode) uses a layer of pure indium tin oxide (ITO) material that contacts the light-emitting film layer EML. The reflective layer (light-shielding pattern LSD / drain electrode Eb) is designed at the bottom, which has a certain optical path difference. The light-emitting film layer EML can be adjusted according to the optical conditions.

[0077] For example, as shown in Figure 6, the backplate also includes a reflective layer RL (light-shielding pattern LSD), which is located on the side of the source electrode Ea and the drain electrode Eb close to the substrate BS.

[0078] The rest can be referred to in the relevant description in Figure 4, and will not be repeated here.

[0079] Figures 4 and 6 illustrate transistor M1 as a switching transistor. However, the embodiments of this disclosure are not limited thereto. Transistor M1 in Figures 4 and 6 can also be a driving transistor. The active layer of the switching transistor can be made of a high-mobility semiconductor material, while the active layer of the driving transistor can be made of a low-mobility semiconductor material.

[0080] For example, as shown in Figures 4 and 6, in a direction parallel to the substrate BS and pointing from the source Ea to the drain Eb, the size of the channel extension layer L0 is larger than the size of the gate GT.

[0081] Figure 7 is a cross-sectional view of a backplane provided in an embodiment of the present disclosure. As shown in Figure 7, the backplane includes: a substrate BS, a transistor M1, a gate insulating layer GI, and a channel extension layer L0; the transistor M1 is located on the substrate BS and includes an active layer AT and a gate GT, wherein the active layer AT is closer to the substrate BS than the gate GT; the gate insulating layer GI is located between the active layer AT and the gate GT; the channel extension layer L0 is connected to the gate GT of the transistor M1.

[0082] An embodiment of this disclosure provides a backplane, as shown in FIG7, wherein a channel extension layer L0 is connected to the gate GT of transistor M1. The channel extension layer L0 is provided to reduce the size of the gate GT connected to the channel extension layer L0, thereby improving PPI.

[0083] As shown in Figure 7, the diffusion barrier layer L0 can prevent hydrogen ions from diffusing into the channel. The channel length of transistor M1 is actually the length of the gate GT. By setting the diffusion barrier layer L0, on the one hand, hydrogen elements are prevented from diffusing into the channel during the fabrication of the upper film layer; on the other hand, the opaque gate GT can be made shorter, maximizing the use of the transparent space to improve the aperture ratio.

[0084] For example, as shown in Figure 7, the diffusion barrier layer L0 is located on the side of the gate GT away from the substrate BS.

[0085] For example, as shown in Figure 7, the diffusion barrier layer L0 covers the side surface of the gate GT and the surface of the gate GT facing away from the substrate. The diffusion barrier layer L0 covers the gate GT.

[0086] As shown in Figure 7, the active layer AT includes a first channel portion ATa, a connecting portion ATb, and a source / drain region ATc. The first channel portion ATa is connected to the source / drain region ATc through the connecting portion ATb. The resistance of the connecting portion ATb is between that of the first channel portion ATa and the source / drain region ATc. The connecting portion ATb is not a channel.

[0087] The grid insulating layer GI in the backplane shown in Figure 7 can be referred to as the first insulating layer Lm.

[0088] For example, as shown in Figure 7, the backplane also includes an interlayer insulating layer ILD2, which covers the diffusion barrier layer L0 (interlayer insulating layer ILD1) and the active layer AT. The interlayer insulating layer ILD2 also covers the gate insulating layer GI and the gate GT.

[0089] As shown in Figure 7, the backplane also includes transistor M2, which is a driving transistor, and transistor M1, which is a switching transistor. The active layer of the switching transistor can be made of a high-mobility semiconductor material, while the active layer of the driving transistor can be made of a low-mobility semiconductor material. Transistor M1 includes an active layer AT, a gate GT, a source Ea, and a drain Eb. Transistor M2 includes an active layer AT2, a gate GT2, a source Ec, and a drain Ed. For example, source Ea, drain Eb, source Ec, and drain Ed are all located on the conductive pattern layer LY2.

[0090] For example, as shown in Figure 7, the oxygen content of the interlayer insulation layer ILD2 is different from that of the diffusion barrier layer L0. For example, the oxygen content of the interlayer insulation layer ILD2 is less than that of the diffusion barrier layer L0.

[0091] As shown in Figure 7, the interlayer insulation layer ILD2 can also be called the second insulation layer Ln.

[0092] For example, as shown in Figure 7, the diffusion barrier layer L0, the source electrode Ea, and the drain electrode Eb are located in different layers. As shown in Figure 7, the source electrode Ea and the drain electrode Eb are located in the conductive pattern layer LY2, and the diffusion barrier layer L0 is located below the conductive pattern layer LY2.

[0093] For example, as shown in Figure 7, the gate GT and the diffusion barrier layer L0 are made of different materials. The gate GT is made of a conductive material, such as a metal, while the diffusion barrier layer L0 is made of an insulating material, such as silicon oxide. For example, as shown in Figure 7, the gate GT is conductive, while the diffusion barrier layer L0 is non-conductive. As shown in Figure 7, the diffusion barrier layer L0 can also be called the interlayer insulating layer ILD1. The diffusion barrier layer L0 can also be made of insulating materials other than silicon oxide. The diffusion barrier layer L0 is a transparent insulating layer.

[0094] During the fabrication of the gate insulating layer GI (silicon oxide or silicon nitride, or silicon oxynitride), silane is used, which results in hydrogen in the film. Hydrogen can affect the channel. Using an insulating layer with high oxygen content on the active layer AT can suppress hydrogen diffusion into the channel.

[0095] In some embodiments, as shown in FIG7, an inorganic layer such as SiOx can be used as the diffusion barrier layer L0 of a short-channel transistor, and as shown in FIG7, the interlayer insulating layer ILD1 serves as the diffusion barrier layer L0.

[0096] As shown in Figure 7, the diffusion barrier layer L0 in the backplane prevents hydrogen from diffusing into the channel. For example, as shown in Figure 7, the diffusion barrier layer L0 is in contact with the active layer AT, which helps to prevent hydrogen (H) from diffusing into the channel.

[0097] As shown in Figure 7, transistor M1 is a short-channel transistor and serves as a switching transistor, while transistor M2 is a driving transistor. Long-channel driving transistors are typically used in the backplane of OLED displays. If the interlayer insulating layer ILD1 in the backplane shown in Figure 7 has a low oxygen content, and this low-oxygen-content ILD1 contacts the active layer AT, it's difficult to prevent hydrogen from diffusing into the channel during the fabrication of the upper film, leading to a negative bias in the threshold voltage Vth of transistor M1. Therefore, we fabricate the interlayer insulating layer ILD1 with a high oxygen content, such as a high-oxygen-content SiOx layer. By controlling the contact distance between the interlayer insulating layer ILD1 and the active layer AT, we can prevent hydrogen (H) from diffusing into the channel. For example, the oxygen content (N2O:SiH4) of the interlayer insulating layer ILD1 can be >50:1. Alternatively, the oxygen content can be increased by simultaneously controlling the deposition temperature of the insulating film, such as the SiOx film. For example, the gate insulating layer GI can be formed by lowering the temperature (below 230°C). However, to ensure the conductivity process, the interlayer insulating layer (ILD2) needs to be fabricated as a low-oxygen insulating layer, such as a SiOx thin film, with N2O:SiH4 ≤ 40:1. In this way, for hydrogen (H) in the interlayer insulating layer (ILD2) and the layers above it to diffuse into the channel, it must pass through the interlayer insulating layer (ILD1). Simultaneously, the surface of the interlayer insulating layer (ILD1) in contact with the active layer (AT) is also in a high-oxygen-content state, i.e., a high-acceptor-defect state, which effectively prevents hydrogen diffusion and ensures the electrical characteristics of the short-channel transistor (transistor M1).

[0098] As shown in Figure 7, the diffusion barrier layer L0 is placed at the switching transistor where the channel length is relatively short in order to improve the characteristics of the switching transistor.

[0099] For example, as shown in Figure 7, the contact distance between the interlayer insulating layer ILD1 and the active layer AT1 cannot be too long. An excessively long contact distance would cause the high-resistivity portion of the active layer AT (connection portion ATb) to become too far away, leading to a decrease in transistor current. Therefore, we control this distance to approximately 1 μm on each side. As shown in Figure 7, the length of the connection portion ATb is less than or equal to 1 μm. The lateral length of the connection portion ATb is less than or equal to 1 μm. The size limitation of the connection portion located to the right of the connection portion ATa can be referenced to the size limitation of the first connection portion located to the left of the first channel portion ATa.

[0100] For example, if the gate GT and the gate insulating layer GI are etched using the same photoresist pattern as a mask, the gate GT will be etched laterally, resulting in a smaller lateral dimension than the gate insulating layer GI.

[0101] The conventional process uses a self-aligned process, achieving barrier at both ends of the gate insulating layer GI through differences in etching bias. However, this method has a short barrier distance, which is insufficient for ultra-high mobility oxides, leading to a tendency for the transistor's threshold voltage Vth to become negatively biased. Furthermore, the gate insulating layer GI is in contact with the channel of transistor M1, directly affecting the overall characteristics of transistor M1. Adjusting the oxygen content of the gate insulating layer GI is very limited. Therefore, using a non-self-aligned method to control the size of the gate insulating layer GI is not as effective as forming the backplane shown in Figure 7.

[0102] For example, as shown in Figure 7, in a direction parallel to the substrate BS and pointing from the source Ea to the drain Eb, the size of the channel extension layer L0 is larger than the size of the gate GT.

[0103] Figure 8 is a cross-sectional view of a backplate according to an embodiment of the present disclosure. Figure 9 is a cross-sectional view of another backplate according to another embodiment of the present disclosure. Figure 10 is a cross-sectional view of another backplate according to another embodiment of the present disclosure.

[0104] As shown in Figure 8, the gate GT2 is larger than the gate GT1, and the gate GT2 serves as the channel extension layer L0. The gate GT2 (channel extension layer L0) is located on the side of the gate GT1 away from the substrate BS. The size of the transistor channel is determined by the gate GT2 (channel extension layer L0). The function of the channel extension layer L0 is as described previously and will not be repeated here.

[0105] For example, as shown in Figures 9 and 10, the size of gate GT1 is larger than that of gate GT2, and gate GT1 serves as the channel extension layer L0. As shown in Figures 9 and 10, gate GT1 (channel extension layer L0) is located on the side of gate GT2 closest to the substrate BS. The size of the transistor's channel is determined by gate GT1 (channel extension layer L0). The function of the channel extension layer L0 is as described previously and will not be repeated here.

[0106] As shown in Figures 8 to 10, the active layer AT includes a first channel section ATa, a second channel section ATb, and a source / drain region ATc.

[0107] The gate insulation layer GI1 in the backplane shown in Figures 8 to 10 can be referred to as the first insulation layer Lm.

[0108] As shown in Figures 8 to 10, the conductive pattern layer LY1 includes a gate GT1 (channel extension layer L0) and a gate GT2.

[0109] As shown in Figures 8 to 10, the channel extension layer L0 is made of a transparent conductive material, such as a conductive metal oxide, such as indium tin oxide.

[0110] As shown in Figures 8 to 10, the gate GT2 can be made of a conductive material such as a metal.

[0111] In some embodiments, as shown in Figures 8 to 10, the gate GT1 and gate insulating layer GI1 are first self-aligned to form the gate GT1 and gate insulating layer GI1 of the transistor. The gate GT1 is fabricated after the active layer AT is formed. The conductive region of the active layer AT can be conductiveized according to normal procedures to form the source-drain region ATc. After the self-alignment process of the gate GT1 and gate insulating layer GI1 is completed, the gate insulating layer GI2 is formed. The gate insulating layer GI2 can be an inorganic film layer, such as SiOx. It is necessary to control the oxygen content of SiOx in the gate insulating layer GI2. For high mobility materials, the gate insulating layer GI1 usually requires a high oxygen content SiOx, while the gate insulating layer GI2, since it contacts the active layer AT in the conductive region (source-drain region), requires a low oxygen content SiOx film. Otherwise, the conduction current Ion of the transistor will be too low. A hole is drilled at the corresponding position of the gate insulating layer GI2, and then the gate GT2 is formed. Cu metal can be used to form the gate GT2 above the gate GT1. The source Ea and drain Eb are formed at both ends of the transistor.

[0112] Compared to the backplane shown in Figures 4 to 6, the backplane shown in Figures 9 to 10 first forms a gate GT1 (channel extension layer L0), then forms a gate GT2 above the gate GT1 (channel extension layer L0), and forms an interlayer insulating layer GI2 in the intermediate layer between the gate GT2 and the gate GT1 (channel extension layer L0). The interlayer insulating layer GI2 can be an inorganic insulating layer.

[0113] For example, as shown in Figure 8, the gate GT2 serves as the channel extension layer L0. In the direction parallel to the substrate BS and pointing from the source Ea to the drain Eb, the size of the channel extension layer L0 is larger than the size of the gate GT1.

[0114] As shown in Figure 8, the gate GT1 is located on the conductive pattern layer LY1 and can be made of a conductive material such as a metal. As shown in Figure 8, the gate GT2 is located on the conductive pattern layer LY2 and can be made of a conductive material such as a metal.

[0115] For example, as shown in Figures 9 and 10, in a direction parallel to the substrate BS and pointing from the source Ea to the drain Eb, the size of the channel extension layer L0 is larger than the size of the gate GT2.

[0116] The backplanes shown in Figures 8 to 10 can also utilize the channel extension layer L0 to block the influence of the low-oxygen inorganic film on the channel, i.e., the diffusion effect, to avoid negative bias of the transistor characteristic threshold voltage Vth. The channel length of the backplane shown in Figure 8 is defined by the gate GT2 (channel extension layer L0), while the channel length of the backplanes shown in Figures 9 and 10 is defined by the gate GT1 (channel extension layer L0). It is indeed impossible to achieve both a short channel length and genuine prevention of the negative threshold voltage Vth caused by the diffusion effect. However, the backplanes shown in Figures 8 to 10 allow the gate GT2 to be fabricated on the same layer as the source Ea and drain Eb, ensuring that the via size above the active layer AT is minimized, without exposing the active layer AT. More effects can be achieved when using the channel extension layer L0 for length compensation.

[0117] As shown in Figures 9 and 10, the source and drain electrodes of the transistor are fabricated using conductive materials such as metal; that is, the source Ea and drain Eb can be made of conductive materials such as metal. Figures 9 and 10 show that the source Ea and drain Eb are located in the conductive pattern layer LY2. For example, the gate GT2, source Ea, and drain Eb are located in the same conductive pattern layer LY2, which is made of conductive materials such as metal. Figures 9 and 10 show vias Va and Vb. As shown in Figures 9 and 10, via Va penetrates the interlayer insulating layer GI2, and via Vb penetrates the interlayer insulating layer GI2.

[0118] Figure 10 shows how this backplane is used in a liquid crystal display (LCD). The channel extension layer L0 and the pixel electrode PX are fabricated on the same layer, both located on the conductive pattern layer LY1, saving the patterning steps for the pixel electrode PX. Compared to the backplane shown in Figure 9, the backplane shown in Figure 8 has a larger gate GT2 to cover the gate GT1 (channel extension layer L0). The size of gate GT2 can be greater than or equal to the size of gate GT1 (channel extension layer L0). Further, for example, the lateral dimension of gate GT2 can be greater than or equal to the lateral dimension of gate GT1 (channel extension layer L0). Since the gate insulating layer GI1 is close to the channel, the oxygen content of the gate insulating layer GI1 cannot be increased indefinitely, otherwise it will lead to forward bias of the transistor characteristics. Therefore, the barrier to diffusion is limited. When ensuring short-channel transistors, if the size of the gate GT2 is slightly larger than the size of the gate GT1 (channel extension layer L0), the oxygen content of the gate insulating layer GI2 can be further increased. Under the premise of ensuring channel stability, the gate insulating layer GI2 can be further used to block diffusion and achieve stable short-channel TFT characteristics.

[0119] Figure 11 is a cross-sectional view of another backplate provided in another embodiment of this disclosure. For example, as shown in Figure 11, the backplate further includes a pixel electrode PX and a connection electrode CE, which are located in the same layer and are made of the same material.

[0120] The backplane shown in Figure 11 can be applied to liquid crystal display (LCD) products. It uses an active layer AT-overlapping method to form transparent vias at the via locations, and simultaneously forms a channel extension layer L0 on the gate GT. The channel extension layer L0 and the common electrode CM are located on the same layer, both situated on the conductive pattern layer LY4. The conductive pattern layer LY4 can be made of a transparent conductive material such as indium tin oxide.

[0121] As shown in Figure 11, for bottom-emitting OLED products, transparent conductive materials such as ITO are used for the source and drain electrodes of the transistors. Specifically, the source electrode Ea and the drain electrode Eb are made of transparent conductive material such as ITO, forming transparent vias, which helps to improve the aperture ratio. Figure 11 shows vias Va and Vb, both of which are transparent vias. As shown in Figure 11, via Va penetrates the buffer layer BF, and the interlayer insulating layer GI2 penetrates the buffer layer BF.

[0122] For example, as shown in Figure 11, the source Ea and drain Eb are located on the side of the active layer AT that is close to the substrate BS, and the active layer AT is connected to the source Ea and drain Eb respectively by bottom overlap.

[0123] For example, as shown in Figure 11, the drain electrode Eb is connected to the active layer AT via the connecting electrode CC3, and the pixel electrode PX and the source electrode Ea are a single integrated structure. As shown in Figure 11, the pixel electrode PX and the connecting electrode CC3 are located in the conductive pattern layer LY2. The conductive pattern layer LY2 can be made of a conductive material such as indium tin oxide.

[0124] For example, as shown in Figure 11, the backplane also includes a light-shielding pattern LSD (drain Eb) located in the conductive pattern layer LY1. The conductive pattern layer LY1 can be made of a conductive material such as metal.

[0125] For example, as shown in Figure 11, the gate GT is located in the conductive pattern layer LY3. The conductive pattern layer LY3 can be made of a conductive material such as metal.

[0126] For example, both the channel extension layer L0 and the diffusion barrier layer L0 can be referred to as the functional layer L0.

[0127] Embodiments of this disclosure also provide a display device including any of the aforementioned backplates.

[0128] For example, the display device provided in the embodiments of this disclosure can be an organic light-emitting diode display device and a liquid crystal display device, as well as any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator, including the display device. The embodiments of this disclosure include, but are not limited to, these.

[0129] Embodiments of this disclosure provide a back panel and a display device that have at least one of the following effects.

[0130] (1) A channel extension layer is provided above the gate so that the opaque gate can be made shorter to improve PPI.

[0131] (2) Based on the top gate bottom contact, a structure formed of transparent conductive material is made on the light-shielding pattern LSD and on or under the gate to obtain a product with high PPI.

[0132] (3) Capacitors can use plates made of transparent conductive materials to increase the aperture ratio.

[0133] For example, in the backplane provided in the embodiments of this disclosure, directions X and Y are parallel to the main surface of the substrate BS. Directions X and Y intersect. For example, directions X and Y are perpendicular. Direction Z is perpendicular to the main surface of the substrate BS. Direction Z is perpendicular to direction X and perpendicular to direction Y. The main surface of the substrate BS is the surface used to fabricate various components.

[0134] For example, in the backplane provided in the embodiments of this disclosure, the substrate can be a flexible substrate or a rigid substrate.

[0135] For example, in the backplane provided in the embodiments of this disclosure, at least one of the conductive pattern layer LY1, conductive pattern layer LY2, and conductive pattern layer LY3 may be made of a conductive material such as metal.

[0136] For example, in the backplane provided in the embodiments of this disclosure, at least one of the buffer layer BF, gate insulating layer GI1, gate insulating layer GI2, interlayer insulating layer ILD, interlayer insulating layer ILD1, interlayer insulating layer ILD2, and passivation layer PVX can be made of inorganic insulating material.

[0137] For example, in the backplane provided in the embodiments of this disclosure, at least one of the planarization layer PLN and the pixel defining layer PDL can be made of an organic insulating material.

[0138] For example, in embodiments of this disclosure, the semiconductor material may be an oxide semiconductor material. For instance, low-mobility oxide materials include indium gallium zinc oxide (IGZO), and high-mobility oxide materials include indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or IZO-doped rare-earth element-related materials, as well as other oxide materials with high indium (In) content. Embodiments of this disclosure include, but are not limited to, these.

[0139] In the embodiments of this disclosure, components located in the same layer means that these components are formed from the same film layer through a patterning process, for example, they can be constructed using the same patterning process.

[0140] The following points need to be explained:

[0141] (1) Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by a person of ordinary skill in the art to which this disclosure pertains.

[0142] (2) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0143] (3) For clarity, the thickness of layers or regions is magnified in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0144] (4) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other.

[0145] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A back panel, comprising: Substrate; A transistor is located on the substrate and includes an active layer and a gate, wherein the active layer is closer to the substrate than the gate. A first insulating layer is located between the active layer and the gate. as well as The functional layer is connected to the gate of the transistor.

2. The backplate according to claim 1, wherein, The functional layer is located on the side of the gate opposite to the substrate.

3. The backplate according to claim 2, wherein, The functional layer covers the sidewalls of the gate and the surface of the gate facing away from the substrate.

4. The backplate according to any one of claims 1-3, wherein, The functional layer is in contact with the gate.

5. The backplate according to any one of claims 1-4, wherein, The functional layer and the gate of the transistor are electrically connected.

6. The backplate according to any one of claims 1-5, wherein, The transistor further includes a source and a drain, which are respectively connected to the active layer.

7. The backplate according to claim 6, wherein, At least one of the source and the drain is located in the same layer as the functional layer and is made of the same material.

8. The backplate according to claim 7, wherein, The functional layer, the source, and the drain are located in different layers.

9. The backplate according to claim 8, wherein, At least one of the source and the drain is on the same layer as the gate.

10. The backplate according to any one of claims 6-9, wherein, The size of the functional layer is larger than the size of the gate in a direction parallel to the substrate and from the source to the drain.

11. The backplate according to any one of claims 6-10, wherein, The source and drain are made of transparent conductive materials.

12. The backplate according to claim 8, wherein, The source and the drain are located on the side of the active layer closest to the substrate.

13. The backplate according to claim 12, further comprising pixel electrodes and connection electrodes, wherein, The pixel electrode and the connection electrode are located in the same layer and are made of the same material.

14. The backplate according to claim 13, wherein, The drain electrode is connected to the active layer via the connecting electrode, and the pixel electrode and the source electrode are integrally structured.

15. The backplate according to any one of claims 6-14, further comprising a first conductive element, wherein, The source electrode and the first conductive element are respectively connected to the active layer through a first via and a second via, and the source electrode and the first conductive element comprise transparent conductive materials.

16. The backplate according to claim 15, further comprising a second conductive element, wherein, The second conductive element is electrically connected to the drain electrode, and the second conductive element comprises a transparent conductive material.

17. The backplate according to claim 16, wherein, The second conductive element is in contact with the drain electrode.

18. The back panel according to any one of claims 1-17, further comprising a reflective layer, wherein, The reflective layer is located on the side of the source and drain electrodes closer to the substrate.

19. The backplate according to any one of claims 1-18, wherein, The material of the gate is different from the material of the functional layer.

20. The backplate according to any one of claims 1-19, wherein, The functional layer is a channel extension layer.

21. The back sheet according to any one of claims 1-4, further comprising a second insulating layer, wherein, The second insulating layer covers the functional layer.

22. The backplate according to claim 21, wherein, The oxygen content of the second insulating layer is different from that of the functional layer.

23. The backplate according to claim 22, wherein, The oxygen content of the second insulating layer is less than that of the functional layer.

24. The backplate according to any one of claims 1-4, 21-23, wherein, The active layer is in contact with the functional layer.

25. The backplate according to claim 24, wherein, The length of one side of the portion of the active layer that contacts the functional layer is less than or equal to 1 μm.

26. The backplate according to any one of claims 1-4, 21-25, wherein, The gate is conductive, while the functional layer is not conductive.

27. The backplate according to any one of claims 1-4, 21-26, wherein, The functional layer is a diffusion barrier layer.

28. A display device comprising a back panel according to any one of claims 1-27.

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