Display apparatus

Abstract

The present application provides a display apparatus, comprising: a plurality of rows of pixels; and multiple stages of gate driving circuits. Each gate driving circuit comprises an eighteenth transistor, a twenty-first transistor, a twenty-second transistor, and a fifth capacitor. One electrode plate of the fifth capacitor is electrically connected to a first control node I, and the other electrode plate thereof is electrically connected to a first or second low-level signal input end. A first low-level signal line or a second low-level signal line is located between the fifth capacitor and a first high-level signal line. The present application mitigates display abnormalities occurring at demarcations between different regions of the display apparatus when a frequency division display function is enabled.

Description

Display device Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] To provide better display effects and user experience, frequency division display technology is widely used in OLED display panels. Frequency division display technology refers to using different refresh rates in different areas of the same display panel. For example, a refresh rate of 120Hz is used in areas displaying dynamic content, while a refresh rate of 60Hz is used in areas displaying static content. This ensures the smoothness of dynamic images while reducing power consumption.

[0003] However, in OLED display panels that use frequency division display technology, when different areas switch refresh rates, display abnormalities may occur at the boundaries between different areas due to design issues in the gate drive circuit. These display abnormalities can affect the display effect and user experience. Invention Overview

[0004] The purpose of this application is to provide a display device to improve the display abnormality that occurs at the boundary between different areas when the display device enables the frequency division display function.

[0005] Embodiments of this application provide a display device, including a display panel. The display panel includes multiple rows of pixels and multiple levels of gate driving circuits. The first-level gate driving circuit includes: a first gate driving sub-circuit, which includes a first-stage transmission circuit and a first output circuit. The first output circuit includes: an eighteenth transistor, the gate of which is electrically connected to a first control node I, and the source of which is electrically connected to a second control node F of the first-stage transmission circuit; and a twenty-first transistor, the gate of which is electrically connected to a third control node G of the first-stage transmission circuit, the source of which is electrically connected to a first low-level signal input terminal of the display panel, and the drain of which is electrically connected to the first... A first scan signal output terminal of a gate driving sub-circuit is electrically connected; a twenty-second transistor, the gate of which is electrically connected to the drain of the eighteenth transistor, the source of which is electrically connected to the first high-level signal input terminal of the display panel, and the drain of which is electrically connected to the first scan signal output terminal; and a fifth capacitor, one plate of which is electrically connected to the first control node I, and the other plate of which is electrically connected to the first low-level signal input terminal; wherein, in the top view of the gate driving circuit, the first high-level signal line is located on the first side of the first low-level signal line, and the fifth capacitor is located on the second side of the first low-level signal line opposite to the first side.

[0006] Embodiments of this application also provide a display device, including a display panel. The display panel includes multiple rows of pixels and multiple levels of gate driving circuits. The first level of the gate driving circuit includes: a first gate driving sub-circuit, which includes a first-stage transmission circuit and a first output circuit. The first output circuit includes: an eighteenth transistor, the gate of which is electrically connected to a first control node I, and the source of which is electrically connected to a second control node F of the first-stage transmission circuit; and a twenty-first transistor, the gate of which is electrically connected to a third control node G of the first-stage transmission circuit, the source of which is electrically connected to a first low-level signal input terminal of the display panel, and the drain of which is electrically connected to a first scan signal output terminal of the first gate driving sub-circuit. The circuit includes: a 22nd transistor, the gate of which is electrically connected to the drain of the 18th transistor; the source of which is electrically connected to the first high-level signal input terminal of the display panel; and the drain of which is electrically connected to the first scan signal output terminal; and a fifth capacitor, one plate of which is electrically connected to the first control node I; and the other plate of which is electrically connected to the second low-level signal input terminal of the display panel; wherein, in the top view of the gate driving circuit, the first high-level signal line is located on the first side of the second low-level signal line, the fifth capacitor is located on the second side of the second low-level signal line opposite to the first side, and the first low-level signal line is located on the side of the first high-level signal line away from the second low-level signal line. Beneficial effects

[0007] In the display device provided in the embodiments of this application, since one plate of the fifth capacitor in the first output circuit of the first gate driving sub-circuit in the gate driving circuit is electrically connected to node I of the first output circuit, and the other plate is electrically connected to the first low-level signal input terminal of the first gate driving sub-circuit or the second low-level signal input terminal of the second gate driving sub-circuit, and the first high-level signal input terminal is insulated from the fifth capacitor, when the first control signal input terminal inputs the first control signal to node I, the fifth capacitor will not have a coupling effect on the potential of the signal transmitted by the first high-level signal input terminal, thereby avoiding the problem of potential fluctuation of the signal transmitted by the first high-level signal input terminal due to the coupling effect between the fifth capacitor and the first high-level signal input terminal.

[0008] Furthermore, since the potential of the signal transmitted at the first high-level signal input terminal will not fluctuate due to the coupling effect of the fifth capacitor, and the first gate driving sub-circuit generates the first scan signal based on the signals transmitted at the first high-level signal input terminal and the first low-level signal input terminal, the potential of the first scan signal will also not fluctuate due to the coupling effect of the fifth capacitor. Because the potential of the first scan signal does not fluctuate, the turning on or off of the third transistor in the pixel driving circuit will not be affected. The second capacitor, which is electrically connected to the drain of the third transistor, will not apply coupling to the gate of the second transistor, which is also electrically connected to the second capacitor, thus not affecting the turning on or off of the second transistor, thereby avoiding the problem of abnormal data signal writing.

[0009] In addition, since the data signal can be written to the pixels normally, when the display device enables the frequency division display function, there will be no display abnormalities caused by abnormal data signal writing at the boundary between different areas, thereby improving the display effect of the display device when the frequency division display function is enabled.

[0010] Furthermore, since one plate of the fifth capacitor is electrically connected to node I of the first output circuit, and the other plate is electrically connected to the first low-level signal input terminal of the first gate driver sub-circuit or the second low-level signal input terminal of the second gate driver sub-circuit, instead of being electrically connected to the first high-level signal input terminal, in the layout of the gate driver circuit, the first low-level signal line of the first gate driver sub-circuit or the second low-level signal line of the second gate driver sub-circuit can be placed between the whole formed by the first high-level signal line and the second high-level signal line and the fifth capacitor. This makes the layout of the first high-level signal line and the second high-level signal line more uniform, avoiding the uneven layout of the first high-level signal line and the second high-level signal line caused by the fifth capacitor being electrically connected to the first high-level signal input terminal and occupying the trace space of the first high-level signal line and / or the second high-level signal line. This avoids the problem of uneven load caused by the uneven layout of the first high-level signal line and the second high-level signal line, and improves the working stability of the gate driver circuit. Attached Figure Description

[0011] Figure 1 is a schematic diagram of the potential fluctuation phenomenon of the first scan signal in a conventional display device.

[0012] Figure 2 is a schematic diagram of a display device provided in an embodiment of this application.

[0013] Figure 3 is a circuit diagram of pixels in a display device provided in an embodiment of this application.

[0014] Figure 4 is a circuit diagram of a first embodiment of the first gate driving sub-circuit in the display device provided in this application.

[0015] Figure 5 is a layout of a first embodiment of the first gate driving sub-circuit in the display device provided in this application.

[0016] Figure 6 is a circuit diagram of a second embodiment of the first gate driving sub-circuit in the display device provided in this application.

[0017] Figure 7 is a layout of a second embodiment of the first gate driving sub-circuit in the display device provided in this application. Embodiments of the present invention

[0018] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0019] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0020] The embodiments of this application can be combined with each other.

[0021] As shown in Figure 1, in a conventional display device, when the first control signal input at the first control signal input terminal CTRL1 switches from a low potential to a high potential, the scan signal (such as Nout2) output by the multi-stage gate drive circuit... <1327> To Nout2 <1338> Potential fluctuations will occur in CPL.

[0022] Fluctuations in the scanning signal's potential can affect the activation or deactivation of the third transistor Tp3 in pixel PX, leading to abnormal data signal writing. When the display device uses frequency division display, the abnormal data signal writing will be more pronounced at the boundaries between different areas because the refresh rates of pixels PX in different regions are different, resulting in display abnormalities.

[0023] The embodiments of this application aim to provide a display device to solve the above-mentioned technical problems.

[0024] As shown in Figure 2, the display device provided in the embodiments of this application includes a display panel, a timing controller, a source drive circuit, and a power management chip. The display panel is an organic light-emitting diode (OLED) display panel.

[0025] The display panel includes a display area and a non-display area. The display area has an array of m×n pixels (PX), where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange driving circuits and various signal lines. The display panel also includes multiple scan lines (SCAN), multiple data lines (DATA), and a gate driving circuit. The multiple scan lines (SCAN) extend along a first direction and are arranged along a second direction, and the multiple data lines (DATA) extend along the second direction and are arranged along the first direction, with the first direction perpendicular to the second direction. The gate driving circuit is located in the non-display area and is electrically connected to the multiple scan lines (SCAN). The source driving circuit is electrically connected to the multiple data lines (DATA) via a flexible circuit board. A timing controller is electrically connected to both the gate driving circuit and the source driving circuit.

[0026] The display panel includes an organic light-emitting diode (OLED) array substrate and an encapsulation layer. The OLED array substrate includes a substrate, a buffer layer disposed on the substrate, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, a first metal layer disposed on the gate insulating layer, an interlayer insulating layer disposed on the first metal layer, a second metal layer disposed on the interlayer insulating layer, a planarization layer disposed on the second metal layer, a first electrode layer disposed on the planarization layer, a pixel defining layer disposed on the first electrode layer, an organic light-emitting layer disposed within an opening area defined by the pixel defining layer, and a second electrode layer disposed on the organic light-emitting layer. The first metal layer includes scan lines (SCAN), a gate electrode, etc. The second metal layer includes data lines (DATA), a source electrode, a drain electrode, etc. The encapsulation layer is sealed to the OLED array substrate to prevent moisture and oxygen from penetrating the organic light-emitting layer.

[0027] Each pixel (PX) includes a pixel driving circuit and an organic light-emitting diode (OLED). The pixel driving circuit includes at least two thin-film transistors (TFTs) and a storage capacitor. One TFT acts as a switching transistor, with its gate electrically connected to the corresponding scan line and its source electrically connected to the corresponding data line. The other TFT acts as a driving transistor, with its gate electrically connected to the drain of the switching transistor, its source electrically connected to a first power supply voltage line, and its drain electrically connected to the anode of the OLED. One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end is electrically connected to either the source or drain of the driving transistor. The cathode of the OLED is electrically connected to a second power supply voltage line. When the scan line outputs a high-potential scan signal, the switching transistor is turned on, and the data signal on the data line is written to the gate of the driving transistor and the storage capacitor through the switching transistor. When the scan line outputs a low-potential scan signal, the switching transistor is turned off, the storage capacitor maintains the voltage at the gate of the driving transistor, and the driving transistor generates a driving current corresponding to the gate voltage, driving the OLED to emit light.

[0028] Each gate drive circuit is electrically connected to one scan line. Under the control of the timing controller, the gate drive circuit sequentially outputs scan signals, scanning the pixels PX of the display area line by line. Under the control of the timing controller, the source drive circuit generates and outputs data signals based on the image data. The timing controller receives and processes externally input image data and timing signals, generates control signals, and transmits the image data to the source drive circuit. The power management chip provides operating voltages to various parts of the display device, including providing a second power supply voltage VSS for the cathode of the organic light-emitting diode OLED, a first power supply voltage VDD for the first power supply voltage line, and gate drive voltages VGH / VGL for the gate drive circuit, etc.

[0029] The display device provided in the embodiments of this application includes a display panel, which includes multiple rows of pixels (PX). Each pixel (PX) includes a pixel driving circuit and a light-emitting device (OLED), and the pixel driving circuit is electrically connected to the light-emitting device (OLED).

[0030] As shown in Figure 3, the pixel driving circuit includes thin-film transistors Tp1, Tp2, Tp3, Tp4, Tp5, Tp6, Tp7, Tp8, capacitor Cst, and capacitor Cboost.

[0031] Among them, thin-film transistors Tp1, Tp2, Tp5, Tp6, Tp7, and Tp8 are P-type thin-film transistors, while thin-film transistors Tp3 and Tp4 are N-type thin-film transistors.

[0032] The gate of thin-film transistor Tp1 is electrically connected to node Q, the source of thin-film transistor Tp1 is electrically connected to node P, and the drain of thin-film transistor Tp1 is electrically connected to node R. The gate of thin-film transistor Tp2 is electrically connected to the second scan signal input terminal Pscan1, the source of thin-film transistor Tp2 is electrically connected to the data signal input terminal Data, and the drain of thin-film transistor Tp2 is electrically connected to node P. The gate of thin-film transistor Tp3 is electrically connected to the first scan signal input terminal Nscan1 (Nout2), the source of thin-film transistor Tp3 is electrically connected to node R, and the drain of thin-film transistor Tp3 is electrically connected to node Q. The gate of thin-film transistor Tp4 is electrically connected to the third scan signal input terminal Nscan2, the source of thin-film transistor Tp4 is electrically connected to the first reset signal input terminal Vi1, and the drain of thin-film transistor Tp4 is electrically connected to node Q. The gate of thin-film transistor Tp5 is electrically connected to the first light-emitting control signal input terminal EM, the source of thin-film transistor Tp5 is electrically connected to the first power supply signal input terminal VDD, and the drain of thin-film transistor Tp5 is electrically connected to node P. The gate of thin-film transistor Tp6 is electrically connected to the first light-emitting control signal input terminal EM, the source of thin-film transistor Tp6 is electrically connected to node R, and the drain of thin-film transistor Tp6 is electrically connected to node S. The gate of thin-film transistor Tp7 is electrically connected to the fourth scan signal input terminal Pscan2, the source of thin-film transistor Tp7 is electrically connected to the second reset signal input terminal Vi2, and the drain of thin-film transistor Tp7 is electrically connected to node S. The gate of thin-film transistor Tp8 is electrically connected to the fourth scan signal input terminal Pscan2, the source of thin-film transistor Tp8 is electrically connected to the third reset signal input terminal Vi3, and the drain of thin-film transistor Tp8 is electrically connected to node R. One plate of capacitor Cst is electrically connected to node Q, and the other plate of capacitor Cst is electrically connected to the first power supply signal input terminal VDD. One plate of capacitor Cboost is electrically connected to node Q, and the other plate of capacitor Cboost is electrically connected to the second scan signal input terminal Pscan1. The anode of the light-emitting device OLED is electrically connected to node S, and the cathode of the light-emitting device OLED is electrically connected to the second power signal input terminal VSS.

[0033] The display panel also includes cascaded multi-stage gate driving circuits. Each stage of the gate driving circuit includes a first gate driving sub-circuit and a second gate driving sub-circuit. The first gate driving sub-circuit outputs a first scan signal Nscan1 (Nout2), and the second gate driving sub-circuit outputs a second scan signal Pscan1. As shown in Figures 4 and 6, the first gate driving sub-circuit includes a first stage transmission circuit 401 and a first output circuit 402. The first stage transmission circuit 401 and the first output circuit 402 are electrically connected. The first output circuit 402 outputs the first scan signal Nscan1 (Nout2) to a row of pixels PX, and the first stage transmission circuit 401 outputs stage transmission signals to the first gate driving sub-circuits of other stages of the gate driving circuit. The second gate driving sub-circuit includes a second stage transmission circuit and a second output circuit. The second stage transmission circuit and the second output circuit are electrically connected. The second output circuit outputs the second scan signal Pscan1 to the row of pixels PX, and the second stage transmission circuit outputs stage transmission signals to the second gate driving sub-circuits of other stages of the gate driving circuit. The technical solution of the embodiments of this application mainly improves the first gate driving sub-circuit.

[0034] The first output circuit 402 includes the eighteenth transistor Ts18, the twentieth transistor Ts20, the twenty-first transistor Ts21, and the fifth capacitor C5.

[0035] The gate of the eighteenth transistor Ts18 is electrically connected to the first control node I, the source of the eighteenth transistor Ts18 is electrically connected to the second control node F of the first-stage transmission circuit 401, and the drain of the eighteenth transistor Ts18 is electrically connected to node H. The gate of the twenty-first transistor Ts21 is electrically connected to node G (the third control node) of the first-stage transmission circuit 401, the source of the twenty-first transistor Ts21 is electrically connected to the first low-level signal input terminal VGL1 of the display panel, and the drain of the twenty-first transistor Ts21 is electrically connected to the first scan signal output terminal Nout2 of the first gate drive sub-circuit. The gate of the twenty-second transistor Ts22 is electrically connected to node H (the drain of the eighteenth transistor Ts18), the source of the twenty-second transistor Ts22 is electrically connected to the first high-level signal input terminal VGH1 of the display panel, and the drain of the twenty-second transistor Ts22 is electrically connected to the first scan signal output terminal Nout2. One plate of the fifth capacitor C5 is electrically connected to the first control node I, and the other plate of the fifth capacitor C5 is electrically connected to the first low-level signal input terminal VGL1 of the first gate drive sub-circuit or the second low-level signal input terminal VGL2 of the display panel (the second low-level signal input terminal VGL2 is electrically connected to the second gate drive sub-circuit).

[0036] The first-stage transmission circuit 401 includes a first transistor Ts1, a second transistor Ts2, a third transistor Ts3, a fourth transistor Ts4, a fifth transistor Ts5, a sixth transistor Ts6, a seventh transistor Ts7, an eighth transistor Ts8, a ninth transistor Ts9, a tenth transistor Ts10, an eleventh transistor Ts11, a twelfth transistor Ts12, a thirteenth transistor Ts13, a fourteenth transistor Ts14, a fifteenth transistor Ts15, a sixteenth transistor Ts16, a seventeenth transistor Ts17, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0037] The gate of the first transistor Ts1 is electrically connected to node C, and the source of the first transistor Ts1 is electrically connected to the first high-level signal input terminal VGH1. The gate of the second transistor Ts2 is electrically connected to node E, the source of the second transistor Ts2 is electrically connected to the first clock signal input terminal CK, and the drain of the second transistor Ts2 is electrically connected to the drain of the first transistor Ts1. The gate of the third transistor Ts3 is electrically connected to the second clock signal input terminal XCK, the source of the third transistor Ts3 is electrically connected to the stage signal input terminal Nin, and the drain of the third transistor Ts3 is electrically connected to node D. The gate of the fourth transistor Ts4 is electrically connected to the second clock signal input terminal XCK, the source of the fourth transistor Ts4 is electrically connected to the first low-level signal input terminal VGL1, and the drain of the fourth transistor Ts4 is electrically connected to node C. The gate of the fifth transistor Ts5 is electrically connected to node D, the source of the fifth transistor Ts5 is electrically connected to the second clock signal input terminal XCK, and the drain of the fifth transistor Ts5 is electrically connected to node C. The gate of the sixth transistor Ts6 is electrically connected to node B, the source of the sixth transistor Ts6 is electrically connected to the first clock signal input terminal CK, and the drain of the sixth transistor Ts6 is electrically connected to node A. The gate of the seventh transistor Ts7 is electrically connected to the first clock signal input terminal CK, and the source of the seventh transistor Ts7 is electrically connected to node A. The gate of the eighth transistor Ts8 is electrically connected to node D, the source of the eighth transistor Ts8 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the eighth transistor Ts8 is electrically connected to node F (the second control node). The gate of the ninth transistor Ts9 is electrically connected to node G (the third control node), the source of the ninth transistor Ts9 is electrically connected to the first low-level signal input terminal VGL1, and the drain of the ninth transistor Ts9 is electrically connected to the first stage signal output terminal Nout1. The gate of the tenth transistor Ts10 is electrically connected to node F (the second control node), the source of the tenth transistor Ts10 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the tenth transistor Ts10 is electrically connected to the first stage signal output terminal Nout1. The gate of the eleventh transistor Ts11 is electrically connected to the first low-level signal input terminal VGL1, the source of the eleventh transistor Ts11 is electrically connected to node C, and the drain of the eleventh transistor Ts11 is electrically connected to node B. The gate of the twelfth transistor Ts12 is electrically connected to the first low-level signal input terminal VGL1, the source of the twelfth transistor Ts12 is electrically connected to node D, and the drain of the twelfth transistor Ts12 is electrically connected to node G (the third control node). The gate of the thirteenth transistor Ts13 is electrically connected to the first control signal input terminal CTRL1, the source of the thirteenth transistor Ts13 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the thirteenth transistor Ts13 is electrically connected to node D.The gate of the fourteenth transistor Ts14 is electrically connected to the second clock signal input terminal XCK, and the source of the fourteenth transistor Ts14 is electrically connected to the first stage signal input terminal Nin. The gate of the fifteenth transistor Ts15 is electrically connected to the first low-level signal input terminal VGL1, the source of the fifteenth transistor Ts15 is electrically connected to the drain of the fourteenth transistor Ts14, and the drain of the fifteenth transistor Ts15 is electrically connected to node E. The gate of the sixteenth transistor Ts16 is electrically connected to node E, the source of the sixteenth transistor Ts16 is electrically connected to node E, and the drain of the sixteenth transistor Ts16 is electrically connected to node G (the third control node). The gate of the seventeenth transistor Ts17 is electrically connected to the second control signal input terminal CTRL2, the source of the seventeenth transistor Ts17 is electrically connected to the drain of the seventh transistor Ts7, and the drain of the seventeenth transistor Ts17 is electrically connected to node F (the second control node). One plate of the first capacitor C1 is electrically connected to node E, and the other plate of the first capacitor C1 is electrically connected to the drain of the first transistor Ts1. One plate of the second capacitor C2 is electrically connected to node A, and the other plate of the second capacitor C2 is electrically connected to node B. One plate of the third capacitor C3 is electrically connected to node F (the second control node), and the other plate of the third capacitor C3 is electrically connected to the first high-level signal input terminal VGH1.

[0038] The first output circuit 402 also includes a nineteenth transistor Ts19, a twentieth transistor Ts20, and a fourth capacitor C4.

[0039] The gate of the nineteenth transistor Ts19 is electrically connected to node D, the source of the nineteenth transistor Ts19 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the nineteenth transistor Ts19 is electrically connected to node H. The gate of the twentieth transistor Ts20 is electrically connected to node D, the source of the twentieth transistor Ts20 is electrically connected to the first control signal input terminal CTRL1, and the drain of the twentieth transistor Ts20 is electrically connected to the gate of the eighteenth transistor Ts18. One plate of the fourth capacitor C4 is electrically connected to node H, and the other plate of the fourth capacitor C4 is electrically connected to the first high-level signal input terminal VGH1.

[0040] In this embodiment, the first transistor Ts1 to the twenty-second transistor Ts22 are all P-type thin-film transistors.

[0041] In the technical solution provided by the embodiments of this application, by electrically connecting one plate of the fifth capacitor C5 to node I (first control node) of the first output circuit 402, and the other plate to the first low-level signal input terminal VGL1 of the first gate driving sub-circuit or the second low-level signal input terminal VGL2 of the second gate driving sub-circuit, instead of electrically connecting it to the first high-level signal input terminal VGH1, the signal transmitted by the first control signal input terminal CTRL1 is prevented from being coupled to the potential of the signal transmitted by the first high-level signal input terminal VGH1 through the fifth capacitor C5. Since the first gate driving sub-circuit generates the first scan signal Nscan1 (Nout2) based on the signals transmitted by the first high-level signal input terminal VGH1 and the first low-level signal input terminal VGL1, the potential of the first scan signal Nscan1 (Nout2) will not be affected by the coupling of the fifth capacitor C5 when the potential of the signal transmitted by the first high-level signal input terminal VGH1 is not affected by the coupling of the fifth capacitor C5.

[0042] As shown in Figures 5 and 7, in the layout of the gate driving circuit, the first high-level signal line VGH1 and the second high-level signal line VGH2 of the display panel are located on the first side of the first low-level signal line VGL1 of the first gate driving sub-circuit. The fifth capacitor C5 is located on the second side of the first low-level signal line VGL1 opposite to the first side. That is, when the other plate of the fifth capacitor C5 is electrically connected to the first low-level signal line VGL1, the first low-level signal line VGL1 is positioned between the entire structure formed by the first high-level signal line VGH1 and the second high-level signal line VGH2 and the fifth capacitor C5. The low-level signal line VGL2 is located on the side away from the fifth capacitor C5, where the entire structure consisting of the first high-level signal line VGH1 and the second high-level signal line VGH2 is formed. Alternatively, when the other plate of the fifth capacitor C5 is electrically connected to the second low-level signal line VGL2, the second low-level signal line VGL2 is located between the entire structure consisting of the first high-level signal line VGH1 and the second high-level signal line VGH2 and the fifth capacitor C5, and the first low-level signal line VGL1 is located on the side away from the fifth capacitor C5, where the entire structure consisting of the first high-level signal line VGH1 and the second high-level signal line VGH2 is formed. Since one plate of the fifth capacitor C5 is electrically connected to node I (first control node) of the first output circuit 402, and the other plate is electrically connected to the first low-level signal input terminal VGL1 of the first gate drive sub-circuit or the second low-level signal input terminal VGL2 of the second gate drive sub-circuit, instead of being electrically connected to the first high-level signal input terminal VGH1, the uneven layout of the first high-level signal line VGH1 and the second high-level signal line VGH2 caused by the fifth capacitor C5 being electrically connected to the first high-level signal input terminal VGH1 and occupying the routing space of the first high-level signal line VGH1 and / or the second high-level signal line VGH2 is avoided. This also avoids the problem of uneven load on the first high-level signal line VGH1 and the second high-level signal line VGH2 caused by uneven layout.

[0043] The first-stage transmission circuit 401 also includes a sixth capacitor C6. One plate of the sixth capacitor C6 is electrically connected to node G (the third control node), and the other plate of the sixth capacitor C6 is electrically connected to the first-stage transmission signal output terminal Nout1.

[0044] In this embodiment, by setting a sixth capacitor C6 between node G (the third control node) and the first-stage signal output terminal Nout1, when the signal of the first-stage signal output terminal Nout1 switches from a high potential to a low potential, the sixth capacitor C6 can pull down the potential of node G (the third control node). The potential of node G (the third control node) controls the twenty-first transistor Ts21 to turn on, thereby reducing the voltage of the stepped waveform portion of the output first scan signal Nscan1 (Nout2), ensuring the stability of the waveform of the first scan signal output by the first scan signal output terminal Nout2, and improving the circuit stability when the display device enables the frequency division display function.

[0045] Furthermore, by incorporating a sixth capacitor C6 in the first-stage transmission circuit 401, the pulse width of the scanning signals output by each stage of the gate drive circuit can be effectively controlled, avoiding the problem in the prior art where the pulse width of the first scanning signal gradually increases with the number of stages. This technical solution not only ensures that the scanning signals output by each stage of the gate drive circuit have a stable pulse width, but also avoids signal interference between adjacent stages caused by an excessively large pulse width of the first scanning signal Nscan1 (Nout2), thereby improving the operational reliability of the gate drive circuit and ultimately enhancing the display quality of the display device.

[0046] The display device provided in the embodiments of this application can be applied to the field of flexible organic light-emitting diode display technology, and is particularly suitable for display panel products with frequency division display function.

[0047] The first embodiment of the display device provided in this application includes a display panel, which is an organic light-emitting diode display panel. The display panel includes multiple rows of pixels and cascaded multi-level gate driving circuits. The first-level gate driving circuit includes a first gate driving sub-circuit and a second gate driving sub-circuit. The first gate driving sub-circuit is used to output a first scan signal Nscan1 (Nout2) to a row of pixels PX, and the second gate driving sub-circuit is used to output a second scan signal to the same row of pixels PX.

[0048] The first gate driving sub-circuit includes a first stage transmission circuit 401 and a first output circuit 402. The first output circuit 402 is used to output a first scan signal Nscan1 (Nout2) to a row of pixels PX.

[0049] The first output circuit 402 includes an eighteenth transistor Ts18, a twenty-first transistor Ts21, a twenty-second transistor Ts22, and a fifth capacitor C5.

[0050] The gate of the eighteenth transistor Ts18 is electrically connected to the first control node I, the source of the eighteenth transistor Ts18 is electrically connected to the second control node F of the first stage transmission circuit 401, and the drain of the eighteenth transistor Ts18 is electrically connected to node H.

[0051] The gate of the 21st transistor Ts21 is electrically connected to node G (the third control node) of the first stage transmission circuit, the source of the 21st transistor Ts21 is electrically connected to the first low-level signal input terminal VGL1, and the drain of the 21st transistor Ts21 is electrically connected to the first scan signal output terminal of the first gate drive sub-circuit.

[0052] The gate of the 22nd transistor Ts22 is electrically connected to node H (the drain of the 18th transistor Ts18), the source of the 22nd transistor Ts22 is electrically connected to the first high-level signal input terminal VGH1 of the display panel, and the drain of the 22nd transistor Ts22 is electrically connected to the first scan signal output terminal.

[0053] One plate of the fifth capacitor C5 is electrically connected to node I (first control node) of the first output circuit 402, and the other plate of the fifth capacitor C5 is electrically connected to the first low-level signal input terminal VGL1 of the first gate drive sub-circuit.

[0054] In the top view of the gate drive circuit, the first high-level signal line VGH1 is located on the first side of the first low-level signal line VGL1, and the fifth capacitor C5 is located on the second side of the first low-level signal line VGL1 opposite to the first side.

[0055] In this embodiment, the first low-level signal line VGL1 of the first gate driving sub-circuit is used to transmit the low-level signal VGL1. The gate driving circuit also includes a first high-level signal line VGH1 and a second high-level signal line VGH2. The first high-level signal line VGH1 and the second high-level signal line VGH2 are used to transmit high-level signals. The first high-level signal line VGH1 is electrically connected to the high-level signal input terminal of the odd-numbered gate driving circuit (including the first high-level signal input terminal VGH1 of the first gate driving sub-circuit and the second high-level signal input terminal VGH2 of the second gate driving sub-circuit). The second high-level signal line VGH2 is electrically connected to the high-level signal input terminal of the even-numbered gate driving circuit (including the first high-level signal input terminal VGH1 of the first gate driving sub-circuit and the second high-level signal input terminal VGH2 of the second gate driving sub-circuit).

[0056] In this embodiment, the first low-level signal input terminal VGL1 of the first gate driver sub-circuit is used to receive the first low-level signal VGL1, and the first high-level signal input terminal VGH1 is used to receive the first high-level signal VGH1. The voltage value of the first low-level signal VGL1 can be, for example, -5 volts, and the voltage value of the first high-level signal VGH1 can be, for example, 15 volts.

[0057] The first output circuit 402 also includes a nineteenth transistor Ts19, a twentieth transistor Ts20, and a fourth capacitor C4.

[0058] The gate of the nineteenth transistor Ts19 is electrically connected to node D, the source of the nineteenth transistor Ts19 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the nineteenth transistor Ts19 is electrically connected to node H.

[0059] The gate of the twentieth transistor Ts20 is electrically connected to node D, the source of the twentieth transistor Ts20 is electrically connected to the first control signal input terminal CTRL1, and the drain of the twentieth transistor Ts20 is electrically connected to the gate of the eighteenth transistor.

[0060] One plate of the fourth capacitor C4 is electrically connected to node H, and the other plate of the fourth capacitor C4 is electrically connected to the first high-level signal input terminal VGH1.

[0061] The first-stage transmission circuit 401 is used to output stage transmission signals to the first gate driver sub-circuit of the gate driver circuits of other stages.

[0062] The first-stage transmission circuit 401 includes a first transistor Ts1, a second transistor Ts2, a third transistor Ts3, a fourth transistor Ts4, a fifth transistor Ts5, a sixth transistor Ts6, a seventh transistor Ts7, an eighth transistor Ts8, a ninth transistor Ts9, a tenth transistor Ts10, an eleventh transistor Ts11, a twelfth transistor Ts12, a thirteenth transistor Ts13, a fourteenth transistor Ts14, a fifteenth transistor Ts15, a sixteenth transistor Ts16, a seventeenth transistor Ts17, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0063] The gate of the first transistor Ts1 is electrically connected to node C, and the source of the first transistor Ts1 is electrically connected to the first high-level signal input terminal VGH1.

[0064] The gate of the second transistor Ts2 is electrically connected to node E, the source of the second transistor Ts2 is electrically connected to the first clock signal input terminal CK, and the drain of the second transistor Ts2 is electrically connected to the drain of the first transistor Ts1.

[0065] The gate of the third transistor Ts3 is electrically connected to the second clock signal input terminal XCK, the source of the third transistor Ts3 is electrically connected to the first stage signal input terminal Nin, and the drain of the third transistor Ts3 is electrically connected to node D.

[0066] The gate of the fourth transistor Ts4 is electrically connected to the second clock signal input terminal XCK, the source of the fourth transistor 4Ts is electrically connected to the first low-level signal input terminal VGL1, and the drain of the fourth transistor Ts4 is electrically connected to node C.

[0067] The gate of the fifth transistor Ts5 is electrically connected to node D, the source of the fifth transistor Ts5 is electrically connected to the second clock signal input terminal XCK, and the drain of the fifth transistor Ts5 is electrically connected to node C.

[0068] The gate of the sixth transistor Ts6 is electrically connected to node B, the source of the sixth transistor Ts6 is electrically connected to the first clock signal input terminal CK, and the drain of the sixth transistor Ts6 is electrically connected to node A.

[0069] The gate of the seventh transistor Ts7 is electrically connected to the first clock signal input terminal CK, and the source of the seventh transistor Ts7 is electrically connected to node A.

[0070] The gate of the eighth transistor Ts8 is electrically connected to node D, the source of the eighth transistor Ts8 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the eighth transistor Ts8 is electrically connected to node F (the second control node).

[0071] The gate of the ninth transistor Ts9 is electrically connected to node G (the third control node), the source of the ninth transistor Ts9 is electrically connected to the first low-level signal input terminal VGL1, and the drain of the ninth transistor Ts9 is electrically connected to the first stage signal output terminal Nout1.

[0072] The gate of the tenth transistor Ts10 is electrically connected to node F (the second control node), the source of the tenth transistor Ts10 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the tenth transistor Ts10 is electrically connected to the first stage signal output terminal Nout1.

[0073] The gate of the eleventh transistor Ts11 is electrically connected to the first low-level signal input terminal VGL1, the source of the eleventh transistor Ts11 is electrically connected to node C, and the drain of the eleventh transistor Ts11 is electrically connected to node B.

[0074] The gate of the twelfth transistor Ts12 is electrically connected to the first low-level signal input terminal VGL1, the source of the twelfth transistor Ts12 is electrically connected to node D, and the drain of the twelfth transistor Ts12 is electrically connected to node G (the third control node).

[0075] The gate of the thirteenth transistor Ts13 is electrically connected to the first control signal input terminal CTRL1, the source of the thirteenth transistor Ts13 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the thirteenth transistor Ts13 is electrically connected to node D.

[0076] The gate of the fourteenth transistor Ts14 is electrically connected to the second clock signal input terminal XCK, and the source of the fourteenth transistor Ts14 is electrically connected to the first stage signal input terminal Nin.

[0077] The gate of the fifteenth transistor Ts15 is electrically connected to the first low-level signal input terminal VGL1, the source of the fifteenth transistor Ts15 is electrically connected to the drain of the fourteenth transistor Ts14, and the drain of the fifteenth transistor Ts15 is electrically connected to node E.

[0078] The gate of the sixteenth transistor Ts16 is electrically connected to node E, the source of the sixteenth transistor Ts16 is electrically connected to node E, and the drain of the sixteenth transistor Ts16 is electrically connected to node G (the third control node).

[0079] The gate of the seventeenth transistor Ts17 is electrically connected to the second control signal input terminal CTRL2, the source of the seventeenth transistor Ts17 is electrically connected to the drain of the seventh transistor Ts7, and the drain of the seventeenth transistor Ts17 is electrically connected to node F (the second control node).

[0080] One plate of the first capacitor C1 is electrically connected to node E, and the other plate of the first capacitor C1 is electrically connected to the drain of the first transistor Ts1.

[0081] One plate of the second capacitor C2 is electrically connected to node A, and the other plate of the second capacitor C2 is electrically connected to node B.

[0082] One plate of the third capacitor C3 is electrically connected to node F (the second control node), and the other plate of the third capacitor C3 is electrically connected to the first high-level signal input terminal VGH1.

[0083] Furthermore, the channel width of the ninth transistor Ts9 in the first-stage transmission circuit 401 is greater than or equal to 20 micrometers. Preferably, the channel width of the ninth transistor Ts9 is in the range of 30 to 50 micrometers, and more preferably, the channel width of the ninth transistor Ts9 is 40 micrometers. By increasing the channel width of the ninth transistor Ts9, the output capability of the ninth transistor Ts9 is improved, thereby further improving the waveform stability of the transmission signal output from the first-stage transmission signal output terminal Nout1, and improving the circuit stability when the display device activates the frequency division display function.

[0084] The first-stage transmission circuit 401 also includes a sixth capacitor C6. One plate of the sixth capacitor C6 is electrically connected to node G (the third control node), and the other plate of the sixth capacitor C6 is electrically connected to the first-stage transmission signal output terminal Nout1.

[0085] By setting a sixth capacitor C6 between node G (the third control node) and the first-stage signal output terminal Nout1, when the signal of the first-stage signal output terminal Nout1 switches from a high potential to a low potential, the sixth capacitor C6 can pull down the potential of node G (the third control node), thereby reducing the voltage of the stepped waveform portion of the output scan signal, ensuring the stability of the waveform of the stage transmission signal output by the first-stage signal output terminal Nout1.

[0086] The display panel also includes a second high-level signal line VGH2, which is electrically connected to the second gate driving sub-circuit. In the top view of the gate driving circuit, the first high-level signal line VGH1 and the second high-level signal line VGH2 cross the first gate driving sub-circuit and the second gate driving sub-circuit, and the first low-level signal line VGL1 and the second low-level signal line VGL2 cross the first gate driving sub-circuit and the second gate driving sub-circuit.

[0087] In the top view of the gate drive circuit, the second high-level signal line VGH2 is located on the first side of the first low-level signal line VGL1 of the first gate drive sub-circuit.

[0088] The line width of any point on the first high-level signal line VGH1 is the same as the line width of any point on the second high-level signal line VGH2, and the line width of any point on the first low-level signal line VGL1 is the same as the line width of any point on the second low-level signal line VGL2. Furthermore, the resistivity of the first high-level signal line VGH1 and the second high-level signal line VGH2 is the same, and the resistivity of the first low-level signal line VGL1 and the second low-level signal line VGL2 is the same. This makes the load on each signal line more uniform, thereby improving the working stability of the gate drive circuit.

[0089] The second embodiment of the display device provided in this application is similar to the first embodiment, except that:

[0090] One plate of the fifth capacitor C5 is electrically connected to node I (first control node) of the first output circuit 402, and the other plate of the fifth capacitor C5 is electrically connected to the second low-level signal input terminal VGL2 of the display panel.

[0091] In the top view of the gate drive circuit, the first high-level signal line VGH1 is located on the first side of the second low-level signal line VGL2, the fifth capacitor C5 is located on the second side of the second low-level signal line VGL2 opposite to the first side, and the first low-level signal line VGL1 is located on the side of the first high-level signal line VGH1 away from the second low-level signal line VGL2.

[0092] By electrically connecting the other plate of the fifth capacitor C5 to the second low-level signal input terminal VGL2, the potential coupling effect of the fifth capacitor C5 on the signal transmitted by the first high-level signal input terminal VGH1 can also be avoided.

[0093] The display panel also includes a second high-level signal line VGH2. In the top view of the gate driving circuit, the second high-level signal line VGH2 is located between the second low-level signal line VGL2 and the first low-level signal line VGL1. That is, in the top view of the gate driving circuit, the second low-level signal line VGL2 of the second gate driving sub-circuit is disposed between the entire structure formed by the first high-level signal line VGH1 and the second high-level signal line VGH2 and the fifth capacitor C5, and the first low-level signal line VGL1 is disposed on the side of the entire structure formed by the first high-level signal line VGH1 and the second high-level signal line VGH2 away from the fifth capacitor C5.

[0094] In the display device provided in the embodiments of this application, since one plate of the fifth capacitor C5 in the first output circuit 402 of the first gate driving sub-circuit in the gate driving circuit is electrically connected to node I (first control node) of the first output circuit 402, and the other plate is electrically connected to the first low-level signal input terminal VGL1 of the first gate driving sub-circuit or the second low-level signal input terminal VGL2 of the second gate driving sub-circuit, and the first high-level signal input terminal VGH1 is insulated from the fifth capacitor C5, when the first control signal input terminal CTRL1 inputs the first control signal to node I (first control node), the fifth capacitor C5 will not have a coupling effect on the potential of the signal transmitted by the first high-level signal input terminal VGH1, thereby avoiding the problem of potential fluctuation of the signal transmitted by the first high-level signal input terminal VGH1 due to the coupling effect between the fifth capacitor C5 and the first high-level signal input terminal VGH1.

[0095] Furthermore, since the potential of the signal transmitted by the first high-level signal input terminal VGH1 will not fluctuate due to the coupling effect of the fifth capacitor C5, and the first gate driving sub-circuit generates the first scan signal Nscan1 (Nout2) based on the signals transmitted by the first high-level signal input terminal VGH1 and the first low-level signal input terminal VGL1, the potential of the first scan signal Nscan1 (Nout2) will also not fluctuate due to the coupling effect of the fifth capacitor C5. Because the potential of the first scan signal Nscan1 (Nout2) does not fluctuate, the turning on or off of the third transistor in the pixel driving circuit of pixel PX will not be affected. The second capacitor, which is electrically connected to the drain of the third transistor, will not apply coupling to the gate of the second transistor, which is also electrically connected to the second capacitor, thus not affecting the turning on or off of the second transistor, thereby avoiding the problem of abnormal data signal writing.

[0096] In addition, since the data signal can be written to the pixel PX normally, when the display device enables the frequency division display function, there will be no display abnormalities caused by abnormal data signal writing at the boundary between different areas, thereby improving the display effect of the display device when the frequency division display function is enabled.

[0097] Furthermore, since one plate of the fifth capacitor C5 is electrically connected to node I (the first control node) of the first output circuit 402, and the other plate is electrically connected to the first low-level signal input terminal VGL1 of the first gate driver sub-circuit or the second low-level signal input terminal VGL2 of the second gate driver sub-circuit, instead of being electrically connected to the first high-level signal input terminal VGH1, in the layout of the gate driver circuit, the first low-level signal line VGL1 of the first gate driver sub-circuit or the second low-level signal line VGL2 of the second gate driver sub-circuit can be set in the configuration of the first high-level signal line VGH1 and the second high-level signal line VGH2. The overall arrangement of the first high-level signal line VGH1 and the second high-level signal line VGH2 is more uniform, avoiding the uneven layout of the first high-level signal line VGH1 and the second high-level signal line VGH2 caused by the fifth capacitor C5 being electrically connected to the first high-level signal input terminal VGH1 and occupying the trace space of the first high-level signal line VGH1 and / or the second high-level signal line VGH2. This, in turn, avoids the problem of uneven load caused by the uneven layout of the first high-level signal line VGH1 and the second high-level signal line VGH2, and improves the working stability of the gate drive circuit.

[0098] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, the display device comprising a display panel, the display panel including multiple rows of pixels and multiple levels of gate driving circuitry, wherein, The gate drive circuit of the first stage includes: A first gate driving sub-circuit, the first gate driving sub-circuit including a first stage transmission circuit and a first output circuit, the first output circuit including: The eighteenth transistor, the gate of which is electrically connected to the first control node I, and the source of which is electrically connected to the second control node F of the first stage transmission circuit; The gate of the 21st transistor is electrically connected to the third control node G of the first stage transmission circuit, the source of the 21st transistor is electrically connected to the first low-level signal input terminal of the display panel, and the drain of the 21st transistor is electrically connected to the first scan signal output terminal of the first gate driving sub-circuit. The gate of the twenty-second transistor is electrically connected to the drain of the eighteenth transistor, the source of the twenty-second transistor is electrically connected to the first high-level signal input terminal of the display panel, and the drain of the twenty-second transistor is electrically connected to the first scan signal output terminal; and The fifth capacitor has one plate electrically connected to the first control node I and the other plate electrically connected to the first low-level signal input terminal. In the top view of the gate drive circuit, the first high-level signal line is located on the first side of the first low-level signal line, and the fifth capacitor is located on the second side of the first low-level signal line opposite to the first side.

2. The display device according to claim 1, wherein, The first output circuit also includes: The nineteenth transistor has its gate electrically connected to node D, its source electrically connected to the first high-level signal input terminal, and its drain electrically connected to node H. The twentieth transistor has its gate electrically connected to node D, its source electrically connected to the first control signal input terminal, and its drain electrically connected to the gate of the eighteenth transistor; and The fourth capacitor has one plate electrically connected to node H and the other plate electrically connected to the first high-level signal input terminal.

3. The display device according to claim 1, wherein, The first-stage transmission circuit includes: The first transistor has its gate electrically connected to node C and its source electrically connected to the first high-level signal input terminal. The second transistor has its gate electrically connected to node E, its source electrically connected to the first clock signal input terminal, and its drain electrically connected to the drain of the first transistor. The third transistor has its gate electrically connected to the second clock signal input terminal, its source electrically connected to the first stage signal input terminal, and its drain electrically connected to node D. The fourth transistor has its gate electrically connected to the second clock signal input terminal, its source electrically connected to the first low-level signal input terminal, and its drain electrically connected to the node C. The fifth transistor has its gate electrically connected to node D, its source electrically connected to the second clock signal input terminal, and its drain electrically connected to node C. The sixth transistor has its gate electrically connected to node B, its source electrically connected to the first clock signal input terminal, and its drain electrically connected to node A. The seventh transistor has its gate electrically connected to the first clock signal input terminal and its source electrically connected to node A. The eighth transistor has its gate electrically connected to node D, its source electrically connected to the first high-level signal input terminal, and its drain electrically connected to the second control node F. The ninth transistor has its gate electrically connected to the third control node G, its source electrically connected to the first low-level signal input terminal, and its drain electrically connected to the first stage signal output terminal. The tenth transistor has its gate electrically connected to the second control node F, its source electrically connected to the first high-level signal input terminal, and its drain electrically connected to the first stage signal output terminal. The eleventh transistor has its gate electrically connected to the first low-level signal input terminal, its source electrically connected to node C, and its drain electrically connected to node B. The twelfth transistor has its gate electrically connected to the first low-level signal input terminal, its source electrically connected to the node D, and its drain electrically connected to the third control node G. The thirteenth transistor has its gate electrically connected to the first control signal input terminal, its source electrically connected to the first high-level signal input terminal, and its drain electrically connected to node D. The fourteenth transistor has its gate electrically connected to the second clock signal input terminal and its source electrically connected to the first stage signal input terminal. The fifteenth transistor has its gate electrically connected to the first low-level signal input terminal, its source electrically connected to the drain of the fourteenth transistor, and its drain electrically connected to node E. The sixteenth transistor has its gate electrically connected to node E, its source electrically connected to node E, and its drain electrically connected to the third control node G. The seventeenth transistor has its gate electrically connected to the second control signal input terminal, its source electrically connected to the drain of the seventh transistor, and its drain electrically connected to the second control node F. A first capacitor, one plate of which is electrically connected to node E, and the other plate of which is electrically connected to the drain of the first transistor. A second capacitor, one plate of which is electrically connected to node A, and the other plate of which is electrically connected to node B; and The third capacitor has one plate electrically connected to the second control node F and the other plate electrically connected to the first high-level signal input terminal.

4. The display device according to claim 3, wherein, The first-stage transmission circuit also includes: The sixth capacitor has one plate electrically connected to the third control node G, and the other plate electrically connected to the first-stage signal output terminal.

5. The display device according to claim 1, wherein, The display panel further includes a second gate driving sub-circuit and a second high-level signal line. The second gate driving sub-circuit is electrically connected to the second high-level signal line. In a top view of the gate driving circuit, the second high-level signal line is located on the first side of the first low-level signal line.

6. The display device according to claim 5, wherein, The first high-level signal line and the second high-level signal line cross the first gate driver sub-circuit and the second gate driver sub-circuit.

7. The display device according to claim 5, wherein, The line width at any point on the first high-level signal line is the same as the line width at any point on the second high-level signal line.

8. The display device according to claim 1, wherein, The channel width of the ninth transistor in the first stage transmission circuit is greater than or equal to 20 micrometers.

9. The display device according to claim 8, wherein, The channel width of the ninth transistor is in the range of 30 micrometers to 50 micrometers.

10. The display device according to claim 9, wherein, The channel width of the ninth transistor is 40 micrometers.

11. A display device, the display device comprising a display panel, the display panel comprising multiple rows of pixels and multiple levels of gate driving circuitry, wherein, The gate drive circuit of the first stage includes: A first gate driving sub-circuit, the first gate driving sub-circuit including a first stage transmission circuit and a first output circuit, the first output circuit including: The eighteenth transistor, the gate of which is electrically connected to the first control node I, and the source of which is electrically connected to the second control node F of the first stage transmission circuit; The gate of the 21st transistor is electrically connected to the third control node G of the first stage transmission circuit, the source of the 21st transistor is electrically connected to the first low-level signal input terminal of the display panel, and the drain of the 21st transistor is electrically connected to the first scan signal output terminal of the first gate driving sub-circuit. The gate of the twenty-second transistor is electrically connected to the drain of the eighteenth transistor, the source of the twenty-second transistor is electrically connected to the first high-level signal input terminal of the display panel, and the drain of the twenty-second transistor is electrically connected to the first scan signal output terminal; and The fifth capacitor has one plate electrically connected to the first control node I, and the other plate electrically connected to the second low-level signal input terminal of the display panel. In the top view of the gate drive circuit, the first high-level signal line is located on the first side of the second low-level signal line, the fifth capacitor is located on the second side of the second low-level signal line opposite to the first side, and the first low-level signal line is located on the side of the first high-level signal line away from the second low-level signal line.

12. The display device according to claim 11, wherein, The first output circuit also includes: The nineteenth transistor has its gate electrically connected to node D, its source electrically connected to the first high-level signal input terminal, and its drain electrically connected to node H. The twentieth transistor has its gate electrically connected to node D, its source electrically connected to the first control signal input terminal, and its drain electrically connected to the gate of the eighteenth transistor; and The fourth capacitor has one plate electrically connected to node H and the other plate electrically connected to the first high-level signal input terminal.

13. The display device according to claim 11, wherein, The first gate driving sub-circuit further includes a first-stage transmission circuit, which includes: The first transistor has its gate electrically connected to node C and its source electrically connected to the first high-level signal input terminal. The second transistor has its gate electrically connected to node E, its source electrically connected to the first clock signal input terminal, and its drain electrically connected to the drain of the first transistor. The third transistor has its gate electrically connected to the second clock signal input terminal, its source electrically connected to the first stage signal input terminal, and its drain electrically connected to node D. The fourth transistor has its gate electrically connected to the second clock signal input terminal, its source electrically connected to the first low-level signal input terminal, and its drain electrically connected to the node C. The fifth transistor has its gate electrically connected to node D, its source electrically connected to the second clock signal input terminal, and its drain electrically connected to node C. The sixth transistor has its gate electrically connected to node B, its source electrically connected to the first clock signal input terminal, and its drain electrically connected to node A. The seventh transistor has its gate electrically connected to the first clock signal input terminal and its source electrically connected to node A. The eighth transistor has its gate electrically connected to node D, its source electrically connected to the first high-level signal input terminal, and its drain electrically connected to the second control node F. The ninth transistor has its gate electrically connected to the third control node G, its source electrically connected to the first low-level signal input terminal, and its drain electrically connected to the first stage signal output terminal. The tenth transistor has its gate electrically connected to the second control node F, its source electrically connected to the first high-level signal input terminal, and its drain electrically connected to the first stage signal output terminal. The eleventh transistor has its gate electrically connected to the first low-level signal input terminal, its source electrically connected to node C, and its drain electrically connected to node B. The twelfth transistor has its gate electrically connected to the first low-level signal input terminal, its source electrically connected to the node D, and its drain electrically connected to the third control node G. The thirteenth transistor has its gate electrically connected to the first control signal input terminal, its source electrically connected to the first high-level signal input terminal, and its drain electrically connected to node D. The fourteenth transistor has its gate electrically connected to the second clock signal input terminal and its source electrically connected to the first stage signal input terminal. The fifteenth transistor has its gate electrically connected to the first low-level signal input terminal, its source electrically connected to the drain of the fourteenth transistor, and its drain electrically connected to node E. The sixteenth transistor has its gate electrically connected to node E, its source electrically connected to node E, and its drain electrically connected to the third control node G. The seventeenth transistor has its gate electrically connected to the second control signal input terminal, its source electrically connected to the drain of the seventh transistor, and its drain electrically connected to the second control node F. A first capacitor, one plate of which is electrically connected to node E, and the other plate of which is electrically connected to the drain of the first transistor. A second capacitor, one plate of which is electrically connected to node A, and the other plate of which is electrically connected to node B; and The third capacitor has one plate electrically connected to the second control node F and the other plate electrically connected to the first high-level signal input terminal.

14. The display device according to claim 13, wherein, The first-stage transmission circuit also includes: The sixth capacitor has one plate electrically connected to the third control node G, and the other plate electrically connected to the first-stage signal output terminal.

15. The display device according to claim 11, wherein, The display panel further includes a second gate driving sub-circuit and a second high-level signal line. The second gate driving sub-circuit is electrically connected to the second high-level signal line and the second low-level signal line. In a top view of the gate driving circuit, the second high-level signal line is located on the first side of the second low-level signal line and is located between the first low-level signal line and the second low-level signal line.

16. The display device according to claim 15, wherein, The first high-level signal line and the second high-level signal line cross the first gate driver sub-circuit and the second gate driver sub-circuit, and the first low-level signal line and the second low-level signal line cross the first gate driver sub-circuit and the second gate driver sub-circuit.

17. The display device according to claim 15, wherein, The line width at any point on the first high-level signal line is the same as the line width at any point on the second high-level signal line.

18. The display device according to claim 11, wherein, The channel width of the ninth transistor in the first stage transmission circuit is greater than or equal to 20 micrometers.

19. The display device according to claim 18, wherein, The channel width of the ninth transistor is in the range of 30 micrometers to 50 micrometers.

20. The display device according to claim 19, wherein, The channel width of the ninth transistor is 40 micrometers.

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