Method for preparing memory, and memory and electronic device

Abstract

Disclosed in the present disclosure are a method for preparing a memory, and a memory and an electronic device. The method for preparing a memory comprises: providing a substrate on which a plurality of memory cells arranged at intervals are formed; and forming on the substrate an interlayer dielectric layer having a double-layer structure, wherein the interlayer dielectric layer of the double-layer structure comprises a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer completely covers the memory cells on the substrate, and the filling height of the first interlayer dielectric layer located in a region between every two memory cells is not less than the height of the memory cells, the second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capability of the first interlayer dielectric layer is better than that of the second interlayer dielectric layer. By means of the solution of the present disclosure, the formation of air gaps between memory cells can be avoided during the preparation of a memory, and the influence of an interlayer dielectric layer on the RC delay problem can also be reduced, thereby improving the quality and performance of the prepared memory. FIG. 2

Description

Methods for fabricating memory, memory and electronic devices Cross-reference of related applications

[0001] This application claims priority to Chinese patent application filed on December 24, 2024, with application number 2024119157501 and entitled "Method for fabricating memory, memory and electronic device". Technical Field

[0002] This disclosure generally relates to the field of memory technology. More specifically, this disclosure relates to a method for fabricating a memory, a memory device, and an electronic device. Background Technology

[0003] Currently, some new types of memory on the market (such as resistive random access memory, RRAM) integrate the memory cells into the logic back-end process during fabrication, and fill the interlayer dielectric after the memory cell process is completed. However, the existing interlayer dielectric filling process creates air gaps (i.e., voids) between memory cells. The presence of these voids may damage the memory cells in subsequent processes. In addition, the presence of voids can also cause leakage between subsequent metal layers.

[0004] In view of this, there is an urgent need to provide a memory fabrication scheme in order to effectively solve the problem of gaps between memory cells during the interlayer dielectric filling process. Summary of the Invention

[0005] In order to at least solve one or more of the technical problems mentioned above, this disclosure proposes a method for fabricating a memory.

[0006] In a first aspect, this disclosure provides a method for fabricating a memory, comprising: providing a substrate on which a plurality of spaced memory cells are formed; and forming an interlayer dielectric layer comprising a dual-layer structure on the substrate, wherein the dual-layer interlayer dielectric layer comprises a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer completely covering the memory cells on the substrate, and the filling height of the first interlayer dielectric layer located in the region between every two memory cells is not less than the height of the memory cells, the second interlayer dielectric layer being formed on the first interlayer dielectric layer, and the filling capacity of the first interlayer dielectric layer being superior to that of the second interlayer dielectric layer.

[0007] In some embodiments, forming a bilayer interlayer dielectric layer on the substrate includes: forming a first interlayer dielectric layer on the substrate using a filler material with strong filling capacity, so that the first interlayer dielectric layer completely covers the memory cells on the substrate; and / or forming a second interlayer dielectric layer on the first interlayer dielectric layer using a filler material with a low dielectric constant.

[0008] In some embodiments, forming a first interlayer dielectric layer on the substrate using a filler material with high filling capacity, so that the first interlayer dielectric layer completely covers the memory cells on the substrate, includes: filling the substrate with a filler material with high filling capacity to form the first interlayer dielectric layer; and planarizing the first interlayer dielectric layer so that the filling height of the first interlayer dielectric layer located in the region between every two memory cells is not less than the height of the memory cells.

[0009] In some embodiments, planarizing the first interlayer dielectric layer includes: planarizing the first interlayer dielectric layer using a chemical mechanical planarization process.

[0010] In some embodiments, the fill height of the first interlayer dielectric layer located in the region between every two memory cells is flush with the height of the memory cells.

[0011] In some embodiments, forming a first interlayer dielectric layer on the substrate using a filling material with strong filling capacity, so that the first interlayer dielectric layer completely covers the memory cell on the substrate, includes: depositing a TEOS thin film on the substrate using a chemical vapor deposition process to obtain the first interlayer dielectric layer.

[0012] In some embodiments, forming a second interlayer dielectric layer on the first interlayer dielectric layer using a filler material comprising a low dielectric constant includes: depositing a black diamond film on the first interlayer dielectric layer using a chemical vapor deposition process to obtain the second interlayer dielectric layer.

[0013] In some embodiments, the distance between any two storage units is less than a threshold.

[0014] In some embodiments, the storage unit includes any one of the following: a resistive random access memory (RRAM) storage unit, a phase change random access memory (PCM) storage unit, a ferroelectric random access memory (FRAM) storage unit, or a magnetic random access memory (MAM) storage unit.

[0015] In a second aspect, this disclosure provides a memory fabricated using the memory fabrication method described in the first aspect.

[0016] In a third aspect, this disclosure provides a memory, comprising: a substrate having a plurality of spaced-apart memory cells formed thereon and an interlayer dielectric comprising a dual-layer structure; wherein the dual-layer interlayer dielectric layer comprises a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer completely covering the memory cells on the substrate, and the filling height of the first interlayer dielectric layer located in the region between every two memory cells is not less than the height of the memory cells, the second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capability of the first interlayer dielectric layer is superior to that of the second interlayer dielectric layer.

[0017] In a fourth aspect, this disclosure provides an electronic device, including: a memory as described in the second aspect or a memory as described in the third aspect.

[0018] The memory fabrication method described above, in this embodiment, involves forming a double-layer interlayer dielectric layer on a substrate with memory cells. A first interlayer dielectric layer with good filling capability completely fills and encapsulates the memory cells and the areas between them, avoiding air gaps between the cells. Simultaneously, a low dielectric constant material, such as BD, is used as the second interlayer dielectric layer, thereby reducing the overall dielectric constant of the interlayer dielectric layer and minimizing RC delay issues in subsequent logic circuits caused by excessively high dielectric constants. Therefore, the disclosed solution can avoid air gaps between memory cells during memory fabrication while simultaneously reducing the impact of the interlayer dielectric layer on RC delay issues, thereby improving the quality and performance of the fabricated memory. Attached Figure Description

[0019] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0020] Figure 1 shows a cross-sectional schematic diagram of a memory in the related art;

[0021] Figure 2 shows a schematic flowchart of a method for fabricating a memory according to an embodiment of this disclosure;

[0022] Figure 3 shows a flowchart illustrating a method for fabricating a memory according to another embodiment of this disclosure; and

[0023] Figures 4a to 4d show cross-sectional schematic diagrams of the memory during the interlayer dielectric layer filling process of the embodiments disclosed herein.

[0024] Figure label:

[0025] 100. Novel memory; 101. Memory cell; 102. BD thin film; 103. Air gap;

[0026] 400, memory cell; 401, substrate; 4011, base; 4012, dielectric layer; 402, memory cell; 4021, lower electrode; 4022, resistive switching layer; 4023, upper electrode; 4024, metal layer; 4025, sidewall protection layer; 403, first interlayer dielectric layer; 404, second interlayer dielectric layer. Detailed Implementation

[0027] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0028] It should be understood that the terms “comprising” and “including” used in this disclosure and claims indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0029] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0030] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0031] Exemplary application scenarios

[0032] As described in the background section above, the existing interlayer dielectric filling process can create air gaps (i.e., voids) between memory cells. The presence of these voids may damage the memory cells in subsequent processes, and may even cause leakage between the two subsequent metal layers.

[0033] In response, the inventors discovered that in relevant interlayer dielectric filling processes, low-dielectric-constant materials are required for the metal interlayer dielectric layer, but currently, mainstream low-dielectric-constant materials have relatively weak filling capabilities. Black diamond (BD) films are typically used as fillers to form the interlayer dielectric layer; however, BD films are suitable for filling on flat structures. As shown in Figure 1, in the fabrication process of novel memory such as RRAM 100, memory cells 101 are integrated into the logic back-end process. After integrating the memory cells 101, a certain distance exists between the memory cells 101, making the overall structure uneven. Continuing to use BD films 102 for interlayer dielectric filling at this point easily leads to the formation of the aforementioned air gaps 103.

[0034] To address this, simply replacing the BD film with a filler material with high fillability can avoid air gaps, but the high fillability of the filler material is more likely to cause RC delay problems in the logic circuit compared to the low fillability of the filler material. To overcome RC delay issues, related technologies employ a method of first depositing a dielectric layer with high fillability, followed by a low-K material with lower fillability as the second dielectric layer. In this technology, the first dielectric layer is relatively thin, and even after its deposition, recessed areas still exist between memory cells. Filling this uneven structure with a low-K material creates gaps or voids, which are then used to reduce RC delay. However, as the process shrinks further, the smaller spacing between memory cells makes it difficult to control the shape and size of these voids. These voids easily connect to the metal trench above the memory cell, leading to poor copper filling in the metal trench. Furthermore, voids appearing at the TE vias above the memory cells can also easily connect to the TE vias above adjacent memory cells, resulting in poor copper filling.

[0035] To address the problems in the aforementioned scenarios, the inventors proposed a memory fabrication scheme that completely fills and encapsulates the memory cells and the areas between them using a first interlayer dielectric layer with good filling capability, thereby avoiding the formation of air gaps between the memory cells. Simultaneously, a material with a low dielectric constant, such as BD, is used as the second interlayer dielectric layer to reduce the overall dielectric constant of the interlayer dielectric layer and minimize the RC delay problem in subsequent logic circuits caused by an excessively high dielectric constant.

[0036] Furthermore, it's important to understand that in this disclosed solution, the filling capacity of a material can be differentiated by its specific filling performance. Strong filling capacity is typically characterized by uniform filling and the absence of pores or defects. Uniform filling means that during the manufacturing process, the material is evenly filled into the designed trenches, pores, or small channels, with little or no incomplete coverage. The absence of pores or defects means the absence or minimal presence of pores, layers, or other defects. Weak or poor filling capacity is characterized by uneven filling and the presence of pores and defects. Uneven filling refers to the uneven filling of the material within a complex microstructure, potentially leading to excessive material in some areas (causing short circuits) or unfilled areas (causing open circuits or poor connections). Pores and defects refer to insufficient filling resulting in pores, layers, defects, or unfilled voids in trenches. These voids affect current flow, increasing resistance and potentially causing electrical open circuits.

[0037] Furthermore, besides using specific filling performance to distinguish the strength of filling ability, the strength of step coverage can also be used to characterize the filling ability of a material. Specifically, filling ability can be understood as step coverage. This step coverage has a fixed calculation formula: step coverage = T top / T bottom. Where T top is the deposition thickness at the upper surface of the trench or hole, and T bottom is the deposition thickness at the bottom of the trench or hole. In the scheme disclosed in this paper, the filling ability can be limited to "1 ≥ step coverage ≥ 0.5", in other words, the value of T top / T bottom needs to be greater than or equal to 0.5, and the maximum value is 1. The endpoint value "1" means that if the material can completely and uniformly cover the entire trench (without "dead corners"), then the step coverage is 1. The endpoint value "0.5" means that if the step coverage value is less than 0.5, it is difficult to meet the requirements for material deposition effect in the scheme disclosed in this paper. For example, gaps or voids or more voids or voids may appear more easily when filling between storage cells. That is, the strong filling capability in this disclosed scheme can be specifically reflected in the step coverage capability value of [0.5, 1].

[0038] The following describes the disclosed scheme in detail with reference to Figures 2 to 4d.

[0039] Figure 2 shows a schematic flowchart of a memory fabrication method 200 according to an embodiment of this disclosure. It should be noted that the memory in the scheme disclosed herein may include resistive random access memory (e.g., RRAM), phase-change random access memory (PCRAM), magnetic random access memory (MRAM), ferroelectric random access memory, or other memories with similar fabrication process requirements.

[0040] As shown in Figure 2, in step S201, a substrate with a plurality of spaced memory cells formed thereon can be provided. The memory cells here can include any one of the following: memory cells of resistive random access memory, memory cells of phase change random access memory, memory cells of ferroelectric random access memory, or memory cells of magnetic random access memory.

[0041] In the disclosed scheme, commonly used memory cell fabrication processes can be employed to fabricate the memory cells. For example, for a resistive random access memory (RRAM), the memory cell may include a structure formed from bottom to top by a lower electrode, a resistive switching layer, and a top electrode (e.g., a trapezoidal or other shaped structure). In some embodiments, the substrate may include a base and a dielectric layer on the base, and the lower electrode may fill the via formed by the dielectric layer. The resistive switching layer is located between the lower electrode and the top electrode, and a metal layer is also disposed between the lower electrode and the resistive switching layer. A sidewall protective layer is also formed on the outer side of the trapezoidal structure. This embodiment does not involve many improvements to the formation of memory cells; therefore, the specific materials of each structure within the memory cell will not be described in detail here.

[0042] In step S202, an interlayer dielectric layer comprising a dual-layer structure is formed on the substrate. The dual-layer interlayer dielectric layer may include a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer completely covers the memory cells on the substrate, and the filling height of the first interlayer dielectric layer located in the region between every two memory cells is not less than the height of the memory cell. The second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capability of the first interlayer dielectric layer is superior to that of the second interlayer dielectric layer.

[0043] In this embodiment, a first interlayer dielectric layer with good filling capability is used to completely encapsulate the memory cells, and the filling height of the first interlayer dielectric layer in the area between every two memory cells is not less than the height of the memory cells. Thus, not only are the individual memory cells completely isolated, but the area between memory cells is also filled with the first interlayer dielectric layer. That is, the obviously uneven areas in the entire structure (memory cells and the area between every two memory cells) are effectively covered by the first interlayer dielectric layer, which helps to make the upper surface of the entire structure nearly planar. Then, a second interlayer dielectric layer is formed on top of the first interlayer dielectric layer. Even if the filling capability of the second interlayer dielectric layer is poor (e.g., using a low dielectric constant filling material such as BD), no air gaps will form in the entire structure. Furthermore, the good filling capability of the first interlayer dielectric layer also means that its dielectric constant may be relatively high. The disclosed solution uses a double-layer structure of interlayer dielectric layers including a first interlayer dielectric layer and a second interlayer dielectric layer to reduce the overall dielectric constant of the interlayer dielectric layers through the low dielectric constant of the second interlayer dielectric layer, minimizing the RC delay problem in subsequent logic circuits caused by an excessively high dielectric constant. Therefore, the disclosed solution can avoid the formation of air gaps between memory cells during the memory fabrication process, while also reducing the impact of interlayer dielectric layers on RC delay issues, thereby improving the quality and performance of the fabricated memory.

[0044] Figure 3 shows a schematic flowchart of a memory fabrication method 300 according to another embodiment of this disclosure. It is understood that the fabrication method 300 in Figure 3 can be interpreted as a further extension or supplement to the fabrication method 200 in Figure 2. Therefore, the descriptions preceding in conjunction with Figure 2 also apply to the following text.

[0045] As shown in Figure 3, in step S301, a substrate with multiple spaced memory cells formed thereon can be provided. As mentioned above, in this embodiment, commonly used memory cell fabrication processes can be used to fabricate the memory cells, which will not be elaborated here. Furthermore, the memory fabricated in this embodiment can be a resistive random access memory (RADM), a phase-change random access memory (PCM), a magnetic random access memory (MRM), a ferroelectric random access memory (FRAM), or other memories with similar fabrication processes.

[0046] The memory cell can be any of the following: a resistive random access memory (RRAM) cell, a phase-change random access memory (PCM) cell, a ferroelectric random access memory (FRAM) cell, or a magnetic random access memory (MAM) cell. In some embodiments, the memory cell may include a structure formed by a lower electrode, a resistive switching layer, and an upper electrode sequentially from bottom to top. Furthermore, as mentioned above, there is a certain distance between the memory cells, and this distance decreases with process requirements, especially for some advanced processes (e.g., semiconductor back-end processes such as 28nm / 22nm / 14nm). In this embodiment, the distance between each pair of memory cells needs to be less than a threshold value, which is specifically set according to the fabrication process requirements. In particular, it needs to be set according to some advanced process requirements; for example, the threshold value needs to meet the distance requirements between memory cells for semiconductor back-end processes such as 28nm / 22nm / 14nm.

[0047] An interlayer dielectric layer comprising a dual-layer structure can be formed on the aforementioned substrate. Specifically, the dual-layer interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer. In this embodiment, the dual-layer interlayer dielectric layer can be formed via steps S302 to S304.

[0048] In practical applications, a filling material with strong filling capacity can be used to form a first interlayer dielectric layer on the substrate, so that the first interlayer dielectric layer completely covers the memory cells on the substrate. Specifically, in step S302, a filling material with strong filling capacity can be filled onto the substrate to form the first interlayer dielectric layer. The filling material with strong filling capacity specifically includes materials with uniform filling and no pores or defects, or materials with a step coverage value of [0.5, 1]. For example, a TEOS thin film can be deposited on the substrate using a chemical vapor deposition process to obtain the first interlayer dielectric layer. It should be noted that the specific material of the filling material with strong filling capacity is not limited here; it can be a TEOS thin film, a material with better or similar filling capacity to a TEOS thin film, or other materials with strong filling capacity. For example, polynitrosilane (PSZ), undoped silicon dioxide (USG), phosphate glass (PSG), and borosilicate glass (BPSG). Then, at step S303, the first interlayer dielectric layer can be planarized so that the filling height of the first interlayer dielectric layer located in the region between every two memory cells is not less than the height of the memory cell.

[0049] In this embodiment, the first interlayer dielectric layer can be planarized using processes including but not limited to etching and polishing. Preferably, a chemical mechanical planarization (CMP) process can be used to planarize the first interlayer dielectric layer. The surface of the first interlayer dielectric layer after CMP treatment is relatively flat, which is beneficial for the formation of the second interlayer dielectric layer.

[0050] Furthermore, in some embodiments, the fill height of the first interlayer dielectric layer located in the region between every two memory cells is flush with the height of the memory cell. In this implementation scenario, the first interlayer dielectric layer can either completely cover or wrap the memory cell and the region between the memory cells, or more space can be reserved to form the second interlayer dielectric layer.

[0051] In step S304, a second interlayer dielectric layer can be formed on the first interlayer dielectric layer using a filler material with a low dielectric constant. In this disclosure, a filler material with a low dielectric constant can be understood as a filler material with a dielectric constant lower than 3.0. For example, a black diamond thin film can be deposited on the first interlayer dielectric layer using chemical vapor deposition to obtain the second interlayer dielectric layer. It should be noted that the description of the low dielectric constant filler material here is merely illustrative, and the disclosure is not limited to using a black diamond thin film as the low dielectric constant filler material; other low dielectric constant materials can also be used as filler materials to form the second interlayer dielectric layer. For example, low dielectric constant filler materials can also include materials such as coral, silk, BCB, fox, and MSQ.

[0052] Furthermore, the disclosed scheme does not limit the filling height ratio of the first interlayer dielectric layer and the second interlayer dielectric layer. For example, the filling height of the first interlayer dielectric layer located in the region between every two memory cells can be set to be flush with or equal to the height of the memory cells, and the remaining space above the first interlayer dielectric layer is used to form the second interlayer dielectric layer. Alternatively, the filling height of the first interlayer dielectric layer located in the region between every two memory cells can be set to be higher than the height of the memory cells, and the remaining space above the first interlayer dielectric layer is used to form the second interlayer dielectric layer. In actual fabrication processes, the memory cells of the memory need to be specifically located between two metal layers; therefore, the filling heights of the first and second interlayer dielectric layers can be specifically set according to the height between the metal layers and the height of the memory cells.

[0053] After the second interlayer dielectric layer is formed, subsequent standard logic processes can be performed to complete the fabrication of the entire memory.

[0054] Therefore, the disclosed solution addresses a series of problems caused by air gaps by forming a first interlayer dielectric layer made of materials such as TEOS during the memory fabrication process. Furthermore, it minimizes the impact of TEOS on issues such as RC delay by grinding away as much TEOS as possible and depositing a low-dielectric-constant material from standard logic processes to form a second interlayer dielectric layer.

[0055] The fabrication process of the above-mentioned memory is further explained below with reference to Figures 4a to 4d.

[0056] In this embodiment, a substrate on which multiple spaced memory cells are formed is first provided, and then a double-layer interlayer dielectric layer is formed on the substrate. The double-layer interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer completely covers the memory cells on the substrate, and the filling height of the first interlayer dielectric layer in the region between every two memory cells is not less than the height of the memory cell. The second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capacity of the first interlayer dielectric layer is superior to that of the second interlayer dielectric layer.

[0057] Specifically, as shown in FIG4a, the memory 400 includes a plurality of spaced memory cells 402, which are specifically formed on a substrate 401. Each memory cell 402 may include a structure formed from bottom to top by a lower electrode 4021, a resistive switching layer 4022, and an upper electrode 4023. In some embodiments, the substrate 401 may include a base 4011 and a dielectric layer 4012 on the base, and the lower electrode 4021 may fill a lower electrode via formed in the dielectric layer 4012. The resistive switching layer 4022 is located between the lower electrode 4021 and the upper electrode 4023. A metal layer 4024 is also disposed between the lower electrode 4021 and the resistive switching layer 4022, and a sidewall protective layer 4025 is formed on the outer side of the trapezoidal structure. It should be noted that the specific structural description of the memory cell here is merely illustrative, and the disclosed solution does not limit the specific structure or formation process of the memory cell.

[0058] After the storage cell 402 is fabricated, an interlayer dielectric can be filled into it. As shown in Figure 4b, a first interlayer dielectric layer 403 can be formed on the substrate 401 using a filling material with strong filling capacity (such as a TEOS film), so that the first interlayer dielectric layer 403 completely covers the storage cell 403 on the substrate. In this embodiment, the first interlayer dielectric layer 403 completely covering the storage cell 403 on the substrate can be understood as completely enclosing each storage cell 402 and the area between the storage cells 402. The filling height of the first interlayer dielectric layer 403 located in the area between every two storage cells 402 is not lower than that of the storage cell 402.

[0059] Next, as shown in Figure 4c, the first interlayer dielectric layer 403 can be planarized to remove excess portions. Preferably, a chemical mechanical planarization process can be used to completely remove the first interlayer dielectric layer 403 located above the top of the memory cell 402, so that the filling height of the first interlayer dielectric layer 403 located in the region between every two memory cells 402 is flush with the height of the memory cell 402.

[0060] Next, as shown in Figure 4d, a second interlayer dielectric layer 404 is formed on the first interlayer dielectric layer 403. For example, a low dielectric constant (i.e., low K value) filling material such as a black diamond thin film can be deposited on the first interlayer dielectric layer 403 using a chemical vapor deposition process to obtain the second interlayer dielectric layer 404. Then, subsequent standard logic processes are performed to complete the fabrication of the memory 400.

[0061] Through the fabrication process of the memory 400 described above, a double-layer interlayer dielectric layer (including a first interlayer dielectric layer 403 and a second interlayer dielectric layer 404) can be formed on the substrate 401 on which the memory cells 402 are fabricated. The first interlayer dielectric layer 403, with its superior filling capability, completely fills and encloses the memory cells 402 and fills the area between the memory cells 402, avoiding air gaps between them. Simultaneously, a low-dielectric-constant material is used as the second interlayer dielectric layer 404 to reduce the overall dielectric constant of the interlayer dielectric layer, minimizing RC delay issues in subsequent logic circuits caused by excessively high dielectric constants. Therefore, when forming the first interlayer dielectric layer 403, because it is formed using a material with strong filling capability, no air gaps are formed. After the memory cells 402 on the substrate are filled by the first interlayer dielectric layer 403, the filling height of the first interlayer dielectric layer in the region between the memory cells is not less than the height of the memory cells, making the overall surface of the filled structure relatively flat (especially after planarization treatment). At this time, the second interlayer dielectric layer 404 with a low dielectric constant is used to continue filling without forming air gaps. It can be seen that the solution disclosed in this paper can avoid the formation of air gaps between memory cells 402, while also reducing the impact of the interlayer dielectric layer on the RC delay problem, thereby improving the quality and performance of the fabricated memory 400.

[0062] Furthermore, the disclosed solution also proposes a memory comprising a substrate on which a plurality of spaced memory cells are formed and an interlayer dielectric comprising a dual-layer structure. The dual-layer interlayer dielectric layer comprises a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer completely covers the memory cells on the substrate, and the filling height of the first interlayer dielectric layer located in the region between every two memory cells is not less than the height of the memory cells. The second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capability of the first interlayer dielectric layer is superior to that of the second interlayer dielectric layer.

[0063] The memory here may include resistive random access memory (RRAM), phase-change random access memory (PCM), ferroelectric random access memory (FRAM), magnetic random access memory (MAM), or other memories with similar fabrication process requirements. The structure of this memory includes the same, similar, or nearly identical structure as shown in Figure 4d. In some embodiments, the first interlayer dielectric layer in this memory can be formed using a filling material with strong filling capacity. This filling material may include TEOS thin film, PSZ, USG, PSG, BPSG, or other materials with uniform filling and no pores or defects, or other materials with a step coverage value of [0.5, 1]. Furthermore, the filling height of the first interlayer dielectric layer located in the region between every two memory cells needs to be flush with the height of the memory cell.

[0064] Furthermore, the second interlayer dielectric layer in this memory can be formed using a filling material with a low dielectric constant. This low dielectric constant filling material can include black diamond film, coral, silk, BCB, Fox, MSQ, or other materials with a dielectric constant lower than 3.0.

[0065] In practical applications, the aforementioned memory can be fabricated using the methods described above in conjunction with Figures 2 to 4d. It should be noted that the fabrication method for the memory with the above structure is not limited to the methods described in Figures 2 to 4d; specific fabrication methods can be developed based on actual application and design requirements to obtain the memory with the above structure.

[0066] Furthermore, the memory fabricated using the methods described in Figures 2 to 4d, or the memory having the above structure, can be applied to various electronic devices such as computers, mobile phones, cameras, game consoles, automobiles, and wearable devices. The specific category of electronic device is not limited here; it can include any device with storage requirements.

[0067] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for fabricating a memory, characterized in that, include: A substrate having a plurality of spaced memory cells formed thereon is provided; as well as An interlayer dielectric layer comprising a dual-layer structure is formed on the substrate, wherein the dual-layer interlayer dielectric layer comprises a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer completely covers the memory cells on the substrate, and the filling height of the first interlayer dielectric layer located in the region between every two memory cells is not less than the height of the memory cells, the second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capacity of the first interlayer dielectric layer is superior to that of the second interlayer dielectric layer.

2. The method for fabricating a memory according to claim 1, characterized in that, The interlayer dielectric layer forming a bilayer structure on the substrate includes: A first interlayer dielectric layer is formed on the substrate using a filler material with strong filling capacity, so that the first interlayer dielectric layer completely covers the memory cells on the substrate; and / or a second interlayer dielectric layer is formed on the first interlayer dielectric layer using a filler material including a low dielectric constant.

3. The method for fabricating a memory according to claim 2, characterized in that, Forming a first interlayer dielectric layer on the substrate using a filler material with strong filling capacity, so that the first interlayer dielectric layer completely covers the memory cells on the substrate, includes: A filler material with strong filling capacity is filled onto the substrate to form the first interlayer dielectric layer; The first interlayer dielectric layer is planarized so that the filling height of the first interlayer dielectric layer in the region between every two memory cells is not less than the height of the memory cell.

4. The method for fabricating a memory according to claim 3, characterized in that, Planarization of the first interlayer dielectric layer includes: The first interlayer dielectric layer is planarized using a chemical mechanical planarization process.

5. The method for fabricating a memory according to claim 1, characterized in that, The filling height of the first interlayer dielectric layer located in the region between every two storage cells is flush with the height of the storage cell.

6. The method for fabricating a memory according to claim 2, characterized in that, Forming a first interlayer dielectric layer on the substrate using a filler material with strong filling capacity, so that the first interlayer dielectric layer completely covers the memory cells on the substrate, includes: A TEOS thin film was deposited on the substrate using a chemical vapor deposition process to obtain the first interlayer dielectric layer.

7. The method for fabricating a memory according to claim 2, characterized in that, Forming a second interlayer dielectric layer on the first interlayer dielectric layer using a filler material with a low dielectric constant includes: A black diamond film is deposited on the first interlayer dielectric layer using a chemical vapor deposition process to obtain the second interlayer dielectric layer.

8. The method for manufacturing a memory according to any one of claims 1 to 7, characterized in that, The distance between any two of the storage units is less than a threshold.

9. The method for manufacturing a memory according to any one of claims 1 to 7, characterized in that, The storage unit includes any one of the following: a resistive random access memory (RRAM) storage unit, a phase change random access memory (PCM) storage unit, a ferroelectric random access memory (FRAM) storage unit, or a magnetic random access memory (MAM) storage unit.

10. A memory, characterized in that, The memory is prepared using the memory preparation method described in any one of claims 1 to 9.

11. A memory, characterized in that, include: A substrate on which multiple spaced memory cells and an interlayer dielectric including a double-layer structure are formed; The interlayer dielectric layer of the dual-layer structure includes a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer completely covers the memory cells on the substrate, and the filling height of the first interlayer dielectric layer located in the region between every two memory cells is not less than the height of the memory cells. The second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capacity of the first interlayer dielectric layer is better than that of the second interlayer dielectric layer.

12. An electronic device, characterized in that, include: The memory as described in claim 10 or the memory as described in claim 11.

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