Memory operation method, memory, electronic device, and storage medium

Abstract

Embodiments of the present invention provide a memory operation method, a memory, an electronic device, and a storage medium. The memory operation method comprises: in response to detecting an error in a storage array of a memory during a working state of the memory, determining an error location of the error in the storage array; after the memory enters an idle state, controlling the memory to initiate a post-package repair process, and on the basis of the error location, performing replacement of a target storage cell at the error location with a replacement storage cell in the storage array used for the post-package repair process; and after the post-package repair process, switching the memory back to the working state, and using the replacement storage cell to replace the target storage cell for operation. The memory operation method can improve the reliability of the memory.

Description

Memory operation methods, memory, electronic devices and storage media

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411930802.2, filed on December 25, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a memory operation method, a memory, an electronic device, and a storage medium. Background Technology

[0004] As modern computer systems continue to increase their demand for memory access, the memory chips operate under high load in harsh environments for extended periods, making them highly susceptible to failure due to aging and other factors. Memory failures can lead to decreased stability in computer systems, and if the failed memory components are not repaired in a timely manner, they can even cause system crashes and other abnormal phenomena. Summary of the Invention

[0005] At least one embodiment of this disclosure provides a memory operation method, the memory operation method comprising: in response to detecting an error in the memory's storage array during the memory's operating state, determining the error location in the storage array; after the memory enters an idle state, controlling the memory to initiate a post-packaging repair process, and, based on the error location, performing a process to replace the target storage cell at the error location with a replacement storage cell in the storage array used for the post-packaging repair process; after the post-packaging repair process, switching the memory back to the operating state, and using the replacement storage cell to replace the target storage cell for operation.

[0006] For example, in the memory operation method provided in at least some embodiments of this disclosure, after the memory enters an idle state, the memory is controlled to start a post-packaging repair process, including: after the memory enters an idle state, the memory array is switched from working mode to repair mode, so that the memory starts a post-packaging repair process.

[0007] For example, the memory operation method provided in at least some embodiments of this disclosure further includes: stopping the reception of new access requests to the memory and clearing existing access requests in the memory, so that the memory enters an idle state.

[0008] For example, in the memory operation method provided in at least some embodiments of this disclosure, before the memory enters an idle state, the memory operation method further includes: releasing the space of the data cache occupied by existing access requests.

[0009] For example, in the memory operation method provided in at least some embodiments of this disclosure, after the memory enters an idle state, the memory operation method further includes: clearing the refresh commands to be sent in the memory, so that the memory array enters a first self-refresh state; and switching the memory array from a working mode to a repair mode in the first self-refresh state.

[0010] For example, in the memory operation method provided in at least some embodiments of this disclosure, the post-packaging repair process includes: in response to the end of the first self-refresh state, backing up the first data corresponding to the error location, and restoring the first data to the replacement storage unit after the target storage unit is replaced by a replacement storage unit.

[0011] For example, in the memory operation method provided in at least some embodiments of this disclosure, backing up the first data corresponding to the erroneous location includes: processing the first data using an error correction algorithm before backing it up.

[0012] For example, in the memory operation method provided in at least some embodiments of this disclosure, backing up the first data corresponding to the error location further includes: backing up the first data corresponding to the error location to the redundant space of the data cache space.

[0013] For example, in the memory operation method provided in at least some embodiments of this disclosure, restoring the first data to the replacement storage unit includes: recombining the first data corresponding to the error location and the second data written in parallel with the first data, and performing a write operation on the recombined data to restore the first data to the replacement storage unit.

[0014] For example, in a memory operation method provided in at least some embodiments of this disclosure, the memory array is configured to support data masking to restore first data to a replacement memory cell, including: restoring the first data to a replacement memory cell by operating the corresponding data mask to mask the operation of writing second data that needs to be written in parallel with the first data corresponding to the error location.

[0015] For example, the memory operation method provided in at least some embodiments of this disclosure further includes: sending a compensated refresh command in response to the completion of the post-packaging repair process.

[0016] For example, the memory operation method provided in at least some embodiments of this disclosure further includes: switching the memory array from repair mode to operating mode in a second self-refresh state in response to the completion of the repair mode.

[0017] For example, in the memory operation method provided in at least some embodiments of this disclosure, before starting the post-packaging repair process, the memory operation method further includes: reading the repair status register corresponding to the error location to determine whether there are available repair resources.

[0018] For example, the memory operation method provided in at least some embodiments of this disclosure further includes: in response to a reset operation or initialization operation of the memory, triggering a hard repair of the memory array to fix the repair result of replacing the target memory cell at the fault location in the memory array with a replacement memory cell in the memory array used for the post-packaging repair process.

[0019] At least one embodiment of this disclosure also provides a memory, which includes a memory array, an operation control module, a memory controller, and a repair module; the memory controller is configured to read and write to the memory array in an operational state; the repair module is configured to perform repair operations on the memory array; the operation control module is configured to: in response to detecting an error in the memory array in the operational state of the memory, determine the error location in the memory array, and after the memory enters an idle state, control the memory to start the repair module to perform a post-packaging repair process, wherein the repair module is further configured to, according to the error location, replace the target memory cell at the error location with a replacement memory cell in the memory array used for the post-packaging repair process; after the post-packaging repair process, switch the memory back to the operational state, whereby the memory controller uses the replacement memory cell to replace the target memory cell for operation.

[0020] At least one embodiment of this disclosure also provides a memory in which an operation control device includes: a selector, the input of which is connected to a memory controller and a repair control module, and the output of which is connected to a memory array; and a permission switching module configured to provide control signals to the selector so that the selector switches the memory array from a working mode to a repair mode, or from a repair mode back to a working mode.

[0021] At least one embodiment of this disclosure also provides a memory, which further includes a data cache configured to provide cache space required by the storage array in either an operating mode or a repair mode.

[0022] At least one embodiment of this disclosure also provides a memory, which further includes a repair status register configured to record whether repair resources are available at the location of the error.

[0023] At least some embodiments of this disclosure also provide an electronic device, including the memory provided in any embodiment of this disclosure.

[0024] At least some embodiments of this disclosure also provide a non-transitory storage medium that non-transitoryly stores computer-executable instructions, wherein when the computer-executable instructions are executed by at least one processor, they implement the memory operation method provided in any embodiment of this disclosure. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0026] Figure 1 shows a schematic flowchart of a memory operation method provided in at least one embodiment of the present disclosure;

[0027] Figure 2 illustrates a data backup schematic diagram provided by at least one embodiment of the present disclosure;

[0028] Figure 3 illustrates a data recovery schematic diagram provided by at least one embodiment of the present disclosure;

[0029] Figure 4 illustrates an exemplary flowchart of a memory operation method provided in at least one embodiment of this disclosure;

[0030] Figure 5 shows a block diagram of a memory provided in at least one embodiment of the present disclosure;

[0031] Figure 6 shows a schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure; and

[0032] Figure 7 shows a schematic diagram of a non-transitory storage medium provided in at least one embodiment of the present disclosure. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0035] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components are omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is indicated by the same or similar reference numerals in each drawing.

[0036] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of this disclosure; however, these terms may vary depending on the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0037] This disclosure uses flowcharts to illustrate the operations performed by a system according to embodiments of this disclosure. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0038] Computer memory, such as main memory, can be random-access memory (RAM), such as dynamic random-access memory (DRAM). The RAS (Reliability, Availability, Serviceability) characteristics of memory refer to three key attributes: reliability, availability, and serviceability. These attributes work together to ensure the stability of the computer system and the integrity of the data.

[0039] For example, the memory may be a memory that uses Double Data Rate Fourth (DDR4) or Double Data Rate Fifth (DDR5) dynamic random access memory technology.

[0040] Checking for bad cells (i.e., faulty or unreliable memory cells) in memory is a crucial step in ensuring system stability and data integrity. Different types of memory (such as DRAM, SRAM, and NAND flash memory) may require different detection methods, including hardware diagnostic tools (such as Built-in Self-Test (BIST)) and software diagnostic tools (such as memory testing software). After bad cells are identified, repair of the memory can be considered depending on the specific circumstances.

[0041] DDR4 memory technology introduced Post Package Repair (PPR), a feature that significantly improves memory reliability and durability. PPR allows for the introduction of redundancy within the memory array and supports the replacement of fixed errors in the array through the PPR process, effectively repairing errors in the memory array. For example, it can repair single-bit errors, multi-bit errors, and entire row errors. DDR4 only limited the repair of fixed error types within the same row of the memory array, but with technological advancements, DDR5 further enhanced the PPR function compared to DDR4. DDR5 memory technology implements two main types of PPR: Post Package Hard Repair (hPPR) and Post Package Soft Repair (sPPR).

[0042] Post-encapsulation hard repair allows each bank in the memory array to correct at least one row address, and the repair is permanent. Once programmed, the electronic fuse cannot be switched back to the unfuse state.

[0043] For example, when the memory detects errors in the memory array, it first needs to determine whether these errors are all confined to the same row in the memory array. If the errors are indeed located in the same row, a system interrupt is sent, causing the system to enter a reset state. After the system exits the reset state, the initialization and training steps of the memory chips in the memory array need to be completed, and the hPPR repair process begins.

[0044] For example, according to the DDR standard protocol, a command is sent to initiate the hPPR repair process for the memory chip. Then, the row address that needs repair is passed to the memory chip, which then replaces the erroneous row address with a row address from a redundant space. After the memory chip completes the hPPR repair process, a command is sent to exit and continue executing the remaining initialization steps. Once the system initialization process is complete, the memory re-enters the working state, and after the erroneous row has been successfully replaced, the memory can perform normal read and write operations.

[0045] Post-package soft repair provides a quick but temporary method to repair a row of addresses on a single memory bank. In contrast to post-package hard repair, the repair results are lost if a power outage or reset occurs after post-package soft repair.

[0046] When a server or computer system needs to maintain a stable working state for a long time, if the memory of the server or computer system is found to have partial failure or error, both hard repair after packaging (hPPR) and soft repair after packaging (sPPR) have certain problems to some extent.

[0047] For example, if a hard repair after packaging (hPPR) is initiated, the working server or computer system needs to be reset. The reset operation takes a long time, which will cause the working state of the server or computer system to be interrupted. If the working state must be maintained, the memory errors cannot be processed in time, thus accumulating and even leading to system crash.

[0048] For example, if a soft repair (sPPR) is initiated to temporarily repair the memory in the working state, the repair will be limited by the amount of redundant space in the memory array used for sPPR, and all repair results will be lost once a power failure or reset operation occurs.

[0049] At least one embodiment of this disclosure provides a memory operation method, the memory operation method comprising: in response to detecting an error in the memory's storage array during the memory's operating state, determining the error location in the storage array; after the memory enters an idle state, controlling the memory to initiate a post-packaging repair process, and, based on the error location, performing a process to replace the target storage cell at the error location with a replacement storage cell in the storage array used for the post-packaging repair process; after the post-packaging repair process, switching the memory back to the operating state, and using the replacement storage cell to replace the target storage cell for operation.

[0050] In the memory operation method of the above embodiments of this disclosure, since it is possible to detect errors in the memory array during the memory's operating state, and after the memory enters an idle state, control to initiate a post-packaging repair process, and after the repair is completed, switch the memory back to the operating state, this allows for timely and dynamic error repair of the memory by triggering the post-packaging repair process while the memory is in the operating state. This improves the operational stability of the memory during operation, avoiding error accumulation caused by the long-term operation of servers or computer systems. Furthermore, this memory operation method maximizes the rational utilization of existing memory logic, avoiding the use of complex logic devices, thus achieving higher returns with lower hardware costs.

[0051] The various embodiments of this disclosure will now be described with reference to specific examples.

[0052] Figure 1 shows a schematic flowchart of a memory operation method provided in at least one embodiment of the present disclosure.

[0053] As shown in Figure 1, in some embodiments of this disclosure, the memory operation method includes steps S30-S32.

[0054] Step S30: In response to detecting an error in the memory's storage array during the memory's operating state, determine the location of the error in the storage array.

[0055] The memory can be RAM. The memory's operational state means it is powered on, for example, after initialization and configuration operations have been completed. Therefore, the memory is in a state that can be accessed or operated, such as being readable or writable. While the memory is in an operational state, the memory system can periodically or at regular intervals check for errors in the memory array. When an error is detected in the memory array while the memory is operational, the location of the error within the memory array is determined.

[0056] For example, a memory includes a memory array, decoding driver circuitry, and read / write circuitry, and is connected to external systems, such as processors and direct memory access (DMA) controllers, via address buses, data buses, and control buses to receive access requests (e.g., read / write requests) from these hosts. The memory array comprises multiple memory cells (memory elements) arranged in a multi-row, multi-column array, addressed by rows and columns. The decoding driver circuitry includes address decoders, word line drivers, bit line drivers, etc. Each memory cell, depending on the type of memory, can be a unit circuit such as a dynamic random access memory (DRAM), static random access memory (SRAM), or flash memory (NAND or NOR).

[0057] For example, the presence of errors in a storage array indicates the presence of bad cells. For instance, it's possible to detect a single faulty row in the storage array, or it's possible to detect several faulty rows.

[0058] For example, the erroneous row can be identified by detecting when a read request sent to a specific row consistently returns erroneous data, or by identifying when a write request sent to a specific row returns an error.

[0059] For example, when an error is detected in a memory array, the memory system can record the location of the error, such as the faulty memory bank group, faulty bank, faulty row, and memory cell number (also called memory chip number). For example, when multiple memory chips are involved, the faulty memory chip (rank) can be recorded; each memory chip is a set of memory chips that respond to the same Chip Select (CS) signal. For example, when multiple dies are stacked in a three-dimensional chip, the faulty component identifier (CID) can be recorded to distinguish different die layers.

[0060] Step S31: After the memory enters an idle state, control the memory to start the post-packaging repair process. Based on the error location, replace the target memory cell at the error location with the replacement memory cell in the memory array used for the post-packaging repair process.

[0061] The idle state (IDLE) of memory refers to a state where all memory cells (e.g., DRAM chips) in the memory array currently have no executable access requests (e.g., read or write requests). The target memory cell can also be called the target memory chip, for example, the target memory chip could be a DRAM chip. The memory is waiting for the next access request to arrive. For example, the idle state of memory could be a low-power mode or a wait mode. For example, the memory can enter an idle state by controlling the power management register (PCON), for example, by setting the IDL bit in the power management register to 1.

[0062] In some embodiments of this disclosure, the operation method of the memory described above further includes step S300.

[0063] Step S300: Stop receiving new access requests to the memory and clear existing access requests in the memory to put the memory into an idle state.

[0064] For example, when an error is detected in the memory array, the memory in the active state has multiple existing access requests pending and is ready to accept new access requests. Therefore, by stopping the acceptance of new access requests to the memory and clearing the existing access requests in the memory, the memory is made idle, leaving no access requests to be executed.

[0065] For example, when there are no available access requests in the memory, the memory system can send a precharge command (Precharge PRE) to the memory array to put the memory into an idle state. The precharge command is used to close open rows in a specified memory array or cancel all open rows in the memory array.

[0066] In some embodiments of this disclosure, the memory operation method further includes step S301 before the memory enters an idle state.

[0067] Step S301: Release the space occupied by the data cache for existing access requests.

[0068] A data cache, often simply called a cache, can be a cache dedicated to memory or a cache that can be reused for other purposes, such as a level 1 cache, level 2 cache, or higher-level caches (e.g., the last level cache (LLC)). For example, caching before accessing the memory array allows the faster storage speed of the cache to address the high latency issues when accessing the memory array, thereby improving the performance of accessing the memory array.

[0069] For example, when the memory receives multiple pending access requests, they can be cached before accessing the memory array. In the above operation steps, although the existing access requests in the memory are cleared, the data cache may have already cached the data of these existing access requests. Since the data corresponding to the existing access requests has been cleared and will no longer be accessed, the space occupied by the data cache for the existing access requests can be released before the memory enters an idle state.

[0070] Post Package Repair (PPR) is a mechanism for repairing faulty cells in a memory array. In this process, repair can be performed by pre-selecting replacement memory cells, or the progress of the PPR process can be controlled and indicated by reading the repair status register.

[0071] In some embodiments of this disclosure, the memory operation method further includes step S310 before initiating the post-packaging repair process.

[0072] Step S310: Read the repair status register corresponding to the error location to determine if there are available repair resources.

[0073] For example, a corresponding repair status register can be provided for each memory cell in the memory array. For instance, the repair status register can be a mode register MR54, MR55, MR56, or MR57 in the memory. The repair status register can be used to check whether there is a usable replacement memory cell in the memory bank or group of memory corresponding to the fault location. For example, the replacement memory cell may be a usable repair resource, such as a replacement row being a usable redundant row, or a replacement column being a usable redundant column.

[0074] For example, the repair status register can determine whether repair resources are available by checking the PPR table.

[0075] For example, in order to initiate the post-packaging repair (PPR) process, a series of operational controls are required. For instance, the memory can be dynamic random access memory (DRAM). For example, according to the DDR4 / DDR5 standard protocol, a series of PPR instruction sequences can be sent to initiate the PPR process of the memory chip.

[0076] First, the PPR process can be initiated by setting certain bits in the repair control register, thus enabling the memory to enter the PPR process. For example, different PPR modes can be initiated by controlling the control bits of the repair control register MR4. For instance, setting bit A13 of the repair control register MR4 to 1 initiates the hard repair after packaging (hPPR) mode; setting bit A5 of the repair control register MR4 to 1 initiates the soft repair after packaging (sPPR) mode.

[0077] Next, a specified security key sequence can be sent. This security key sequence is used to ensure the legality and correctness of the operations in the PPR process.

[0078] Subsequently, in order to replace the target storage cell at the error location with a replacement storage cell in the storage array used for the post-packaging repair process, the error location (e.g., the target row address of the target storage cell) needs to be sent via an active command. The active command is used to prepare the target storage cell in the memory that needs to be replaced, so that subsequent operations can be performed on the specified target storage cell (e.g., the erroneous row).

[0079] Following the activation command, a write command is sent to the memory to write data to the previously activated target memory cell. This allows the target memory cell for which the PPR process needs to be performed to be selected by writing the data. Since the write command typically includes the data to be written and the target column address of the target memory cell, the exact location of the target memory cell for which the PPR process needs to be performed can be determined (i.e., the target row address and target column address of the target memory cell are known).

[0080] In some embodiments of this disclosure, after the memory enters an idle state in step S31, the memory is controlled to start the post-packaging repair process. The operation method of the memory includes step S311.

[0081] Step S311: After the memory enters an idle state, switch the memory array from working mode to repair mode to enable the memory to start the post-packaging repair process.

[0082] When the storage array is in working mode, the memory is in a working state, and the storage array performs read and write operations in this state. When the storage array is in repair mode, the memory initiates the post-packaging repair process, and the storage array repairs the faulty locations through the post-packaging repair process.

[0083] For example, the memory includes a memory controller that controls the memory array to read and write operations during operation. The memory also includes a repair module that can perform repair operations on the faulty locations in the memory array through a post-packaging repair process. For instance, in response to an error detected in the memory array during operation, control of the memory array can be switched from the memory controller to the repair module, switching the memory array from operating mode to repair mode and initiating the post-packaging repair process.

[0084] After the memory enters the post-packaging repair process, the target memory cell (also known as the target memory chip) at the fault location can be replaced with a replacement memory cell in the memory array used for the post-packaging repair process, based on the fault location of the memory array.

[0085] In at least one example, the replacement storage unit is a storage unit that can respond normally to access requests. The replacement storage unit may be a storage unit in the storage array that has been pre-allocated for the post-installation repair process.

[0086] Step S32: After the post-packaging repair process, switch the memory back to the working state and use a replacement memory cell to replace the target memory cell for operation.

[0087] Switching the memory back to the working state ends the post-packaging repair process. For example, the end of the PPR process can be controlled by setting certain bits in the repair control register. For instance, the end of the PPR process can be controlled by setting the control bits of the repair control register MR4. For example, setting bit A13 of the repair control register MR4 to 0 ends the hPPR mode, and setting bit A5 of the repair control register MR4 to 0 ends the sPPR mode.

[0088] For example, the memory array can be switched from repair mode to operating mode, enabling the memory to complete the repair process after packaging. Alternatively, control of the memory array can be switched from the repair module to the memory controller, enabling the memory to complete the repair process after packaging.

[0089] Since the target memory cell at the fault location has been replaced with a replacement memory cell that can normally respond to access requests during the post-packaging repair process, when the memory switches back to the working state, if the memory receives an access request for the target memory cell at the fault location of the memory array, it will directly access the replacement memory cell, allowing the replacement memory cell to replace the target memory cell in responding to the access request.

[0090] Through the above steps S30-S32, when the memory is in the working state, it is possible to detect errors in the memory's storage array and promptly and dynamically trigger the post-packaging repair process to repair errors in the memory in the working state, thereby improving the reliability of the memory.

[0091] In some embodiments of this disclosure, after the memory enters an idle state, the memory operation method further includes step S313.

[0092] Step S313: Clear the pending refresh commands in the memory to put the memory array into the first self-refresh state; in the first self-refresh state, switch the memory array from working mode to repair mode.

[0093] For example, in at least one instance, after the memory enters an idle state, the post-packaging repair process may not be able to start immediately, and the memory may need to wait in the idle state. For example, if the memory is dynamic random access memory (DRAM), DRAM needs to be refreshed according to a preset period to maintain data integrity. For example, after the memory enters an idle state, the memory controller in the memory also needs to issue a refresh command (REF) according to a preset period.

[0094] Since the waiting time in the idle state is unknown, to ensure a smoother process for initiating the post-packaging repair process from the memory's operating state and to prevent data loss, the pending refresh commands in the memory can be cleared, allowing the memory array to enter a self-refresh state (also known as the first self-refresh state). For example, after clearing the pending refresh commands in the memory controller, the memory controller can send a self-refresh entry (SRE) command to the memory array, causing the memory to enter the first self-refresh state.

[0095] Self-refresh mode is a low-power mode of memory. In this mode, the memory array can use an internal counter to trigger a refresh without the need for an external refresh command, thus ensuring that the data inside the memory is not lost even in low-power mode.

[0096] For example, in the first self-refresh state, the storage array can be switched from the working mode to the repair mode. For example, in the first self-refresh state, the control of the storage array can be switched from the storage controller to the repair module, so that the memory can start the repair process after packaging.

[0097] In some embodiments of this disclosure, the memory operation method further includes step S314.

[0098] Step S314: In response to the completion of the repair mode, switch the storage array from repair mode to working mode in the second self-refresh state.

[0099] For example, after the repair mode is completed, the memory may not immediately return to the working mode, and there may be a situation where the memory needs to wait. Since the waiting time is unknown, in order to prevent data loss and avoid excessive power consumption, the memory can enter a second self-refresh state. For example, a self-refresh entry (SRE) command can be sent to the memory array to put the memory into a second self-refresh state.

[0100] When the memory can be switched, the memory array can be switched from repair mode to working mode in the second self-refresh state. For example, in the second self-refresh state, the control of the memory array can be switched from the repair module to the memory controller, so that the memory can return to the working state.

[0101] In some embodiments of this disclosure, the above-described post-encapsulation repair process may include steps S40 and S41.

[0102] Step S40: In response to the end of the first self-refresh state, back up the first data corresponding to the error location.

[0103] After entering the post-packaging repair process, in order to avoid replacing the target storage unit at the fault location with a replacement storage unit, which would cause the data originally written to the target storage unit to be lost (for example, the data in the target storage unit is corrupted), it is necessary to back up the data corresponding to the target storage unit at the fault location (also known as the first data) before replacing the target storage unit.

[0104] Since the memory array has been set to the first self-refresh state before entering the post-packaging repair process, and data cannot be backed up in the self-refresh state, the memory controller can send a self-refresh exit command (SRX) to allow the memory array to exit the first self-refresh state in order to back up the first data corresponding to the error location.

[0105] Figure 2 illustrates a data backup schematic diagram provided by at least one embodiment of the present disclosure.

[0106] As shown in Figure 2, in this embodiment, the memory adopts the structure of a Dual Inline Memory Module (DIMM) using DDR5 memory technology. In the illustrated DDR5 memory, each DIMM has two channels, namely channels CHA and CHB as shown in the figure. For example, channels CHA and CHB each have control logic corresponding to their respective channels. For example, each channel of channels CHA and CHB has the same number of memory arrays. Channels CHA and CHB can work in parallel, thereby significantly improving the memory bandwidth and data transfer rate.

[0107] For example, each channel in channel CHA and channel CHB includes five memory arrays: DRAM 0, DRAM 1, DRAM 2, DRAM 3, and DRAM 4. Each memory array (Bank Group) includes multiple memory banks. For example, each of the five memory arrays DRAM 0 to DRAM 4 includes multiple memory banks Bank 0 to Bank N, where N is a positive integer.

[0108] For example, taking each of the five memory arrays DRAM0-DRAM4 as an example, if an error is detected in the memory bank Bank0 of memory array DRAM1, that is, there is an error in memory array DRAM1, then the erroneous row in the memory bank Bank0 of memory array DRAM1 can be determined, for example, the erroneous row is Row N, where N is a positive integer.

[0109] For example, a read command for the erroneous row N can be sent first through the data backup logic. After the read command accesses the erroneous row N of channel CHA through the command interface, the target storage unit (also known as the target storage particle) of the erroneous row N will return data for backup.

[0110] For example, in bank interleaving, access requests can be distributed among multiple banks belonging to different memory arrays. When an access request is issued, the accessed data is distributed across banks in different memory arrays. For instance, the accessed data in a single request might be stored in Bank 0 of five memory arrays DRAM 0 through DRAM 4. Bank interleaving significantly improves memory parallelism and reduces latency caused by waiting for individual bank operations to complete, thereby reducing data access latency.

[0111] For example, in a memory employing memory interleaving technology, upon receiving a read instruction for an erroneous Row N in Bank 0 of DRAM 1, since the access data is written in parallel simultaneously to Bank 0 of all five DRAM arrays (DRAM 0-DRAM 4), when reading the erroneous Row N in Bank 0 of DRAM 1, the corresponding Row N in Bank 0 of the other DRAM arrays will also be read. That is, the data of the corresponding Row N in Bank 0 of all five DRAM arrays (DRAM 0-DRAM 4) will be read in parallel as the returned read data.

[0112] In some embodiments of this disclosure, step S40 includes step S400.

[0113] Step S400: After processing the first data using an error correction algorithm, perform a backup.

[0114] For example, after reading the data, error checking and correction (ECC) can be performed on the data to obtain the corrected data, thus ensuring that the data to be backed up is correct.

[0115] In some embodiments of this disclosure, step S400 further includes step S4001.

[0116] Step S4001: Back up the first data corresponding to the error location to the redundant space of the data cache space.

[0117] For example, the data (also called the first data) of the target memory chip in the erroneous row Row N of the memory bank Bank0 of the DRAM 1 memory array can be extracted from the error-corrected read data and stored in the data buffer.

[0118] For example, the first data can be stored in the space occupied by the released existing access requests, so that there is no need to allocate a backup storage space for the first data, and no need to introduce additional storage devices in the memory.

[0119] In some embodiments of this disclosure, during the backup process, if the number of bits in the read data is too large—that is, if the number of columns in the DRAM 0-DRAM 4 memory chips in channel CHA exceeds the number of columns the memory controller can process at once—the memory controller cannot access so many bits simultaneously in a single operation. Therefore, it can be handled using partial column access, where a portion of the columns are read at a time. For example, if the read data is 64 bits, in the above embodiments, a read command can be sent to read columns 0-15 first, then columns 16-31, then columns 32-47, and finally columns 48-63. Thus, through multiple cyclic reads, all columns (i.e., all bits) of the read data are covered, thereby completing the backup of the first data.

[0120] It should be noted that the above description is based on a DDR5 DIMM memory structure, but does not represent a limitation on the memory structure type disclosed herein; the above description is based on a memory including two channels, but does not represent a limitation on the number of channels in the memory; the above description is based on one channel including 5 memory arrays, but does not represent a limitation on the number of memory arrays in the memory.

[0121] The above embodiments of this disclosure are illustrated using an example of a faulty row in a storage cell of a storage array. If there are multiple faulty locations in multiple storage cells in the storage array, or if a faulty location includes multiple faulty rows, the backup process for any faulty row is the same as the example above.

[0122] It should be noted that, in the above example, the data backup process when any storage array in channel CHB has an error is the same as the data backup process in channel CHA, and will not be repeated here.

[0123] Step S41: After the target storage unit is replaced with the replacement storage unit, the first data is restored to the replacement storage unit.

[0124] For example, after a target storage unit is replaced with a replacement storage unit, it is necessary to restore the data (e.g., the first data) of the previously replaced target storage unit (also known as the target storage particle) to the replacement storage unit.

[0125] In some embodiments of this disclosure, step S41 includes step S410.

[0126] Step S410: Reassemble the first data corresponding to the error location and the second data written in parallel with the first data, and perform a write operation on the reassembled data to restore the first data to the replacement storage unit.

[0127] Figure 3 illustrates a data recovery schematic diagram provided by at least one embodiment of the present disclosure.

[0128] As shown in Figure 3, in this embodiment, the memory adopts the structure of a dual in-line memory module with DDR5 memory technology. In the DDR5 memory shown in the figure, each DIMM has two channels, namely channels CHA and CHB as shown in the figure. For example, channels CHA and CHB have control logic corresponding to their respective channels. For example, each channel of channels CHA and CHB has the same number of memory arrays. Channels CHA and CHB can work in parallel, thereby significantly improving the bandwidth of the memory and also improving the data transfer rate.

[0129] For example, each channel in channel CHA and channel CHB includes five memory arrays: DRAM 0, DRAM 1, DRAM 2, DRAM 3, and DRAM 4. Each memory array (Bank Group) includes multiple memory banks. For example, each of the five memory arrays DRAM 0 to DRAM 4 includes multiple memory banks Bank 0 to Bank N, where N is a positive integer.

[0130] Taking the CHA channel using memory interleaving technology as an example, the control logic corresponding to the CHA channel includes data reconstruction and recovery of complete write data logic, data recovery control logic, and data buffer.

[0131] First, after the target memory cell (also known as the target memory particle) is replaced with the replacement memory cell, a read command is sent to the replaced channel CHA.

[0132] Subsequently, in response to the read command, channel CHA reads the data from the replacement memory cell in memory array DRAM 1, as well as the data (also called second data) from other memory arrays read in parallel with memory array DRAM 1. For example, the data read in parallel includes: the data in row N of memory bank 0 of memory array DRAM 0, the data from the replacement memory cell in memory bank 0 of memory array DRAM 1, the data in row N of memory bank 0 of memory array DRAM 2, the data in row N of memory bank 0 of memory array DRAM 3, and the data in row N of memory bank 0 of memory array DRAM 4.

[0133] Subsequently, the data of the erroneous row Row N (i.e., the target memory cell) in Bank 0 of DRAM 1 is extracted from the data buffer (hereinafter referred to as "first data").

[0134] Next, the first and second data need to be reassembled to recover the complete written data. It should be noted that the second data is written in parallel with the first data.

[0135] For example, the data from the replacement memory cell in the read data can be replaced with the first data through data reconstruction, and the first data and the second data can be reconstructed to restore the complete write data. For example, during the data reconstruction process, the data from the replacement memory cell in Bank 0 of the memory bank DRAM 1 in the read data can be replaced with the first data to restore the complete write data.

[0136] For example, the recovered complete write data consists of: the data in row N of memory bank Bank 0 of memory array DRAM 0, the first data, the data in row N of memory bank Bank 0 of memory array DRAM 2, the data in row N of memory bank Bank 0 of memory array DRAM 3, and the data in row N of memory bank Bank 0 of memory array DRAM 4. Here, the second data includes all other data in the write data except for the first data.

[0137] After the data recovery control logic sends a write command to channel CHA, the control writes the reconstructed data to the memory arrays DRAM 0-DRAM 4 of channel CHA. For example, the first data is written to the replacement memory cell in Bank 0 of memory array DRAM 1, and the second data is written to memory arrays DRAM 0, DRAM 2, DRAM 3 and DRAM 4 respectively.

[0138] By recombining the read data from multiple storage arrays with the first data as described above, it is possible to ensure that for a memory employing memory interleaving technology, the normal data in other storage arrays will not be overwritten or destroyed due to the recovery of an error in one of the multiple storage arrays.

[0139] In some embodiments of this disclosure, step S41 includes step S411.

[0140] Step S411: By operating the corresponding data mask, the operation of writing the second data in parallel with the first data corresponding to the error position is blocked, and the first data is restored to the replacement storage unit.

[0141] For example, if the memory supports a data mask function, then when restoring data (also called the first data) from the target memory cell to the replacement memory cell, the data mask can be used to mask the operation of writing the second data, which needs to be written in parallel with the first data corresponding to the error location. This way, data reconstruction can be performed directly to restore the first data to the replacement memory cell without needing to reassemble the data. The data mask method eliminates the need for the aforementioned Read-Modify-Write (RMW) process; that is, it eliminates the need to first send a read request to read the data to be written in parallel (i.e., read), then perform data reconstruction (i.e., correct), and finally write the reconstructed data (i.e., write). This further optimizes the recovery process after encapsulation and repair, thus shortening the time consumed by post-encapsulation repair.

[0142] For example, in the channel CHA shown in Figure 3, the five memory arrays DRAM 0-DRAM 4 each have corresponding data mask bits. For instance, if the target memory cell at the error location in Bank 0 of memory array DRAM 1 has been replaced with a replacement memory cell, then even though the memory uses memory interleaving technology and the five memory arrays need to be read and written in parallel, the data mask bits can be set to mask memory arrays DRAM 0, DRAM 2, DRAM 3, and DRAM 4, allowing memory array DRAM 1 to be operated. In this way, after reading the first data in the data buffer, the operation of writing the second data, which needs to be written in parallel with the first data corresponding to the error location, can be masked, and the first data can be directly restored to the replacement memory cell.

[0143] It should be noted that in the case of excessively large first data, read data, and write data in the recovery process of the storage array, that is, when the number of columns of the storage chips in DRAM 0-DRAM 4 or DRAM 1 in the channel CHA exceeds the number of columns that the storage controller can process at one time, the Partial Column Access method can also be used to process the first data, read data, or write data. Through multiple loops, until all columns (i.e. all bits) of the first data, read data, and write data are covered, the recovery of the first data is completed.

[0144] It should be noted that in the above examples, the data recovery process for any storage array in channel CHB is the same as that in channel CHA, and will not be repeated here.

[0145] In some embodiments of this disclosure, the memory operation method further includes step S33.

[0146] Step S33: In response to the completion of the post-encapsulation repair process, send a compensation refresh command.

[0147] By sending a compensated refresh command, the memory can compensate for refresh operations that could not be performed during the PPR process after the post-packaging repair (PPR) process is completed.

[0148] For example, a compensating refresh command can be sent after the first data is restored to the replacement storage unit.

[0149] By sending a compensation refresh command, the integrity of the data in the memory is not affected by charge leakage caused by the lack of refresh during the PPR process, and the stability of the data in the memory is also maintained.

[0150] In some embodiments of this disclosure, the memory operation method further includes step S34.

[0151] Step S34: In response to a reset or initialization operation on the memory, a hard repair of the memory array is triggered to fix the repair result of replacing the target memory cell at the fault location in the memory array with the replacement memory cell in the memory array used for the post-packaging repair process.

[0152] For example, the above-mentioned post-packaging repair process can be a short-duration post-packaging soft repair (sPPR). To fix the repair results of the above-mentioned post-packaging repair process, the repair results can be recorded in advance. When the memory performs a reset or initialization operation, a hard repair of the memory array is triggered based on the recorded repair results (i.e., the replacement relationship of replacing the target memory cell at the error location with the replacement memory cell). For example, this hard repair can be a post-packaging hard repair (hPPR), which physically changes the memory chips in the memory array to fix the repair results in the memory array.

[0153] Figure 4 shows an exemplary flowchart of a memory operation method provided in at least one embodiment of the present disclosure.

[0154] As shown in Figure 4, the memory operation method can be as follows: issue an access request to the memory to access the memory, detect errors in the memory array during the memory's working state, and determine the location of the error in the memory array.

[0155] Then, the post-packaging soft repair (sPPR) process is initiated, notifying the processor to stop generating new access requests.

[0156] Then, the storage controller is notified to clear the existing access requests in the memory, release the data cache occupied by the existing access requests, and send a precharge command to wait for the storage array to enter an idle state.

[0157] After entering the idle state, if waiting is required, the pending refresh commands can be cleared, and a self-refresh command can be sent to make the storage array enter the first self-refresh state. In the first self-refresh state, the control of the storage array can be switched to the repair module. If waiting is not required, the control of the storage array can be switched to the repair module directly in the idle state, thereby entering the post-packaging soft repair process.

[0158] If you switch control of the storage array to the repair module in the first self-refresh state, you need to exit the first self-refresh state before backing up the first data. If you switch control of the storage array to the repair module directly in the idle state, you can start backing up the first data directly.

[0159] Then, a sequence of instructions to initiate the sPPR process is sent, and the sPPR process is executed on the target memory cell at the fault location in the memory array, replacing the target memory cell with a replacement memory cell.

[0160] Afterwards, the first data is restored to the replacement storage unit, and a compensation refresh command is sent after the recovery process is completed.

[0161] If waiting is required, a self-refresh command can be sent to put the storage array into a second self-refresh state. In the second self-refresh state, control of the storage array can be switched to the storage controller. If waiting is not required, control of the storage array can be switched directly to the storage controller.

[0162] If the storage array control is switched to the storage controller in the second self-refresh state, the storage controller can send a self-refresh exit command to make the storage array exit the second self-refresh state and send a compensation refresh command.

[0163] By correcting the errors in the memory array as described above, normal access to the memory is restored.

[0164] The technical effects of the embodiments disclosed above are the same as those of the memory operation method described above, and therefore will not be repeated here.

[0165] Figure 5 shows a block diagram of a memory provided in at least one embodiment of the present disclosure.

[0166] As shown in Figure 5, at least one embodiment of this disclosure also provides a memory 600, which includes a memory array 610, an operation control module 620, a memory controller 630, and a repair module 640.

[0167] The storage controller 630 is configured to read from and write to the storage array 610 in operation.

[0168] The repair module 640 is configured to perform repair operations on the storage array 610.

[0169] The operation control module 620 is configured to: in response to detecting an error in the storage array 610 of the memory 600 during the working state of the memory 600, determine the location of the error in the storage array 610, and control the memory 600 to start the repair module 640 to perform the post-encapsulation repair process after the memory 600 enters the idle state.

[0170] The repair module 640 is further configured to replace the target storage cell at the error location with a replacement storage cell in the storage array 610 for the post-packaging repair process, based on the error location; after the post-packaging repair process, the memory 600 is switched back to the operating state, whereby the storage controller 630 uses the replacement storage cell to replace the target storage cell for operation.

[0171] For example, the memory 600 can be memory, and the corresponding storage controller 630 can be a memory controller.

[0172] For example, the storage controller 630 is also configured to manage the refresh operations of the storage array 610.

[0173] For example, the repair module 640 is configured to control the sending of a series of PPR instruction sequences to the storage array 610 during the post-packaging repair process to initiate the PPR process.

[0174] In some embodiments of this disclosure, the operation control device includes a selector 6201 and a permission switching module 6202.

[0175] Selector 6201 is, for example, a multiple-to-one selector. The input of selector 6201 is connected to the storage controller 630 and the repair control module, and the output of selector 6201 is connected to the storage array 610.

[0176] The permission switching module 6202 is configured to provide control signals to the selector 6201 so that the selector 6201 switches the storage array 610 from the working mode to the repair mode, or from the repair mode back to the working mode.

[0177] In some embodiments of this disclosure, the memory 600 further includes a data cache 650. The data cache 650 is configured to provide cache space required by the storage array 610 in either an operating mode or a repair mode. For example, the data cache 650 is configured to temporarily store read / write data in the operating state of the memory. For example, the data cache 650 is configured to provide cache space for a first backup of data corresponding to the error location in the repair mode of the memory.

[0178] For example, in the memory's operating mode, the access control module 6202 transfers control of the storage array 610 to the storage controller 630 via the selector 6201. At this time, the storage controller 630 can normally respond to read / write requests issued by the processor, and the data cache 650 can temporarily store read / write data. When the memory needs to perform a repair operation on the storage array 610, a control switching process is initiated. When the memory 600 clears existing access requests and allows the storage array 610 to enter the first self-refresh state, the access control module 6202 transfers control of the storage array 610 to the repair module 640 via the selector 6201, and then begins the post-packaging repair process. At this time, the data cache 650 is configured to temporarily store erroneous row data (first data). After the post-packaging repair process is completed, the access control module 6202 then transfers control of the storage array 610 back to the storage controller 630 via the selector 6201, and restores the storage array 610 to its normal state.

[0179] In some embodiments of this disclosure, the memory 600 also includes a repair status register 660. The repair status register 660 is configured to record whether repair resources are available at the location of the error.

[0180] In some embodiments of this disclosure, the operation control module 620 may include a repair control register (not shown in the figures).

[0181] In some embodiments of this disclosure, the storage controller 630 is also configured to stop receiving new access requests to the memory 600 and clear existing access requests in the memory 600, so that the memory 600 enters an idle state.

[0182] In some embodiments of this disclosure, the storage controller 630 is also configured to release space in the data cache 650 occupied by existing access requests.

[0183] In some embodiments of this disclosure, the storage controller 630 is further configured to clear the pending refresh commands in the memory 600, causing the storage array 610 to enter a first self-refresh state; the operation control module 620 is further configured to switch the storage array 610 from the working mode to the repair mode in the first self-refresh state.

[0184] In some embodiments of this disclosure, the repair module 640 is further configured to, in response to the end of the first self-refresh state, back up the first data corresponding to the error location, and restore the first data to the replacement storage unit after the target storage unit is replaced by a replacement storage unit.

[0185] In some embodiments of this disclosure, the repair module 640 is also configured to back up the first data after processing it using an error correction algorithm.

[0186] In some embodiments of this disclosure, the repair module 640 is also configured to back up the first data corresponding to the error location to the redundant space of the data cache 650.

[0187] In some embodiments of this disclosure, the repair module 640 is further configured to reassemble the first data corresponding to the error location and the second data written in parallel with the first data, and to perform a write operation on the reassembled data to restore the first data to the replacement storage unit.

[0188] In some embodiments of this disclosure, the storage array 610 is configured to support data masking, and the repair module 640 is further configured to restore the first data to the replacement storage unit by operating the corresponding data mask to block the operation of writing the second data that needs to be written in parallel with the first data corresponding to the error location.

[0189] In some embodiments of this disclosure, the storage controller 630 is also configured to send a compensated refresh command in response to the completion of the post-packaging repair process.

[0190] In some embodiments of this disclosure, the operation control module 620 is also configured to switch the storage array 610 from repair mode to operating mode in a second self-refresh state in response to the completion of the repair mode.

[0191] In some embodiments of this disclosure, the storage controller 630 is also configured to read the repair status register 660 corresponding to the error location to determine whether there are available repair resources.

[0192] In some embodiments of this disclosure, the repair module 640 is also configured to trigger a hard repair of the storage array 610 in response to a reset or initialization operation on the memory 600, so as to fix the repair result of replacing the target storage cell at the fault location in the storage array 610 of the memory 600 with a replacement storage cell in the storage array used for the post-packaging repair process.

[0193] The operation control module 620, repair module 640, and permission switching module 6202 in the embodiments of this disclosure can be implemented by hardware, software, firmware, or any combination thereof, for example, by digital circuitry. The technical effects of the memory in the above embodiments of this disclosure are the same as the technical effects of the above memory operation method, and therefore will not be repeated.

[0194] At least one embodiment of this disclosure also provides an electronic device, wherein the electronic device includes the memory described in the at least one embodiment above.

[0195] Figure 6 is a schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure.

[0196] The electronic devices in this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. The electronic device 1000 shown in Figure 6 is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of this disclosure.

[0197] Referring to FIG6, in some examples, electronic device 1000 includes a processing device (e.g., central memory, graphics memory, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1008 into random access memory (RAM) 1003. The RAM 1003 also stores various programs and data required for the operation of the computer system; for example, the RAM 1003 can be the memory described in at least one embodiment of this disclosure above, wherein the processing device 1001, ROM 1002, and RAM 1003 are connected via an interconnect network 1004. An input / output (I / O) interface 1005 is also connected to the interconnect network 1004.

[0198] For example, the following components can be connected to I / O interface 1005: input devices 1006 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1007 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1008 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009, such as network interface cards like LAN cards and modems, etc. Communication device 1009 allows electronic device 1000 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1010 is also connected to I / O interface 1005 as needed. Removable media 1011, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage device 1008 as needed. Although FIG6 shows electronic device 1000 including various devices, it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included alternatively.

[0199] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1009 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0200] For example, the electronic device 1000 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or it can be any combination of memory operating device and hardware. The embodiments disclosed herein do not limit this.

[0201] At least one embodiment of this disclosure also provides a non-transitory storage medium for non-transitory storage of computer-executable instructions. For example, when the computer-executable instructions are executed by memory, the memory operation method provided in at least one embodiment of this disclosure is implemented.

[0202] Figure 7 is a schematic diagram of a non-transitory storage medium provided in some embodiments of the present disclosure. As shown in Figure 7, the non-transitory storage medium 900 can non-transitory store computer-executable instructions 910, which, when executed by a computer, implement the memory operation method provided in any embodiment of the present disclosure.

[0203] The following points need to be clarified regarding this disclosure:

[0204] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0205] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0206] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory operation method, comprising: In response to detecting an error in the memory's storage array during the memory's operating state, the location of the error in the storage array is determined; After the memory enters an idle state, the memory is controlled to start the post-packaging repair process. According to the error location, the target storage cell at the error location is replaced with a replacement storage cell in the storage array used for the post-packaging repair process. After the post-packaging repair process, the memory is switched back to the working state, and the replacement memory unit is used to replace the target memory unit for operation.

2. The memory operation method of claim 1, wherein, After the memory enters an idle state, the process of controlling the memory to start the post-packaging repair procedure includes: After the memory enters an idle state, the memory array is switched from working mode to repair mode, so that the memory starts the post-packaging repair process.

3. The memory operation method as described in claim 2, further comprising: Stop receiving new access requests to the memory and clear existing access requests in the memory, so that the memory enters the idle state.

4. The memory operation method of claim 3, wherein, Before the memory enters the idle state, the memory operation method further includes: Release the space occupied by the data cache for the existing access request.

5. The memory operation method as described in claim 4, wherein, After the memory enters the idle state, the memory operation method further includes: Clear the pending refresh commands in the memory, so that the memory array enters the first self-refresh state; In the first self-refresh state, control of the storage array is switched from the working mode to the repair mode.

6. The memory operation method of claim 5, wherein, The post-packaging repair process includes: In response to the end of the first self-refresh state, the first data corresponding to the error location is backed up, and after the target storage unit is replaced by the replacement storage unit, the first data is restored to the replacement storage unit.

7. The memory operation method of claim 6, wherein, The backup of the first data corresponding to the error location includes: The first data is processed using an error correction algorithm and then backed up.

8. The memory operation method of claim 6 or 7, wherein, The backup of the first data corresponding to the error location also includes: The first data corresponding to the error location is backed up to the redundant space of the data cache space.

9. The memory operation method of any of claims 6-8, wherein, Restoring the first data to the replacement storage unit includes: The first data corresponding to the error location and the second data written in parallel with the first data are reassembled, and the reassembled data is written to restore the first data to the replacement storage unit.

10. The memory operation method of any one of claims 6-8, wherein, The storage array is configured to support data masking. Restoring the first data to the replacement storage unit includes: By manipulating the corresponding data mask to block the operation of writing the second data in parallel with the first data corresponding to the error location, the first data is restored to the replacement storage unit.

11. The memory operation method according to any one of claims 5-10, further comprising: In response to the completion of the post-encapsulation repair process, a compensation refresh command is sent.

12. The memory operation method according to any one of claims 5-11, further comprising: In response to the completion of the repair mode, control of the storage array is switched from the repair mode to the working mode in the second self-refresh state.

13. The memory operation method of any one of claims 1-12, wherein, Before initiating the post-packaging repair process, the method further includes: Read the repair status register corresponding to the error location to determine if there are available repair resources.

14. The memory operation method according to any one of claims 1-13, further comprising: In response to a reset or initialization operation of the memory, a hard repair of the memory array is triggered to fix the repair result of replacing the target memory cell at the fault location in the memory array with a replacement memory cell in the memory array used for the post-packaging repair process.

15. A memory, comprising a memory array, an operation control module, a memory controller, and a repair module; The storage controller is configured to read and write to the storage array during operation. The repair module is configured to perform repair operations on the storage array; The operation control module is configured as follows: In response to detecting an error in the memory's storage array during the memory's operating state, the location of the error in the storage array is determined. After the memory enters an idle state, the memory is controlled to start the repair module to perform the post-packaging repair process, wherein... The repair module is further configured to replace the target storage unit at the error location with a replacement storage unit in the storage array used for the post-packaging repair process, based on the error location. After the post-packaging repair process, the memory is switched back to the operating state, whereby the memory controller uses the replacement memory unit to replace the target memory unit for operation.

16. The memory of claim 15, wherein, The operation control device includes: The selector has its input connected to the storage controller and the repair control module, and its output connected to the storage array. The permission switching module is configured to provide control signals to the selector so that the selector switches control of the storage array from the operating mode to the repair mode, or switches back from the repair mode to the operating mode.

17. The memory of claim 15 or 16, further comprising: A data cache is configured to provide the cache space required by the storage array in the operating mode or repair mode.

18. The memory according to any one of claims 15-17, further comprising: The repair status register is configured to record whether repair resources are available at the location of the error.

19. An electronic device comprising the memory according to any one of claims 15-18.

20. A non-transitory storage medium non-transitorily storing computer- executable instructions, wherein, When the computer-executable instructions are executed by at least one processor, the memory operation method according to any one of claims 1-14 is implemented.

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