Display panel and display apparatus

Abstract

Embodiments of the present invention provide a display panel and a display apparatus. The display panel comprises a shift register, and the shift register comprises a plurality of shift register units. Each shift register unit comprises an input module, an output module, and a voltage stabilizing module. The input module is configured to separately write voltages to a first node and a second node on the basis of at least an input signal and a first clock signal. The output module is separately connected to the first node and the second node. The output module is configured to output a high-level signal on the basis of the voltage of the first node, and is further configured to output a low-level signal on the basis of the voltage of the second node. The voltage stabilizing module is at least connected to the first node. During at least part of a period when the first node is at a high potential, the voltage stabilizing module is configured to pull up the potential of the first node on the basis of the voltage of the first node and a first voltage signal. The present invention can ensure that each shift register unit stably outputs a high-level enable signal, thereby improving the reliability of product performance.

Description

Display panel and display device

[0001] This invention claims priority to Chinese Patent Application No. 202411958860.6, filed with the State Intellectual Property Office of China on December 27, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0003] Indium gallium zinc oxide (IGZO) is a material used in the channel layer of next-generation thin-film transistor (TFT) technology, and is a type of metal oxide panel technology. IGZO transistors have the advantages of high mobility and low leakage current, which can better improve display ghosting and reduce costs. Currently, pixel circuits made entirely of metal oxide transistors are becoming a technological trend, therefore, providing a matching and suitable shift drive circuit is a pressing technical problem to be solved. Summary of the Invention

[0004] To address the problems existing in the prior art, the present invention provides a display panel and a display device, which provides a shift drive circuit capable of stably outputting scanning signals, thereby improving product yield.

[0005] In a first aspect, embodiments of the present invention provide a display panel, the display panel including a shift register, the shift register including a plurality of shift register units; the shift register unit includes an input module, an output module and a voltage regulator module;

[0006] The input module is configured to write voltages to the first node and the second node respectively based on at least the input signal and the first clock signal; the output module is connected to the first node and the second node respectively; the output module is configured to output a high-level signal based on the voltage of the first node, and is also configured to output a low-level signal based on the voltage of the second node.

[0007] The voltage regulator module is connected to at least the first node; during at least a portion of the time when the first node is at a high potential, the voltage regulator module is configured to pull the potential of the first node high based on the voltage of the first node and a first voltage signal.

[0008] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of the present invention.

[0009] The display panel and display device provided in this embodiment of the invention have the following beneficial effects: The display panel is provided with multiple cascaded shift register units, each of which contains an n-type transistor. A voltage regulator module is added to each shift register unit. This voltage regulator module can pull up the potential of the first node during at least a portion of the time when the first node is at a high potential, thus maintaining the first node stably at a high potential. This ensures that the shift register unit stably outputs a high-level signal. Therefore, the shift register unit can stably provide a high-level enable signal to the n-type transistors in the pixel circuit, ensuring stable operation of the pixel circuit and improving product performance reliability. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 is a schematic diagram of a pixel circuit in the related technology;

[0012] Figure 2 is a schematic diagram of a shift register unit in the related technology;

[0013] Figure 3 is a timing diagram of the shift register unit in the embodiment of Figure 2;

[0014] Figure 4 is a simplified schematic diagram of a display panel provided in an embodiment of the present invention;

[0015] Figure 5 is a schematic diagram of a shift register unit provided in an embodiment of the present invention;

[0016] Figure 6 is a timing diagram provided by an embodiment of the present invention;

[0017] Figure 7 is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0018] Figure 8 is another timing diagram provided by an embodiment of the present invention;

[0019] Figure 9 is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0020] Figure 10 is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0021] Figure 11 is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0022] Figure 12 is another timing diagram provided by an embodiment of the present invention;

[0023] Figure 13 is another timing diagram provided by an embodiment of the present invention;

[0024] Figure 14 is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0025] Figure 15 is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0026] Figure 16 is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0027] Figure 17 is another timing diagram provided by an embodiment of the present invention;

[0028] Figure 18 is a schematic diagram of a cascaded shift register unit provided in an embodiment of the present invention;

[0029] Figure 19 is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0030] Figure 20 is a schematic diagram of another cascaded shift register unit provided in an embodiment of the present invention;

[0031] Figure 21 is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0032] Figure 22 is another timing diagram provided by an embodiment of the present invention;

[0033] Figure 23 is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0034] Figure 24 is another timing diagram provided by an embodiment of the present invention;

[0035] Figure 25 is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0036] Figure 26 is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0037] Figure 27 is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] Various modifications and variations can be made to this invention without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this invention can be combined with each other without contradiction.

[0040] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0041] Figure 1 is a schematic diagram of a pixel circuit in the related art. As shown in Figure 1, the pixel circuit includes a driving transistor DT, a data writing transistor T1, a gate reset transistor T2, a light emission control transistor T3, an electrode reset transistor T4, and a storage capacitor C1. The driving transistor DT has a dual-gate structure, including a top gate and a bottom gate. Its top gate is connected to one plate of the data writing transistor T1, the gate reset transistor T2, and the storage capacitor C1, and its bottom gate is connected to the other plate of the storage capacitor C1. The operation of the pixel circuit also requires a first power supply signal ELVDD, a reset signal Vref, a constant voltage signal Vini, a data signal Data, a light emission control signal EM1, a scan signal G1, a scan signal G2, and a scan signal G3. The pixel circuit is connected to the first electrode of the light-emitting device OLED (Organic Light-Emitting Diode), and the second electrode of the light-emitting device OLED is connected to the second power supply signal ELVSS. "Coled" represents the parasitic capacitance of the light-emitting device OLED itself. The active layer of each transistor in the pixel circuit includes metal oxide, and the transistors are n-type transistors. The control signals required by the pixel circuit, such as the light emission control signal EM1, scan signal G1, scan signal G2, and scan signal G3, have a high enable level. Therefore, a shift register unit that can provide a high enable level is needed.

[0042] Figure 2 is a schematic diagram of a shift register unit in the related art. As shown in Figure 2, the shift register unit includes an input module 01 and an output module 02. The output module 02 includes a first output transistor T1' and a second output transistor T2', a second capacitor C2, and a third capacitor C3. The output terminal of the input module 01 is connected to nodes N1 and NB1. The control terminal of the first output transistor T1' is connected to node N2. Node N2 is connected to node N1 through a switch transistor T3'. The control terminal of the second output transistor T2' is connected to node NB1. The first terminal of the first output transistor T1' receives a high-level signal VGH, and the second terminal is connected to the output terminal OUT of the shift register unit. The first terminal of the second output transistor T2' receives a low-level signal VGL, and the second terminal is connected to the output terminal OUT of the shift register unit. The control terminal of the switch transistor T3' receives a high-level signal VGH. The first output transistor T1', the second output transistor T2', and the switch transistor T3' are all n-type transistors. The input module 01 writes signals to nodes N1 and NB1 respectively under the control of the input signal STV and the clock signal CK'.

[0043] Figure 3 is a timing diagram of the shift register unit in the embodiment of Figure 2. Figure 3 illustrates the potential changes at each node. As shown in Figure 3, when node N2 is at a high level, the first output transistor T1' is turned on, providing a high-level signal VGH to the output terminal OUT, and the output terminal OUT outputs a high-level signal; when node NB1 is at a high level, the second output transistor T2' is turned on, providing a low-level signal VGL to the output terminal OUT, and the output terminal OUT outputs a low-level signal. Due to the small threshold voltage range of the n-type transistor, when a high level is written to node N2, node N2 will leak current to node N1 through the switching transistor T3', causing the potential of node N2 to decrease (as indicated by the arrow in Figure 3). The potential change of node N2 affects the on-state of the first output transistor T1', thereby affecting the output capability of the high-level signal. When the high-level signal is used as an enable signal, it affects the operation of the pixel circuit, leading to display abnormalities.

[0044] To address the problems existing in related technologies, embodiments of the present invention provide a display panel in which a voltage regulator module is incorporated in the shift register unit. This voltage regulator module stabilizes the potential at the control terminal of the output module, enabling the output module to stably output a high-level enable signal. In application, the shift register unit outputs a stable high-level enable signal to drive the n-type transistors in the pixel circuit.

[0045] Figure 4 is a simplified schematic diagram of a display panel provided by an embodiment of the present invention. As shown in Figure 4, the display panel includes multiple pixel circuits 10 arranged in an array, forming a pixel circuit row 10H in the horizontal direction. Multiple cascaded shift register units 20 form a shift register 2, and the output terminals of the shift register units 20 are connected to each pixel circuit 10 in the pixel circuit row 10H via scan lines 30. Each pixel circuit 10 includes at least one n-type transistor, and the output terminal of the shift register unit 20 outputs a high-level enable signal to drive the n-type transistor in the pixel circuit 10. Figure 4 illustrates a shift register unit 20 disposed on one side of the pixel circuit row 10H; in other embodiments, shift register units 20 are disposed on both sides of the pixel circuit row 10H.

[0046] Figure 5 is a schematic diagram of a shift register unit provided in an embodiment of the present invention. As shown in Figure 5, the shift register unit includes an input module 21, an output module 22, and a voltage regulator module 23. The input module 21 is configured to write voltages to the first node Q1 and the second node Q2 based on at least the input signal STV and the first clock signal CK1, respectively. The output module 22 is connected to the first node Q1 and the second node Q2, respectively. The output module 22 is configured to output a high-level signal based on the voltage of the first node Q1 and also configured to output a low-level signal based on the voltage of the second node Q2. Optionally, the output module 22 includes a third output transistor M3 and a fourth output transistor M4. The third output transistor M3 provides a high-level signal VGH to the output terminal OUT under the high-level control of the first node Q1, and the fourth output transistor M4 provides a low-level signal VGL to the output terminal OUT under the high-level control of the second node Q2. The high-level signal output by the output terminal OUT serves as the enable signal for the n-type transistor in the driving pixel circuit.

[0047] In this configuration, the voltage regulator module 23 is connected to at least the first node Q1; during at least a portion of the time when the first node Q1 is at a high potential, the voltage regulator module 23 is configured to pull the potential of the first node Q1 high based on the voltage of the first node Q1 and a first voltage signal VG1. The first voltage signal VG1 is a high-level signal during at least a portion of the time.

[0048] This invention provides a display panel in which a voltage regulator module 23 is added to the shift register unit 20. The voltage regulator module 23 can pull up the potential of the first node Q1 at least for a part of the time when the first node Q1 is at a high potential, so that the first node Q1 is stably maintained at a high potential. This ensures that the shift register unit 20 can stably output a high-level signal, and the shift register unit 20 can stably provide a high-level enable signal to the n-type transistor in the pixel circuit 10, ensuring the stable operation of the pixel circuit 10 and improving the reliability of product performance.

[0049] In some embodiments, at least one transistor connected to the first node Q1 in the output module 22 is an n-type transistor. The n-type transistor is turned on under high-level control and turned off under low-level control. In this embodiment, the voltage regulator module 23 is configured to maintain a stable high potential during the period when the first node Q1 is at a high potential, ensuring that the n-type transistors in the output module 22 remain stably turned on, thereby enabling the shift register unit 20 to stably output a high-level signal. Optionally, all transistors in the output module 22 are n-type transistors.

[0050] In some embodiments, all transistors in the shift register unit 20 are n-type transistors. This arrangement allows the active layers of each transistor to be made of the same material, simplifying the film layer fabrication process of the display panel and reducing manufacturing costs. Furthermore, when at least some transistors in the pixel circuit of the display panel are made of n-type transistors, the shift register unit 20 can also be matched with the pixel circuit fabrication process to simplify the display panel manufacturing process.

[0051] In this embodiment of the invention, the active layer of the n-type transistor in the shift register unit 20 includes indium gallium zinc oxide. Indium gallium zinc oxide transistors have the advantages of high mobility and low leakage current, which can improve the circuit performance reliability of the shift register unit 20.

[0052] In some embodiments, FIG6 is a timing diagram provided by an embodiment of the present invention, which can be used to drive the shift register unit 20 provided in FIG5. As shown in FIG6, the operation of the shift register unit 20 includes a first time period t1 and a second time period t2; at least in the first time period t1 and the second time period t2, the first node Q1 is at a high potential. In the first time period t1, the voltage of the first node Q1 is V1; in the second time period t2, the voltage of the first node Q1 is V2, V2>V1. As can be seen from the timing diagram in FIG6, the potential of the first node Q1 in the second time period t2 is higher than its potential in the first time period t1. In this embodiment, the voltage regulator module 23 pulls the potential of the first node Q1 even higher in the second time period t2, so that the first node Q1 can be stably maintained at a high potential, thereby ensuring that the shift register unit 20 stably outputs a high-level signal. Then, the shift register unit 20 can provide a stable high-level enable signal to the n-type transistor in the pixel circuit 10, ensuring the stable operation of the pixel circuit 10 and improving the reliability of product performance.

[0053] In some implementations, the shift register unit 20 operates through m first time periods t1 and m second time periods t2, where m is an integer and m ≥ 1. In terms of time sequence, the first time periods t1 and the second time periods t2 alternate, with the first first time period t1 preceding the first second time period t2. Figure 6 illustrates an embodiment where m = 2. It can be understood that the number of m is related to the duration for which the first node Q1 maintains a high level; the larger m is, the longer the first node Q1 maintains a high level. The potential writing of the first node Q1 is controlled by the input module 21, meaning the duration for which the first node Q1 maintains a high level is related to the duration of the high level of the input signal STV. The longer the first node Q1 maintains a high level, the longer the shift register unit 20 outputs a high level. In this embodiment, the number of m is set according to the required duration of the high-level enable level in the application.

[0054] In some implementations, during the first time period t1, the input module 21 writes a high potential to the first node Q1 based on the high-level signal of the first clock signal CK1. Under the control of the first node Q1, the voltage regulator module 23 writes a low-level signal of the first voltage signal VG1 to the third node Q3 in the voltage regulator module 23. During the second time period t2, under the control of the first node Q1, the voltage regulator module 23 writes a high-level signal of the first voltage signal VG1 to the third node Q3, and pulls the potential of the first node Q1 high based on the potential change of the third node Q3. This implementation sets a third node Q3 in the voltage regulator module 23, writes a low level to the third node Q3 during the first time period t1, writes a high level to the third node Q3 during the second time period t2, and uses the potential change of the third node Q3 to pull the potential of the first node Q1 high. Even if there is leakage current from the first node Q1 to other nodes, the leakage current can be compensated to ensure that the first node Q1 has a relatively stable high potential, so that the output tube controlled by it can be stably turned on, thereby ensuring that the shift register unit 20 stably outputs a high-level signal. The shift register unit 20 can provide a stable high-level enable signal to the n-type transistor in the pixel circuit 10, ensuring the stable operation of the pixel circuit 10 and improving the reliability of product performance.

[0055] In some embodiments, Figure 7 is a schematic diagram of another shift register unit provided by an embodiment of the present invention. As shown in Figure 7, the voltage regulator module 23 includes a first transistor T1, a second transistor T2, and a first capacitor C1. The control terminal of the first transistor T1 is connected to the first node Q1, and the control terminal of the second transistor T2 is connected to the second node Q2. The first terminal of the first transistor T1 receives a first voltage signal VG1, and the second terminals of the first transistor T1 and the second transistor T2 are connected to the third node Q3. The first terminal of the second transistor T2 receives a second voltage signal VG2. One plate of the first capacitor C1 is connected to the first node Q1, and the other plate is connected to the third node Q3. In addition, the shift register unit 20 also includes a protection transistor M5. The control terminal of the protection transistor M5 receives a high-level signal VGH. The protection transistor M5 is connected between an output terminal of the input module 21 and the first node Q1, and the protection transistor M5 and the output terminal of the input module 21 are connected to the fifth node Q5.

[0056] Referring to the timing diagram in Figure 6, during the first time period t1, the voltage regulator module 23, under the control of the high potential of the first node Q1, writes the low-level signal of the first voltage signal VG1 to the third node Q3. Specifically, the high potential of the first node Q1 controls the first transistor T1 to turn on and write the low-level signal of the first voltage signal VG1 to the third node Q3. During this time period, the third node Q3 is at a low potential, so the plate of the first capacitor C1 connected to the first node Q1 is at a high potential, and the plate connected to the third node Q3 is at a low potential.

[0057] During the second time period t2, the voltage regulator module 23, under the control of the high potential of the first node Q1, writes the high-level signal of the first voltage signal VG1 into the third node Q3. Specifically, the high potential of the first node Q1 controls the first transistor T1 to turn on, writing the high-level signal of the first voltage signal VG1 into the third node Q3, making the third node Q3 high. The potential of the third node Q3 jumps from low to high, and due to the coupling effect of the first capacitor C1, the potential of the first node Q1 is pulled up.

[0058] In this embodiment, the voltage regulator module 23 operates under the control of the first node Q1's potential. Utilizing the coupling effect of the first capacitor C1, it pulls the potential of the first node Q1 high, ensuring that the potential of the first node Q1 is higher than its potential in the first time period t1 after the second time period t2 is raised. This compensates for the leakage current from the first node Q1 to the fifth node Q5 through the protection transistor M5, ensuring that the first node Q1 is stably maintained at a high potential. Consequently, the output transistor controlled by the first node Q1 can be stably turned on, guaranteeing a stable high-level enable signal output from the shift register unit 20.

[0059] In some implementations, as shown in FIG6, the operation of the shift register unit 20 further includes a reset period t30; during the reset period t30, the first node Q1 is at a low potential and the second node Q2 is at a high potential. During the reset period t30, the voltage regulator module 23, based on the control of the second node Q2, writes the low potential of the second voltage signal VG2 into the third node Q3. This enables the third node Q3 to be reset. Specifically, referring to FIG7, during the period when the second node Q2 is at a high level, the second node Q2 controls the second transistor T2 to turn on and write the second voltage signal VG2 into the third node Q3 to reset the third node Q3. Optionally, the second voltage signal VG2 is a low-level signal VGL.

[0060] Figure 7 also illustrates the structure of output module 22, which includes a third output transistor M3, a fourth output transistor M4, capacitors C01 and C02. The control terminal of the third output transistor M3 is connected to the first node Q1, receives a high-level signal VGH at its first terminal, and is connected to the output terminal OUT of output module 22 at its second terminal. The control terminal of the fourth output transistor M4 is connected to the second node Q2, receives a low-level signal VGL at its first terminal, and is connected to the output terminal OUT of output module 22 at its second terminal. When the first node Q1 is high, it controls the third output transistor M3 to turn on, and the shift register unit outputs a high-level signal. When the second node Q2 is high, it controls the fourth output transistor M4 to turn on, and the shift register unit outputs a low-level signal.

[0061] In some embodiments, the first voltage signal VG1 is the second clock signal CK2. The first clock signal CK1 and the second clock signal CK2 can be a pair of clock signals with the same period. During a first time period t1, the first clock signal CK1 is high and the second clock signal CK2 is low; during a second time period t2, the first clock signal CK1 is low and the second clock signal CK2 is high. The first clock signal CK1 and the second clock signal CK2 together drive the cascaded multiple shift register units 20. Setting the first voltage signal VG1 as the second clock signal CK2 in this embodiment simplifies the types of signals required to drive the shift register units 20 and also helps reduce the wiring of the display panel and narrow the bezel.

[0062] In some other embodiments, FIG. 8 is another timing diagram provided by an embodiment of the present invention, which can be used to drive the shift register unit 20 provided by the embodiment of the present invention. As shown in FIG. 8, the operation of the shift register unit 20 includes a first period t1 and a second period t2; at least in the first period t1 and the second period t2, the first node Q1 is at a high potential. In the first period t1, the voltage of the first node Q1 is V1; in the second period t2, the voltage of the first node Q1 is V2, and V2 > V1. In terms of time sequence, the first period t1 is earlier than the second period t2; the length of the first period t1 is t01, and the length of the second period t2 is t02, and t02 > t01. That is, the duration of the first period t1 is less than the duration of the second period t2, and the time when the potential of the first node Q1 is pulled up is longer when it is at a higher potential. The high potential of the first node Q1 controls the output module 22 to output a high-level enable signal, and the longer the time when the first node Q1 is at a higher potential, the better the stability of the high-level signal output by the shift register unit.

[0063] In some embodiments, in the first period t1, the input module 21 writes a high potential to the first node Q1 based on the high-level signal of the first clock signal CK1, and the voltage stabilizing module 23 writes the high level of the input signal STV to the fourth node Q4 in the voltage stabilizing module 23 under the control of the high-level signal of the first clock signal CK1, and writes the low-level signal of the first voltage signal VG1 to the third node Q3 under the control of the high potential of the fourth node Q4.

[0064] The second period t2 includes a first sub-period t21 and a second sub-period t22. In the first sub-period t21, the voltage stabilizing module 23 writes the high-level signal of the first voltage signal VG1 to the third node Q3 under the control of the fourth node Q4, raises the potential of the fourth node Q4 based on the potential change of the third node Q3, the voltage of the fourth node Q4 is V3, the fourth node Q4 and the first node Q1 are unidirectionally conductive, and writes the voltage of the fourth node Q4 to the first node Q1; in the second sub-period t22, the voltage stabilizing module 23 writes the low-level signal of the first voltage signal VG1 to the third node Q3 under the control of the high potential of the fourth node Q4, and the voltage stabilizing module 23 writes the voltage of the input signal STV to the fourth node Q4 under the high-level control of the first clock signal CK1, the voltage of the fourth node Q4 is V4, and V4 < V3. Since the fourth node Q4 and the first node Q1 are unidirectionally conductive, the first node Q1 will not leak to the fourth node Q4, so that the first node Q1 can maintain a high potential. It can be seen from the timing diagram of FIG. 8 that in the second period t2, the first node Q1 maintains a relatively higher potential, and although the fourth node Q4 maintains a high potential, its high potential fluctuates.

[0065] In this embodiment, a third node Q3 and a fourth node Q4 are configured in the voltage regulator module 23. A low-level signal is written to the third node Q3 during the first time period t1. During the first sub-segment t21 of the second time period t2, a high-level signal is written to the third node Q3. This change in the potential of the third node Q3 pulls the potential of the fourth node Q4 high, which in turn pulls the potential of the first node Q1 high. Then, during the second sub-segment t21, the potential of the fourth node Q4 is pulled low, cutting off the path between the fourth node Q4 and the first node Q1. This ensures that the first node Q1 remains stably at a relatively higher potential after the first sub-segment t21, thereby enabling the output transistor controlled by the first node Q1 to be stably turned on, ensuring that the output terminal of the shift register unit 20 outputs a stable high-level enable signal.

[0066] In some embodiments, Figure 9 is a schematic diagram of another shift register unit provided by an embodiment of the present invention. As shown in Figure 9, the voltage regulator module 23 includes a first transistor T1, a second transistor T2, a first capacitor C1, a third transistor T3, and a sub-input module 231. The control terminal of the first transistor T1 is connected to the first node Q1 through the third transistor T3, and the control terminal of the second transistor T2 is connected to the second node Q2. The first terminal of the first transistor T1 receives a first voltage signal VG1, and the second terminals of the first transistor T1 and the second transistor T2 are connected to the third node Q3. The first terminal of the second transistor T2 receives a second voltage signal VG2. The first voltage signal VG1 can be a second clock signal CK2, and the second voltage signal VG2 can be a low-level signal VGL. The control terminal of the first transistor T1, one plate of the first capacitor C1, and the control terminal of the third transistor T3 are connected to the fourth node Q4. The first terminal of the third transistor T3 is connected to the fourth node Q4, and the second terminal of the third transistor T3 is connected to the first node Q1. The output of sub-input module 231 is connected to the fourth node Q4. Sub-input module 231 is configured to write voltage to the fourth node Q4 based on the input signal STV and the first clock signal CK1.

[0067] Referring to the timing diagram in Figure 8, in the first time period t1, the sub-input module 231, under the control of the first clock signal CK1, writes the high level of the input signal STV into the fourth node Q4 of the voltage regulator module 23. The high potential of the fourth node Q4 controls the first transistor T1 to turn on and writes the low level signal of the first voltage signal VG1 into the third node Q3. In the second time period t2, in the first sub-segment t21, the high potential of the fourth node Q4 controls the first transistor T1 to turn on and writes the high level signal of the first voltage signal VG1 into the third node Q3. The third node Q3 jumps from a low potential to a high potential. Due to the coupling effect of the first capacitor C1, the potential of the fourth node Q4 is pulled high. The high potential of the fourth node Q4 controls the third transistor T3 to turn on and writes the high potential of the fourth node Q4 into the first node Q1, thereby pulling the potential of the first node Q1 high. In addition, in the embodiment of Figure 9, the control terminal and the first terminal of the third transistor T3 are both connected to the fourth node Q4. The third transistor T3 forms a diode-like structure, giving it unidirectional conduction characteristics. In the second sub-segment t21, under the high potential control of the fourth node Q4, the low level signal of the first voltage signal VG1 is written to the third node Q3, and the voltage regulator module 23, under the high level control of the first clock signal CK1, writes the high level of the input signal STV to the fourth node Q4. At this time, the potential of the fourth node Q4 is lower than its potential in the first sub-segment t21. However, since the third transistor T3 forms a diode-like structure, it can prevent the first node Q1 from discharging to the fourth node Q4, making the high potential stability of the first node Q1 better. Therefore, the first node Q1 can still maintain a relatively higher high potential in the second sub-segment t22.

[0068] In addition, in the embodiment shown in Figure 9, the operation of the shift register unit 20 also includes a reset period t30. During the reset period t30, the first node Q1 is at a low potential, and the second node Q2 is at a high potential. During the reset period t30, the voltage regulator module 23 writes the low potential of the second voltage signal VG2 into the third node Q3 based on the control of the second node Q2. Specifically, during the period when the second node Q2 is at a high level, the second node Q2 controls the second transistor T2 to turn on and write the second voltage signal VG2 into the third node Q3 to reset the third node Q3.

[0069] In some embodiments, Figure 10 is a schematic diagram of another shift register unit provided by an embodiment of the present invention. As shown in Figure 10, the sub-input module 231 includes a fourth transistor T4 and a fifth transistor T5. The control terminal of the fourth transistor T4 receives a first clock signal CK1, the first terminal receives an input signal STV, and the second terminal is connected to the sixth node Q6. The control terminal of the fifth transistor T5 receives a third voltage signal VG3, the first terminal is connected to the sixth node Q6, and the second terminal is connected to the fourth node Q4. The third voltage signal VG3 is a high-level signal VGH. During the first time period t1, the fourth transistor T4 is turned on under the high-level control of the first clock signal CK1, writing the high level of the input signal STV to the sixth node Q6. The fifth transistor T5 is turned on under the control of the third voltage signal VG3, writing the high potential of the sixth node Q6 to the fourth node Q4. During the second time period t2, in the first sub-segment t21, the first clock signal CK1 is at a low level, so the fourth transistor T4 is turned off, and the path for the sub-input module 231 to write signals to the fourth node Q4 is closed, causing the fourth node Q4 to maintain a high potential. In the second sub-segment t22 of the second time period t2, the first clock signal CK1 is at a high level, then the fourth transistor T4 is turned on, and the sub-input module 231 writes the signal provided by the input signal STV to the fourth node Q4.

[0070] In some embodiments, as shown in FIG10, the voltage regulator module 23 further includes a sixth transistor T6. The control terminal of the sixth transistor T6 is connected to the sixth node Q6, the first terminal receives the second voltage signal VG2, and the second terminal is connected to the second node Q2. During the first time period t1 and the second time period t2 when the first node Q1 is at a high potential, the sixth node Q6 is at a high potential. The high potential of the sixth node Q6 controls the sixth transistor T6 to turn on and write the low level of the second voltage signal VG2 to the second node Q2, so that the second node Q2 is well maintained in a low level state.

[0071] In other embodiments, Figure 11 is a schematic diagram of another shift register unit provided by an embodiment of the present invention, and Figure 12 is a timing diagram of another embodiment of the present invention. The signal timing provided in Figure 12 can be used to drive the shift register unit provided in Figure 11. As shown in Figure 11, the voltage regulator module 23 includes a seventh transistor T7 and an eighth transistor T8. The control terminal of the seventh transistor T7 receives a first clock signal CK1. The first terminal of the seventh transistor T7 and an output terminal of the input module 21 are connected to the fifth node Q5, and the second terminal of the seventh transistor T7 is connected to the first node Q1. The control terminal of the eighth transistor T8 is connected to the first node Q1. The first terminal of the eighth transistor T8 receives a first voltage signal VG1, which is either the input signal STV or a high-level signal VGH. The second terminal of the eighth transistor T8 is connected to the fifth node Q5.

[0072] Referring to the timing diagram shown in Figure 12, the operation of the shift register unit 20 includes a first time period t1 and a second time period t2; during both the first time period t1 and the second time period t2, the first node Q1 is at a high potential.

[0073] During the first time period t1, the first clock signal CK1 and the first voltage signal VG1 are both high-level signals. Under the control of the first node Q1 potential, the voltage regulator module 23 writes the high-level signal of the first voltage signal VG1 to the fifth node Q5, and under the control of the high-level signal of the first clock signal CK1, it writes the high potential of the fifth node Q5 to the first node Q1. Specifically, the high potential of the first node Q1 controls the eighth transistor T8 to turn on, writing the high-level signal VGH (or the high-level signal of the input signal STV) to the fifth node Q5. The high-level signal of the first clock signal CK1 controls the seventh transistor T7 to turn on, writing the high potential of the fifth node Q5 to the first node Q5. During this time period, both the first node Q1 and the fifth node Q5 are at high potentials.

[0074] During the second time period t2, the first clock signal CK1 is at a low level and the first voltage signal VG1 is at a high level. The voltage regulator module 23, under the control of the first node Q1 potential, writes the high-level signal of the first voltage signal VG1 to the fifth node Q5, and under the control of the low-level signal of the first clock signal CK1, cuts off the path between the fifth node Q5 and the first node Q1. Specifically, the high potential of the first node Q1 controls the eighth transistor T8 to turn on, writing the high-level signal VGH (or the high-level signal of the input signal STV) to the fifth node Q5. At this time, the first clock signal CK1 is at a low level, so the seventh transistor T7 is off. During this time period, both the first node Q1 and the fifth node Q5 are at high potentials, and the path between the two nodes is cut off, allowing the first node Q1 to maintain a high potential and preventing leakage from the first node Q1 to other nodes from affecting the output of the high-level signal of the shift register unit.

[0075] In some embodiments, as shown in FIG7, the input module 21 includes a first submodule 211, a second submodule 212, and a third submodule 213. The first submodule 211 is configured to write a voltage to the first node Q1 based on the input signal STV and the first clock signal CK1; the second submodule 212 is configured to write a high level to the second node Q2 based at least on the input signal STV and the first clock signal CK1; and the third submodule 213 is configured to write a low level to the second node Q2 based on the control of the output signal of the first submodule 211. In this embodiment, the first submodule 211, the second submodule 212, and the third submodule 213 cooperate to realize the writing of signals to the first node Q1 and the second node Q2.

[0076] Figure 7 illustrates that the shift register unit 20 also includes a protection transistor M5. One output terminal of the input module 21 is connected to the fifth node Q5, and the protection transistor M5 is connected between the fifth node Q5 and the first node Q1. The first submodule 211 is configured to write voltage to the fifth node Q5 based on the input signal STV and the first clock signal CK1, and then write voltage to the first node Q1 through the protection transistor M5.

[0077] In one embodiment, as shown in FIG7, the second submodule 212 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The control terminal of the ninth transistor T9 receives an input signal STV, and the first terminal of the ninth transistor T9 receives a second voltage signal VG2, which may be a low-level signal VGL. The second terminal of the ninth transistor T9 and the control terminal of the tenth transistor T10 are connected to the seventh node Q7. The first terminal of the tenth transistor T10 receives a first clock signal CK1, and the second terminal is connected to the second node Q2. One plate of the second capacitor C2 receives the first clock signal CK1, and the other plate is connected to the seventh node Q7.

[0078] The first submodule 211 includes an eighteenth transistor T18. The control terminal of the eighteenth transistor T18 receives a first clock signal CK1, the first terminal receives an input signal STV, and the second terminal is connected to the first node Q1. The third submodule 213 includes a nineteenth transistor T19. The control terminal of the nineteenth transistor T19 is connected to the output terminal of the first submodule 211 (i.e., connected to the fifth node Q5), the first terminal receives a second voltage signal VG2, and the second terminal is connected to the second node Q2.

[0079] Figure 13 is another timing diagram provided by an embodiment of the present invention, which can be used to drive the shift register unit provided in the embodiment of Figure 7. The operation of the input module 21 can be viewed in conjunction with Figures 7 and 13. The operation of the shift register unit 20 includes a first time period t1, a second time period t2, and a third time period t3 ordered by time.

[0080] During the first time period t1, input module 21 is turned on under the control of the high level of the first clock signal CK1 and the high level of the input signal STV, writing the high level of the input signal STV to the first node Q1 and the low level of the second voltage signal VG2 to the second node Q2 and the seventh node Q7. Specifically, the high level of the first clock signal CK1 controls the eighteenth transistor T18 in the first submodule 211 to turn on, writing the high level of the input signal STV to the fifth node Q5. The high level of the fifth node Q5 is then written to the first node Q1 through the protection transistor M5. The high level of the fifth node Q5 controls the nineteenth transistor T19 in the third submodule 213 to turn on, writing the low level of the second voltage signal VG2 to the second node Q2. In addition, the high level of the input signal STV controls the ninth transistor T9 in the second submodule 212 to turn on, writing the low level of the second voltage signal VG2 to the seventh node Q7. During this time period, the fifth node Q5 and the first node Q1 are at a high potential, while the second node Q2 and the seventh node Q7 are at a low potential.

[0081] During the second time period t2, input module 21 is turned off under the control of the low level signal of the first clock signal CK1, the first node Q1 remains at a high potential, and the second node Q2 and the seventh node Q7 remain at a low potential. Specifically, the low level signal of the first clock signal CK1 controls the eighteenth transistor T18 to turn off, thus the fifth node Q5 remains at a high potential. The high level of the fifth node Q5 controls the nineteenth transistor T19 in the third submodule 213 to turn on, and the second node Q2 remains at a low potential. The high level of the input signal STV controls the ninth transistor T9 in the second submodule 212 to turn on, and the seventh node Q7 remains at a low potential. Combining the above description of the voltage regulator module 23, it can be seen that during this time period, the first node Q1 remains at a high potential due to the function of the voltage regulator module 23.

[0082] During the third time period t3, input module 21 is turned on under the control of the high-level signal of the first clock signal CK1, writing the low level of the input signal STV to the first node Q1, and based on the high level of the first clock signal CK1, pulling up the potential of the seventh node Q7 and writing the high level of the first clock signal CK1 to the second node Q2. Specifically, the high level of the first clock signal CK1 controls the eighteenth transistor T18 in the first submodule 211 to turn on, writing the low level of the input signal STV to the fifth node Q5. The low level of the fifth node Q5 is then written to the first node Q1 through the protection transistor M5, making the first node Q1 a low potential. In addition, the low level of the input signal STV controls the ninth transistor T9 in the second submodule 212 to turn off. During this time period, the first clock signal CK1 jumps from a low level to a high potential. Due to the coupling effect of the second capacitor C2, the potential of the seventh node Q7 is pulled up, making the seventh node Q7 a high potential. The high potential of the seventh node Q7 controls the tenth transistor T10 in the second submodule 212 to turn on, writing the high level of the first clock signal CK1 to the second node Q2. During this period, the first node Q1 is at a low potential, and the second node Q2 is at a high potential.

[0083] In addition, the structure of the input module 21 shown in the embodiment of Figure 11 is the same as that of the input module 21 in Figure 7. The working process of the input module 21 shown in the embodiment of Figure 11 can be understood with reference to the above description, and will not be repeated here.

[0084] In some embodiments, as shown in FIG10, the input module 21 includes a first submodule 211, a second submodule 212, and a third submodule 213. The first submodule 211 is configured to write a voltage to the first node Q1 based on the input signal STV and the first clock signal CK1; the second submodule 212 is configured to write a high level to the second node Q2 based at least on the input signal STV and the first clock signal CK1; and the third submodule 213 is configured to write a low level to the second node Q2 based on the control of the output signal of the first submodule 211.

[0085] The second submodule 212 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The ninth transistor T9 includes a first subtransistor T91 and a second subtransistor T92. The control terminals of the first and second subtransistors T91 and T92 receive the input signal STV. The first terminal of the first subtransistor T91 receives the second voltage signal VG2. The second terminals of the first and second subtransistors T91 and T92 are connected to the eighth node Q8, and the second terminal of the second subtransistor T92 is connected to the seventh node Q7. The control terminal of the tenth transistor T10 is connected to the seventh node Q7, its first terminal receives the first clock signal CK1, and its second terminal is connected to the second node Q2. One plate of the second capacitor C2 receives the first clock signal CK1, and its other plate is connected to the seventh node Q7. The second submodule 212 also includes an eleventh transistor T11. The control terminal of the eleventh transistor T11 is connected to the seventh node Q7, its first terminal receives the third voltage signal VG3, and its second terminal is connected to the eighth node Q8. The second voltage signal VG2 can be a low-level signal VGL, and the third voltage signal VG3 can be a high-level signal VGH. Figure 10 also illustrates that the first submodule 211 includes the eighteenth transistor T18, and the third submodule 213 includes the nineteenth transistor T19.

[0086] In another embodiment, FIG14 is a schematic diagram of another shift register unit provided by an embodiment of the present invention. As shown in FIG14, the input module 21 includes a first submodule 211, a second submodule 212, and a third submodule 213. The first submodule 211 includes an eighteenth transistor T18, and the third submodule 213 includes a nineteenth transistor T19. The second submodule 212 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The difference between the input module 21 in FIG14 and FIG10 is that in the embodiment of FIG14, the first terminal of the eleventh transistor T11 receives a first clock signal CK1, and the control terminal of the eleventh transistor T11 is connected to the second terminal of the tenth transistor T10.

[0087] In another embodiment, FIG15 is a schematic diagram of another shift register unit provided by the present invention. The difference between FIG15 and FIG14 is that in the embodiment of FIG15, the first terminal of the eleventh transistor T11 receives the third voltage signal VG3, and the control terminal of the eleventh transistor T11 is connected to the seventh node Q7.

[0088] The operation of the input module 21 in the embodiments of Figures 10, 14, and 15 can be understood in conjunction with the timing diagram provided in Figure 13. Taking the embodiment of Figure 10 as an example, the operation of the second sub-module 212 is as follows: In the first time period t1, the input signal STV is high, controlling the first sub-transistor T91 and the second sub-transistor T92 to turn on, while the eighth node Q8 and the seventh node Q7 are written to a low level. The low level of the seventh node Q7 controls the eleventh transistor T11 to turn off. In the second time period t2, the eighth node Q8 and the seventh node Q7 remain at a low level. In the third time period t3, the input signal STV is low, controlling the first sub-transistor T91 and the second sub-transistor T92 to turn off, and the first clock signal CK1 jumps from a low level to a high level. Due to the coupling effect of the second capacitor C2, the potential of the seventh node Q7 is pulled high. The high potential of the seventh node Q7 controls the eleventh transistor T11 to turn on, writing the high level of the third voltage signal VG3 to the eighth node Q8. At this point, both node 8 (Q8) and node 7 (Q7) are at a high level, and both the first sub-transistor T91 and the second sub-transistor T92 are in the off state. This prevents leakage current from node 7 (Q7) when the ninth transistor T9 is in a negative bias state. This also ensures that the tenth transistor T10 is in a stable on state, allowing node 2 (Q2) to stably receive the high-level signal provided by the first clock signal CK1, and node 2 (Q2) to be at a stable high potential.

[0089] In some implementations, as shown in Figures 9 and 10, the shift register unit further includes a leakage protection module 24. The leakage protection module 24 is connected between the second node Q2 and the output module 22, and is configured to be turned off under the control of the first clock signal CK1. Taking Figure 10 as an example, and referring to the timing diagram in Figure 13, during the third time period t3, the first clock signal CK1 is high, and the second node Q2 is written with a high potential. The leakage protection module 24 then turns on, writing the high level of the second node Q2 to the control terminal of the fourth output transistor M4 in the output module 22, thereby causing the shift register unit to output a low-level signal VGL. The third time period t3 is the period during which a high-level signal is written to the control terminal of the fourth output transistor M4. During the fourth time period t4, the first clock signal CK1 is low, and the leakage protection module 24 is turned off, thereby closing the leakage path of the control terminal of the fourth output transistor M4, thus stabilizing the potential of the output terminal of the fourth output transistor M4, and enabling the shift register unit to stably output a low-level signal.

[0090] As shown in Figure 10, the leakage protection module 24 includes a twelfth transistor T12. The control terminal of the twelfth transistor T12 receives the first clock signal CK1, the first terminal is connected to the second node Q2, and the second terminal is connected to a control terminal of the output module 22. Specifically, the second terminal is connected to the control terminal of the fourth output transistor M4.

[0091] In some embodiments, FIG16 is a schematic diagram of another shift register unit provided by an embodiment of the present invention. As shown in FIG16, the input module 21 includes a first submodule 211, a second submodule 212, and a third submodule 213. The first submodule 211 is configured to write a voltage to the first node Q1 based on the input signal STV and the first clock signal CK1. The second submodule 212 is configured to write a voltage to the second node Q2 based at least on the output signal of the first submodule 211, the first clock signal CK1, and the second clock signal CK2. The third submodule 213 is configured to write a low level to the second node Q2 based on the control of the output signal of the first submodule 211.

[0092] As shown in Figure 16, the second submodule 212 includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, and a third capacitor C3. The control terminal of the thirteenth transistor T13 is connected to the output terminal of the first submodule 211; its first terminal receives a second voltage signal VG2; and its second terminal is connected to the second terminal of the fourteenth transistor T14. Optionally, the second voltage signal VG2 is a low-level signal VGL. The control terminal of the fourteenth transistor T14 receives a first clock signal CK1, and the control terminal of the fifteenth transistor T15 receives a third voltage signal VG3. Optionally, the third voltage signal VG3 is a high-level signal VGH. The first terminal of the fourteenth transistor T14 receives the third voltage signal VG3, and its second terminal is connected to the first terminal of the fifteenth transistor T15. The second terminal of the fifteenth transistor T15 and the control terminal of the sixteenth transistor T16 are connected to the ninth node Q9. The first terminal of the sixteenth transistor T16 receives the second clock signal CK2, and the second terminal is connected to the tenth node Q10. One plate of the third capacitor C3 is connected to the ninth node Q9, and the other plate is connected to the tenth node Q10. The control terminal of the seventeenth transistor T17 receives the second clock signal CK2, the first terminal is connected to the tenth node Q10, and the second terminal is connected to the second node Q2.

[0093] Additionally, the first submodule 211 includes an eighteenth transistor T18. The control terminal of the eighteenth transistor T18 receives a first clock signal CK1, the first terminal receives an input signal STV, and the second terminal is connected to the first node Q1. Optionally, as shown in Figure 16, the second terminal of the eighteenth transistor T18 is connected to the fifth node Q5, and the fifth node Q5 is connected to the first node Q1 through a protection transistor M5. The third submodule 213 includes a nineteenth transistor T19. The control terminal of the nineteenth transistor T19 is connected to the output terminal of the first submodule 211, the first terminal receives a second voltage signal VG2, and the second terminal is connected to the second node Q2.

[0094] Figure 17 is another timing diagram provided by an embodiment of the present invention, which can be used to drive the shift register unit provided in the embodiment of Figure 16. The working process of the input module 21 can be understood in conjunction with Figures 16 and 17. As shown in Figure 17, the operation of the shift register unit 20 includes a first time period t1, a second time period t2, a third time period t3, and a fourth time period t4 ordered by time.

[0095] During the first time period t1, input module 21, under the control of the high-level signal of the first clock signal CK1, turns on and writes the high level of the input signal STV to the first node Q1, the low level of the second voltage signal VG2 to the second node Q2, and the low level to the ninth node Q9. Under the control of the low level of the second clock signal CK2, the path between the tenth node Q10 and the second node Q2 is cut off. Specifically, the high level of the first clock signal CK1 turns on the eighteenth transistor T18 in the first submodule 211, writing the high level of the input signal STV to the fifth node Q5. The fifth node Q5 then writes the high level to the first node Q1 through the protection transistor M5. During this time period, the output of the first submodule 211 is high, controlling the nineteenth transistor T19 in the third submodule 213 to turn on, writing the low level of the second voltage signal VG2 to the second node Q2. The high level at the output of the first submodule 211 also controls the thirteenth transistor T13 in the second submodule 212 to turn on. Simultaneously, the first clock signal CK1 controls the fourteenth transistor T14 to turn on. The high level of the third voltage signal VG3 written through the fourteenth transistor T14 will leak through the thirteenth transistor T13. Meanwhile, the fifteenth transistor turns on under the control of the high level of the third voltage signal VG3, so at this moment, the ninth node Q9 is written with a low potential. With the ninth node Q9 at a low potential and the second clock signal CK2 at a low level, both the sixteenth transistor T16 and the seventeenth transistor T17 are turned off. During this period, the first node Q1 is at a high potential, the second node Q2 is at a low potential, the third output terminal M3 in the output module 22 turns on, and the output terminal OUT outputs a high-level signal.

[0096] During the second time period t2, input module 21 is turned off under the control of the low level of the first clock signal CK1. First node Q1 remains at a high potential, while second node Q2 and ninth node Q9 remain at a low potential. Under the control of the high level of the second clock signal CK2, the path between tenth node Q10 and second node Q2 is opened. Specifically, when the first clock signal CK1 is low, the eighteenth transistor T18 and the fourteenth transistor T14 are turned off. Fifth node Q5 and first node Q1 remain at a high potential. During this period, second node Q2 and ninth node Q9 remain at a low potential. Furthermore, the high level of the second clock signal CK2 controls the seventeenth transistor T17 to turn on, thus opening the path between tenth node Q10 and second node Q2. During this period, first node Q1 is at a high potential, second node Q2 is at a low potential, the third output terminal M3 of output module 22 is turned on, and output terminal OUT outputs a high-level signal.

[0097] During the third time period t3, input module 21 is turned on under the control of the high level signal of the first clock signal CK1, writing the low level of the input signal STV to the first node Q1, writing the high level of the third voltage signal VG3 to the ninth node Q9, and under the control of the ninth node Q9, writing the low level of the second clock signal CK2 to the tenth node Q10. Under the control of the low level of the second clock signal CK2, the path between the tenth node Q10 and the second node Q2 is cut off, and the second node Q2 remains at a low potential. Specifically, the high level signal of the first clock signal CK1 controls the eighteenth transistor T18 and the fourteenth transistor T14 to turn on. The eighteenth transistor T18 writes the low level of the input signal STV to the fifth node Q5, and the fifth node Q5 writes the low level to the first node Q1 through the protection transistor M5. At the same time, the low level of the fifth node Q5 controls the thirteenth transistor T13 to turn off, while the fourteenth transistor T14 and the fifteenth transistor T15 turn on and write the high level of the third voltage signal VG3 to the ninth node Q9. The high level of node Q9 at the ninth node controls the sixteenth transistor T16 to turn on, writing the low level of the second clock signal CK2 into node Q10 at the tenth node. The low level of the second clock signal CK2 controls the seventeenth transistor T17 to turn off, cutting off the path between node Q10 at the tenth node and node Q2 at the second node. During this period, node Q2 at the second node is at a low potential, node Q1 at the first node is at a low potential, and the output terminal OUT of output module 22 maintains the output state of the previous period and outputs a high-level signal.

[0098] During the fourth time period t4, input module 21 is turned off under the control of the low level signal of the first clock signal CK1. The first node Q1 maintains a low potential, and the ninth node Q9 maintains a high potential. Under the control of the ninth node Q9, the high level of the second clock signal CK2 is written to the tenth node Q10. Due to the coupling effect of the third capacitor C3, the potential change of the tenth node Q10 pulls the potential of the ninth node Q9 high. Under the control of the high level of the second clock signal CK2, the path between the tenth node Q10 and the second node Q2 is turned on, and the second node Q2 is written to a high potential. During this period, the second node Q2 is at a high potential, the first node Q1 is at a low potential, the fourth output terminal M4 of the output module 22 is turned on, and the output terminal OUT outputs a low level signal.

[0099] In some embodiments, Figure 18 is a schematic diagram of a cascaded shift register unit provided by an embodiment of the present invention. As shown in Figure 18, the shift register unit 20 includes an input module 21, an output module 22, and a voltage regulator module 23. The output terminal OUT of the output module 22 in the i-th stage shift register unit 20(i) is connected to the input terminal of the input module 21 in the (i+1)-th stage shift register unit 20(i+1), where i is a positive integer. That is, the signal output by the output terminal OUT of the output module 22 in the shift register unit 20 serves as the input signal STV received by the input module 21 in the next stage shift register unit 20.

[0100] In other embodiments, Figure 19 is a schematic diagram of another shift register unit provided by an embodiment of the present invention, and Figure 20 is a schematic diagram of another cascaded shift register unit provided by an embodiment of the present invention. As shown in Figure 19, the shift register unit 20 further includes a cascade module 25, which is connected to the first node Q1 and the second node Q2 respectively. The cascade module 25 is configured to output a high-level signal based on the voltage of the first node Q1 and to output a low-level signal based on the voltage of the second node Q2. In application, the signal output from the Next terminal of the cascade module 25 is used to cascade and provide to the input terminal of the next-level shift register unit, and the signal output from the OUT terminal of the output module 22 is used to provide to the scan line to drive the pixel circuit. This reduces the voltage drop of the scan signal output by the shift register unit 20, which is beneficial to improving display uniformity.

[0101] Referring to Figure 20, the output terminal Next of the transmission module 25 in the i-th stage shift register unit 20(i) is connected to the input terminal of the input module 21 in the (i+1)-th stage shift register unit 20(i+1), where i is a positive integer. That is, the signal output from the output terminal Next of the transmission module 25 in the shift register unit 20 serves as the input signal STV received by the input module 21 in the next stage shift register unit 20.

[0102] In some embodiments, FIG21 is a schematic diagram of another shift register unit provided by an embodiment of the present invention. FIG22 is a timing diagram provided by an embodiment of the present invention, which can be used to drive the shift register unit provided in FIG21. As shown in FIG21, the shift register unit 20 includes an input module 21, an output module 22, a voltage regulator module 23, and a transmission module 25. The transmission module 25 includes a first output transistor M1 and a second output transistor M2. The control terminal of the first output transistor M1 is connected to the first node Q1, the first terminal receives the third voltage signal VG3, and the second terminal is connected to the output terminal Next of the transmission module 25. The control terminal of the second output transistor M2 is connected to the second node Q2, the first terminal receives the second voltage signal VG2, and the second terminal is connected to the output terminal Next of the transmission module 25. Specifically, the protection transistor M5 is connected between the first node Q1 and the output terminal of the input module 21, and the control terminal of the second output transistor M2 is connected to the second node Q2 through the twelfth transistor T12. Among them, the third voltage signal VG3 provides a high-level signal, and the second voltage signal VG2 provides a low-level signal. Figure 21 also shows capacitor C03, one plate of which is connected to the control terminal of the second output tube M2, and the other plate receives the second voltage signal VG2.

[0103] Output module 22 includes a third output transistor M3 and a fourth output transistor M4. The control terminal of the third output transistor M3 is connected to the first node Q1, receives the fourth voltage signal VG4 at its first terminal, and is connected to the output terminal OUT of output module 22 at its second terminal. The control terminal of the fourth output transistor M4 is connected to the second node Q2, receives the fifth voltage signal VG5 at its first terminal, and is connected to the output terminal OUT of output module 22 at its second terminal. Specifically, the control terminal of the fourth output transistor M4 is connected to the second node Q2 through the twelfth transistor T12. The fourth voltage signal VG4 provides a high-level signal, and the fifth voltage signal VG5 provides a low-level signal.

[0104] In addition, the input module 21 in the embodiment of Figure 21 has the same structure as the input module 21 in the embodiment of Figure 10, and the voltage regulator module 22 has the same structure as the voltage regulator module 22 in the embodiment of Figure 1, which will not be described again here.

[0105] In some other embodiments, FIG23 is a schematic diagram of another shift register unit provided by an embodiment of the present invention. FIG24 is a timing diagram provided by an embodiment of the present invention, which can be used to drive the shift register unit provided in FIG23. As shown in FIG23, the shift register unit 20 includes an input module 21, an output module 22, a voltage regulator module 23, and a transmission module 25. The input module 21 in the embodiment of FIG23 has the same structure as the input module 21 in the embodiment of FIG10, and the voltage regulator module 22 has the same structure as the voltage regulator module 22 in the embodiment of FIG10.

[0106] In some other embodiments, FIG25 is a schematic diagram of another shift register unit provided by an embodiment of the present invention. As shown in FIG25, the shift register unit 20 includes an input module 21, an output module 22, a voltage regulator module 23, a leakage protection module 24, and a transmission module 25. The input module 21 in the embodiment of FIG23 has the same structure as the input module 21 in the embodiment of FIG10, and the voltage regulator module 22 has the same structure as the voltage regulator module 22 in the embodiment of FIG11.

[0107] In some other embodiments, FIG26 is a schematic diagram of another shift register unit provided by an embodiment of the present invention. As shown in FIG25, the shift register unit 20 includes an input module 21, an output module 22, a leakage protection module 24, and a transmission module 25. Figure 26 also shows capacitors C04 and C05.

[0108] In some implementations, both the third voltage signal VG3 and the fourth voltage signal VG5 provide high-level signals, with the voltage value of the third voltage signal VG3 being VGH1 and the voltage value of the fourth voltage signal VG4 being VGH2, where VGH2 ≤ VGH1. This configuration allows the potential control of the first node Q1 to more fully turn on the third output transistor M3, resulting in a more stable high-level enable level at the output terminal OUT of the output module 22.

[0109] In some implementations, both the second voltage signal VG2 and the fifth voltage signal VG5 provide low-level signals, with the voltage value of the second voltage signal VG2 being VGL1 and the voltage value of the fifth voltage signal VG5 being VGL2, where VGL2 ≥ VGL1. This configuration ensures that when the fourth output transistor M4 is in a negative bias state and the output terminal OUT of the output module 22 outputs a high level, the fourth output transistor M4 can be completely turned off, thereby guaranteeing the stability of the high-level output at the output terminal OUT of the output module 22.

[0110] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 27 is a schematic diagram of a display device provided in an embodiment of the present invention. As shown in Figure 27, the display device includes a display panel 100 provided in any embodiment of the present invention. The structure of the display panel has been described in the above embodiments and will not be repeated here. The display device provided in the embodiments of the present invention can be, for example, an electronic device such as a mobile phone, tablet, television, or smart wearable product.

[0111] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized by, The display panel comprises a shift register, the shift register comprises a plurality of shift register units; the shift register unit comprises an input module, an output module and a voltage stabilizing module; The input module is configured to write voltages to the first node and the second node based on at least the input signal and the first clock signal, and the output module is connected to the first node and the second node respectively; the output module is configured to output a high-level signal based on the voltage of the first node, and is also configured to output a low-level signal based on the voltage of the second node; The voltage stabilizing module is connected to at least the first node; during at least part of the period when the first node is at a high potential, the voltage stabilizing module is configured to pull up the potential of the first node based on the voltage of the first node and the first voltage signal.

2. The display panel of claim 1, wherein The operation of the shift register unit comprises a first period and a second period; during the first period and the second period, the first node is at a high potential; During the first period, the voltage of the first node is V1; during the second period, the voltage of the first node is V2, V2>V1.

3. The display panel of claim 2, wherein The operation of the shift register unit comprises m first periods and m second periods, m is an integer, m≥1; In time sequence, the first period and the second period are alternately arranged, and the first first period is earlier than the first second period.

4. The display panel of claim 3, wherein During the first period, the input module writes a high potential to the first node based on the high-level signal of the first clock signal, and the voltage stabilizing module writes a low-level signal of the first voltage signal to a third node in the voltage stabilizing module under the control of the first node; During the second period, the voltage stabilizing module writes a high-level signal of the first voltage signal to the third node under the control of the first node, and pulls up the potential of the first node based on the potential change of the third node.

5. The display panel of claim 2, wherein In time sequence, the first period is earlier than the second period; The length of the first period is t01, and the length of the second period is t02, t02>t01.

6. The display panel of claim 5, wherein During the first period, the input module writes a high potential to the first node based on the high-level signal of the first clock signal, and the voltage stabilizing module writes a high-level of the input signal to a fourth node in the voltage stabilizing module under the control of the high-level signal of the first clock signal, and writes a low-level signal of the first voltage signal to a third node under the control of the high potential of the fourth node; The second period comprises a first sub-period and a second sub-period; In the first sub-segment, the voltage regulator module, under the control of the fourth node, writes the high-level signal of the first voltage signal into the third node, pulls up the potential of the fourth node based on the potential change of the third node, the voltage of the fourth node is V3, the fourth node and the first node are unidirectionally conductive, and writes the voltage of the fourth node into the first node. In the second sub-segment, under the high-potential control of the fourth node, the voltage regulator module writes the low-level signal of the first voltage signal to the third node. Under the high-level control of the first clock signal, the voltage regulator module writes the voltage of the input signal to the fourth node. The voltage of the fourth node is V4. <V3。 7. The display panel according to claim 1, characterized in that, The operation of the shift register unit includes a first time period and a second time period; during the first time period and the second time period, the first node is at a high potential; During the first time period, the first clock signal is a high-level signal and the first voltage signal is a high-level signal. Under the control of the first node, the voltage regulator module writes the high-level signal of the first voltage signal into the fifth node, and under the control of the first clock signal, writes the high potential of the fifth node into the first node. During the second time period, the first clock signal is a low-level signal and the first voltage signal is a high-level signal. Under the control of the first node, the voltage regulator module writes the high-level signal of the first voltage signal into the fifth node, and under the control of the first clock signal, cuts off the path between the fifth node and the first node.

8. The display panel according to claim 1, characterized in that, The voltage regulator module includes a first transistor, a second transistor, and a first capacitor; The control terminal of the first transistor is connected to the first node, the control terminal of the second transistor is connected to the second node, the first terminal of the first transistor receives the first voltage signal, the second terminals of the first transistor and the second terminal of the second transistor are connected to the third node, and the first terminal of the second transistor receives the second voltage signal. One plate of the first capacitor is connected to the first node, and the other plate is connected to the third node.

9. The display panel according to claim 8, characterized in that, The first voltage signal is the second clock signal.

10. The display panel according to claim 8, characterized in that, The voltage regulator module also includes a third transistor and a sub-input module; The control terminal of the first transistor, one plate of the first capacitor, and the control terminal of the third transistor are connected to the fourth node. The first terminal of the third transistor is connected to the fourth node, and the second terminal of the third transistor is connected to the first node. The output terminal of the sub-input module is connected to the fourth node, and the sub-input module is configured to write voltage to the fourth node based on the input signal and the first clock signal.

11. The display panel according to claim 10, characterized in that, The sub-input module comprises a fourth transistor and a fifth transistor; The control end of the fourth transistor receives the first clock signal, the first end receives the input signal, and the second end is connected to a sixth node; the control end of the fifth transistor receives a third voltage signal, the first end is connected to the sixth node, and the second end is connected to the fourth node. 12.The display panel of claim 11, wherein, The voltage stabilizing module further comprises a sixth transistor, the control end of the sixth transistor is connected to the sixth node, the first end receives the second voltage signal, and the second end is connected to the second node. 13.The display panel of claim 1, wherein, The voltage stabilizing module comprises a seventh transistor and an eighth transistor; The control end of the seventh transistor receives the first clock signal, the first end of the seventh transistor and one output end of the input module are connected to a fifth node, and the second end of the seventh transistor is connected to the first node; The control end of the eighth transistor is connected to the first node, the first end of the eighth transistor receives the first voltage signal, the first voltage signal is the input signal or a high-level signal, and the second end of the eighth transistor is connected to the fifth node. 14.The display panel of claim 1, wherein, The input module comprises a first sub-module, a second sub-module, and a third sub-module; The first sub-module is configured to write a voltage to the first node based on the input signal and the first clock signal; The second sub-module is configured to write a high level to the second node based on at least the input signal and the first clock signal; The third sub-module is configured to write a low level to the second node based on the control of the output signal of the first sub-module. 15.The display panel of claim 14, wherein, The second sub-module comprises a ninth transistor, a tenth transistor, and a second capacitor; The control end of the ninth transistor receives the input signal, the first end of the ninth transistor receives a second voltage signal, the second end of the ninth transistor and the control end of the tenth transistor are connected to a seventh node; the first end of the tenth transistor receives the first clock signal, and the second end is connected to the second node; one plate of the second capacitor receives the first clock signal, and the other plate is connected to the seventh node. 16.The display panel of claim 15, wherein, The ninth transistor comprises a first sub-transistor and a second sub-transistor, the control end of the first sub-transistor and the control end of the second sub-transistor receive the input signal, the first end of the first sub-transistor receives a second voltage signal, the second end of the first sub-transistor and the first end of the second sub-transistor are connected to an eighth node, and the second end of the second sub-transistor is connected to the seventh node. The second sub-module further includes an eleventh transistor, a control end of the eleventh transistor is connected to the seventh node or a second end of the tenth transistor, a first end receives a third voltage signal or the first clock signal, and a second end is connected to the eighth node. 17.The display panel of claim 1, wherein, The shift register unit further includes an anti-leakage module, the anti-leakage module is connected between the second node and the output module, and the anti-leakage module is configured to be closed under control of the first clock signal. 18.The display panel of claim 17, wherein, The anti-leakage module includes a twelfth transistor, a control end of the twelfth transistor receives the first clock signal, a first end is connected to the second node, and a second end is connected to one control end of the output module. 19.The display panel of claim 1, wherein, The input module includes a first sub-module, a second sub-module, and a third sub-module; The first sub-module is configured to write a voltage to the first node based on the input signal and the first clock signal; The second sub-module is configured to write a voltage to the second node based on at least an output signal of the first sub-module, the first clock signal, and a second clock signal; The third sub-module is configured to write a low voltage to the second node based on control of the output signal of the first sub-module. 20.The display panel of claim 19, wherein, The second sub-module includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor; A control end of the thirteenth transistor is connected to an output end of the first sub-module, a first end receives a second voltage signal, and a second end is connected to a second end of the fourteenth transistor; a control end of the fourteenth transistor receives the first clock signal, a control end of the fifteenth transistor receives a third voltage signal, a first end of the fourteenth transistor receives the third voltage signal, and a second end is connected to a first end of the fifteenth transistor; a second end of the fifteenth transistor and a control end of the sixteenth transistor are connected to a ninth node; A first end of the sixteenth transistor receives the second clock signal, and a second end is connected to a tenth node; A control end of the seventeenth transistor receives the second clock signal, a first end is connected to the tenth node, and a second end is connected to the second node. 21.The display panel of claim 14 or 19, wherein, The first sub-module includes an eighteenth transistor, a control end of the eighteenth transistor receives the first clock signal, a first end receives the input signal, and a second end is connected to the first node; and / or the third sub-module includes a nineteenth transistor, a control end of the nineteenth transistor is connected to an output end of the first sub-module, a first end receives a second voltage signal, and a second end is connected to the second node. 22.The display panel of claim 1, wherein, ​ An output terminal of the output module in the i-th shift register unit is connected to an input terminal of the input module in the (i+1)-th shift register unit, where i is a positive integer. 23.The display panel of claim 1, wherein, The shift register unit further comprises a stage transmission module connected to the first node and the second node respectively; the stage transmission module is configured to output a high-level signal based on the voltage of the first node, and is configured to output a low-level signal based on the voltage of the second node. An output terminal of the stage transmission module in the i-th shift register unit is connected to an input terminal of the input module in the (i+1)-th shift register unit, where i is a positive integer. 24.The display panel of claim 23, wherein, The stage transmission module comprises a first output transistor and a second output transistor; a control terminal of the first output transistor is connected to the first node, a first terminal receives a third voltage signal, and a second terminal is connected to an output terminal of the stage transmission module; a control terminal of the second output transistor is connected to the second node, a first terminal receives a second voltage signal, and a second terminal is connected to the output terminal of the stage transmission module. The output module comprises a third output transistor and a fourth output transistor; a control terminal of the third output transistor is connected to the first node, a first terminal receives a fourth voltage signal, and a second terminal is connected to an output terminal of the output module; a control terminal of the fourth output transistor is connected to the second node, a first terminal receives a fifth voltage signal, and a second terminal is connected to the output terminal of the output module; wherein, The third voltage signal has a voltage value of VGH1, the fourth voltage signal has a voltage value of VGH2, and VGH2≤VGH1; and / or, the second voltage signal has a voltage value of VGL1, the fifth voltage signal has a voltage value of VGL2, and VGL2≥VGL1. 25.The display panel of claim 1, wherein, At least one transistor in the output module connected to the first node is an n-type transistor. 26.The display panel of claim 25, wherein, All transistors in the shift register unit are the n-type transistors. 27.The display panel of claim 25, wherein, An active layer of the n-type transistor comprises indium gallium zinc oxide.

28. A display device comprising: A display panel according to any one of claims 1 to 27.

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