Terminal structure of power device, manufacturing method, and chip

Abstract

Embodiments of the present disclosure provide a terminal structure of a power device, a manufacturing method, and a chip. The terminal structure comprises: an N-type substrate; a junction terminal extension region, a junction gradient doped region, and a plurality of field limiting rings that are arranged on the N-type substrate, the junction terminal extension region being connected to the junction gradient doped region, a depth of the junction gradient doped region gradually decreasing in the direction away from the junction terminal extension region, the plurality of field limiting rings being arranged at the end of the junction gradient doped region away from the junction terminal extension region, and distances of the plurality of field limiting rings relative to the junction gradient doped region gradually increasing; the junction terminal extension region, the junction gradient doped region, and the plurality of field limiting rings being doped with P-type ions; a trench, provided in the N-type substrate, the trench being provided on the side of the field limiting ring farthest from the junction gradient doped region away from the junction gradient doped region. By means of a composite terminal structure comprising the junction terminal extension region, the junction gradient doped region, the plurality of field limiting rings, the trench, and a polycrystalline silicon field plate, a maximum electric field strength of the chip can be effectively reduced, and a voltage withstand performance of the device can be improved.

Description

A power device's termination structure, manufacturing method, and chip

[0001] Cross-reference of related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 202411906647.0, filed on December 23, 2024, entitled "Terminal Structure, Manufacturing Method and Chip of a Power Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a terminal structure, manufacturing method and chip for a power device. Background Technology

[0004] Modern power devices (such as MOSFETs and IGBTs) are typically composed of thousands of identical cells connected in parallel. Each cell is a small power device, and these cells connected in parallel increase the overall current handling capability of the device. The surface voltage of each cell is roughly the same because they share the same voltage source and load. In power devices, the voltage difference between the termination cells (cells near the device edge) and the substrate (the bottom layer of the device) can be large because the termination cells need to withstand higher voltages to prevent breakdown caused by electric field concentration. This voltage difference leads to electric field concentration in the termination region, affecting the device's breakdown voltage. To improve the device's breakdown voltage, measures need to be taken to reduce the surface electric field. This is usually achieved by optimizing the termination structure, such as using techniques like field limiting rings (FLRs). Field limiting rings can introduce additional doped regions in the termination area to disperse the electric field and prevent breakdown caused by electric field concentration. Modern silicon power devices typically employ a shallow planar structure. This structure improves the device's breakdown voltage. In field-limiting ring (FLL) design, FLLs are often used to reduce surface electric field concentration caused by junction curvature effects, thereby improving the breakdown voltage. While FLLs can increase breakdown voltage, they also significantly increase chip area because they require the introduction of additional doped regions in the termination region, which occupy a portion of the chip area. Planar FLLs may exhibit peak electric fields at the injection junction corners (i.e., the corners of the doped regions). These peak electric fields can degrade the device's breakdown characteristics because electric field concentration increases the risk of breakdown. To further increase the junction depth (i.e., the depth of the doped region) and reduce the peak electric field at the injection junction corner, a trench field limiting ring (TFLR) termination structure can be used. The trench field limiting ring further disperses the electric field and reduces the peak electric field by introducing a trench structure in the termination region. Although the trench field limiting ring can reduce the peak electric field, it also increases the expansion capability of the lateral space charge region at the termination of the field limiting ring. This means that the termination region needs a larger area to accommodate these expanded space charge regions, resulting in an increase in the termination area.

[0005] In power devices, the main junction ring (Main Junction) refers to the main PN junction or Schottky junction. To improve the device's breakdown voltage, the surface of the Main Junction Ring is typically implanted with a high dose of doping. The implantation dose is usually between 1e12 and 1e15 / cm². 2The order of magnitude of the doping intensity. High-dose doping implantation leads to an increase in the surface electric field intensity of the main junction ring. Since the electric field concentration effect is more pronounced at the corners of the main junction ring (i.e., the corners of the doped regions), breakdown typically occurs at these corners. This means that the electric field intensity at the corners of the main junction is the highest, making them prone to breakdown. In actual production, the implantation dose may be affected by deviations in the production line equipment. This deviation can lead to uneven implantation dose, thus affecting device performance and reliability. JTE (Junction Termination Extension) is a termination protection technology used to improve the breakdown voltage capability of devices. The JTE structure disperses the electric field by introducing an additional doped region in the termination region, preventing breakdown caused by electric field concentration. However, if the implantation dose deviation results in a low doping concentration in the JTE structure, the effectiveness of the JTE structure will be affected. If the doping concentration of the JTE structure is low, the electric field distribution will be uneven, causing breakdown to occur at the JTE lateral junction termination extension structure. This means that the JTE structure fails to effectively disperse the electric field and instead becomes the location of breakdown. Because of the low doping concentration in the JTE structure, breakdown occurs at the JTE structure itself, resulting in poor terminal reliability and insufficient withstand voltage. This means that the device is prone to failure under high voltage or high temperature environments, affecting the system's stability and lifespan. Summary of the Invention

[0006] In view of the above problems, embodiments of the present disclosure are proposed to provide a power device terminal structure, manufacturing method and chip that overcomes or at least partially solves the above problems.

[0007] To address the aforementioned problems, this disclosure provides a termination structure for a power device, the termination structure comprising:

[0008] N-type substrate;

[0009] The N-type substrate includes a junction termination extension region, a junction gradient doped region, and multiple field-limiting rings. The junction termination extension region is connected to the junction gradient doped region. The depth of the junction gradient doped region gradually decreases away from the junction termination extension region. The multiple field-limiting rings are located at the end of the junction gradient doped region away from the junction termination extension region, and the distance between the multiple field-limiting rings and the junction gradient doped region gradually increases. P-type ions are doped within the junction termination extension region, the junction gradient doped region, and the multiple field-limiting rings.

[0010] A trench is provided on the N-type substrate, the trench being located on the side of the field limiting ring furthest from the junction graded doping region; polysilicon is deposited in the trench;

[0011] A P-well region and a cutoff ring N+ region are disposed on the N-type substrate. The P-well region is connected to the junction termination extension region, and the cutoff ring N+ region is disposed on the side of the trench away from the field limiting ring.

[0012] An oxide layer disposed on one side surface of the N-type substrate;

[0013] A polycrystalline silicon field plate is disposed on the surface of the oxide layer away from the N-type substrate in a target region, wherein the target region is a region of a predetermined width covering the edges of the plurality of field limiting rings;

[0014] Metal layers disposed on the surface of the P-well region, on the surface of a portion of the junction terminal extension region near the P-well region, above the plurality of field limiting rings, on the surface of the N+ region of the stop ring, and on the surface of a portion of the oxide layer near the N+ region of the stop ring.

[0015] In some embodiments, the N-type substrate is an N-type substrate, and the terminal structure further includes:

[0016] An N+ type buffer layer is formed on the other side surface of the N-type substrate;

[0017] A P+ type collector region is formed on the surface of the N+ type buffer layer away from the N- type substrate;

[0018] The collector electrode is formed on the surface of the P+ type collector region away from the N+ type buffer layer.

[0019] In some embodiments, the width range of each field limiting ring is 5-12 μm.

[0020] In some embodiments, the depth of the trench ranges from 4 to 6 μm, and the width of the trench ranges from 0.6 to 2 μm.

[0021] In some embodiments, the thickness of the metal layer ranges from 3 to 5 μm.

[0022] Accordingly, this disclosure provides a method for manufacturing a termination structure of a power device, used to manufacture the termination structure of the power device as described above, the method comprising:

[0023] Provide N-type substrates;

[0024] A junction termination extension region, a junction gradient doped region, and multiple field confinement rings are formed on the N-type substrate; the junction termination extension region is connected to the junction gradient doped region, the depth of the junction gradient doped region gradually decreases along the direction away from the junction termination extension region, and the multiple field confinement rings are disposed at one end of the junction gradient doped region away from the junction termination extension region.

[0025] In the N-type substrate, a trench is formed, the trench being located on the side of the field limiting ring furthest from the junction graded doped region.

[0026] Polycrystalline silicon is deposited within the trench;

[0027] A P-well region and a cutoff ring N+ region are formed on the N-type substrate; the P-well region is connected to the junction termination extension region, and the cutoff ring N+ region is located on the side of the trench away from the field limiting ring;

[0028] An oxide layer is grown on the surface of the N-type substrate;

[0029] Remove the oxide layer corresponding to the surface of the P-well region, the central region of the plurality of field limiting rings, and the N+ region of the stop ring;

[0030] A polycrystalline silicon field plate is formed on the surface of the target region of the oxide layer; the target region is a region of a predetermined width covering the edges of the plurality of field limiting rings;

[0031] A metal layer is formed on the surface of the P-well region, the surface of a portion of the junction terminal extension region near the P-well region, above the plurality of field limiting rings, the surface of the N+ region of the stop ring, and the surface of a portion of the oxide layer near the N+ region of the stop ring.

[0032] In some embodiments, the N-type substrate is an N-type substrate, and the method further includes:

[0033] The N-type substrate is back-side thinned on the other side of the N-type substrate;

[0034] On the other side of the N-type substrate, the N-type substrate is subjected to high-concentration N-type doping to form an N+ type buffer layer;

[0035] High-concentration P-type doping is performed on the N+ type buffer layer to form a P+ type collector region;

[0036] A metal layer is deposited on the P+ type collector region to form a collector electrode.

[0037] In some embodiments, the distance between the plurality of field-limiting rings and the junction graded-doped region gradually increases; the junction terminal extension region, the junction graded-doped region, and the plurality of field-limiting rings are doped with P-type ions; the width of each field-limiting ring is in the range of 5-12 μm.

[0038] In some embodiments, the coverage range of the edges covering the plurality of field limiting rings is 0.5 to 1.5 μm.

[0039] In some embodiments, the depth of the trench ranges from 4 to 6 μm, and the width of the trench ranges from 0.6 to 2 μm.

[0040] In some embodiments, the thickness of the metal layer ranges from 3 to 5 μm.

[0041] Accordingly, this disclosure provides a chip including the terminal structure of the power device as described above.

[0042] The embodiments disclosed herein have the following advantages:

[0043] The power device termination structure of this disclosure includes an N-type substrate; a junction termination extension region, a junction gradient doped region, and multiple field-limiting rings disposed on the N-type substrate; the junction termination extension region is connected to the junction gradient doped region; the depth of the junction gradient doped region gradually decreases in the direction away from the junction termination extension region; the multiple field-limiting rings are disposed at one end of the junction gradient doped region away from the junction termination extension region, and the distance between the multiple field-limiting rings and the junction gradient doped region gradually increases; P-type ions are doped in the junction termination extension region, the junction gradient doped region, and the multiple field-limiting rings; a trench is disposed on the N-type substrate, the trench being located at the field-limiting ring farthest from the junction gradient doped region. The structure comprises: one side of a gradient-doped region; polysilicon deposited within the trench; a P-well region and a cutoff ring N+ region on an N-type substrate, the P-well region being connected to a junction termination extension region, and the cutoff ring N+ region being located on the side of the trench away from the field limiting ring; an oxide layer on the surface of the N-type substrate; a polysilicon field plate on the surface of a target region of the oxide layer, the target region being a region of a predetermined width covering the edges of multiple field limiting rings; and metal layers on the surface of the P-well region, the surface of a portion of the junction termination extension region near the P-well region, above the multiple field limiting rings, the surface of the cutoff ring N+ region, and the surface of a portion of the oxide layer near the cutoff ring N+ region. This composite termination structure, including a junction termination extension region, a junction gradient-doped region, multiple field limiting rings, a trench, and a polysilicon field plate, effectively reduces the maximum electric field strength of the chip and improves the device's breakdown voltage performance. Attached Figure Description

[0044] Figure 1 is a schematic diagram of the terminal structure of a power device according to an embodiment of the present disclosure;

[0045] Figure 2 is a schematic diagram of the terminal structure of another power device according to an embodiment of the present disclosure;

[0046] Figure 3 is a flowchart of the manufacturing steps of a power device terminal structure according to an embodiment of the present disclosure;

[0047] Figure 4 is a structural diagram of the manufacturing of a power device terminal structure according to an embodiment of the present disclosure;

[0048] Figure 5 is a structural diagram of the manufacturing of another power device terminal structure according to an embodiment of the present disclosure;

[0049] Figure 6 is a structural diagram of the manufacturing of another power device terminal structure according to an embodiment of the present disclosure;

[0050] Figure 7 is a structural diagram of the manufacturing of another power device terminal structure according to an embodiment of the present disclosure;

[0051] Figure 8 is a structural diagram of the manufacturing of another power device terminal structure according to an embodiment of the present disclosure;

[0052] Figure 9 is a structural diagram of the manufacturing of another power device terminal structure according to an embodiment of the present disclosure;

[0053] Figure 10 is an electric field intensity curve of the terminal structure of a power device according to an embodiment of the present disclosure;

[0054] Figure 11 is a concentration-dependent withstand voltage curve of a single-zone JTE terminal according to an embodiment of this disclosure;

[0055] Figure 12 is a concentration-dependent withstand voltage curve of the terminal structure of a power device according to an embodiment of the present disclosure.

[0056] Reference numerals: N-type substrate 101, junction termination extension region 102, junction gradient doped region 103, field limiting ring 104, trench 105, P-well region 106, stop ring N+ region 107, oxide layer 108, polysilicon field plate 109, metal layer 110, N+ type buffer layer 111, P+ type collector region 112, collector terminal 113. Detailed Implementation

[0057] To make the above-mentioned objectives, features and advantages of this disclosure more apparent and understandable, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0058] Power semiconductor devices are one of the core components of power electronic circuits and are widely used in automobiles, power supplies, and motors. Currently, power semiconductor devices have lateral termination structures (JTE). However, the surface implantation dose of JTE termination structures is currently low, basically on the order of 1e12. Without field protection, they are greatly affected by the charge introduced by the process line.

[0059] Modern power devices are primarily formed by connecting tens of thousands of identical cells in parallel within the source region. While the surface voltage of each cell is roughly the same, the voltage between the terminating cell and the substrate differs significantly. Measures are needed to reduce the surface electric field and improve the breakdown voltage. Modern silicon power devices generally employ a shallow planar structure. In high-voltage device design, field-limiting rings are often used to reduce the concentration of the surface electric field caused by junction curvature effects, thereby improving the breakdown voltage. However, this structure significantly increases the chip area. Furthermore, planar field-limiting rings often exhibit peak electric fields at the injection junction corners, causing degradation of the device's breakdown characteristics. To further increase the junction depth and reduce the peak electric field at the injection junction corners, trench field-limiting ring terminating structures can be used to increase the junction depth. However, trench field-limiting ring terminating structures also have drawbacks; the reduction in peak electric field increases the expansion capability of the lateral space charge region at the field-limiting ring termination, leading to an increase in the termination area.

[0060] For the termination of power devices, due to the high surface injection dose of the main junction ring (specifically on the order of 1e12 to 1e15 / cm⁻²), the breakdown location of the termination structure is at the corner of the main junction, where the electric field strength is greatest. However, in actual manufacturing processes, deviations in the injection dose from the production line equipment can affect the JTE lateral junction termination extension structure, resulting in lower concentrations. Consequently, breakdown occurs at the JTE lateral junction termination extension structure, leading to poor termination reliability and insufficient withstand voltage in the actual fabricated chip.

[0061] One of the core concepts of this disclosure is that a composite terminal structure, including a junction terminal extension region, a junction gradient doped region, multiple field confinement rings, trenches, and a polysilicon field plate, solves the problems of insufficient withstand voltage and concentration-dose sensitivity of traditional JTE terminals.

[0062] Referring to Figure 1, a schematic diagram of the terminal structure of a power device according to an embodiment of the present disclosure is shown, which may specifically include the following structure:

[0063] N-type substrate 101.

[0064] N-type substrates refer to silicon (or other semiconductor materials) doped with donor impurities (such as phosphorus, arsenic, etc.) as the base material in semiconductor device manufacturing. The donor impurities in N-type substrates provide free electrons, making the material generally negatively charged, hence the name N-type. Characteristics of N-type substrates include: high electron concentration (due to the donor impurities, they have a high concentration of free electrons, making electrons the majority carriers); low hole concentration (due to the high electron concentration, the hole (positively charged carrier) concentration is relatively low, making them minority carriers); and high conductivity (due to the presence of free electrons, N-type substrates have high conductivity, making them suitable for applications requiring high conductivity.

[0065] The N-type substrate 101 includes a junction termination extension region 102, a junction gradient doped region 103, and a plurality of field confinement rings 104. The junction termination extension region 102 is connected to the junction gradient doped region 103. The depth of the junction gradient doped region 103 gradually decreases in the direction away from the junction termination extension region 102. The plurality of field confinement rings 104 are located at one end of the junction gradient doped region 103 away from the junction termination extension region 102, and the distance between the plurality of field confinement rings 104 and the junction gradient doped region 103 gradually increases. P-type ions are doped in the junction termination extension region 102, the junction gradient doped region 103, and the plurality of field confinement rings 104.

[0066] The junction termination extension region 102 is a key technology for improving the breakdown voltage performance of semiconductor devices. By introducing a lightly doped extension region at the edge of the PN junction, a buffer layer is formed, effectively reducing the electric field concentration at the PN junction edge and improving the device's breakdown voltage capability. At the edge of the PN junction, the electric field is usually concentrated in a small area, leading to excessively high local electric field strength, which can easily cause breakdown. Introducing a lightly doped extension region at the PN junction edge makes the electric field distribution more uniform, avoiding the problem of excessively high local electric fields. Through the buffering effect of the extension region, the device's breakdown voltage capability is significantly enhanced, enabling it to withstand higher reverse voltages, effectively improving the device's breakdown voltage while reducing leakage current; it also reduces sensitivity to doping concentration, making the device performance more stable.

[0067] The gradient doped region 103 optimizes the electric field distribution by introducing a gradient doping concentration distribution in the PN junction region, thereby improving the device's breakdown voltage performance. VLD (Variable Latticed Doping) is a special gradient doping technique that further optimizes the electric field distribution by precisely controlling the change in doping concentration, reducing the maximum electric field strength, and improving the device's breakdown voltage capability. In traditional abrupt junctions, the doping concentration on both sides of the PN junction is abrupt, causing the electric field to concentrate at the junction edge, which easily leads to breakdown. By introducing a gradient doped region, the doping concentration gradually changes from one side to the other, resulting in a more uniform electric field distribution. This avoids the problem of excessively high local electric fields, effectively disperses the electric field, reduces the maximum electric field strength, and thus improves the device's breakdown voltage. By optimizing the doping distribution, the device's breakdown voltage capability is significantly enhanced. Gradient doping technology, through structural optimization, reduces the sensitivity to doping concentration, making the device performance more stable. VLD technology allows the doping concentration to gradually change in the junction region, forming a smooth doping gradient. The change in doping concentration can be achieved through processes such as ion implantation and diffusion. By precisely controlling the doping gradient, the electric field distribution becomes more uniform, the maximum electric field strength is reduced, and the breakdown voltage capability of the device can be significantly improved.

[0068] The Field Limiting Ring (FLR) 104 introduces a series of ring-shaped doped regions at the edge of the PN junction of a device, forming an electric field confinement structure. This effectively reduces the electric field concentration at the PN junction edge, improving the device's breakdown voltage. The working principle of the FLR is as follows: At the edge of the PN junction, the electric field is usually concentrated in a small area, leading to excessively high local electric field strength and potential breakdown. By introducing a series of ring-shaped doped regions at the PN junction edge, the electric field distribution becomes more uniform, avoiding the problem of excessively high local electric fields. Through the buffering effect of the ring-shaped doped regions, the device's breakdown voltage is significantly enhanced, enabling it to withstand higher reverse voltages. The core of the FLR is the introduction of a series of ring-shaped doped regions at the PN junction edge. These regions typically have the opposite doping type to the substrate and usually consist of multiple ring-shaped doped regions, forming a multi-level structure. The doping concentration and width of each ring-shaped doped region gradually change, forming a buffer layer that further optimizes the electric field distribution.

[0069] A trench 105 is provided on the N-type substrate 101, the trench 105 is provided on the side of the field limiting ring 104 furthest from the junction graded doped region 103 away from the junction graded doped region 103; polysilicon is deposited in the trench 105.

[0070] A P-well region 106 and a cutoff ring N+ region 107 are provided on the N-type substrate 101. The P-well region 106 is connected to the junction termination extension region 102, and the cutoff ring N+ region 107 is provided on the side of the trench 105 away from the field limiting ring 104.

[0071] The P-well region 106 is a region formed by implanting P-type impurities (such as boron) into an N-type substrate. It is used to isolate and construct NMOS devices. In CMOS processes, the P-well region is used to isolate NMOS transistors and avoid interference between different transistors. The P-well region isolates the NMOS device from the N-type substrate, forming a local P-type region. The source and drain of the NMOS transistor can be formed in the P-well region. These regions are usually N-type doped. The P-well region and the N-type source and drain regions form a PN junction, which constitutes the basic structure of the NMOS transistor. This can reduce the formation of parasitic PNP transistors, thereby reducing parasitic effects and improving device performance.

[0072] The N+ region of the stop ring (GR) is a termination technology used to improve the breakdown voltage performance of semiconductor devices. The N+ region refers to the N-type region with a high doping concentration, which is usually used to construct the conductive channel or termination structure of the device. The working principle of the stop ring is as follows: In the edge region of the PN junction, the electric field is usually concentrated in a small area, resulting in excessively high local electric field strength, which can easily lead to breakdown. The stop ring introduces a series of ring-shaped doped regions at the edge of the PN junction to make the electric field distribution more uniform and avoid the problem of excessively high local electric field. Through the buffering effect of the ring-shaped doped regions, the breakdown voltage of the device is significantly enhanced, and it can withstand higher reverse voltages. It can effectively improve the breakdown voltage of the device, while reducing leakage current and reducing sensitivity to doping concentration, making the device performance more stable.

[0073] An oxide layer 108 is provided on the surface of the N-type substrate 101.

[0074] Oxide layer 108 is the ILD (Interlayer Dielectric) oxide layer region. The functions of the ILD oxide layer region are: to isolate the electrical connection between different metal layers, prevent short circuits and leakage, and to ensure electrical insulation between the layers by filling the gaps between the metal layers. The ILD oxide layer region provides mechanical support for the metal wiring of the chip and prevents physical contact between the metal layers. The high hardness and stability of the oxide layer help protect the chip structure. The ILD oxide layer region achieves surface planarization through chemical mechanical polishing, providing a smooth surface for subsequent processes (such as metal wiring) and protecting the underlying devices and metal wiring from environmental influences (such as moisture, contaminants, etc.).

[0075] A polysilicon field plate 109 is disposed on the surface of the target region of the oxide layer 108, wherein the target region is a region of a predetermined width covering the edges of the plurality of field limiting rings 104. The polysilicon field plate 109 can effectively reduce the electric field concentration phenomenon at the edge of the PN junction and improve the voltage withstand capability of the device.

[0076] A metal layer 110 is disposed on the surface of the P-well region 106, the surface of the junction termination extension region 102 near the P-well region 106, above the plurality of field limiting rings 104, the surface of the stop ring N+ region 107, and the surface of the oxide layer 108 near the stop ring N+ region 107. The metal layer 110 disposed on the surface of the P-well region 106 and the surface of the junction termination extension region 102 near the P-well region 106 is a front metal layer, which can form an ohmic contact with Si (silicon).

[0077] The power device termination structure of this disclosure includes an N-type substrate; a junction termination extension region, a junction gradient doped region, and multiple field-limiting rings disposed on the N-type substrate; the junction termination extension region is connected to the junction gradient doped region; the depth of the junction gradient doped region gradually decreases away from the junction termination extension region; the multiple field-limiting rings are disposed at one end of the junction gradient doped region away from the junction termination extension region, and the distance between the multiple field-limiting rings and the junction gradient doped region gradually increases; the junction termination extension region, the junction gradient doped region, and the multiple field-limiting rings are doped with P-type ions; and a trench is disposed on the N-type substrate, the trench being located at the field-limiting ring furthest from the junction gradient doped region. The trench comprises: one side of the variable doping region; polysilicon deposited within the trench; a P-well region and a cutoff ring N+ region disposed on the N-type substrate, the P-well region being connected to the junction termination extension region, and the cutoff ring N+ region being disposed on the side of the trench away from the field limiting ring; an oxide layer disposed on the surface of the N-type substrate; a polysilicon field plate disposed on the surface of a target region of the oxide layer, the target region being a region of a predetermined width covering the edges of the multiple field limiting rings; and metal layers disposed on the surface of the P-well region, the surface of a portion of the junction termination extension region near the P-well region, above the multiple field limiting rings, the surface of the cutoff ring N+ region, and the surface of a portion of the oxide layer near the cutoff ring N+ region. Through this composite termination structure including a junction termination extension region, a junction gradient doping region, multiple field limiting rings, a trench, and a polysilicon field plate, the maximum electric field strength of the chip can be effectively reduced, and the device's withstand voltage performance can be improved.

[0078] Referring to Figure 2, in this embodiment of the disclosure, the N-type substrate 101 is an N-type substrate, and the terminal structure further includes:

[0079] An N+ type buffer layer 111 is formed on the other side of the N-type substrate.

[0080] The N-type substrate 101 is a lightly doped N-type material with high resistivity and low carrier concentration. The N+ type buffer layer 111 is a heavily doped N-type material with low resistivity and high carrier concentration. Introducing an N+ type buffer layer on the N-type substrate can optimize the electric field distribution and reduce the electric field concentration at the edge of the PN junction. The N+ type buffer layer 111 can effectively disperse the electric field and reduce the maximum electric field strength, thereby improving the breakdown voltage of the device. By optimizing the electric field distribution, the device's withstand voltage capability is significantly enhanced.

[0081] A P+ type collector region 112 is formed on the N+ type buffer layer 111.

[0082] The P+ type collector region 112 is a highly doped P-type material with low resistivity and high hole concentration. Introducing the P+ type collector region 112 on the N+ type buffer layer 111 can optimize the electric field distribution and reduce the electric field concentration phenomenon at the edge of the PN junction.

[0083] The collector electrode 113 is formed on the P+ type collector region.

[0084] The collector terminal 113 forms an ohmic metal contact on the back side. Ohmic metal refers to a metallic material used in semiconductor device manufacturing to form a low-resistance, non-rectifying electrical contact with semiconductor materials (such as silicon). The main function of ohmic metal is to achieve low-loss current transmission between the semiconductor and external circuits, ensuring the normal operation of the device. Ohmic metals include Ni, Ti, or Ti / Ni alloys, as well as AlCu, etc.

[0085] In this embodiment, the width of each field limiting ring is between 5 and 12 μm, and all field limiting rings have the same width. For example, the injection port width of the field limiting ring is 5-12 μm, the width of the field limiting ring itself is between 3 and 8 μm, and the minimum spacing between the field limiting rings is between 8 and 13 μm. Of course, the specific dimensions can be set according to actual needs in practical applications.

[0086] In this embodiment of the disclosure, the coverage range of the edges of the plurality of field limiting rings is 0.5 to 1.5 μm. The polysilicon field plate 109 needs to cover the edges of the field limiting rings 104 by 0.5 to 1.5 μm.

[0087] In this embodiment, the depth of the trench ranges from 4 to 6 μm, and the width of the trench ranges from 0.6 to 2 μm. Of course, the specific dimensions can be set according to actual needs in practical applications.

[0088] In this embodiment of the disclosure, the thickness of the metal layer ranges from 3 to 5 μm.

[0089] Referring to Figure 3, a flowchart of a method for manufacturing a terminal structure of a power device according to an embodiment of the present disclosure is shown. This method, used to manufacture the terminal structure of the power device as described above, may specifically include the following steps:

[0090] Step 201: Provide an N-type substrate.

[0091] Referring to Figure 4, an N-type substrate is provided. The N-type substrate is a lightly doped N-type material with a low doping concentration and high resistivity.

[0092] Step 202: A junction termination extension region 102, a junction gradient doped region 103, and a plurality of field confinement rings 104 are formed on the N-type substrate 101; the junction termination extension region 102 is connected to the junction gradient doped region 103, the depth of the junction gradient doped region 103 gradually decreases in the direction away from the junction termination extension region 102, and the plurality of field confinement rings 104 are disposed at one end of the junction gradient doped region 103 away from the junction termination extension region 102.

[0093] Referring to Figure 5, based on the N-type substrate 101, a P-type JTE implantation window, a VLD gradient doping implantation window, and a field confinement ring implantation window are fabricated through growth medium masking, photolithography, and etching. Then, P-type boron ion doping is performed, with the doping ion concentration ranged from approximately 1e12 to 1e13. High-temperature annealing is then performed, with the annealing temperature around 1050-1150°C and the time around 200-350 minutes, forming a junction termination extension region 102, a junction gradient doping region 103, and multiple field confinement rings 104.

[0094] Growth dielectric masks are typically used to control the direction and area of ​​epitaxial growth. By forming a mask material on the wafer surface, a growth dielectric mask prevents the growth of epitaxial material in specific areas, thereby achieving precise control over the device structure. The functions of a growth dielectric mask include: defining the area for epitaxial growth, preventing epitaxial material from growing in unwanted areas, enabling precise control over the device structure through mask design; optimizing the electrical performance of the device, such as reducing leakage current and increasing breakdown voltage; and optimizing the electric field distribution to improve the device's breakdown voltage capability.

[0095] Photolithography is used to define micron- or nanometer-scale patterns and structures on semiconductor wafers. Photolithography technology uses photosensitive materials (photoresist) and optical systems to transfer designed patterns onto the wafer surface, thereby achieving precise control over device structures. The photolithography process involves: uniformly coating a layer of photoresist onto the wafer surface. Photoresist is a photosensitive material, and there are two types: positive and negative. With positive photoresist, the exposed areas dissolve while the unexposed areas remain; with negative photoresist, the exposed areas remain while the unexposed areas dissolve. A photomask is aligned with the wafer, ensuring precise matching between the pattern on the photomask and its position on the wafer. The photomask contains the designed pattern, which is projected onto the wafer surface using an optical system. A light source (such as ultraviolet light, deep ultraviolet light, extreme ultraviolet light, etc.) is used to expose the photoresist through the photomask. The exposed areas of the photoresist glow. A biochemical reaction alters the photoresist's solubility; the exposed wafer is then placed in a developer to dissolve the photoresist in the exposed or unexposed areas, forming a pattern. After development, a pattern corresponding to the photomask pattern remains on the wafer surface. The pattern is transferred to a material layer (such as an oxide layer or polysilicon layer) on the wafer surface through etching processes (such as dry etching or wet etching) or ion implantation. After etching or ion implantation, a structure corresponding to the photoresist pattern is formed on the wafer surface. The remaining photoresist is removed through a lift-off process (such as wet lift-off or plasma lift-off), completing the photolithography process.

[0096] After ion implantation or diffusion processes, doped atoms are usually in an inactive state. High-temperature annealing can enable doped atoms to enter lattice sites and become free charge carriers, thereby improving the conductivity of semiconductors. Ion implantation or diffusion processes introduce lattice damage (such as vacancies and interstitial atoms) into semiconductor materials. High-temperature annealing can repair these damages, restore lattice integrity, and improve device performance and reliability. In the region where metal and silicon meet, high-temperature annealing can promote the reaction between metal and silicon to form low-resistance metal silicides. Metal silicides have low contact resistance and are a key step in forming ohmic contacts. High-temperature annealing can optimize the electrical performance of devices, such as reducing leakage current, increasing breakdown voltage, and improving electric field distribution.

[0097] Step 203: A trench 105 is formed on the N-type substrate 101. The trench 105 is located on the side of the field limiting ring 104 furthest from the junction gradient doped region 103 that is away from the junction gradient doped region 103.

[0098] Referring to Figure 6, a trench 105 is fabricated on the right side of the field limiting ring using processes such as photolithography, etching, sacrificial oxidation, gate oxide oxidation, polysilicon deposition and etching, and oxide deposition.

[0099] Step 204: Deposit polycrystalline silicon in the trench.

[0100] Polysilicon deposition and etching are performed to fill the trenches with polysilicon.

[0101] Step 205: A P-well region 106 and a cutoff ring N+ region 107 are formed on the N-type substrate 101; the P-well region 106 is connected to the junction termination extension region 102, and the cutoff ring N+ region 107 is located on the side of the trench 105 away from the field limiting ring 104.

[0102] Referring to Figure 7, a P-well region 106 and a stop ring N+ region 107 are formed through processes such as growth medium masking, photolithography, etching, and ion implantation. The P-type ion concentration ranges from 5e12 to 5e13, and the N-type ion concentration ranges from 1e14 to 2e15. The region is then subjected to corresponding annealing treatment at a temperature of approximately 1050-1200℃ for approximately 40-120 minutes.

[0103] Step 206: An oxide layer 108 is grown on the surface of the N-type substrate 101, and the oxide layer 108 corresponding to the surface of the P-well region 106, the central region of the plurality of field limiting rings 104, and the N+ region of the cutoff ring 107 is removed.

[0104] Referring to Figure 8, an ILD oxide layer is deposited on the ion implantation region using a deposition process as an isolation and protection layer.

[0105] Step 207: A polycrystalline silicon field plate 109 is generated on the surface of the target area of ​​the oxide layer 108; the target area is a region of a predetermined width covering the edges of the plurality of field limiting rings.

[0106] Referring to Figure 9, a polysilicon field plate 109 of a certain length and thickness is then formed near the field limiting ring. The polysilicon field plate 109 is located on the surface of the oxide layer 108.

[0107] Step 208: A metal layer 110 is formed on the surface of the P-well region 106, on the surface of a portion of the junction terminal extension region 102 near the P-well region 106, above the plurality of field limiting rings 104, on the surface of the stop ring N+ region 107, and on the surface of a portion of the oxide layer 108 near the stop ring N+ region 107.

[0108] Referring to Figure 1, a front-side metal is formed through photolithography, metallization, and lift-off processes. Then, it is annealed at high temperature to form an ohmic contact with Si. The ohmic metal is Ni, Ti, or a Ti / Ni alloy, as well as AlCu.

[0109] The power device termination structure of this disclosure includes an N-type substrate; a junction termination extension region, a junction gradient doped region, and multiple field-limiting rings disposed on the N-type substrate; the junction termination extension region is connected to the junction gradient doped region; the depth of the junction gradient doped region gradually decreases away from the junction termination extension region; the multiple field-limiting rings are disposed at one end of the junction gradient doped region away from the junction termination extension region, and the distance between the multiple field-limiting rings and the junction gradient doped region gradually increases; the junction termination extension region, the junction gradient doped region, and the multiple field-limiting rings are doped with P-type ions; and a trench is disposed on the N-type substrate, the trench being located at the field-limiting ring furthest from the junction gradient doped region. The trench comprises: one side of the variable doping region; polysilicon deposited within the trench; a P-well region and a cutoff ring N+ region disposed on the N-type substrate, the P-well region being connected to the junction termination extension region, and the cutoff ring N+ region being disposed on the side of the trench away from the field limiting ring; an oxide layer disposed on the surface of the N-type substrate; a polysilicon field plate disposed on the surface of a target region of the oxide layer, the target region being a region of a predetermined width covering the edges of the multiple field limiting rings; and metal layers disposed on the surface of the P-well region, the surface of a portion of the junction termination extension region near the P-well region, above the multiple field limiting rings, the surface of the cutoff ring N+ region, and the surface of a portion of the oxide layer near the cutoff ring N+ region. Through this composite termination structure including a junction termination extension region, a junction gradient doping region, multiple field limiting rings, a trench, and a polysilicon field plate, the maximum electric field strength of the chip can be effectively reduced, and the device's withstand voltage performance can be improved.

[0110] In this embodiment of the disclosure, the N-type substrate 101 is an N-type substrate, and the method further includes:

[0111] The N-type substrate is back-side thinned on the other side of the N-type substrate;

[0112] On the other side of the N-type substrate, the N-type substrate is subjected to high-concentration N-type doping to form an N+ type buffer layer 111;

[0113] A high concentration of P-type doping is performed on the N+ type buffer layer 111 to form a P+ type collector region 112;

[0114] A metal layer is deposited on the P+ type collector region 112 to form a collector electrode 113.

[0115] Specifically, referring to Figure 2, the back-side process is performed. On the back side of the high-resistivity semiconductor region of the N-substrate, the chip is first thinned to a suitable thickness through a back-side thinning process. Then, N-type doping with a concentration gradient is performed twice along the lateral direction of the device to obtain a heavily doped N+ type buffer layer 111 with electric field cutoff. P-type heavy doping is performed on the buffer layer to obtain a P+ type collector region 112. Finally, a thin metal layer is deposited from the P+ type collector region 112 and led out as the collector terminal 113. An ohmic metal contact is formed on the back side. The ohmic metal is Ni, Ti or Ti / Ni alloy and AlCu.

[0116] In this embodiment, the distance between the plurality of field-limiting rings and the junction graded-doped region gradually increases; the junction terminal extension region, the junction graded-doped region, and the plurality of field-limiting rings are doped with P-type ions; the width of each field-limiting ring is 5-12 μm.

[0117] In this embodiment of the disclosure, the coverage range of the edges covering the plurality of field limiting rings is 0.5 to 1.5 μm.

[0118] In this embodiment of the disclosure, the depth of the trench ranges from 4 to 6 μm, and the width of the trench ranges from 0.6 to 2 μm.

[0119] In this embodiment of the disclosure, the thickness of the metal layer ranges from 3 to 5 μm.

[0120] Referring to Figure 10, an electric field intensity curve of the termination structure of a power device according to an embodiment of this disclosure is shown. Figure 10 shows the electric field intensity distribution along the horizontal direction of the termination for a junction-terminated extension (JTE) termination structure and the structure of this disclosure at the same length. The result is obtained by the tangent of the electric field distribution diagram after BV simulation of the device. The vertical axis represents the electric field intensity, and the horizontal axis represents the distance along the horizontal direction of the termination. The results show that, under the same injection concentration, the electric field intensity of the JTE termination is highly uneven in the horizontal direction, with the electric field concentrated near the main junction and in the JTE end region, where the maximum electric field intensity is 2.32e5V / m. The electric field intensity of the termination of this disclosure is relatively uniform in the horizontal direction, with a maximum electric field intensity of only 2.23e5V / m, which is lower than that of the former structure, resulting in better withstand voltage performance.

[0121] Referring to Figure 11, a concentration-dependent withstand voltage curve of a single-zone JTE terminal according to an embodiment of the present disclosure is shown. Referring to Figure 12, a concentration-dependent withstand voltage curve of a power device terminal structure according to an embodiment of the present disclosure is shown. The horizontal axis represents the injection concentration, and the vertical axis represents the withstand voltage value. As can be seen from Figures 11 and 12, the withstand voltage of the single-zone JTE terminal changes drastically with the change of injection concentration, and is very sensitive to concentration changes. The terminal of the present disclosure shows a relatively small change in BV (breakdown voltage) with the change of injection concentration, and its sensitivity to concentration dependence is reduced, which is beneficial to the stability of the power device terminal structure.

[0122] Based on the traditional single-region JTE terminal structure, this disclosure presents a composite terminal structure consisting of junction gradient doping, field confinement ring, field plate, and trench through a reasonable structural design. Due to the gradient doping concentration of the terminal structure, the electric field concentration phenomenon in the horizontal direction is significantly reduced, and the maximum concentrated electric field intensity is reduced by nearly 10% compared to the single-region JTE terminal structure. In addition, the terminal structure of this disclosure is less affected by changes in doping concentration, thereby improving the device's breakdown voltage stability.

[0123] By incorporating trench technology into the junction-graded doped terminal, the overall length of the terminal can be reduced, thus lowering costs. On the other hand, the voltage withstand performance of the terminal can be optimized, and problems such as electric field concentration in traditional JTE terminals can be improved, reducing leakage current and dependence on doping concentration can be addressed.

[0124] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this disclosure are not limited to the described order of actions, because according to the embodiments of this disclosure, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of this disclosure.

[0125] This disclosure provides an embodiment of a chip that includes a terminal structure of the power device as described above.

[0126] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0127] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, apparatus, or computer program products. Therefore, embodiments of this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0128] This disclosure describes embodiments of methods, terminal devices (systems), and computer program products according to embodiments of this disclosure with reference to flowchart illustrations and / or block diagrams. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0129] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0130] These computer program instructions may also be loaded onto a computer or other programmable data processing terminal equipment to cause a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable terminal equipment, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0131] While preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0132] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0133] The foregoing has provided a detailed description of the terminal structure, manufacturing method, and chip of a power device provided in this disclosure. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A termination structure of a power device, characterized by, The terminal structure includes: N-type substrate; The N-type substrate includes a junction termination extension region, a junction gradient doped region, and multiple field-limiting rings. The junction termination extension region is connected to the junction gradient doped region. The depth of the junction gradient doped region gradually decreases away from the junction termination extension region. The multiple field-limiting rings are located at the end of the junction gradient doped region away from the junction termination extension region, and the distance between the multiple field-limiting rings and the junction gradient doped region gradually increases. P-type ions are doped within the junction termination extension region, the junction gradient doped region, and the multiple field-limiting rings. A trench is provided on the N-type substrate, the trench being located on the side of the field limiting ring furthest from the junction graded doping region; polysilicon is deposited in the trench; A P-well region and a cutoff ring N+ region are disposed on the N-type substrate. The P-well region is connected to the junction termination extension region, and the cutoff ring N+ region is disposed on the side of the trench away from the field limiting ring. An oxide layer disposed on one side surface of the N-type substrate; A polycrystalline silicon field plate is disposed on the surface of the oxide layer away from the N-type substrate in a target region, wherein the target region is a region of a predetermined width covering the edges of the plurality of field limiting rings; Metal layers disposed on the surface of the P-well region, on the surface of a portion of the junction terminal extension region near the P-well region, above the plurality of field limiting rings, on the surface of the N+ region of the stop ring, and on the surface of a portion of the oxide layer near the N+ region of the stop ring.

2. The termination structure for a power device according to claim 1, wherein The N-type substrate is an N-type substrate, and the terminal structure further includes: An N+ type buffer layer is formed on the other side surface of the N-type substrate; A P+ type collector region is formed on the surface of the N+ type buffer layer away from the N- type substrate; The collector electrode is formed on the surface of the P+ type collector region away from the N+ type buffer layer.

3. The termination structure for a power device according to claim 1, wherein The width range of each field limiting ring is 5-12 μm.

4. The termination structure for a power device according to claim 1, wherein The preset width of the edge covering the plurality of field limiting rings is 0.5 to 1.5 μm.

5. The termination structure for a power device according to claim 1, wherein The depth of the trench ranges from 4 to 6 μm, and the width of the trench ranges from 0.6 to 2 μm.

6. The termination structure for a power device according to claim 1, wherein The thickness of the metal layer ranges from 3 to 5 μm.

7. A method of manufacturing a termination structure of a power device, characterized by, The method for manufacturing a termination structure for a power device as described in any one of claims 1 to 6 includes: Provide N-type substrates; A junction termination extension region, a junction gradient doped region, and multiple field confinement rings are formed on the N-type substrate; the junction termination extension region is connected to the junction gradient doped region, the depth of the junction gradient doped region gradually decreases along the direction away from the junction termination extension region, and the multiple field confinement rings are disposed at one end of the junction gradient doped region away from the junction termination extension region. In the N-type substrate, a trench is formed, the trench being located on the side of the field limiting ring furthest from the junction graded doped region. Polycrystalline silicon is deposited within the trench; A P-well region and a cutoff ring N+ region are formed on the N-type substrate; the P-well region is connected to the junction termination extension region, and the cutoff ring N+ region is located on the side of the trench away from the field limiting ring; An oxide layer is grown on the surface of the N-type substrate, and the oxide layers corresponding to the surfaces of the P-well region, the central regions of the plurality of field limiting rings, and the N+ region of the cutoff ring are removed. A polycrystalline silicon field plate is formed on the surface of the target region of the oxide layer; the target region is a region of a predetermined width covering the edges of the plurality of field limiting rings; A metal layer is formed on the surface of the P-well region, the surface of a portion of the junction terminal extension region near the P-well region, above the plurality of field limiting rings, the surface of the N+ region of the stop ring, and the surface of a portion of the oxide layer near the N+ region of the stop ring.

8. The manufacturing method of a termination structure of a power device according to claim 7, wherein The N-type substrate is an N-type substrate, and the method further includes: The N-type substrate is back-side thinned on the other side of the N-type substrate; On the other side of the N-type substrate, the N-type substrate is subjected to high-concentration N-type doping to form an N+ type buffer layer; High-concentration P-type doping is performed on the N+ type buffer layer to form a P+ type collector region; A metal layer is deposited on the P+ type collector region to form a collector electrode.

9. The manufacturing method of a termination structure of a power device according to Claim 7, wherein The distance between the plurality of field-limiting rings and the junction graded-doped region gradually increases; the junction terminal extension region, the junction graded-doped region, and the plurality of field-limiting rings are doped with P-type ions; the width of each field-limiting ring is 5-12 μm.

10. The method of manufacturing a termination structure of a power device according to claim 7, wherein The coverage range of the edges of the plurality of field limiting rings is 0.5 to 1.5 μm.

11. The method of manufacturing a termination structure of a power device according to claim 7, wherein The depth of the trench ranges from 4 to 6 μm, and the width of the trench ranges from 0.6 to 2 μm.

12. The method of manufacturing a termination structure of a power device according to Claim 7, wherein The thickness of the metal layer ranges from 3 to 5 μm.

13. A chip, characterized by The termination structure includes the power device as described in any one of claims 1-6 above.

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