A double-gate MOSFET transistor and method of forming the same
By employing N-type ion implantation and bump structures in dual-gate MOSFET transistors, the electric field strength and thermal conductivity are optimized, solving the problems of self-heating effect and floating body effect, and improving the reliability and stability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2023-03-31
- Publication Date
- 2026-06-26
AI Technical Summary
Traditional dual-gate SOI MOSFET transistors suffer from self-heating and floating body effects, which affect device reliability and stability.
A dual-gate MOSFET transistor is formed in a bump structure using an N-type ion implantation process. By forming a floating gate between the source and drain, the electric field strength and thermal conductivity are optimized using the N-type doped bump structure.
It effectively improves the floating body effect and self-heating effect, thereby enhancing the reliability and stability of the transistor.
Smart Images
Figure CN116230548B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a dual-gate MOSFET transistor and a method for forming the same. Background Technology
[0002] Compared with traditional MOS (Metal-Oxide-Semiconductor) technology, SOI (Silicon On Insulator) technology has advantages such as small parasitic capacitance, low leakage current, high speed, and small short-channel effect.
[0003] like Figure 1 As shown, a conventional dual-gate SOI MOSFET transistor has a back gate (BG), a buried oxide layer (11), and an epitaxial layer (12) sequentially formed on a substrate (10). A source (S) and a drain (D) are formed in the epitaxial layer (12) at intervals. A floating gate (FG) is formed on the epitaxial layer between the source (S) and drain (D). Both the source (S) and drain (D) are doped with N-type ions, the substrate (10) is a p-type substrate, and the epitaxial layer (12) is a p-type epitaxial layer. Conventional SOI MOSFET transistors suffer from self-heating and floating body effects, which reduce the gain of the semiconductor device and severely affect its reliability and stability. Summary of the Invention
[0004] The purpose of this invention is to provide a dual-gate MOSFET transistor and a method for forming the same, which can improve the problems of floating body effect and self-heating effect existing in conventional SOI MOSFET transistors.
[0005] To address the above problems, the present invention provides a method for forming a dual-gate MOSFET transistor, comprising the following steps:
[0006] Step S1: Provide a first substrate, on which a metal layer and a first insulating layer are sequentially formed;
[0007] Step S2: Provide a second substrate, the surface of which has two spaced-apart protrusions;
[0008] Step S3: A second insulating layer is formed on the second substrate, the second insulating layer covers the protrusion structure, and an N-type ion implantation process is performed on the protrusion structure;
[0009] Step S4: Planarize the second insulating layer and bond the first substrate and the second substrate together. At this time, the first insulating layer is disposed facing the second insulating layer.
[0010] Step S5: A source and a drain are formed on the side of the second substrate away from the first substrate, and a floating gate is formed on the second substrate between the source and the drain. The source and the drain are respectively overlapped with one of the protrusion structures to form a dual-gate MOSFET transistor.
[0011] Optionally, the N-type ion includes germanium ions.
[0012] Furthermore, the N-type ion implantation process includes: the energy range of the N-type ions is 20 KeV to 100 KeV, and the doping concentration range of the N-type ions is 1*10⁻⁶. 15 cm -3 ~9*10 15 cm -3 .
[0013] Optionally, both the first substrate and the second substrate are p-type 100-oriented silicon substrates.
[0014] Optionally, both the first insulating layer and the second insulating layer are silicon oxide layers.
[0015] Optionally, step S5 includes:
[0016] A source, a drain, and a channel are formed on the side of the second substrate away from the first substrate by an ion implantation process. The channel is located between the source and the drain, and the channel is located between the two protrusions and has an overlapping area with both of the protrusions.
[0017] A floating grid oxide layer and a floating grid are formed above the channel.
[0018] Furthermore, the source and drain are doped with N-type ions, and the channel is doped with P-type ions.
[0019] On the other hand, the present invention provides a dual-gate MOSFET transistor, including a first substrate and a second substrate, a back gate and a buried insulating layer located between the first substrate and the second substrate, the back gate being disposed close to the first substrate, the second substrate having a protrusion structure on the surface facing the first substrate, the protrusion structure being embedded in the buried insulating layer, the protrusion structure being doped with N-type ions, a source and a drain being formed on the side of the second substrate away from the first substrate, the source and drain being respectively overlapped with a protrusion structure, and a floating gate being formed on the second substrate between the source and the drain.
[0020] Optionally, the embedded insulating layer includes a first insulating layer and a second insulating layer from bottom to top, and the protruding structure is embedded in the second insulating layer.
[0021] Optionally, the N-type ion includes germanium ions.
[0022] Compared with the prior art, the present invention has the following beneficial effects:
[0023] This invention provides a dual-gate MOSFET transistor and a method for forming the same. The method includes the following steps: Step S1: Providing a first substrate, on which a metal layer and a first insulating layer are sequentially formed; Step S2: Providing a second substrate, on which two spaced-apart protrusions are formed; Step S3: Forming a second insulating layer on the second substrate, the second insulating layer covering the protrusions, and performing an N-type ion implantation process on the protrusions; Step S4: Planarizing the second insulating layer, and bonding the first and second substrates, wherein the first insulating layer faces the second insulating layer; Step S5: Forming a source and a drain on the side of the second substrate away from the first substrate, and forming a floating gate on the second substrate between the source and drain, wherein the source and drain are each overlapped with one of the protrusions, thereby forming a dual-gate MOSFET transistor. This invention optimizes the electric field strength and hole concentration of the drain through the N-type doped protrusions. The N-type ion implantation process makes the thermal conductivity of the bump structure higher than that of the first and second insulating layers, effectively improving the floating body effect and self-heating effect of the dual-gate MOSFET transistor. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of the structure of a traditional dual-gate SOI MOSFET transistor;
[0025] Figure 2 This is a schematic flowchart illustrating a method for forming a dual-gate MOSFET transistor according to an embodiment of the present invention.
[0026] Figures 3-8 This is a schematic diagram of the structure of a dual-gate MOSFET transistor during its formation process, according to an embodiment of the present invention.
[0027] Explanation of reference numerals in the attached figures:
[0028] Figure 1 middle:
[0029] 10 - Substrate; 11 - Buried oxide layer; 12 - Epitaxial layer; S - Source; D - Drain; FG - Floating gate; BG - Back gate;
[0030] Figures 3-8 middle:
[0031] 100 - First substrate; 110 - Back gate; 120 - First insulating layer; 200 - Second substrate; 210 - Metal layer; 220 - Second insulating layer; S - Source; D - Drain; FG - Floating gate. Detailed Implementation
[0032] The following will provide a more detailed description of a dual-gate MOSFET transistor and its formation method according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.
[0033] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.
[0034] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.
[0035] Figure 2 This is a schematic flowchart illustrating a method for forming a dual-gate MOSFET transistor according to this embodiment. Figure 2 As shown, this embodiment provides a method for forming a dual-gate MOSFET transistor, including the following steps:
[0036] Step S1: Provide a first substrate, on which a metal layer and a first insulating layer are sequentially formed;
[0037] Step S2: Provide a second substrate, the surface of which has two spaced-apart protrusions;
[0038] Step S3: A second insulating layer is formed on the second substrate, the second insulating layer covers the protrusion structure, and an N-type ion implantation process is performed on the protrusion structure;
[0039] Step S4: Planarize the second insulating layer and bond the first substrate and the second substrate together. At this time, the first insulating layer is disposed facing the second insulating layer.
[0040] Step S5: A source and a drain are formed on the side of the second substrate away from the first substrate, and a floating gate is formed on the second substrate between the source and the drain. The source and the drain are respectively overlapped with one of the protrusion structures to form a dual-gate MOSFET transistor.
[0041] The following combination Figures 3-8 The method for forming a dual-gate MOSFET transistor provided in this embodiment will be described in detail.
[0042] like Figure 3 As shown, step S1 is first performed to provide a first substrate 100, on which a metal layer 110 and a first insulating layer 120 are sequentially formed.
[0043] This step specifically includes:
[0044] First, a first substrate 100 is provided, which is a silicon substrate. Specifically, the first substrate 100 can be a p-type doped (100) oriented silicon substrate.
[0045] Next, a metal layer is formed on the first substrate 100 by a deposition process. The metal layer can be a metal stack, that is, the metal layer includes multiple metal films such as Ti, Ni, and Ag from bottom to top. The metal layer serves as the back gate of the subsequently formed dual-gate MOSFET transistor.
[0046] Next, a first insulating layer 120 is formed on the metal layer 110 by a deposition process, wherein the first insulating layer 120 is a silicon oxide layer, and the material used is, for example, silicon dioxide.
[0047] like Figure 4 As shown, step S2 is then performed, providing a second substrate 200 on which two spaced-apart protrusions 210 are formed.
[0048] This step specifically includes:
[0049] First, a second substrate 200 is provided, which is a silicon substrate. Specifically, the second substrate 200 can be a p-type doped (100) oriented silicon substrate.
[0050] Next, a groove of a predetermined depth and a protrusion structure 210 between adjacent grooves are formed on the second substrate 200 by an etching process.
[0051] like Figure 5 As shown, step S3 is then performed, in which a second insulating layer 220 is formed on the second substrate 200, the second insulating layer 220 covers the protrusion structure 210, and an N-type ion implantation process is performed on the protrusion structure 210.
[0052] This step specifically includes:
[0053] First, a patterned photoresist layer is formed on the second insulating layer 220, the patterned photoresist layer exposing the second insulating layer 220 above the protrusion structure 210, the second insulating layer 220 covering the protrusion structure 210, wherein the second insulating layer 220 is a silicon oxide layer, and the material used is, for example, silicon dioxide.
[0054] Next, using the patterned photoresist layer as a mask, an N-type ion implantation process is performed on the protrusion structure 210 from above the second insulating layer 220 to form an N-type doped protrusion structure 210.
[0055] The N-type ions include germanium ions, and the process parameters for N-type ion implantation include: the energy range of germanium ions is 20 KeV to 100 KeV, and the doping concentration range of germanium ions is 1*10⁻⁶. 15 cm -3 ~9*10 15 cm -3 .
[0056] In this embodiment, the subsequently formed source and drain both overlap with one of the bump structures, and both bump structures 210 overlap with the channel of the dual-gate MOSFET transistor to optimize the electric field strength and hole concentration of the drain. Furthermore, since the thermal conductivity of the silicon-germanium bump structure is higher than that of the first and second insulating layers, it effectively improves the floating body effect and self-heating effect of the dual-gate MOSFET transistor.
[0057] Next, the remaining photoresist layer is removed.
[0058] like Figures 6-7 As shown, step S4 is then performed to planarize the second insulating layer 220 and bond the first substrate 100 and the second substrate 200. At this time, the first insulating layer 120 is disposed facing the second insulating layer 220.
[0059] This step specifically includes:
[0060] like Figure 6 As shown, firstly, the second insulating layer 220 is planarized using a CMP process to eliminate residual defect areas.
[0061] like Figure 7As shown, the first insulating layer 120 is then positioned facing the second insulating layer 220, and the first substrate 100 and the second substrate 200 are bonded together. At this point, the first insulating layer 120 and the second insulating layer 220 constitute the buried insulating layer for the subsequently formed dual-gate MOSFET transistor.
[0062] Next, the second substrate 200 is thinned from the side of the second substrate 200 away from the first substrate 100.
[0063] like Figure 8 As shown, step S5 is then performed, in which a source S and a drain D are formed on the side of the second substrate 200 away from the first substrate 100, and a floating gate FG is formed on the second substrate 200 between the source S and the drain D. The source S and the drain D are respectively overlapped with a protrusion structure 210, thereby forming a dual-gate MOSFET transistor.
[0064] This step specifically includes:
[0065] First, a source electrode (S), a drain electrode (D), and a channel are formed on the side of the second substrate 200 away from the first substrate 100 using an ion implantation process. The source electrode (S) and drain electrode (D) are, for example, doped with N-type ions, and the channel is doped with P-type ions, such that the source electrode (S), drain electrode (D), and channel form a PN junction. The channel is located between the source electrode (S) and drain electrode (D). One of the protrusions 210 is located at the junction of the source electrode (S) and the channel, and another protrusion 210 is located at the junction of the drain electrode (D) and the channel, such that the channel covers portions of both protrusions 210.
[0066] Next, a floating gate oxide layer and a floating gate FG are formed above the channel.
[0067] Please see Figure 8This embodiment also provides a dual-gate MOSFET transistor, including a first substrate 100 and a second substrate 200, a buried insulating layer located between the first substrate 100 and the second substrate 200, and two protrusion structures 210 on the surface of the second substrate 200 facing the first substrate 100. The protrusion structure 210 is a silicon material layer doped with N-type ions, such as germanium, and the material of the protrusion structure 210 is the same as that of the second substrate 200, which is silicon (100). The protrusion structure 210 is embedded in the buried insulating layer. A source S, a drain D, and a channel are formed in the second substrate 200. The channel is located between the source S and the drain D, and between two protrusion structures 210, with overlapping regions with both protrusion structures 210. The source S and the drain D are each located on one of the protrusion structures 210 and overlap with one of the protrusion structures 210, so that there is a protrusion structure 210 below the junction of the source S and the channel. SiGe protrusion structures are constructed in the buried insulating layer below the PN junction of the source S and the channel, and in the buried insulating layer below the PN junction of the drain D and the channel. The introduction of the SiGe protrusion structure optimizes the electric field strength and hole concentration of the drain D. In addition, since the SiGe protrusion structure has a higher thermal conductivity than the SiO2 material buried insulating layer, it improves the floating body effect and self-heating effect of the dual-gate MOSFET transistor. The surface of the channel away from the first substrate has a floating gate FG.
[0068] In summary, this invention provides a dual-gate MOSFET transistor and a method for forming the same. The method for forming the dual-gate MOSFET transistor includes the following steps: Step S1: Providing a first substrate, on which a metal layer and a first insulating layer are sequentially formed; Step S2: Providing a second substrate, on which two spaced-apart protrusions are formed; Step S3: Forming a second insulating layer on the second substrate, the second insulating layer covering the protrusions, and performing an N-type ion implantation process on the protrusions; Step S4: Planarizing the second insulating layer, and bonding the first and second substrates, wherein the first insulating layer faces the second insulating layer; Step S5: Forming a source and a drain on the side of the second substrate away from the first substrate, and forming a floating gate on the second substrate between the source and drain, wherein the source and drain are respectively overlapped with one of the protrusions, thereby forming a dual-gate MOSFET transistor. This invention optimizes the electric field strength and hole concentration of the drain through the N-type doped protrusion structure. The N-type ion implantation process makes the thermal conductivity of the bump structure higher than that of the first and second insulating layers, effectively improving the floating body effect and self-heating effect of the dual-gate MOSFET transistor.
[0069] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.
[0070] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.
Claims
1. A method for forming a dual-gate MOSFET transistor, characterized in that, Includes the following steps: Step S1: Provide a first substrate, on which a metal layer and a first insulating layer are sequentially formed; Step S2: Provide a second substrate, the surface of which has two spaced-apart protrusions; Step S3: A second insulating layer is formed on the second substrate, the second insulating layer covers the protrusion structure, and an N-type ion implantation process is performed on the protrusion structure, wherein the N-type ions include germanium ions; Step S4: Planarize the second insulating layer and bond the first substrate and the second substrate together. At this time, the first insulating layer is disposed facing the second insulating layer. Step S5: A source and a drain are formed on the side of the second substrate away from the first substrate, and a floating gate is formed on the second substrate between the source and the drain. The source and the drain are respectively overlapped with one of the protrusion structures to form a dual-gate MOSFET transistor.
2. The method for forming a dual-gate MOSFET transistor as described in claim 1, characterized in that, The N-type ion implantation process includes: the energy range of N-type ions is 20 KeV~100 KeV, and the doping concentration range of the N-type ions is 1*10⁻⁶. 15 cm -3 ~9*10 15 cm -3 .
3. The method for forming a dual-gate MOSFET transistor as described in claim 1, characterized in that, Both the first substrate and the second substrate are p-type 100-oriented silicon substrates.
4. The method for forming a dual-gate MOSFET transistor as described in claim 1, characterized in that, Both the first insulating layer and the second insulating layer are silicon oxide layers.
5. The method for forming a dual-gate MOSFET transistor as described in claim 1, characterized in that, Step S5 includes: A source, a drain, and a channel are formed on the side of the second substrate away from the first substrate by an ion implantation process. The channel is located between the source and the drain, and the channel is located between the two protrusions and has an overlapping area with both of the protrusions. A floating grid oxide layer and a floating grid are formed above the channel.
6. The method for forming a dual-gate MOSFET transistor as described in claim 5, characterized in that, The source and drain are doped with N-type ions, and the channel is doped with P-type ions.
7. A dual-gate MOSFET transistor, fabricated using the method for forming a dual-gate MOSFET transistor as described in claim 1, characterized in that, The device includes a first substrate and a second substrate, a back gate and a buried insulating layer located between the first substrate and the second substrate, the back gate being disposed close to the first substrate, the second substrate having a raised structure on its surface facing the first substrate, the raised structure being embedded in the buried insulating layer, the raised structure being doped with N-type ions, a source and a drain being formed on the side of the second substrate away from the first substrate, the source and drain being respectively overlapped with a raised structure, and a floating gate being formed on the second substrate between the source and the drain, the N-type ions including germanium ions.
8. The dual-gate MOSFET transistor as claimed in claim 7, characterized in that, The embedded insulating layer comprises, from bottom to top, a first insulating layer and a second insulating layer, and the protruding structure is embedded in the second insulating layer.