Semiconductor device structure, preparation method therefor, and corresponding chip
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SHENZHEN UNITED BLUE OCEAN APPLIED MATERIALS TECH CO LTD
- Filing Date
- 2025-10-21
- Publication Date
- 2026-07-02
Smart Images
Figure CN2025128940_02072026_PF_FP_ABST
Abstract
Description
A semiconductor device structure, its fabrication method, and a corresponding chip Technical Field
[0001] This invention belongs to the field of semiconductor device technology, and relates to a semiconductor device structure, its fabrication method, and a corresponding chip. Background Technology
[0002] Flip chip technology is mainly divided into two categories. One is bonding with reflow solder balls. Although lead-free soldering materials are now mature, the solder becomes liquid at high temperatures, which may lead to bridging between adjacent solder bumps, making it unsuitable for fine-pitch flip chip applications. The other is bonding with non-reflowable columnar gold bumps, where the gold bumps are electrically connected to the substrate via thermoforming soldering or anisotropic conductive adhesive. Although gold bumps have excellent reliability and no bridging issues between adjacent gold bumps, the material cost of gold is very high. For chip-on-film packaging, the amount of gold used on a 12-inch wafer is approximately 0.8 grams, and for chip-on-Glass packaging, it is approximately 1.9 grams. With the rising price of gold, developing new materials to replace gold is currently a hot research topic. Considering the requirements for gold bump characteristics, such as hardness, roughness, and solderability, there are not many alternative solutions. Among them, gold-silver alloys are one of the most promising solutions for replacing gold bumps.
[0003] TWI469288B mentions electroplated gold and silver bumps. To prevent silver oxidation, the top or sides of the gold and silver bumps are electroplated or electrolessly plated with one of gold, palladium, copper, or nickel. Copper or nickel oxidizes more easily than silver. TW201044527A mentions that electroplated gold and silver bumps contain no less than 80% silver, and then a protective layer is formed on the gold and silver surface by substitution or reduction of gold to prevent silver oxidation. TW201019440A mentions that the material of the silver bumps can be selected from pure silver or silver alloys. The silver alloy of these silver bumps can contain no less than 80% silver, and then a layer of pure gold or gold alloy is plated on the surface of the silver alloy to solve the problem of anti-oxidation.
[0004] CN117542818B discovered that increasing the gold content in gold-silver bumps to over 60% can significantly improve the oxidation or sulfidation resistance of silver in the bumps. This was achieved by first preparing a gold-silver alloy substrate with a gold content of 20%–50% as a bonding layer in the same electroplating bath using a low current density, and then preparing a protective layer with a gold content of over 60% on the bump surface under a high current density. The height of the protective layer ranged from 10 to 500 nm. CN118398588B, to address potential welding defects caused by silver oxidation, proposed using electrochemical etching to selectively remove metallic silver from the bump surface, forming a nanoporous gold structure. This method avoids affecting the hardness of the bump itself and prevents welding defects.
[0005] While the above technical solutions address issues such as hardness, oxidation, or sulfidation-induced poor welding of gold and silver bumps, none address the bonding strength between the gold / silver bumps and different metal layers during manufacturing. After bump fabrication, various reliability tests are required, such as TCT (Temperature Cycle Test): -65℃ (15min) ~ 150℃ (15min), more than 350 cycles; PCT (Pressure Cooker Test): 121℃, 100% RH, 2atm, 168 hrs; THT (Temperature Humidity Test): 85℃ / 85% RH, 1000 hrs; HTST (High Temperature Storage Life Test): 150℃, 1000 hrs; LTST (Low Temperature Storage Life Test): -65℃, 1000 hrs. These tests are used to verify the bonding strength between the bump and the under bump metal (UBM). Specifically, the bump that has undergone the above reliability tests is subjected to a thrust shear test to check whether the underlying UBM layer is exposed.
[0006] Most reliability failures occur due to poor adhesion between the bump and the UBM layer; therefore, the choice of UBM material metal has a significant impact on adhesion strength. During their attempt to replace gold bumps with gold-silver alloy bumps in flip chips, the inventors discovered that if the existing UBM layer used for gold bumps is employed, the UBM layer will be exposed during thrust shear testing after high and low temperature cycling tests, leading to reliability failure. Only by passing both the aforementioned reliability tests and thrust shear tests can gold-silver alloy bumps be used as a substitute for gold bumps in flip chips. Therefore, only by solving the technical problem that gold-silver alloy bumps cannot pass the high and low temperature cycling reliability test with the existing UBM layer can gold-silver alloy bumps replace gold bumps in the flip chip field, thereby significantly reducing production costs. Technical issues
[0007] The purpose of this invention is to solve the technical problem that gold-silver alloy bumps cannot pass high and low temperature cycling reliability tests with existing UBM layers. By selecting a suitable UBM material, the gold-silver alloy bumps can pass various reliability tests, ensuring the bonding strength of the device after reliability testing. To solve this technical problem, the inventors conducted extensive theoretical analysis and experimental research, determining that the difference in the coefficient of thermal expansion between the gold-silver alloy bumps and the UBM material is the key factor, and ultimately obtained the technical solution provided by this invention, the details of which are as follows. Technical solutions
[0008] A primary aspect of this invention is to provide a semiconductor device structure comprising gold-silver alloy bumps and a UBM layer. The UBM layer consists of a seed layer and an adhesion layer. The bottom of the gold-silver alloy bumps is connected to the seed layer, and the adhesion layer is connected to the chip electrode. The difference in the coefficient of thermal expansion between the gold-silver alloy bumps and the adhesion layer is less than 9 ppm / K, where ppm is approximately 10 ppm. -6 .
[0009] Furthermore, the thickness of the gold-silver alloy bump is 5~20 μm.
[0010] Furthermore, the gold content in the gold-silver alloy bump is 10~60wt%. If the gold content is too low, the hardness, roughness, and resistance to oxidation and sulfidation of the gold-silver alloy bump will differ significantly from those of a gold bump; if the gold content is too high, firstly, the hardness will be too high, and defects such as gold nodules will easily occur, and secondly, it will be difficult to reduce costs.
[0011] When the gold content in the gold-silver alloy is 10~60wt%, in order to ensure that the difference in thermal expansion coefficient between the gold-silver alloy bump and the adhesive layer is below 9ppm / K, and to meet other performance requirements of flip chips, the adhesive layer is preferably a Ti layer, a TiN layer, or a double layer of Ti and TiN layers.
[0012] Furthermore, the thickness of the adhesion layer is 10~1000nm.
[0013] Furthermore, the seed layer is a gold layer, a silver layer, a gold-silver alloy layer, or a double layer of gold and silver.
[0014] Furthermore, the thickness of the seed layer is 10~1000nm.
[0015] Another aspect of the present invention is to provide a method for fabricating the above-described semiconductor device structure, comprising the following steps:
[0016] S1 is selected to ensure that the difference in the coefficient of thermal expansion between the gold-silver alloy bumps and the adhesive layer is below 9ppm / K;
[0017] S2 uses physical vapor deposition (e.g., evaporation or magnetron sputtering) to sequentially prepare an adhesion layer and a seed layer on a chip wafer to obtain a UBM layer;
[0018] S3 Coating photoresist and exposing the area to be electroplated;
[0019] S4 Gold and silver alloy bumps are prepared by electroplating using a gold and silver plating solution;
[0020] S5 removes excess photoresist and UBM layer.
[0021] The key to the preparation method provided by this invention lies in selecting a suitable material to prepare the adhesion layer, ensuring that the difference in the coefficient of thermal expansion between the gold-silver alloy bump and the adhesion layer is below 9 ppm / K. Specific operations such as physical vapor deposition for preparing the adhesion layer and seed layer, coating with photoresist, and electroplating for preparing the gold-silver alloy bump can all employ existing technical solutions.
[0022] Another aspect of the present invention is to provide a chip, said chip comprising the semiconductor device structure provided by the present invention.
[0023] Furthermore, the chip can be a liquid crystal driver chip, a memory chip, a logic chip, or a power chip. Beneficial effects
[0024] The technical solution provided by this invention solves the technical problem that gold-silver alloy bumps and existing UBM layers cannot pass high and low temperature cycle reliability tests. The obtained semiconductor device structure and corresponding chip can pass various reliability tests, making it feasible to replace pure gold bumps with gold-silver alloys, thereby significantly reducing the production cost of flip chips. Attached Figure Description
[0025] Figure 1 is a schematic diagram of the semiconductor device structure provided by the present invention.
[0026] Reference numerals: 101-Wafer substrate, 102-Electrode, 103-Passivation layer, 104-Adhesion layer, 105-Seed layer, 106-Gold-silver alloy bump.
[0027] Figure 2 is an optical photograph of the semiconductor device structures of Example 1 and Comparative Example 1 after thrust shearing following TCT testing.
[0028] Figure 3 shows the SEM analysis results of the semiconductor device structures of Example 1 and Comparative Example 1 after thrust shearing after TCT testing. Figure a shows the overall morphology of Example 1, Figure b shows the magnification of the boxed area in Figure a, Figure c shows the FIB slice of Figure b; Figure d shows the overall morphology of Comparative Example 1, Figure e shows the magnification of the boxed area in Figure d, and Figure f shows the EDX element analysis of point 1 in Figure e.
[0029] Figure 4 shows the SEM analysis results of the semiconductor device structures of Example 1 and Comparative Example 1 after TCT testing without thrust shearing. Embodiments of the present invention
[0030] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention. Example 1
[0031] A semiconductor device structure, as shown in Figure 1, includes a gold-silver alloy bump 106 and a UBM layer. The UBM layer consists of a seed layer 105 and an adhesion layer 104. The bottom of the gold-silver alloy bump 106 is connected to the seed layer 105, and the adhesion layer 104 is connected to the chip electrode 102. The overall chip structure is as follows: the bottom layer is a silicon-based wafer substrate 101 on which transistors have been deployed; above this is a conductive aluminum electrode 102; on both sides of the aluminum electrode are passivation layers 103, whose main function is to protect and isolate the circuit. The passivation layer material can be silicon dioxide or silicon nitride, etc., and is prepared by vapor deposition or magnetron sputtering; above the aluminum electrode 102 is the UBM layer, which includes an adhesion layer 104 and a seed layer 105. The adhesion layer 104 is made of titanium and has a thickness of 50 nm; the seed layer 105 is made of gold and has a thickness of 30 nm; the gold-silver alloy bump 106 has a gold content of 18 wt% and a thickness of 9 μm.
[0032] The specific fabrication process is as follows. On the completed 12-inch LCD driver chip wafer, a 50nm Ti adhesion layer was first sputtered using magnetron sputtering. The sputtering conditions were: vacuum degree of 0.003 Torr, bias voltage of 90V, power of 5kW, and sputtering time of 200s. Then, in the same cavity, an Au target was switched to sputter a 30nm Au seed layer. The sputtering conditions were: vacuum degree of 0.003 Torr, bias voltage of 60V, power of 2kW, and sputtering time of 150s. Nitrogen gas was introduced to cool the wafer before it was removed. JSR 121 photoresist was spin-coated onto the wafer to expose the area to be electroplated. The photoresist height was 20μm. After plasma cleaning, a gold-silver conductive metal layer was prepared using a gold-silver alloy electroplating solution. The plating solution temperature was 30℃, pH was 9.0, current density was 0.5ASD, and electroplating time was 36min. Finally, the photoresist and UBM layer were removed. Example 2
[0033] A semiconductor device structure is identical in overall structure to that in Example 1, except that the thickness of the adhesion layer is 150 nm and the thickness of the seed layer is 50 nm. Example 3
[0034] A semiconductor device structure is the same as that in Example 1, except that the thickness of the adhesion layer is 300 nm and the thickness of the seed layer is 100 nm. Example 4
[0035] A semiconductor device structure is identical in overall structure to that of Example 1, except that the thickness of the adhesion layer is 500 nm and the seed layer is made of silver with a thickness of 300 nm. Example 5
[0036] A semiconductor device structure is identical in overall structure to that of Example 1, except that the thickness of the adhesion layer is 750 nm and the seed layer is made of silver with a thickness of 500 nm. Example 6
[0037] A semiconductor device structure is identical to that in Example 1, except that: the thickness of the adhesion layer is 1000 nm; the seed layer is made of a gold-silver alloy and has a thickness of 1000 nm; and the gold content of the gold-silver alloy bumps is 10 wt%. Example 7
[0038] A semiconductor device structure is identical in overall structure to that of Example 1, except that the material of the adhesion layer is titanium nitride with a thickness of 100 nm; and the gold content of the gold-silver alloy bumps is 32 wt%. Example 8
[0039] A semiconductor device structure is identical to that in Example 1, except that the adhesion layer is made of titanium nitride with a thickness of 100 nm; the seed layer is made of silver; and the gold content of the gold-silver alloy bumps is 50 wt%. Example 9
[0040] A semiconductor device structure is identical to that in Example 1, except that the adhesion layer is a double-layer structure of titanium layer and titanium nitride layer, wherein the titanium layer is connected to the gold-silver alloy bumps, and the thickness of both the titanium layer and the titanium nitride layer is 50 nm; the thickness of the seed layer is 80 nm; and the gold content of the gold-silver alloy bumps is 32 wt%. Example 10
[0041] A semiconductor device structure is identical to that in Example 1, except that the adhesion layer is a double-layer structure of titanium nitride layer and titanium layer, wherein the titanium nitride layer is connected to the gold-silver alloy bump, and the thickness of both the titanium nitride layer and the titanium layer is 100 nm; the thickness of the seed layer is 80 nm; and the gold content of the gold-silver alloy bump is 50 wt%.
[0042] Comparative Example 1
[0043] A semiconductor device structure is identical in overall structure to that of Example 1, except that the material of the adhesion layer is TiW.
[0044] Comparative Example 2
[0045] A semiconductor device structure, the overall structure of which is the same as that of Comparative Example 1, except that the bumps are made of pure gold. Example 11
[0046] The semiconductor device structures of Example 1 and Comparative Example 1 were subjected to TCT, LTST, PCT, HTST and THT tests, respectively. The semiconductor device structure of Comparative Example 2 was subjected to TCT test. The test results are shown in Table 1.
[0047] Table 1. Test results under different reliability test conditions
[0048]
[0049] As shown in Table 1, the semiconductor device structure of Example 1 passed all reliability tests, the semiconductor device structure of Comparative Example 1 passed most reliability tests but failed the TCT test, and Comparative Example 2 passed the TCT test. Therefore, the key to passing the TCT test lies in the matching of the bumps and the adhesive layer: the pure gold bumps of the prior art can match the TiW adhesive layer of the prior art (Comparative Example 2); the gold-silver alloy bumps cannot match the TiW adhesive layer of the prior art (Comparative Example 1); and the gold-silver alloy bumps can match the Ti adhesive layer (Example 1).
[0050] As can be seen from Figure 2, after the TCT test, the semiconductor device structure of Comparative Example 1 underwent a push-shear test, and a flat interface was clearly exposed on the right side of the bump. This was caused by the poor bonding force between the TiW layer and the upper alloy bump, which exposed the underlying TiW layer after the push-shear test. The semiconductor device structure of Example 1 did not expose the UBM layer after the TCT test and could pass the high and low temperature reliability test.
[0051] To further confirm the above experimental results, SEM analysis was performed on the samples subjected to thrust shear after TCT testing, as shown in Figure 3. In Example 1, the gold-silver alloy layer fractured at the edge after thrust shear showed a honeycomb pattern, indicating ductile fracture. The interface structure showed that the thinnest part was 242 nm. Since the Ti layer was only 50 nm and the Au layer was 30 nm, it can be concluded that the UBM structure layer was not exposed. In Comparative Example 1, it can be clearly seen that the UBM structure layer was exposed after thrust shear. EDX elemental analysis showed that W and Ti were the main elements, which are the UBM adhesion layer.
[0052] Figure 4 shows cross-sections of the interfaces of the semiconductor device structures of Example 1 and Comparative Example 1 after TCT testing, before push shearing. When Ti is used as the UBM layer, there is no separation at the interface between the metal layers. However, when TiW is used as the UBM layer, significant separation occurs between the gold seed layer and the underlying TiW layer (circled in the figure). This indicates that the interface separation during high and low temperature cycling is closely related to the material properties.
[0053] Returning to the results shown in Table 1, when the UBM layer is TiW, the gold and silver bumps can pass the LTST low temperature test (-65℃), PCT high temperature, high pressure and high humidity test (121℃), HTST high temperature test (150℃), and THT (85℃) high temperature and high humidity test, but cannot pass the TCT high and low temperature thermal cycling test (-65℃~150℃). The inventors therefore thought that the failure of the TCT test may be due to the difference in thermal expansion coefficients between different metals.
[0054] The inventors attempted to explain the above phenomena using the theory of thermal expansion. When the thermal expansion coefficients of the electroplated metal bump conductive layer and the UBM layer adhesion layer differ significantly, the deformation mismatch of the materials increases further with thermal shock, leading to fracture at the edges. Table 2 lists the thermal expansion coefficients of different metals. The thermal expansion coefficient of alloys is calculated using a simple approximation. For example, in the UBM layer Ti1W9, where Ti atoms account for 10% and W atoms for 90%, the thermal expansion coefficient of Ti1W9 can be calculated based on the thermal expansion coefficient of Ti (10.8) and W (4.5). That is, the thermal expansion coefficient of Ti1W9 is 10.8 × 0.1 + 4.5 × 0.9 = 5.1.
[0055] Table 2. Coefficients of thermal expansion of different metals and differences in coefficients of thermal expansion between different metal pairs.
[0056]
[0057] For the currently mature gold bump process in liquid crystals, Ti1W9 is used as the adhesive layer for the UBM (Underlying Microblading). Table 1 shows that it can pass high and low temperature cycling tests. Therefore, the difference in thermal expansion coefficients between pure gold and Ti1W9, 9.07, is used as a reference value. A thermal expansion coefficient between the electroplated metal bump and the UBM that is higher than this value indicates a risk of interface failure during high and low temperature testing. Table 2 shows that when AuAg alloy is used as the bump and the UBM adhesive layer is a TiW layer, the difference in thermal expansion coefficients can reach 12.25~13.31, which is much higher than the difference in thermal expansion coefficients between the Au-TiW metal pair, thus causing sample failure. When the UBM adhesive layer material is Ti or TiN, the difference in thermal expansion coefficients between the electroplated gold / silver bump and the UBM layer is lower than the reference value for Au-Ti1W9, which shows promise in solving the problem of interface failure during high and low temperature testing. When the UBM adhesive layer is TiW or Ta, due to its higher value than the reference value for Au-Ti1W9, there is a risk of interface failure after high and low temperature cycling tests.
[0058] Table 2 also shows that when the gold content in the gold-silver alloy bumps is high, the coefficient of thermal expansion of the AuAg alloy is low. For example, the coefficient of thermal expansion of Au2Ag8 is 18.4, while that of Au4Ag6 is 17.4. Since the coefficient of thermal expansion of the gold-silver bumps is higher than that of the UBM adhesion layer, increasing the gold content in the gold-silver bumps can reduce the difference in the coefficient of thermal expansion between the gold-silver alloy and the UBM layer, which is beneficial to reducing the risk of interface failure.
[0059] It is feasible to use gold, silver, or a combination of both as the seed layer in UBM, because the hardness of the plating is reduced after annealing following electroplating. During this process, diffusion occurs between the seed layer and the electroplated gold-silver alloy, thus ensuring sufficient adhesion between the seed layer and the electroplated gold-silver alloy.
[0060] The semiconductor device structures of Examples 1-10 were subjected to TCT tests (-65℃ (15min) ~ 150℃ (15min), 350 cycles), and the test results are shown in Table 3.
[0061] Table 3. Thrust-shear test results of semiconductor device structures after TCT testing in Examples 1-10
[0062]
[0063] As can be seen from Table 3, when the adhesion layer of UBM uses Ti or TiN of different thicknesses or a stack of both, the seed layer is Au or Ag of different thicknesses or a gold-silver alloy, and the bumps are gold-silver alloys of different proportions. The thrust shear test results after TCT test do not expose the UBM layer.
[0064] To address the technical problem that gold-silver alloy bumps and existing UBM layers cannot pass high and low temperature cycling reliability tests, based on the technical solution of this invention, those skilled in the art can further select the materials for the adhesion layer and seed layer. Any adhesion layer and seed layer material that ensures the difference in thermal expansion coefficients between the gold-silver alloy bumps and the adhesion layer is below 9 ppm / K, while simultaneously meeting other physicochemical performance requirements of the UBM layer, is suitable.
[0065] Although embodiments of the present invention have been shown and described above, it is understood that these embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and alterations to the above embodiments within the scope of the present invention without departing from its principles and spirit. The scope of protection of the present invention is defined by the claims and their equivalents. Industrial applicability
[0066] The technical solution provided by this invention solves the technical problem that gold-silver alloy bumps and existing UBM layers cannot pass high and low temperature cycle reliability tests. The obtained semiconductor device structure and corresponding chip can pass various reliability tests and have broad application prospects in the field of semiconductor devices.
Claims
1. A semiconductor device structure comprising gold-silver alloy bumps and a UBM layer, wherein the UBM layer consists of a seed layer and an adhesion layer, the bottom of the gold-silver alloy bumps is connected to the seed layer, and the adhesion layer is connected to the chip electrode, characterized in that, The difference in the coefficient of thermal expansion between the gold and silver alloy bumps and the adhesive layer is less than 9 ppm / K.
2. The semiconductor device structure according to claim 1, characterized in that, The thickness of the gold-silver alloy bump is 5~20 μm.
3. The semiconductor device structure according to claim 1, characterized in that, The gold content in the gold-silver alloy bump is 10~60wt%.
4. The semiconductor device structure according to claim 3, characterized in that, The adhesion layer is a Ti layer, a TiN layer, or a combination of a Ti layer and a TiN layer.
5. The semiconductor device structure according to claim 1, characterized in that, The thickness of the adhesion layer is 10~1000nm.
6. The semiconductor device structure according to claim 1, characterized in that, The seed layer is a gold layer, a silver layer, a gold-silver alloy layer, or a double layer of gold and silver.
7. The semiconductor device structure according to claim 1, characterized in that, The thickness of the seed layer is 10~1000nm.
8. The method for fabricating a semiconductor device structure according to any one of claims 1-7, characterized in that, Includes the following steps: S1 is selected to ensure that the difference in the coefficient of thermal expansion between the gold-silver alloy bumps and the adhesive layer is below 9ppm / K; S2 uses physical vapor deposition to sequentially prepare an adhesion layer and a seed layer on a chip wafer to obtain a UBM layer; S3 Coating photoresist and exposing the area to be electroplated; S4 Gold and silver alloy bumps are prepared by electroplating using a gold and silver plating solution; S5 removes excess photoresist and UBM layer.
9. A chip, characterized in that, The chip includes the semiconductor device structure according to any one of claims 1-7.
10. The chip according to claim 9, characterized in that, The chip can be a liquid crystal driver chip, a memory chip, a logic chip, or a power chip.