Final polishing method for wafer, and polished wafer

Abstract

A final polishing method for a wafer, and a polished wafer. In the final polishing method for a wafer, the wafer comprises a first layer to be removed and a second layer to be removed, which are adjacent to each other and made of different materials. The final polishing method comprises: performing first polishing on a wafer, so as to remove a part of a first layer to be removed; and performing second polishing on the wafer that has been subjected to the first polishing, so as to remove the remaining part of said first layer and a second layer to be removed, wherein the material removal rate of the second polishing is less than the material removal rate of the first polishing.

Description

Final polishing methods for wafers and polishing wafers

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411949921.2, filed in China on December 27, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to a final polishing method for wafers and a polished wafer. Background Technology

[0004] As a common technique in semiconductor wafer manufacturing, back-sealing primarily utilizes vapor deposition to form a back-sealing film, such as a polysilicon thin film, on the back side of the wafer to improve wafer quality. Back-sealing is particularly suitable for heavily doped wafers, as polysilicon thin films possess excellent gettering capabilities, effectively preventing dopant diffusion. However, in practice, some equipment may, due to design or technological limitations, not be able to ensure that the film is formed only on the back side of the wafer, and may instead form a film on the front side as well.

[0005] Final wafer polishing, a critical process stage in wafer surface treatment, aims to remove damage layers and surface irregularities introduced by previous processing steps on the wafer's front side, ensuring the wafer surface achieves the required smoothness and flatness. With the advancement of semiconductor technology, wafer diameters are continuously increasing. To meet the demands of manufacturing higher-performance devices, the final wafer polishing process needs to achieve even more stringent flatness standards.

[0006] For wafers where a thin film layer has formed on the damaged layer on the front side due to the back-sealing process, the thin film layer outside the damaged layer needs to be removed before the damaged layer can be removed during the final polishing process. In this case, the conventional polishing process used to directly remove the damaged layer has poor control over the surface morphology of such wafers, leading to a tendency for the wafer's flatness to deteriorate during the final polishing stage, especially resulting in a deterioration of the wafer's nanotopography. Summary of the Invention

[0007] This section provides a general overview of this disclosure, rather than a full disclosure of the entire scope or all features of this disclosure.

[0008] The purpose of this disclosure is to provide a final polishing method for wafers that can avoid or mitigate the deterioration of wafer flatness during the final polishing process.

[0009] To achieve the above objectives, according to a first aspect of this disclosure, a final polishing method for a wafer is provided. The wafer includes a first layer to be removed and a second layer to be removed, the first layer to be removed and the second layer to be removed being adjacent to each other and made of different materials. The final polishing method for the wafer includes:

[0010] The wafer is first polished to remove a portion of the first layer to be removed; and

[0011] The wafer that has undergone the first polishing is then subjected to a second polishing to remove the remaining portion of the first layer to be removed and the second layer to be removed, wherein the material removal rate of the second polishing is less than the material removal rate of the first polishing.

[0012] In some embodiments, the final polishing method for a wafer may further include a third polishing of the wafer after the second polishing, wherein the material removal rate of the third polishing is less than that of the second polishing.

[0013] In some implementations, the second polishing may be performed with a second target removal thickness, and the third polishing may be performed with a third target removal thickness, wherein the second target removal thickness may be greater than the third target removal thickness.

[0014] In some implementations, the ratio of the single-crystal silicon removal thickness in the second target removal thickness to the third target removal thickness can be 6:1 to 4:1.

[0015] In some implementations, the sum of the single-crystal silicon removal thickness in the second target removal thickness and the third target removal thickness can be greater than or equal to 150% of the thickness of the damaged layer of the wafer to be first polished.

[0016] In some embodiments, the first polishing can use a first polishing liquid containing an alkaline additive, and the second polishing can use a second polishing liquid containing an alkaline additive. The proportion of the alkaline additive in the second polishing liquid can be less than the proportion of the alkaline additive in the first polishing liquid.

[0017] In some embodiments, the first polishing can use a first polishing liquid containing an alkaline additive, the second polishing can use a second polishing liquid containing an alkaline additive, and the third polishing can use a third polishing liquid without an alkaline additive, wherein the proportion of alkaline additive in the second polishing liquid can be less than the proportion of alkaline additive in the first polishing liquid.

[0018] In some implementations, the thickness of a portion of the first layer to be removed can be 85% to 95% of the total thickness of the first layer to be removed.

[0019] In some implementations, the material of the first layer to be removed can be polycrystalline silicon, and the material of the second layer to be removed can be monocrystalline silicon.

[0020] According to a second aspect of this disclosure, a polished wafer is provided, which is obtained using a final polishing method for wafers according to a first aspect of this disclosure, wherein the nano 2mm × 2mm of the polished wafer is less than 15nm.

[0021] According to the above technical solution, for a wafer with a first layer to be removed and a second layer to be removed that are adjacent to each other and made of different materials, two polishing steps with different intensity levels are performed sequentially on the first layer to be removed. Specifically, by switching to a second polishing step with a lower material removal rate before the first polishing step with a higher material removal rate reaches the interface between the first layer to be removed and the second layer to be removed, the remaining part of the first layer to be removed, including the interface, can be removed in a relatively gentler manner. This avoids or reduces the flatness deterioration of the wafer in the final polishing process, so that the polished wafer obtained after final polishing has good surface flatness, such as good nano-morphology. Attached Figure Description

[0022] The features and advantages of embodiments of the present disclosure will become more readily understood from the following description with reference to the accompanying drawings. The drawings are not drawn to scale and some features may be enlarged or reduced to show details of specific components. In the drawings:

[0023] Figure 1 is a flowchart of a final polishing method for a wafer according to an embodiment of the present disclosure.

[0024] Figure 2 is a schematic diagram of the final polishing apparatus according to an embodiment of the present disclosure.

[0025] Figure 3 is a schematic diagram of a wafer to be finally polished using the final polishing method for wafers according to an embodiment of the present disclosure.

[0026] Figure 4 shows the test results of nanomorphic values ​​within a 2 mm × 2 mm dimension obtained by taking different thickness removal percentages in the first polishing using the final polishing method for wafers according to an embodiment of the present disclosure.

[0027] Figure 5 shows the test results of the nano-morphology values ​​of the polished wafers obtained by taking 85% to 95% of the thickness removal percentage in the first polishing in Figure 4 within a size of 2 mm × 2 mm.

[0028] In the accompanying drawings, the same or corresponding technical features or components are represented by the same or corresponding reference numerals. Detailed Implementation

[0029] The present disclosure will now be described in detail with reference to the accompanying drawings and exemplary embodiments. It should be noted that the following detailed description of the present disclosure is for illustrative purposes only and is not intended to limit the scope of the disclosure.

[0030] Before the final polishing stage, wafers are generally obtained through the following processes: First, single-crystal silicon rods are pulled using the Czochralski (CZ) method in a crystal pulling furnace. Then, the single-crystal silicon rods are cut into multiple single-crystal silicon rod segments. Subsequently, each single-crystal silicon rod segment is cut into wafer-like sheets, for example, using multi-wire dicing. Afterward, the wafers undergo other processing steps as needed, such as edge polishing, double-sided grinding, and back sealing. These processes may introduce damage to the wafer surface, such as mechanical damage like micro-scratches or cracks introduced by double-sided grinding. To address this, final polishing is typically used to remove the surface damage layer of the wafer to achieve the desired wafer surface quality.

[0031] When the wafer to be final polished is a wafer that has not undergone a back-sealing process, the surface material layer to be removed by the final polishing is only the previous process damage layer of monocrystalline silicon. However, when the wafer to be final polished has undergone a back-sealing process, as mentioned earlier, after the back-sealing process, a back-sealing film is formed not only on the back side of the wafer but also possibly on the front side. In this case, the surface material layer to be removed by the final polishing includes not only the previous process damage layer of monocrystalline silicon but may also include a thin film layer, such as a polycrystalline silicon thin film layer, covering the previous process damage layer.

[0032] For wafers where a thin film layer has formed on the damaged layer on the front side due to the back-sealing process, conventional final polishing processes used to directly remove the damaged layer are not effective in controlling the surface morphology of such wafers. Specifically, on the one hand, the formation of a thin film layer covering the damaged layer from the previous process increases the amount of material to be removed, leading to a tendency for wafer surface flatness to deteriorate during final polishing. On the other hand, for example, single-crystal silicon grown using the Czochralski method differs in crystal structure and physical properties from polycrystalline silicon layers grown using methods such as chemical vapor deposition. Therefore, conventional final polishing processes, such as those used for non-back-sealed wafers, are not suitable for the final polishing of such wafers and may increase the tendency for wafer surface flatness to deteriorate, especially the deterioration of nano-morphology.

[0033] To address the aforementioned problems, referring to Figure 1, according to an embodiment of this disclosure, a final polishing method for a wafer is provided. The wafer includes a first layer to be removed and a second layer to be removed, the first layer to be removed and the second layer to be removed being adjacent to each other and made of different materials. The final polishing method includes:

[0034] S100: Perform a first polishing on the wafer to remove a portion of the first layer to be removed; and

[0035] S200: Perform a second polishing on the wafer that has undergone the first polishing to remove the remaining portion of the first layer to be removed and the second layer to be removed;

[0036] The material removal rate of the second polishing process is less than that of the first polishing process.

[0037] It should be understood that the final polishing referred to in this disclosure refers to the single-sided final polishing of the front side of the wafer, and not the double-sided grinding or double-sided polishing of the wafer, nor the partial polishing of the wafer such as edge polishing.

[0038] For ease of understanding of the technical solution, Figure 2 exemplarily illustrates the final polishing apparatus 1. As shown in Figure 2, the final polishing apparatus 1 includes a polishing head 2, a polishing table 3, and a polishing slurry supply line 4. The polishing head 2 includes an adsorption pad 5, which is used to contact the back side of the wafer W to be finally polished and hold the wafer W in an adsorption manner. A polishing pad 6 is disposed on the upper surface of the polishing table 3, which is used to contact the front side of the wafer W. The final polishing apparatus 1 also includes a rotary drive 7 for driving the polishing head 2 to rotate and a rotary drive 8 for driving the polishing table 3 to rotate. The polishing slurry supply line 4 is used to supply polishing slurry to the polishing pad 6 so that, when the polishing pad 6 is in contact with the wafer W, the front side of the wafer W is finally polished by the relative rotational movement of the polishing head 2 and the polishing table 3.

[0039] Figure 3 exemplarily illustrates a wafer W to be finalized. In Figure 3, the front side of wafer W is shown as the upper surface, and the back side of wafer W is shown as the lower surface. Wafer W includes a first layer L1 to be removed and a second layer L2 to be removed on one side of its front side.

[0040] Wafer W is a wafer that has undergone a back-side coating process prior to this. The back-side coating process can include wafer back-side thin film growth processes, such as a back-sealing process. The first layer to be removed, L1, is formed on wafer W during the coating process. For example, wafer W undergoes a back-sealing process to form a back-side film L0 on its back side and simultaneously forms the first layer to be removed L1 on its front side, specifically outside the second layer to be removed, L2. It is understood that the back-side film L0 and the first layer to be removed L1 are made of the same material. The material of the first layer to be removed L1 is, for example, polycrystalline silicon, but is not limited to this; it could also be silicon dioxide, silicon nitride, etc.

[0041] The second layer to be removed, L2, is a material layer that already exists on the front side of wafer W before the back-side coating process. This material layer is a surface damage layer caused by the processing steps (hereinafter referred to as the preceding process) before the final polishing of wafer W, specifically before the back-side coating process. The second layer to be removed, L2, is part of wafer W itself, and its material is the same as that of wafer W itself, which is monocrystalline silicon.

[0042] The first layer L1 and the second layer L2 are adjacent to each other and form an interface A between them. The first layer L1 is located outside the second layer L2. During the final polishing, the first layer L1 will be polished first. More specifically, the side of the first layer L1 that is away from the interface A will be polished first.

[0043] In step S100 (also known as the first polishing step), the front side of the wafer W to be polished is first polished to remove a portion of the first layer L1 to be removed. That is, the first polishing step is designed not to completely remove the first layer L1 to be removed, but to leave a certain thickness near the interface A, ensuring that the first polishing ends before the interface A is touched.

[0044] The material removal rate in the first polishing stage is relatively high in order to shorten the first polishing time, reduce the overall processing time of the equipment, and increase the equipment's output per unit time.

[0045] In step S200 (also known as the second polishing step), the wafer W that has undergone the first polishing is subjected to a second polishing to remove the remaining portion of the first layer to be removed L1 and the second layer to be removed L2. Thus, the interface A will be removed during the second polishing process.

[0046] Compared to the first polishing, the second polishing employs a lower material removal rate to achieve a gentler polishing process. This not only helps reduce damage caused by this process, but also allows for relatively gentler and more meticulous surface material removal near interface A, mitigating potential flatness degradation when polishing the critical thickness area where interface A is located.

[0047] Through the above technical solution, for a wafer with a first layer to be removed and a second layer to be removed that are adjacent to each other and made of different materials, two polishing steps with different intensity levels are performed sequentially on the first layer to be removed. Specifically, by switching to a second polishing step with a lower material removal rate before the first polishing step with a higher material removal rate reaches the interface between the first layer to be removed and the second layer to be removed on the wafer, the remaining part of the first layer to be removed, including the interface, can be removed in a relatively gentler manner.

[0048] Compared to removing the entire first layer to be removed in one step at a higher polishing rate, the final polishing method for wafers disclosed herein can avoid or mitigate wafer flatness deterioration in the final polishing process stage, and effectively control the possible wafer flatness deterioration (especially the deterioration of nano-morphology), thereby giving the polished wafer obtained after final polishing better surface flatness, such as better nano-morphology.

[0049] In this disclosure, the flatness level of a wafer is evaluated using numerical results of nano-morphology values ​​within a 2mm × 2mm dimension, referred to as Nano 2mm × 2mm. Specifically, after dividing the wafer surface into analysis regions according to a set size (e.g., 2mm × 2mm), the peak and valley values ​​in the filtered measurement data at each sampling point within each analysis region are sorted in ascending order, and the value at the corresponding position in this ascending order is selected as the wafer's nano-morphology value according to a set percentile (e.g., 99.5%). It can be understood that the smaller the Nano 2mm × 2mm, the better the wafer's nano-morphology and the better its flatness.

[0050] In some embodiments, the final polishing method for the wafer may further include step S300: performing a third polishing on the wafer W that has undergone the second polishing. The third polishing is used to repair damage caused by the preceding polishing steps, particularly the second polishing, to obtain a highly flat and smooth surface, achieving a mirror finish on the wafer surface.

[0051] The material removal rate of the third polishing is lower than that of the second polishing to provide a gentler operating condition than the second polishing, thereby avoiding an overly rough polishing effect caused by an excessively fast material removal rate. This is conducive to achieving a finer surface treatment than the second polishing, thereby further improving the nano-morphological characteristics of the wafer surface.

[0052] For example, for a wafer with a previous process damage layer thickness of 200 nm and a polycrystalline silicon thin film layer covering the previous process damage layer with a thickness of 400 nm, if the processing time for the first polishing, the second polishing and the third polishing are all 400 s, and the removal thickness of the single crystal silicon in the second polishing and the third polishing is 150% of the thickness of the previous process damage layer, the material removal rate of the first polishing can be 0.8 nm / s to 1.1 nm / s, the material removal rate of the second polishing can be 0.5 nm / s to 0.8 nm / s, and the material removal rate of the third polishing can be 0.08 nm / s to 0.2 nm / s.

[0053] In some embodiments, the thickness of said portion of the first layer to be removed can be 85% to 95% of the total thickness of the first layer to be removed.

[0054] As mentioned earlier, using a second polishing process with a relatively low material removal rate to remove the thick region including the interface can help improve the flatness level. In this case, the thickness of the portion of the first layer to be removed removed by the first polishing can be made as close as possible to the total thickness of the first layer to be removed, thereby minimizing the processing time of the second polishing process with a relatively low material removal rate and thus improving the overall efficiency of the final polishing process.

[0055] However, if the thickness of the portion removed by the first polishing is greater than 95% of the total thickness of the first layer to be removed, the end of the first polishing or the start of the second polishing will be too close to the interface, which can easily lead to deterioration of flatness, especially deterioration of nano-morphology.

[0056] As can be seen from the test results in Figures 4 and 5, when the percentage is greater than 95%, the overall nano-morphology value of the polished wafer is higher than that in the range of 65% to 95%, and there is a tendency to increase. This indicates that the flatness level of the polished wafer is relatively worse and there is a tendency to gradually deteriorate.

[0057] On the other hand, due to limitations in equipment precision, a redundancy of at least 85% (i.e., greater than or equal to 85%) is set. This ensures that even if the percentage does not reach 95% due to equipment precision, as long as it is above 85%, the removal efficiency can be guaranteed when the material removal rate of the first polishing is between 0.8 nm / s and 1.1 nm / s, the material removal rate of the second polishing is between 0.5 nm / s and 0.8 nm / s, and the material removal rate of the third polishing is between 0.08 nm / s and 0.2 nm / s, without causing deterioration of the nanostructure.

[0058] The thickness of the first layer to be removed can be, for example, to However, it is understood that this thickness range is merely exemplary, and the thickness of the first layer to be removed will be determined based on the requirements of the desired wafer product.

[0059] In some implementations, the first polishing can be performed with a first target removal thickness. The first target removal thickness can be predetermined based on the needs or specifications of the back-end customer.

[0060] In some implementations, the second polishing may be performed with a second target removal thickness, and the third polishing may be performed with a third target removal thickness, wherein the second target removal thickness may be greater than the third target removal thickness.

[0061] In this configuration, the second and third polishing processes can remove wafer surface material by progressively decreasing the target workload. Thus, the target workload of the second and third polishing processes can be matched with their respective material removal rates; for example, a relatively large material removal rate can be matched with a relatively large target removal thickness, thereby optimizing the entire final polishing process and improving its overall efficiency.

[0062] In some implementations, the ratio of the single-crystal silicon removal thickness in the second target removal thickness to the third target removal thickness can be 6:1 to 4:1.

[0063] As mentioned earlier, the portion removed by the second polishing includes the remaining portion of the first layer to be removed and the second layer to be removed. That is, the material removed by the second polishing includes the thin film material (e.g., polycrystalline silicon) corresponding to the remaining portion and the material corresponding to the second layer to be removed (i.e., monocrystalline silicon). In this case, the second target removal thickness is actually composed of the thin film material removal thickness and the monocrystalline silicon removal thickness.

[0064] By making the ratio of the single-crystal silicon removal thickness in the second target removal thickness to the third target removal thickness reach 6:1 to 4:1, it is possible to make the removal of the damaged layer more thorough while ensuring that no excessive loss of single-crystal silicon material is lost.

[0065] In some implementations, the sum of the single-crystal silicon removal thickness in the second target removal thickness and the third target removal thickness can be greater than or equal to 150% of the thickness of the damaged layer of the wafer to be first polished. In this way, sufficient removal of damage from the previous process can be ensured to the greatest extent.

[0066] It should be noted that the damage layer here refers to the damage layer that already exists on the surface of the wafer to be polished when it is about to undergo final polishing or just before the first polishing. This damage layer is the area of ​​damage introduced onto the wafer surface by the preceding pre-polishing processes.

[0067] It is understood that the thickness of the damage layer refers to the depth of the damage relative to the surface of the wafer in a direction perpendicular to that surface. The thickness of the damage layer can, for example, range from 50 nm to 1000 nm. However, it is understood that this thickness range is merely exemplary, and the thickness of the damage layer will vary depending on the type of damage.

[0068] It is conceivable that the material removal rates of the first polishing, the second polishing, and / or the third polishing can be configured by adjusting the polishing process parameters. These polishing process parameters include, but are not limited to, the composition of the polishing slurry, the operating pressure, and the rotation speed.

[0069] For example, the polishing slurry comprises an alkaline additive. In some embodiments, the first polishing can use a first polishing slurry containing an alkaline additive, and the second polishing can use a second polishing slurry containing an alkaline additive. The proportion of the alkaline additive in the second polishing slurry can be less than the proportion of the alkaline additive in the first polishing slurry, so that the alkalinity concentration of the second polishing slurry is lower than that of the first polishing slurry. Therefore, the chemical corrosion effect of the second polishing is weaker than that of the first polishing, resulting in a lower material removal rate in the second polishing compared to the first polishing.

[0070] In embodiments including a third polishing step, the first polishing can use a first polishing liquid containing an alkaline additive, and the second polishing can use a second polishing liquid containing an alkaline additive, wherein the proportion of the alkaline additive in the second polishing liquid can be less than the proportion of the alkaline additive in the first polishing liquid. The third polishing can use a third polishing liquid without an alkaline additive, such that the material removal rate of the third polishing is less than the material removal rate of the second polishing.

[0071] By using a third polishing fluid that does not contain alkaline additives, the deterioration of wafer surface flatness that may be caused by chemical corrosion during the third polishing process can be avoided.

[0072] For example, the alkaline additive can be an organic base or an inorganic base. For instance, the alkaline additive may include KOH, NaOH, or NH4OH, etc.

[0073] Furthermore, the polishing slurry also includes abrasive particles, which are used to remove surface material by physically grinding the wafer surface. The material removal rate can also be configured by the particle size and uniformity of the abrasive particles in the polishing slurry. For example, compared to the second polishing, the third polishing can use smaller and more uniform abrasive particles to maximize the mirror finish of the wafer surface.

[0074] Furthermore, the operating pressure and speed used in the first polishing can be greater than those used in the second polishing, and when the third polishing is included, the operating pressure and speed used in the second polishing can be greater than those used in the third polishing.

[0075] As can be understood from Figure 2, the operating pressure refers to the pressure applied to the wafer W undergoing polishing, such as the pressure applied by the polishing head 2. The rotational speed refers to the rotational speed of the polishing head 2, i.e., the rotational speed of the wafer W, the rotational speed of the polishing table 3, i.e., the rotational speed of the polishing pad 6, or the relative rotational speed between the wafer W and the polishing pad 6.

[0076] It is understandable that the aforementioned polishing process parameters can be configured by reasonable combination and adjustment to obtain the material removal rate required for each polishing step, thereby achieving precise control over the entire final polishing process.

[0077] According to embodiments of the present disclosure, a polished wafer is also provided, which is obtained using a final polishing method for wafers according to embodiments of the present disclosure, wherein the nano 2mm × 2mm of the polished wafer is less than 15nm.

[0078] Referring to Figures 4 and 5, the polished wafers obtained using the final polishing method for wafers according to embodiments of the present disclosure have Nano 2mm × 2mm dimensions that are all less than 15nm. Specifically, when the thickness of said portion of the first layer to be removed is 85% to 95% of the total thickness of the first layer to be removed, the Nano 2mm × 2mm dimension is specifically less than 10nm.

[0079] This demonstrates that the polished wafer obtained by the final polishing method for wafers according to the embodiments of this disclosure can achieve better nanomorphology, i.e., the polished wafer has better flatness characteristics.

[0080] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “comprising” and “including” are open-ended, meaning that a system, apparatus, article, composition, formulation, or method that includes elements other than those listed after such terms in the claims is still considered to fall within the scope of the claims.

[0081] Although this disclosure has been described with reference to exemplary embodiments, it should be understood that this disclosure is not limited to the specific embodiments described and shown herein. Various changes can be made to the exemplary embodiments by those skilled in the art without departing from the scope defined by the claims of this disclosure.

[0082] The features mentioned and / or shown in the foregoing description of exemplary embodiments of this disclosure may be combined in the same or similar manner with one or more other embodiments, combined with features in other embodiments, or substituted for corresponding features in other embodiments. These combined or substituted technical solutions should also be considered to be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A final polishing method for a wafer, the wafer comprising a first layer to be removed and a second layer to be removed, the first layer to be removed and the second layer to be removed being adjacent to each other and made of different materials, the final polishing method comprising: The wafer is first polished to remove a portion of the first layer to be removed; as well as The wafer that has undergone the first polishing is subjected to a second polishing to remove the remaining portion of the first layer to be removed and the second layer to be removed, wherein the material removal rate of the second polishing is less than the material removal rate of the first polishing.

2. The final polishing method for wafers according to claim 1, wherein, It also includes performing a third polishing on the wafer that has undergone the second polishing, wherein the material removal rate of the third polishing is less than the material removal rate of the second polishing.

3. The final polishing method for wafers according to claim 2, wherein, The second polishing is performed with a second target removal thickness, and the third polishing is performed with a third target removal thickness, wherein the second target removal thickness is greater than the third target removal thickness.

4. The final polishing method for wafers according to claim 3, wherein, The ratio of the single-crystal silicon removal thickness in the second target removal thickness to the third target removal thickness is 6:1 to 4:

1.

5. The final polishing method for wafers according to claim 3 or 4, wherein, The sum of the single-crystal silicon removal thickness in the second target removal thickness and the third target removal thickness is greater than or equal to 150% of the thickness of the damaged layer of the wafer to be first polished.

6. The final polishing method for wafers according to claim 1, wherein, The first polishing uses a first polishing liquid containing an alkaline additive, and the second polishing uses a second polishing liquid containing an alkaline additive, wherein the proportion of alkaline additive in the second polishing liquid is less than the proportion of alkaline additive in the first polishing liquid.

7. The final polishing method for wafers according to claim 2, wherein, The first polishing uses a first polishing liquid containing an alkaline additive, the second polishing uses a second polishing liquid containing an alkaline additive, and the third polishing uses a third polishing liquid without an alkaline additive, wherein the proportion of alkaline additive in the second polishing liquid is less than the proportion of alkaline additive in the first polishing liquid.

8. The final polishing method for wafers according to claim 1, wherein, The thickness of the portion of the first layer to be removed is 85% to 95% of the total thickness of the first layer to be removed.

9. The final polishing method for wafers according to claim 1, wherein, The material of the first layer to be removed is polycrystalline silicon, and the material of the second layer to be removed is monocrystalline silicon.

10. A polished wafer obtained using a final polishing method for a wafer according to any one of claims 1 to 9, wherein the nano 2mm × 2mm of the polished wafer is less than 15nm.

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