Drive substrate, display panel, and display apparatus

Abstract

The present disclosure belongs to the technical field of display. Provided are a drive substrate, a display panel, and a display apparatus. The drive substrate comprises a demultiplexing circuit area, wherein the demultiplexing circuit area comprises a first demultiplexing circuit sub-area, and a second demultiplexing circuit sub-area located on the side of the first demultiplexing circuit sub-area that is away from a display area; in the first demultiplexing circuit sub-area, the drive substrate is provided with a plurality of demultiplexing circuits arranged in a row direction, and each demultiplexing circuit comprises a plurality of transistor units; first electrodes of transistors in the same demultiplexing circuit are all electrically connected to the same source-end signal line, and second electrodes of transistors in the same transistor unit are electrically connected to the same data line; and the second demultiplexing circuit sub-area is provided with a plurality of gating signal lines that correspond to the plurality of transistor units in the demultiplexing circuits on a one-to-one basis and extend in the row direction, and gate electrodes of transistors in the transistor units are all electrically connected to the corresponding gating signal lines. The drive substrate can reduce restrictions imposed by demultiplexing circuits on the performance of a display panel.

Description

Driver substrate, display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese Patent Application No. 202411944394.6, filed on December 26, 2024, entitled "Driver Substrate, Display Panel and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to a driving substrate, a display panel, and a display device. Background Technology

[0004] Micro OLED technology is an OLED display technology that uses a silicon-based driving substrate for driving. It often has high resolution, such as over 3000 PPI. As users' demand for smaller-sized products increases, their requirements for display clarity and display effect are also increasing.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a driving substrate, a display panel, and a display device to reduce the limitation of the multiplexing circuit on the performance of the display panel.

[0007] According to one aspect of the present disclosure, a driving substrate is provided, including a display area and a decomposition circuit area; the display area is provided with data lines for loading data voltages onto pixel driving circuits; the decomposition circuit area includes a first decomposition circuit sub-region and a second decomposition circuit sub-region located on the side of the first decomposition circuit sub-region away from the display area.

[0008] In the first decomposition circuit subregion, the driving substrate is provided with a plurality of multiple decomposition circuits arranged along the row direction, each multiple decomposition circuit including a plurality of transistor units; the first terminal of each transistor in the same multiple decomposition circuit is electrically connected to the same source signal line, and the second terminal of each transistor in the same transistor unit is electrically connected to the same data line.

[0009] The second decomposition circuit subregion has multiple gating signal lines that correspond one-to-one with multiple transistor units in the multiplex decomposition circuit and extend along the row direction. The gate of each transistor in the transistor unit is electrically connected to the corresponding gating signal line.

[0010] According to one embodiment of this disclosure, the dimension of the multiplexing circuit along the column direction is a first dimension; the distance between the edge of the gating signal line closest to the display area and the edge of the gating signal line furthest from the display area is a second dimension; the second dimension is greater than the first dimension.

[0011] According to one embodiment of this disclosure, the width of the strobe signal line is greater than half the width of the channel region of the transistor in the multiplexing circuit.

[0012] According to one embodiment of the present disclosure, the driving substrate includes a transistor layer and multiple metal layers stacked sequentially; the transistor layer and the first metal layer are electrically connected through metallized vias, and two adjacent metal layers are electrically connected through metallized vias.

[0013] In the second decomposition circuit subregion, the driving substrate is provided with a first transfer line for gating signals corresponding to each transistor unit. The first transfer line for gating signals extends along the column direction and is electrically connected to the gate of each transistor in the corresponding transistor unit.

[0014] There is at least one metal layer between the metal layer where the first adapter wire of the strobe signal is located and the metal layer where the strobe signal line is located.

[0015] According to one embodiment of this disclosure, the first adapter wire of the gating signal is arranged to overlap with each of the gating signal lines.

[0016] According to one embodiment of this disclosure, a fourth select signal adapter is provided between the first select signal adapter and the electrically connected select signal line. The first select signal adapter is electrically connected to the corresponding select signal line through the fourth select signal adapter. When the metal layer where the fourth select signal adapter is located is adjacent to the metal layer where the first select signal adapter is located, the first select signal adapter and the fourth select signal adapter are electrically connected to each other through at least two columns of metallized vias. Each column of metallized vias includes at least three metallized vias arranged sequentially along the column direction.

[0017] According to one embodiment of the present disclosure, the first metal layer has a second gating signal adapter line in the first decomposition circuit subregion that corresponds one-to-one with each transistor unit. The second gating signal adapter line is electrically connected to the gate of each transistor of the corresponding transistor unit through a metallized via.

[0018] The second adapter wire for the strobe signal has a via portion for connection with a metallized via and a trace portion for connection with the via portion; the width of the trace portion of the second adapter wire for the strobe signal is smaller than the width of the first adapter wire for the strobe signal.

[0019] According to one embodiment of the present disclosure, the driving substrate includes a transistor layer and multiple metal layers stacked sequentially; the transistor layer and the first metal layer are electrically connected through metallized vias, and two adjacent metal layers are electrically connected through metallized vias.

[0020] In the second decomposition circuit subregion, the driving substrate is provided with a source signal first adapter line extending along the column direction. One end of the source signal first adapter line is electrically connected to the source signal line, and the other end is electrically connected to the first electrode of each transistor of at least one transistor unit.

[0021] There is at least one metal layer between the metal layer where the first adapter line of the source signal is located and the metal layer where the strobe signal line is located.

[0022] According to one embodiment of the present disclosure, the transistor unit includes a plurality of transistors connected in parallel, each of the transistors being arranged sequentially along the column direction, and the channel region length direction of each transistor being the row direction;

[0023] The driving substrate has a first driving voltage adapter line that corresponds one-to-one with the transistor unit and extends along the column direction in the first decomposition circuit subregion. The first driving voltage adapter line is electrically connected to the second electrode of each transistor in the transistor unit and is also electrically connected to the data line.

[0024] According to one embodiment of the present disclosure, the multiplexing circuit includes a plurality of transistor unit groups, each of the transistor unit groups including two adjacent transistor units;

[0025] The driving substrate has a source signal second adapter wire in the first decomposition circuit subregion that corresponds one-to-one with the transistor unit group. The source signal second adapter wire is electrically connected to the first electrode of each transistor in the corresponding transistor unit group.

[0026] According to one embodiment of the present disclosure, the driving substrate includes a data line group corresponding one-to-one with at least a portion of the transistor unit groups, the data line group includes two non-adjacent data lines, and the pixel driving circuit driven by the two data lines of the data line group is used to drive sub-pixels of the same color.

[0027] One data line of the data line group is electrically connected to the second electrode of each transistor in a transistor unit of the corresponding transistor unit group, and the other data line of the data line group is electrically connected to the second electrode of each transistor in another transistor unit of the corresponding transistor unit group.

[0028] According to one embodiment of the present disclosure, the first decomposition circuit subregion has an annular back gate structure, and each of the multiplexed decomposition circuits is located within the space surrounded by the back gate structure.

[0029] The gating signal line is located on the side of the back grid structure away from the display area.

[0030] According to one embodiment of the present disclosure, the driving substrate includes a semiconductor substrate and multiple metal layers stacked sequentially.

[0031] The back gate structure includes an annular back gate doped region located on the semiconductor substrate and a back gate trace located on the first metal layer. The back gate trace is electrically connected to the back gate doped region through a metallized via.

[0032] The driving substrate is further provided with a metal structure that spans the back gate structure, and the metal layer where the metal structure spanning the back gate structure is located is spaced apart from the first metal layer by at least one metal layer.

[0033] According to another aspect of this disclosure, a display panel is provided, including the driving substrate described above.

[0034] According to another aspect of this disclosure, a display device is provided, including the display panel described above.

[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0037] Figure 1 is a schematic diagram of the structure of the display panel in one embodiment of this disclosure.

[0038] Figure 2 is a schematic diagram of the structure of the display panel in one embodiment of this disclosure.

[0039] Figure 3 is a partial structural schematic diagram of the driving substrate in one embodiment of this disclosure.

[0040] Figure 4 is a partial structural schematic diagram of the driving substrate in one embodiment of this disclosure.

[0041] Figure 5 is a partial structural schematic diagram of the driving substrate in one embodiment of this disclosure.

[0042] Figure 6 is a schematic diagram of the multi-path decomposition circuit of the driving substrate in one embodiment of this disclosure.

[0043] Figure 7 is a schematic diagram of the driving timing of the multiplexing circuit of the driving substrate in one embodiment of the present disclosure.

[0044] Figure 8 is a schematic diagram of the structure of the doped region of the driving substrate in one embodiment of this disclosure.

[0045] Figure 9 is a schematic diagram of the gate layer structure in one embodiment of this disclosure.

[0046] Figure 10 is a schematic diagram of the stacked structure of the doped region and the gate layer in one embodiment of this disclosure.

[0047] Figure 11 is a partially enlarged schematic diagram of the doped region of the driving substrate in one embodiment of the present disclosure.

[0048] Figure 12 is a partially enlarged schematic diagram of the stacked doped region and gate layer in one embodiment of this disclosure.

[0049] Figure 13 is a schematic diagram of the structure of the first metal layer in one embodiment of this disclosure.

[0050] Figure 14 is a schematic diagram of the stacked structure of the first metal layer, the first metallized via, the gate layer, and the doped region in one embodiment of this disclosure.

[0051] Figure 15 is a schematic diagram of the structure of the second metal layer in one embodiment of this disclosure.

[0052] Figure 16 is a schematic diagram of the stacked structure of the first metal layer, the second metallized via, and the second metal layer in one embodiment of this disclosure.

[0053] Figure 17 is a schematic diagram of the structure of the third metal layer in one embodiment of this disclosure.

[0054] Figure 18 is a schematic diagram of the stacked structure of the second metal layer, the third metallized via, and the third metal layer in one embodiment of this disclosure.

[0055] Figure 19 is a schematic diagram of the structure of the fourth metal layer in one embodiment of this disclosure.

[0056] Figure 20 is a schematic diagram of the stacked structure of the third metal layer, the fourth metallized via, and the fourth metal layer in one embodiment of this disclosure.

[0057] Figure 21 is a schematic diagram of the stacked structure of the doped region, gate layer, first metal layer, second metal layer, third metal layer and fourth metal layer in one embodiment of the present disclosure.

[0058] Figure 22 is a partial schematic diagram of the stacked structure of the doped region, gate layer, first metal layer, second metal layer, third metal layer and fourth metal layer in one embodiment of the present disclosure. Detailed Implementation

[0059] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0060] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0061] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0062] This disclosure provides a display panel PNL and a driving substrate BP used in the display panel PNL. Referring to FIG1, the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA, for example, the peripheral area BB surrounds the display area AA. In the display area AA, the display panel PNL is provided with an array of display units UU, each display unit UU including a sub-pixel PX and a pixel driving circuit PDC driving the sub-pixel PX. The display panel PNL does not provide display units UU in the peripheral area BB, or the provided display units UU are not used for displaying images. Referring to FIG1, the display panel PNL is provided with a plurality of scan signal lines GateL extending along the row direction DH in the display area AA, each scan signal line GateL corresponding to a row of display units UU. The pixel driving circuit PDC of each display unit UU in the row of display units UU is electrically connected to the corresponding scan signal line GateL. The display panel PNL is also provided with a plurality of data lines DL extending along the column direction DV in the display area AA, each data line DL corresponding to a column of display units UU. Each pixel drive circuit (PDC) of the display unit UU column is electrically connected to its corresponding data line DL. Thus, each display unit UU's PDC is connected to a scan signal line GateL and a data line DL. When a scan signal is applied to the scan signal line GateL, the driving voltage applied to the data line DL is written into the pixel drive circuit PDC, allowing the PDC to control the brightness of the sub-pixel PX based on the written driving voltage.

[0063] In some embodiments of this disclosure, sub-pixels PX may include a variety of sub-pixels PX of different colors, such as red sub-pixels for emitting red light, green sub-pixels for emitting green light, and blue sub-pixels for emitting blue light. It is understood that in other embodiments of this disclosure, sub-pixels PX in the display area AA may also have sub-pixels PX of other colors (e.g., yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0064] In one embodiment of this disclosure, referring to FIG2, the display panel PNL includes a driving substrate BP and a sub-pixel layer PXL stacked sequentially. A light-emitting element LD for emitting light, such as an OLED, is disposed in the sub-pixel layer PXL; a pixel driving circuit PDC for driving the light-emitting element LD is disposed in the driving substrate BP. In the example of FIG2, the sub-pixel PX includes the light-emitting element LD and a color filter unit located on the light-emitting side of the light-emitting element LD (e.g., the side away from the driving substrate BP). The light-emitting element LD can emit white light, for example, the light-emitting element LD can emit white light formed by mixing multiple colored lights; the white light emitted by the light-emitting element LD passes through the color filter unit and is emitted as colored light. For example, white light emitted by the light-emitting element LD is filtered by the red color filter unit and then emitted as red light, so the sub-pixel PX is a red sub-pixel; white light emitted by the light-emitting element LD is filtered by the green color filter unit and then emitted as green light, so the sub-pixel PX is a green sub-pixel; white light emitted by the light-emitting element LD is filtered by the blue color filter unit and then emitted as blue light, so the sub-pixel PX is a blue sub-pixel.

[0065] Optionally, the light-emitting element LD can be a current-driven self-emissive element, such as any one of OLED, PLED, QLED, MicroOLED, MiniLED, etc.

[0066] In one example, the light-emitting element LD is an OLED, such as a white OLED.

[0067] It is understood that in other embodiments of this disclosure, the sub-pixel PX may also adopt other structures, such as OLED or MicroOLED light-emitting elements, which can be directly used as sub-pixel PX for light emission and display without further color conversion.

[0068] In one embodiment of this disclosure, referring to FIG3, the driving substrate BP includes a transistor layer ML and multiple metal layers stacked sequentially; transistors are disposed in the transistor layer ML, such as transistors required for the pixel driving circuit PDC, transistors required for the multiplexing circuit DM, etc. Depending on the needs, the transistors can be NMOS transistors or PMOS transistors.

[0069] In this embodiment of the disclosure, the metal layer closest to the transistor layer ML is referred to as the first metal layer M1. An insulating layer (such as an inorganic insulating layer, such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer) is provided between the first metal layer M1 and the transistor layer ML, and between adjacent metal layers; metallized vias (such as tungsten pillars) are provided in the insulating layers to enable electrical connection between the first metal layer M1 and the transistor layer ML, and to enable electrical connection between adjacent metal layers.

[0070] In one example, referring to Figure 3, the driving substrate BP includes a semiconductor substrate SBT (e.g., a single-crystal silicon substrate). The desired doped regions can be formed on the semiconductor substrate SBT using CMOS processes, where a portion of the doped region can serve as the active region BAA to form a transistor. On the surface of the semiconductor substrate SBT, a gate insulating layer GI and a gate layer GT can be sequentially formed and patterned. Thus, the active region BAA, gate insulating layer GI, and gate layer GT of the semiconductor substrate SBT can form the desired transistor. In one example, the gate layer GT can be made of a non-metallic material; for example, the gate layer can be made of conductive polycrystalline silicon.

[0071] In one example, referring to Figure 3, the driving substrate BP includes a first insulating layer D1, a first metal layer M1, a second insulating layer D2, a second metal layer M2, a third insulating layer D3, a third metal layer M3, a fourth insulating layer D4, and a fourth metal layer M4, which are sequentially stacked on one side of the transistor layer ML. The first insulating layer D1 contains a tungsten pillar embedded within it, serving as a first metallization via V1. The transistor layer ML is electrically connected to the first metal layer M1 through the first metallization via V1; for example, the source, drain, and gate of the transistor are electrically connected to the first metal layer M1 through the first metallization via V1. A second metallized via V2 is provided in the second insulating layer D2, through which the second metal layer M2 is electrically connected to the first metal layer M1; a third metallized via V3 is provided in the third insulating layer D3, through which the third metal layer M3 is electrically connected to the second metal layer M2; a fourth metallized via V4 is provided in the fourth insulating layer D4, through which the fourth metal layer M4 is electrically connected to the third metal layer M3, and so on. In the example of Figure 3, only four metal layers are shown. The driving substrate BP can be provided with more metal layers as needed.

[0072] In one embodiment of this disclosure, the driving substrate BP is fabricated using a single-crystal silicon CMOS process.

[0073] In one embodiment of this disclosure, the driving substrate BP can support high-resolution displays, such as 4K displays. In one example, the display panel PNL can achieve a resolution of 3956 PPI or higher.

[0074] Figure 4 is a schematic diagram of the planar structure of the driving substrate BP in one embodiment of this disclosure. Referring to the example in Figure 4, the driving substrate BP has a decomposition circuit region DMA and a source signal line SL in the peripheral region BB. The decomposition circuit region DMA contains multiple decomposition circuits DM, and the source signal line SL can be electrically connected to the signal terminal of the source driving circuit. The multiple decomposition circuits DM are arranged one-to-one with the source signal line SL, and are electrically connected to multiple data lines DL and multiple selection signal lines. Under the control of the selection signal on the selection signal line, the multiple decomposition circuits DM can selectively and sequentially connect the source signal line SL to the data lines DL connected to the multiple decomposition circuits DM, thereby allowing the driving voltage applied to the source signal line SL to be applied to different data lines DL in a time-division manner. In this way, one signal terminal of the source driving circuit can drive multiple data lines DL, thereby reducing the cost or size of the source driving circuit.

[0075] In one example, the source driving circuit may be part of the driving substrate BP, for example, the source driving circuit is fabricated synchronously with the display area AA, or the source driving circuit is pre-packaged onto the driving substrate BP by a packaging process.

[0076] In another example, the source driving circuit is not part of the driving substrate BP, but is connected to the driving substrate BP after the driving substrate BP is fabricated. For example, the source driving circuit (which can be a source driving chip or a display driving chip or other chip that can realize source driving) is bonded or bonded to the chip bonding area reserved in the driving substrate BP by using a surface mount process.

[0077] The multiplexing circuit DM has multiple channel units, each including one or more transistors. Each channel unit is electrically connected to a data line DL and a strobe signal line, and also electrically connected to a source signal line SL. Specifically, the gate of each transistor within the channel unit is electrically connected to a strobe signal line, the second terminal of each transistor within the channel unit is electrically connected to a data line DL, and the first terminal of each transistor within the channel unit is electrically connected to the source signal line SL. When a strobe signal (e.g., a high or low level that enables the transistors within the channel unit to conduct) is applied to the strobe signal line connected to the channel unit, the channel unit turns on, allowing the signal applied on the source signal line SL to be applied to the data line DL.

[0078] As an example, a multiplexing circuit DM can have 3 to 12 channel units; for example, a multiplexing circuit DM can have 6 channel units.

[0079] In this embodiment, for ease of description, each conductive structure can be assigned to a corresponding signal channel based on its connection to the channel unit. Each signal channel is a set of conductive structures carrying the same type of signal. Specifically, a structure electrically connected to the gate of each transistor in the channel unit, such as the transistor gate, a gating signal line electrically connected to the transistor gate, or a trace electrically connecting the transistor gate to the gating signal line, is considered a gating signal channel. When a gating signal (e.g., a low-level signal or a high-level signal) is applied to the gating signal line of this gating signal channel, the channel unit controlled by this gating signal channel is turned on. A structure electrically connected to the second electrode of each transistor in the channel unit, such as the second electrode of the transistor, a data line DL electrically connected to the second electrode of the transistor, or a trace electrically connecting the second electrode of the transistor to the data line DL, is considered a data voltage channel. When each transistor in the channel unit is turned on, the voltage on the first electrode of the transistor can be written into this data voltage channel. A structure electrically connected to the first terminal of each transistor in a channel unit, such as the first terminal of the transistor, the source signal line SL electrically connected to the first terminal of the transistor, and the trace that electrically connects the first terminal of the transistor to the source signal line SL, constitutes a source signal channel. As an example, a multiplexer circuit DM connects a source signal channel and connects multiple gating signal channels and drive voltage channels.

[0080] In the peripheral area BB, the driving substrate BP can be provided with other circuits. These circuits can be directly fabricated by CMOS process during the fabrication of the driving substrate BP, or they can be formed on the driving substrate BP by packaging process.

[0081] In one example, the driving substrate BP has a variety of functional units with different functions pre-fabricated or packaged on the peripheral region BB. For example, one or more of the functional units such as memory, timing controller, communication interface, image processing module, source driving circuit, and gate driving circuit are provided on the peripheral region BB.

[0082] In another example, the driver substrate BP has one or more chip bonding areas on its peripheral area BB, and each chip bonding area contains bonding pads for bonding with a specific chip. For example, the driver substrate BP may have pre-selected chip bonding areas on its peripheral area BB for bonding a display driver chip, and the driver substrate BP can be bonded and connected to the display driver chip.

[0083] This disclosure also provides a display device, which includes any of the display panels described in the above-described display panel embodiments. Optionally, the display device can be a wearable device, personal digital assistant, clock, GPS receiver / navigator, virtual reality device, augmented reality device, mixed reality device, extended reality device, sight, rangefinder, or other display products or components with high pixel density.

[0084] In related technologies, the multiplexing circuit DM and the gating signal line controlling the multiplexing circuit DM are overlapped. This causes the data line DL connected to any channel to overlap with each gating signal line, which increases the load on the data line DL and causes a significant delay in the transmission of the driving voltage. This not only easily leads to insufficient charging of the factor pixel PX, resulting in poor image display (such as horizontal lines), but also limits the improvement of the refresh rate of the display panel PNL.

[0085] This disclosure optimizes the structure in the decomposed circuit region DMA to reduce interference between different signal channels, thereby improving display quality and refresh rate.

[0086] In this embodiment of the disclosure, referring to Figures 5 and 6, the driving substrate BP has a decomposition circuit region DMA in the peripheral area BB. The decomposition circuit region DMA includes a first decomposition circuit subregion DMA1 and a second decomposition circuit subregion DMA2 located on the side of the first decomposition circuit subregion DMA1 away from the display area AA. In the first decomposition circuit subregion DMA1, the driving substrate BP has a plurality of multiplexed decomposition circuits DM arranged sequentially along the row direction DH. Each multiplexed decomposition circuit DM includes a plurality of transistor units MU as channel units. The first terminal MS of each transistor in the same multiplexed decomposition circuit DM is electrically connected to the same source terminal signal line SL, and the second terminal MD of each transistor in the same transistor unit MU is electrically connected to the same data line DL. The second decomposition circuit subregion DMA2 has a plurality of gating signal lines MUXL corresponding one-to-one with the plurality of transistor units MU in the multiplexed decomposition circuit DM. The gate MG of each transistor in the transistor unit MU is electrically connected to the corresponding gating signal line MUXL. The gating signal line MUXL extends along the row direction DH.

[0087] In this embodiment, the multiplexing circuit DM is located in the first decomposition circuit subregion DMA1, while the gating signal line MUXL is located in the second decomposition circuit subregion DMA2. Therefore, the second terminal MD of each transistor in the multiplexing circuit DM does not overlap with the gating signal line MUXL. This prevents the formation or near-absence of coupling capacitance between the driving voltage channel and the gating signal channel, avoiding excessive parasitic capacitance in the driving voltage channel that could lead to excessive signal delay when the driving voltage is applied. This, in turn, avoids insufficient charging rate of the pixel driving circuit PDC due to excessive parasitic capacitance in the driving voltage channel. This can improve the display quality degradation caused by insufficient charging rate. Furthermore, the reduced signal delay of the driving voltage on the driving voltage channel is beneficial for improving the refresh rate of the display panel.

[0088] On the other hand, the absence or near absence of coupling capacitance between the gating signal line MUXL and the data line DL can reduce the impact of signal changes on the driving voltage channel on the signal, thereby improving the accuracy and stability of the driving voltage on the driving voltage channel and thus improving the quality of the display panel.

[0089] Furthermore, each transistor unit MU of the multiplexing circuit DM is a channel unit with multiple transistors. These transistors in the same channel unit are connected in parallel, which helps to increase the current when the source signal channel applies the drive voltage to the drive voltage channel, and avoids the limitation of the refresh rate due to insufficient drive capability of the transistor unit MU.

[0090] Furthermore, the reduced coupling capacitance between the data line DL and the strobe signal line MUXL also reduces the crosstalk of the driving voltage on the driving voltage channel to the strobe signal line MUXL, improving the stability of the strobe signal on the strobe signal line MUXL. This prevents the signal waveform on the strobe signal line MUXL from deteriorating and thus limiting the refresh rate of the display panel PNL.

[0091] In the example of Figure 6, each multiplexer circuit DM includes six transistor units MU, labeled as first transistor unit MU1, second transistor unit MU2, third transistor unit MU3, fourth transistor unit MU4, fifth transistor unit MU5, and sixth transistor unit MU6, respectively. Each transistor unit MU includes three transistors. Correspondingly, there are six gating signal lines MUXL, each corresponding one-to-one with one of the six transistor units MU, namely first gating signal line MUXL1, second gating signal line MUXL2, third gating signal line MUXL3, fourth gating signal line MUXL4, fifth gating signal line MUXL5, and sixth gating signal line MUXL6. Specifically, the first gating signal line MUXL1 is electrically connected to the gate MG of each transistor in the first transistor unit MU1; the second gating signal line MUXL2 is electrically connected to the gate MG of each transistor in the second transistor unit MU2; the third gating signal line MUXL3 is electrically connected to the gate MG of each transistor in the third transistor unit MU3; the fourth gating signal line MUXL4 is electrically connected to the gate MG of each transistor in the fourth transistor unit MU4; the fifth gating signal line MUXL5 is electrically connected to the gate MG of each transistor in the fifth transistor unit MU5; and the sixth gating signal line MUXL6 is electrically connected to the gate MG of each transistor in the sixth transistor unit MU6. The source signal line SL is electrically connected to the first terminal MS of each transistor.

[0092] In one embodiment of this disclosure, referring to FIG5, the first decomposition circuit subregion DMA1 has a ring-shaped back gate structure BG, and each of the multiplexing circuits DM is located within the space surrounded by the back gate structure BG; the gating signal line MUXL is located on the side of the back gate structure BG away from the display area AA.

[0093] Optionally, referring to Figure 3, the back gate structure BG includes an annular back gate doped region BG1 located on the semiconductor substrate SBT and a back gate trace BG2 located on the first metal layer M1. The back gate trace BG2 is electrically connected to the back gate doped region BG1 through a metallized via. The driving substrate BP is further provided with a metal structure spanning the back gate structure BG. The metal layer containing the metal structure spanning the back gate structure BG is spaced apart from the first metal layer M1 by at least one metal layer to reduce the coupling between the metal structure spanning the back gate structure BG and the back gate trace BG2.

[0094] For example, the source signal channel needs to cross the back gate structure BG to be electrically connected to the first electrode MS of the transistor. The metal structure of the source signal channel crossing the back gate structure BG can be set in the third metal layer M3, the fourth metal layer M4, or a metal layer further away from the semiconductor substrate SBT.

[0095] For example, the gating signal channel needs to cross the back gate structure BG to be electrically connected to the gate MG of the transistor. The metal structure of the gating signal channel crossing the back gate structure BG can be set in the third metal layer M3, the fourth metal layer M4, or a metal layer further away from the semiconductor substrate SBT.

[0096] For example, the driving voltage channel needs to cross the back gate structure BG to be electrically connected to the multiplexing circuit DM. The metal structure of the driving voltage channel crossing the back gate structure BG can be set in the third metal layer M3, the fourth metal layer M4, or a metal layer further away from the semiconductor substrate SBT.

[0097] In related technologies, the gating signal lines and the multiplexing circuit DM are overlapped so that the signals on the gating signal lines can be applied to the gates of the transistors in the multiplexing circuit DM. The total width of each gating signal line and the gaps between the gating signal lines cannot exceed the width of the multiplexing circuit DM. However, the width of the multiplexing circuit DM (the dimension along the column direction DV) is limited, which restricts the width of the gating signal lines and the gaps between them. The gating signal lines cannot be set to a larger width as needed, resulting in higher impedance and greater delay. The limited gap size between the gating signal lines makes them prone to crosstalk, leading to waveform degradation. Larger coupling capacitance between the gating signal lines further increases the load on the gating signal, further increasing its delay. Therefore, in related technologies, there is a risk of large gating signal delay and waveform degradation, which limits the improvement of the refresh rate of the display panel PNL.

[0098] In this embodiment, the gating signal line MUXL and the multiplexing circuit DM no longer overlap, and their widths, as well as the widths of the gaps between adjacent gating signal lines MUXL, are no longer constrained by the dimensions of the multiplexing circuit DM. Therefore, the delay and waveform of the gating signal can be improved by increasing the width of the gating signal line MUXL, or by increasing the gaps between the gating signal lines MUXL, or by simultaneously increasing both the width of the gating signal line MUXL and the gaps between the gating signal lines MUXL.

[0099] In one embodiment of this disclosure, referring to FIG12, the dimension of the multiplexing circuit DM along the column direction DV is a first dimension X1; referring to FIG17, the distance between the edge of the gating signal line MUXL closest to the display area AA and the edge of the gating signal line MUXL furthest from the display area AA is a second dimension X2; the second dimension X2 is greater than the first dimension X1. This second dimension is the sum of the widths of each gating signal line MUXL and the width of the gap between the gating signal lines MUXL.

[0100] Optionally, the second size is 1.5 to 5 times the first size. For example, the second size is 1.5, 1.7, 1.9, 2.1, 2.3, 2.5, 2.7, 2.9, or 3.1 times the first size.

[0101] In one embodiment of this disclosure, the width of the gating signal line MUXL is greater than half the width of the channel region of the transistor in the multiplexing circuit DM. Thus, the gating signal line MUXL has a larger width, which reduces impedance.

[0102] Optionally, the width of the strobe signal line MUXL is 0.6 to 1.5 times the width of the transistor's channel region, for example, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, or 1.5 times. As an example, the width of the strobe signal line MUXL is 0.9 to 1.1 times the width of the transistor's channel region.

[0103] In one embodiment of this disclosure, the width of the gap between the gating signal lines MUXL can be no less than 0.2 times the channel width of the transistor in the multiplexing circuit DM. Thus, the larger gap between the gating signal lines MUXL results in smaller parasitic capacitance between adjacent gating signal lines MUXL, which can reduce the load on the gating signal channel to lower power consumption and improve the delay and waveform of the gating signal on the gating signal channel.

[0104] Optionally, the width of the select signal line MUXL is 0.3 to 0.7 times the width of the channel region of the transistor, for example, 0.3 times, 0.35 times, 0.4 times, 0.45 times, 0.5 times, 0.55 times, 0.6 times, 0.65 times, or 0.7 times.

[0105] In one example, the spacing between the strobe signal lines MUXL is not less than 0.5 micrometers, for example, 0.5 to 1.0 micrometers. For example, the spacing between the strobe signal lines MUXL is 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, 0.9 micrometers, or 1.0 micrometers.

[0106] In one example, the width of the strobe line MUXL is not less than 1.75 micrometers, and particularly not less than 2 micrometers, for example, between 2.0 and 3.5 micrometers. For example, the width of the strobe line MUXL is 2.0 micrometers, 2.3 micrometers, 2.6 micrometers, 2.9 micrometers, 3.2 micrometers, or 3.5 micrometers.

[0107] In one embodiment of this disclosure, each gating signal line MUXL is disposed on the same metal layer, which can avoid the gating signal lines MUXL overlapping and causing excessive coupling capacitance.

[0108] In one embodiment of this disclosure, referring to Figures 6, 13, and 14, in the second decomposition circuit subregion DMA2, the driving substrate BP is provided with a first gating signal adapter line GL1 corresponding to each transistor unit MU. The first gating signal adapter line GL1 extends along the column direction DV and is electrically connected to the gate MG of each transistor in the corresponding transistor unit MU. At least one metal layer exists between the metal layer where the first gating signal adapter line GL1 is located and the metal layer where the gating signal line MUXL is located.

[0109] In this embodiment, the gating signal on the gating signal line MUXL can be transferred to the gating signal first transfer line GL1, and then loaded to the gate MG of each transistor in the corresponding transistor unit MU through the gating signal first transfer line GL1. At least part of the gating signal first transfer line GL1 inevitably needs to overlap with the gating signal lines MUXL of other gating signal channels in the second decomposition circuit subregion DMA2. In this embodiment, by placing the gating signal first transfer line GL1 and the gating signal line MUXL on non-adjacent metal layers, a larger spacing can be ensured between the gating signal first transfer line GL1 and the gating signal lines MUXL of other gating signal channels, thereby reducing the coupling capacitance between the gating signal first transfer line GL1 and the gating signal lines MUXL of other gating signal channels.

[0110] In one example, the strobe signal line MUXL and the first strobe signal adapter line GL1 are separated by 1 to 3 metal layers, for example, 1, 2 or 3 metal layers apart.

[0111] In one example, referring to Figures 6 and 21, the first adapter wire GL1 of the gating signal is arranged to overlap with each of the gating signal lines MUXL. For example, each first adapter wire GL1 of the gating signal is of the same length and is arranged to overlap with each of the gating signal lines MUXL to ensure that the load of different gating signal channels is the same.

[0112] In this embodiment, compared to the first switching line GL1, the switching line MUXL can be disposed on a metal layer closer to the transistor layer ML or on a metal layer farther away from the transistor layer ML.

[0113] In this embodiment, referring to Figures 13-18, each metal layer between the first select signal adapter GL1 and the electrically connected select signal line MUXL can be provided with a fourth select signal adapter GL4 corresponding to the first select signal adapter GL1. The first select signal adapter GL1, the fourth select signal adapter GL4 adjacent to the first select signal adapter GL1, the adjacent fourth select signal adapter GL4s, and the select signal line MUXL and the adjacent fourth select signal adapter GL4 are electrically connected through metallized vias. Thus, the first select signal adapter GL1 and the corresponding select signal line MUXL are electrically connected through metallized vias and the fourth select signal adapter GL4. In other words, on the same select signal channel, the first select signal adapter GL1 and the first select signal line MUXL1 are electrically connected through the fourth select signal adapter GL4.

[0114] In one example, referring to Figures 16 and 18, the orthographic projection of the fourth gating signal line GL4 corresponding to the first gating signal line GL1 onto the plane of the driving substrate BP lies within the orthographic projection range of the first gating signal line GL1 onto the plane of the driving substrate BP, and also within the orthographic projection range of the corresponding gating signal line MUXL onto the plane of the driving substrate BP. Thus, the fourth gating signal line GL4 only overlaps with the first gating signal line GL1 and the gating signal line MUXL of the same gating signal channel, and does not overlap with the gating signal lines MUXL and GL1 of other gating signal channels, thus not causing an increase in the load of that gating signal channel.

[0115] In one example, referring to Figure 16, within the same gating signal channel, the first gating signal adapter GL1 and the adjacent fourth gating signal adapter GL4 are electrically connected to each other through at least two rows of metallized vias. Each row of metallized vias includes at least three metallized vias arranged sequentially along the column direction DV. Thus, the multiple metallized vias between the first gating signal adapter GL1 and the adjacent fourth gating signal adapter GL4 result in lower resistance, which helps reduce the load and delay of the gating signal channel.

[0116] In this example, the first gating signal adapter GL1 is connected to the adjacent fourth gating signal adapter GL4 via at least six metallized vias, arranged in at least two columns. This is primarily because the gating signal line MUXL is located in the second decomposition circuit subregion DMA2, and its size is no longer limited by the size of the first decomposition circuit subregion DMA1. The electrical connections between different metal layers also have more flexible design space to reduce resistance. Optionally, the first gating signal adapter GL1 is connected to the adjacent fourth gating signal adapter GL4 via at least six metallized vias, such as six, eight, ten, twelve, fourteen, sixteen, eighteen, or twenty metallized vias, arranged in at least two columns. Further, the first gating signal adapter GL1 is connected to the adjacent fourth gating signal adapter GL4 via at least ten metallized vias.

[0117] Accordingly, within the same strobe signal channel, adjacent strobe signal fourth adapter wires GL4 are connected by no fewer than six metallized vias, and these metallized vias are arranged in at least two columns. For example, they are connected by 6 to 20 metallized vias. It is understood that when there is only one metal layer between the strobe signal first adapter wire GL1 and the strobe signal line MUXL, only one strobe signal fourth adapter wire GL4 is provided between the strobe signal first adapter wire GL1 and the strobe signal line MUXL, rather than multiple strobe signal fourth adapter wires GL4.

[0118] Accordingly, referring to Figure 18, within the same strobe signal channel, the fourth strobe signal adapter GL4 is connected to the adjacent strobe signal line MUXL via at least six metallized vias, and these metallized vias are arranged in at least two columns; for example, they are connected via 6 to 20 metallized vias. Further, the fourth strobe signal adapter GL4 is connected to the adjacent strobe signal line MUXL via at least 10 metallized vias.

[0119] In one embodiment of this disclosure, referring to Figures 6, 13, and 14, the first metal layer M1 has a second gating signal adapter GL2 in the first decomposition circuit subregion DMA1, corresponding one-to-one with each transistor unit MU. The second gating signal adapter GL2 is electrically connected to the gate MG of each transistor in the corresponding transistor unit MU through a metallized via. The first metal layer M1 also needs to provide a second source signal adapter SL2 in the first decomposition circuit subregion DMA1. This second source signal adapter SL2 is electrically connected to the first terminal MS of each transistor in the transistor unit MU through a metallized via. The first metal layer M1 also needs to provide a first driving voltage adapter DL1 in the first decomposition circuit subregion DMA1, corresponding one-to-one with each transistor unit MU. This first driving voltage adapter DL1 is electrically connected to the second terminal MD of each transistor in the corresponding transistor unit MU. Thus, the first driving voltage adapter DL1, the second gating signal adapter GL2, and the second source signal adapter SL2 are all located in the first metal layer M1 and are all electrically connected to the transistors, but belong to different signal channels. To reduce coupling between the three signal channels, the width of the second gating signal adapter GL2 needs to be limited. For example, the second gating signal adapter GL2 has a via portion L22 for connection to a metallized via and a trace portion L21 connected to the via portion L22. The via portion has a larger width so that it can be electrically connected to the transistor's gate MG through more first metallized vias V1. The trace portion L21 is narrower than the via portion to reduce the spacing between the trace portion L21 and the first drive voltage adapter DL1 and the second source signal adapter SL2.

[0120] In one example, referring to Figure 16, the width of the trace portion of the second gating signal adapter GL2 is smaller than the width of the first gating signal adapter GL1. In other words, the first gating signal adapter GL1 located in the second decomposition circuit subregion DMA2 can have a larger width. Since no drive voltage path is provided in this second decomposition circuit subregion DMA2, there is sufficient space to accommodate a larger width for the first gating signal adapter GL1. Furthermore, the width of the first gating signal adapter GL1 is greater than the width of the via portion of the second gating signal adapter GL2. Therefore, the resistance of the first gating signal adapter GL1 is smaller, and although the gating signal line MUXL is located outside the first decomposition circuit subregion DMA1, it does not result in a large resistance between the gating signal line MUXL and the second gating signal adapter GL2.

[0121] In one embodiment of this disclosure, the first switching line GL1 and the second switching line GL2 of the gating signal are directly connected to each other, or they can be connected through other metal structures to ensure the electrical continuity of the gating signal channel.

[0122] In one example, referring to Figure 6, the gating signal channel further includes a third gating signal adapter GL3, which spans the back gate structure BG and is electrically connected at both ends to the first gating signal adapter GL1 and the second gating signal adapter GL2, respectively. It is understood that the third gating signal adapter GL3 can be directly electrically connected to the first gating signal adapter GL1 via a metallized via VV, or indirectly connected to it via another metal layer. Similarly, the third gating signal adapter GL3 can be directly electrically connected to the second gating signal adapter GL2 via a metallized via VV, or indirectly connected to it via another metal layer. Furthermore, the metal layer containing the third gating signal adapter GL3 is at least one metal layer apart from the first metal layer M1.

[0123] In one embodiment of this disclosure, referring to Figures 6 and 16, in the second decomposition circuit subregion DMA2, the driving substrate BP is provided with a source signal first adapter line SL1 extending along the column direction DV. One end of the source signal first adapter line SL1 is electrically connected to the source signal line SL, and the other end is electrically connected to the first terminal MS of each transistor of at least one transistor unit MU. There is at least one metal layer between the metal layer where the source signal first adapter line SL1 is located and the metal layer where the gating signal line MUXL is located. This reduces the coupling between the source signal channel and the gating signal channel.

[0124] In one embodiment of this disclosure, referring to FIG16, the first adapter cable SL1 for the source signal and the first adapter cable GL1 for the gating signal can be disposed on the same metal layer and arranged side by side.

[0125] In one embodiment of this disclosure, referring to FIG16, the source signal line SL may be disposed on the same metal layer as the source signal first adapter line SL1. For example, the end of the source signal line SL near the second decomposition circuit subregion DMA2 has a side branch extending in the row direction DH, and the end of the source signal first adapter line SL1 near the source signal line SL is connected to the side branch of the source signal line SL.

[0126] In one embodiment of this disclosure, referring to FIG6, the source signal channel further includes a third source signal adapter SL3. The third source signal adapter SL3 spans the back gate structure BG and its two ends are electrically connected to the first source signal adapter SL1 and the second source signal adapter SL2, respectively. It is understood that the third source signal adapter SL3 can be directly electrically connected to the first source signal adapter SL1 via a metallized via VV, or indirectly electrically connected to the first source signal adapter SL1 via other metal layers. Similarly, the third source signal adapter SL3 can be directly electrically connected to the second source signal adapter SL2 via a metallized via VV, or indirectly electrically connected to the second source signal adapter SL2 via other metal layers.

[0127] In one embodiment of this disclosure, referring to FIG6, the driving voltage channel further includes a second driving voltage adapter DL2. The second driving voltage adapter DL2 spans the back gate structure BG and its two ends are electrically connected to the first driving voltage adapter DL1 and the data line DL, respectively. It is understood that the second driving voltage adapter DL2 can be directly electrically connected to the first driving voltage adapter DL1 via a metallized via VV, or indirectly electrically connected to the first driving voltage adapter DL1 via other metal layers. Similarly, the second driving voltage adapter DL2 can be directly electrically connected to the data line DL via a metallized via VV, or indirectly electrically connected to the data line DL via other metal layers.

[0128] In one embodiment of this disclosure, referring to Figures 6 and 12, the transistor unit MU includes multiple transistors connected in parallel. These transistors are arranged sequentially along the column direction DV, and the channel length of each transistor is along the row direction DH. Within the same transistor unit MU, the gates MG of each transistor are arranged linearly along the column direction DV, the first terminals MS of each transistor are arranged linearly along the column direction DV, and the second terminals MD of each transistor are arranged linearly along the column direction DV. The first drive voltage adapter line DL1 electrically connected to the transistor unit MU can extend along the column direction DV and is electrically connected to the second terminals MD of each transistor through a first metallized via V1.

[0129] Accordingly, referring to Figure 6, the second adapter line GL2 of the strobe signal electrically connected to the transistor unit MU can also extend along the column direction DV and be electrically connected to the gate MG of each transistor through the first metallized via V1.

[0130] Accordingly, referring to Figure 6, the source signal second adapter line SL2 of the transistor unit MU can also extend along the column direction DV and be electrically connected to the first pole MS of each transistor through the first metallized via V1.

[0131] In one embodiment of this disclosure, referring to Figures 6 and 12, the multiplexing circuit DM includes multiple transistor unit groups MUS, each transistor unit group MUS including two adjacent transistor units MU; the driving substrate BP is provided with a source-end signal second adapter line SL2 corresponding one-to-one with the transistor unit group MUS in the first decomposition circuit subregion DMA1, the source-end signal second adapter line SL2 being electrically connected to the first terminal MS of each transistor in the corresponding transistor unit group MUS. In other words, two transistor units MU in the same transistor unit group MUS can share the same source-end signal second adapter line SL2, thereby reducing the number of traces such as the source-end signal second adapter line SL2 and the source-end signal first adapter line SL1, which is beneficial for increasing the distribution density of the multiplexing circuit DM in the decomposition circuit region DMA and for reducing the coupling capacitance between the source signal channel and the gating signal channel.

[0132] In one example, referring to Figure 12, the transistor cell group MUS includes multiple transistor pairs MP arranged sequentially along the column direction DV. Each transistor pair MP includes transistors belonging to two transistor cells MU respectively, and the two transistors of the transistor pair MP share a first electrode. The two transistors of the transistor pair are arranged along the row direction DH.

[0133] In one example, referring to Figure 6, each transistor cell group MUS is connected to two gating signal second adapter lines GL2, two driving voltage first adapter lines DL1, and one source signal second adapter line SL2; along the row direction DH, the driving voltage first adapter line DL1, the gating signal second adapter line GL2, the source signal second adapter line SL2, the gating signal second adapter line GL2, and the driving voltage first adapter line DL1 are arranged in sequence, and these traces all extend in a straight line along the column direction DV.

[0134] In one example, referring to Figures 11 and 12, the semiconductor substrate SBT has an active region BAA corresponding one-to-one with a transistor pair in the first decomposition circuit subregion DMA1, with a transistor pair MP disposed within each active region BAA. In other words, the transistor pairs share the same active region. This allows for a more compact arrangement of the transistor pairs. For example, along the row direction DH, the active region includes a first doped region A1, a second doped region B1, a third doped region A2, a fourth doped region B2, and a fifth doped region A3 arranged sequentially. The first doped region A1, the third doped region A2, and the fifth doped region A3 can have the same doping type and be conductive, while the second doped region B1 and the fourth doped region B2 can have the opposite doping type to the first doped region A1 while maintaining semiconductor characteristics. When the first doped region A1, the third doped region A2, and the fifth doped region A3 are all N-type doped, and the second doped region B1 and the fourth doped region B2 are P-type doped, the transistor in this transistor pair is an N-type transistor, and the gating signal corresponding to the transistor unit MU is high. When the first doped region A1, the third doped region A2, and the fifth doped region A3 are all P-type doped, and the second doped region B1 and the fourth doped region B2 are N-type doped, the transistor in this transistor pair is a P-type transistor, and the strobe signal corresponding to the transistor unit MU is low.

[0135] The first doped region A1, the third doped region A2, and the fifth doped region A3 can be electrically connected to the first driving voltage adapter line DL1, the second source signal adapter line SL2, and the first driving voltage adapter line DL1 respectively through the first metallization via V1; the second doped region B1 and the fourth doped region B2 can be overlapped with the gates of the two transistors respectively, and overlapped with the second gating signal adapter lines GL2 respectively.

[0136] In one example, referring to Figure 6, the driving substrate BP includes data line groups DLS corresponding one-to-one with at least a portion of the transistor unit groups MUS. Each data line group DLS includes two non-adjacent data lines DL, and the pixel driving circuit PDC driven by the two data lines DL of the data line group DLS is used to drive sub-pixels of the same color. One data line DL of the data line group DLS is electrically connected to the second electrode MD of each transistor in one transistor unit MU of the corresponding transistor unit group MUS, and the other data line DL of the data line group DLS is electrically connected to the second electrode MD of each transistor in another transistor unit MU of the corresponding transistor unit group MUS.

[0137] For example, in the example of Figure 6, each multiplexer circuit DM drives six data lines DL. The six data lines DL are labeled as first data line DL(1), second data line DL(2), third data line DL(3), fourth data line DL(4), fifth data line DL(5), and sixth data line DL(6) in the order of their arrangement in the display area AA along the row direction DH. Among them, the sub-pixels driven by the first data line DL(1) and the fourth data line DL(4) are red sub-pixels, the sub-pixels driven by the second data line DL(2) and the fifth data line DL(5) are green sub-pixels, and the sub-pixels driven by the third data line DL(3) and the sixth data line DL(6) are blue sub-pixels. The multiplexer circuit DM includes three transistor unit groups MUS, and each transistor unit group MUS includes two transistor units MU. Along the row direction DH, the six transistor units MU are labeled as first transistor unit MU1, second transistor unit MU2, third transistor unit MU3, fourth transistor unit MU4, fifth transistor unit MU5, and sixth transistor unit MU6, respectively. In this configuration, the first transistor unit MU1 and the second transistor unit MU2 belong to the same transistor unit group MUS, and the first data line DL(1) and the fourth data line DL(4) belong to the same data line group DLS. The first transistor unit MU1 drives the first data line DL(1), and the second transistor unit MU2 drives the fourth data line DL(4). The third transistor unit MU3 and the fourth transistor unit MU4 belong to the same transistor unit group MUS, and the second data line DL(2) and the fifth data line DL(5) belong to the same data line group DLS. The third transistor unit MU3 drives the second data line DL(2), and the fourth transistor unit MU4 drives the fifth data line DL(5). The fifth transistor unit MU5 and the sixth transistor unit MU6 belong to the same transistor unit group MUS, and the third data line DL(3) and the sixth data line DL(6) belong to the same data line group DLS. The fifth transistor unit MU5 drives the third data line DL(3), and the sixth transistor unit MU6 drives the sixth data line DL(6).

[0138] In this embodiment, although the same transistor unit group MUS provides two different driving voltage channels, the sub-pixels PX driven by these two driving voltage channels are sub-pixels of the same color. Since the driving voltage range required for sub-pixels of the same color is consistent, the fluctuation range of the driving voltage is small, and the driving voltage fluctuation caused by the transistor to the common source region is relatively small, which helps to reduce crosstalk between the two driving voltage channels of the transistor unit group MUS.

[0139] In this embodiment, the gating signal line MUXL driving the multiplexing circuit DM corresponds one-to-one with the data line DL driven by the multiplexing circuit DM to ensure the correct driving algorithm. For example, the transistor unit MU controlled by the first gating signal line MUXL1 is used to drive the first data line DL (1), the transistor unit MU controlled by the second gating signal line MUXL2 is used to drive the second data line DL (2), the transistor unit MU controlled by the third gating signal line MUXL3 is used to drive the third data line DL (3), the transistor unit MU controlled by the fourth gating signal line MUXL4 is used to drive the fourth data line DL (4), the transistor unit MU controlled by the fifth gating signal line MUXL5 is used to drive the fifth data line DL (5), and the transistor unit MU controlled by the sixth gating signal line MUXL6 is used to drive the sixth data line DL (6). Therefore, it is necessary to determine the gating signal line MUXL that controls the transistor unit MU according to the data line DL driven by the transistor unit MU, and then change the connection order between the gating signal line MUXL and the transistor unit MU while keeping the position of the gating signal line MUXL unchanged.

[0140] For example, in the example of Figure 6, the first strobe signal line MUXL1 is electrically connected to the strobe signal first adapter line GL1 connected to the first transistor unit MU1; the fourth strobe signal line MUXL4 is electrically connected to the strobe signal first adapter line GL1 connected to the second transistor unit MU2; the second strobe signal line MUXL2 is electrically connected to the strobe signal first adapter line GL1 connected to the third transistor unit MU3; the fifth strobe signal line MUXL5 is electrically connected to the strobe signal first adapter line GL1 connected to the fourth transistor unit MU4; the third strobe signal line MUXL3 is electrically connected to the strobe signal first adapter line GL1 connected to the fifth transistor unit MU5; and the sixth strobe signal line MUXL6 is electrically connected to the strobe signal first adapter line GL1 connected to the sixth transistor unit MU6.

[0141] In one example, referring to Figures 6 and 22, the driving substrate BP has a transition area BA between the first decomposition circuit sub-region DMA1 and the display area AA. A third driving voltage transition line DL3 is provided within the transition area BA in the driving voltage channel. The third driving voltage transition line DL3 is used to electrically connect the second driving voltage transition line DL2 to the corresponding data line DL. Along the horizontal direction DH, the order of the second driving voltage transition lines DL2 of each transistor unit MU of the multiplexer DM may not be consistent with the order of the data lines DL that need to be electrically connected to each transistor unit MU of the multiplexer DM. Therefore, at least part of the third driving voltage transition line DL3 needs to be bent in the horizontal direction DH to ensure that the second driving voltage transition line DL2 and the data line DL within the same driving voltage channel are electrically connected.

[0142] It is understandable that the third adapter cable DL3 for some driving voltages may not be bent in the row direction DH, in order to ensure the electrical continuity of the driving voltage channel.

[0143] In one example, referring to Figures 6 and 22, the first drive voltage adapter line DL1 and the second drive voltage adapter line DL2 of the same drive voltage channel can be arranged in a straight line along the column direction DV. Thus, the arrangement order of the ends of the second drive voltage adapter line DL2 is consistent with the order of the drive voltages output by the multiplexer circuit DM.

[0144] In the examples of Figures 6 and 22, the third sub-transformer line DL3 of the driving voltage includes the first sub-transformer line DL31 corresponding to the first transistor unit MU1, the second sub-transformer line DL32 corresponding to the second transistor unit MU2, the third sub-transformer line DL33 corresponding to the third transistor unit MU3, the fourth sub-transformer line DL34 corresponding to the fourth transistor unit MU4, the fifth sub-transformer line DL35 corresponding to the fifth transistor unit MU5, and the sixth sub-transformer line DL36 corresponding to the sixth transistor unit MU6. Among them, the second driving voltage adapter DL2 corresponding to the first transistor unit MU1 is electrically connected to the first data line DL(1) through the first sub-adapter DL31; the second driving voltage adapter DL2 corresponding to the second transistor unit MU2 is electrically connected to the fourth data line DL(4) through the second sub-adapter DL32; the second driving voltage adapter DL2 corresponding to the third transistor unit MU3 is electrically connected to the second data line DL(2) through the third sub-adapter DL33; the second driving voltage adapter DL2 corresponding to the fourth transistor unit MU4 is electrically connected to the fifth data line DL(5) through the fourth sub-adapter DL34; the second driving voltage adapter DL2 corresponding to the fifth transistor unit MU5 is electrically connected to the third data line DL(3) through the fifth sub-adapter DL35; and the second driving voltage adapter DL2 corresponding to the sixth transistor unit MU6 is electrically connected to the sixth data line DL(6) through the sixth sub-adapter DL36.

[0145] The following describes, using the multiplexing circuit DM illustrated in Figure 6 as an example, an exemplary driving method for the multiplexing circuit DM provided in this disclosure. Figure 7 is a schematic diagram of a driving timing for the multiplexing circuit DM. It is understood that the multiplexing circuit DM illustrated in Figure 6 can also be driven using other timing sequences.

[0146] Referring to Figure 7, within a display frame (from one horizontal sync signal HSYNC to another), the source signal line SL is sequentially loaded with reset voltage Vofs, first driving voltage S1, second driving voltage S2, third driving voltage S3, fourth driving voltage S4, fifth driving voltage S5, and sixth driving voltage S6 during time periods t0 to t6. At time t0, the first gating signal line MUXL1 to the sixth gating signal line MUXL6 are simultaneously loaded with gating signals (in the example of Figure 7, the gating signals are low-level signals), which causes the first transistor unit MU1 to the sixth transistor unit MU6 to conduct simultaneously, so that the pixel driving circuit PDC on the six data lines DL driven by the multiplexing circuit DM is synchronously reset. At time t1, the first gating signal line MUXL1 is loaded with a gating signal, which causes the first transistor unit MU1 to conduct, and the first driving voltage S1 on the source signal line SL is applied to the data lines DL driven by the first transistor unit MU1. At time t2, the second strobe signal line MUXL2 is strobe-enabled, turning on the second transistor unit MU2. The second driving voltage S2 on the source signal line SL is applied to the data line DL driven by the second transistor unit MU2. Similarly, at time t3, the third strobe signal line MUXL3 is strobe-enabled, turning on the third transistor unit MU3. The third driving voltage S3 on the source signal line SL is applied to the data line DL driven by the third transistor unit MU3. At time t4, the fourth strobe signal line MUXL4 is strobe-enabled, turning on the fourth transistor unit MU4. The fourth driving voltage S4 on the source signal line SL is applied to the data line DL driven by the fourth transistor unit MU4. At time t5, the fifth strobe signal line MUXL5 is strobe-enabled, turning on the fifth transistor unit MU5. The fifth driving voltage S5 on the source signal line SL is applied to the data line DL driven by the fifth transistor unit MU5. At time t6, the sixth strobe signal line MUXL6 is loaded with a strobe pad, the sixth transistor unit MU6 is turned on, and the sixth drive voltage S6 on the source signal line SL is applied to the data line DL driven by the sixth transistor unit MU6.

[0147] In one example, the driving substrate BP can be fabricated using a wafer fabrication process, such as a semiconductor process with a diameter of 0.04 to 0.4 micrometers, or a semiconductor process with a diameter of 0.11 micrometers.

[0148] In one example, the width-to-length ratio of the transistor's channel region can be 4:1 to 8:1, for example, 5:1.

[0149] In one example, the display panel PNL provided in this disclosure can provide a refresh rate of 90Hz or higher, such as 120Hz, 144Hz or 180Hz, by reducing the impact of the multiplexing circuit DM on the refresh rate.

[0150] For example, the display panel PNL provided in this disclosure can provide a 120Hz refresh rate display capability when the resolution reaches 4K (e.g., 3956 PPI or above), and the picture is stable and smooth. It can reduce the dizziness in VR applications and the screen door effect in AR applications, greatly increase the immersion and improve the user experience.

[0151] Figures 8 to 22 illustrate specific film layer arrangements for the multiplexer circuit DM shown in Figure 6. Using the examples in Figures 8 to 22 as examples, the arrangement of the multiplexer circuit DM on the driving substrate BP according to this embodiment will be described exemplarily. In the examples in Figures 8 to 22, only one multiplexer circuit DM and its associated signal channels are shown.

[0152] Referring to Figures 8 to 22, in the decomposed circuit region DMA, the driving substrate BP includes at least a semiconductor substrate SBT, a gate insulating layer GI, a gate layer GT, a first insulating layer D1, a first metal layer M1, a second insulating layer D2, a second metal layer M2, a third insulating layer D3, a third metal layer M3, a fourth insulating layer D4, and a fourth metal layer M4, which are stacked sequentially.

[0153] Referring to Figures 8-12, the semiconductor substrate SBT is doped to form the active region BAA and back gate doped region BG1 corresponding to each transistor pair MP within the first decomposition circuit subregion DMA1. Each active region BAA is divided into a first doped region A1, a second doped region B1, a third doped region A2, a fourth doped region B2, and a fifth doped region A3. Further doping (e.g., ion implantation after the formation of the gate layer GT) allows each doped region to acquire the desired doping characteristics. The gate layer GT forms the gate MG of each transistor. The transistors within the same transistor unit MU share a common gate, meaning the gate MGs of the transistors within the same transistor unit MU are directly connected. The transistor gate MG can overlap with either the second doped region B1 or the fourth doped region B2 to protect the second doped region B1 and the fourth doped region B2 during ion implantation after the formation of the gate layer GT.

[0154] In this process, the doped region of the semiconductor substrate SBT, together with the gate insulating layer GI and the gate layer GT, forms a transistor layer, enabling the arrangement of the transistor units MU within the decomposed circuit region DMA.

[0155] Referring to Figures 13-22, the first metal layer M1 to the fourth metal layer M4 are used to route the various traces to load signals onto the multiplexing circuit DM and to enable the multiplexing circuit DM to output signals. In this example, these traces are mainly distributed on the first metal layer M1 and the third metal layer M3, while the second metal layer M2 and the fourth metal layer M4 are mainly used for signal switching. Furthermore, in this example, the data line DL is located on the fourth metal layer M4.

[0156] In this example, the first metal layer M1 is provided with a back gate trace BG2 that substantially overlaps with the back gate doped region BG1. The back gate doped region BG1 and the back gate trace BG2 are electrically connected through a first metallized via V1 to form the back gate structure BG.

[0157] In this example, the source signal channel includes a source signal line SL, a first source signal adapter SL1, a fourth source signal adapter SL4, a third source signal adapter SL3, a fifth source signal adapter SL5, and a second source signal adapter SL2 connected in sequence, and finally connected to the first terminal MS of the transistor. The source signal line SL is located on the side of the decomposition circuit region DMA away from the display area AA and is disposed on the first metal layer M1; the first source signal adapter SL1 has a side branch at its end near the decomposition circuit region DMA. The first source signal adapter SL1 is disposed on the first metal layer M1 and located in the second decomposition circuit subregion DMA2, and its end near the source signal line SL is connected to the side branch of the source signal line SL. After extending to near the back gate structure BG, the source signal line SL is connected to the fourth source signal adapter SL4 located on the second metal layer M2 through the second metallized via V2; the fourth source signal adapter SL4 is connected to the third source signal adapter SL3 located on the third metallized via V3. The third source signal adapter SL3 spans the back gate structure BG, specifically across the first decomposition circuit subregion DMA1 and the second decomposition circuit subregion DMA2. The end of the third source signal adapter SL3 located in the first decomposition circuit subregion DMA1 is connected via a third metallized via V3 to the fifth source signal adapter SL5 located on the second metallized layer M2. The fifth source signal adapter SL5 is connected via a second metallized via V2 to the second source signal adapter SL2 located in the first decomposition circuit subregion DMA1 and on the first metallized layer M1. The second source signal adapter SL2 is electrically connected to the first terminal MS of the transistor via a first metallized via V1.

[0158] In this example, the gating signal channel includes a gating signal line MUXL, a fourth gating signal adapter GL4, a first gating signal adapter GL1, a fifth gating signal adapter GL5, a third gating signal adapter GL3, a sixth gating signal adapter GL6, and a second gating signal adapter GL2 connected in sequence, and finally connected to the gate MG of the transistor. The gating signal line MUXL is located in the second decomposition circuit subregion DMA2 and extends along the row direction DH; the gating signal line MUXL is disposed on the third metal layer M3. The gating signal line MUXL is electrically connected to the fourth gating signal adapter GL4 located on the second metal layer M2 through the third metallized via V3, and the fourth gating signal adapter GL4 is electrically connected to the first gating signal adapter GL1 located on the first metal layer M1 through the second metallized via V2. The first gating signal adapter GL1 extends along the column direction DV to near the back gate structure BG. The end of the first gating signal adapter GL1 near the back gate structure BG is electrically connected to the fifth gating signal adapter GL5 located in the second metallized layer M2 via the second metallized via V2. The fifth gating signal adapter GL5 is electrically connected to the third gating signal adapter GL3 located in the third metallized layer M3 via the third metallized via V3. The third gating signal adapter GL3 crosses the back gate structure BG, with one end located in the first decomposition circuit subregion DMA1 and the other end located in the second decomposition circuit subregion DMA2. The third strobe signal adapter GL3 is located at the end of the first decomposition circuit subregion DMA1 and is electrically connected to the sixth strobe signal adapter GL6 located in the second metal layer M2 through the third metallized via V3. The sixth strobe signal adapter GL6 is electrically connected to the second strobe signal adapter GL2 located in the first metal layer M1 through the second metallized via V2. The second strobe signal adapter GL2 is electrically connected to the gate MG of the transistor through the first metallized via V1.

[0159] In this example, the first transistor unit MU1 drives the first data line DL (1), thus electrically connecting the first strobe signal adapter GL1 to the first strobe signal line MUXL1. The second transistor unit MU2 drives the fourth data line DL (4), thus electrically connecting the first strobe signal adapter GL1 to the second strobe signal line MUXL4. The third transistor unit MU3 drives the second data line DL (2), thus electrically connecting the first strobe signal adapter GL1 to the third strobe signal line MUXL2. The fourth transistor unit MU4 drives the fifth data line DL (5), thus electrically connecting the first strobe signal adapter GL1 to the fourth strobe signal line MUXL5. The fifth transistor unit MU5 drives the third data line DL (3), thus electrically connecting the first strobe signal adapter GL1 to the fifth strobe signal line MUXL5. The sixth transistor unit MU6 is used to drive the sixth data line DL(6), thus making the first adapter line GL1 of the strobe signal electrically connected to the sixth transistor unit MU6 electrically connected to the sixth strobe signal line MUXL6. In this way, the source drive circuit can output signals according to the arrangement order of the data lines DL in the display area AA without changing the drive algorithm; the multiplexing circuit DM loads the source signal to the corresponding data line DL through hardware conversion.

[0160] In this example, the driving voltage channel includes the second terminal MD of the transistor, the first driving voltage adapter line DL1, the first adapter pad DLP1, the second adapter pad DLP2, the second driving voltage adapter line DL2, and the data line DL, which are connected in sequence. A third driving voltage adapter line DL3 is provided between the second driving voltage adapter line DL2 and the data line DL, as well as the necessary structure for electrically connecting the third driving voltage adapter line DL3 with the second driving voltage adapter line DL2 and the data line DL.

[0161] The first driving voltage adapter line DL1 is disposed on the first metal layer M1 and located in the first sub-region DMA1 of the decomposition circuit. It is electrically connected to the second terminal MD of the transistor through the first metallized via V1. The first driving voltage adapter line DL1 extends to the end near the back gate structure BG (near the end near the display area AA), and is then connected to the first adapter pad DLP1 located on the second metal layer M2 through the second metallized via V2. The first adapter pad DLP1 is connected to the second adapter pad DLP2 located on the third metal layer M3 through the third metallized via V3. The second adapter pad DLP2 is connected to the second driving voltage adapter line DL2 located on the fourth metal layer M4 through the fourth metallized via V4. The second driving voltage adapter line DL2 crosses the back gate structure BG; that is, one end of the second driving voltage adapter line DL2 is located in the first sub-region DMA1 of the decomposition circuit, and the other end extends to the adapter area BA. The data line DL is disposed on the fourth metal layer M4.

[0162] The driving voltage channel connected to the first transistor unit MU1 includes the first sub-transformer DL31 located in the fourth metal layer M4. The second driving voltage transformer DL2, the first sub-transformer DL31, and the first data line DL(1) are all located in the fourth metal layer M4 and are directly connected in sequence.

[0163] The driving voltage channel connected to the second transistor unit MU2 also includes the third adapter pad DLP3, the fourth adapter pad DLP4, the second sub-adapter pad DL32, the fifth adapter pad DLP5, and the sixth adapter pad DLP6, which are connected sequentially starting from the second adapter line DL2 of the driving voltage. Among them, the second adapter line DL2 of the driving voltage is connected to the third adapter pad DLP3 located in the third metal layer M3 through the fourth metallized via V4 at the end of the adapter area BA. The third adapter pad DLP3 is connected to the fourth adapter pad DLP4 located in the second metal layer M2 through the third metallized via V3. The fourth adapter pad DLP4 is connected to the second sub-adapter line DL32 located in the first metal layer M1 through the second metallized via V2. The second sub-adapter line DL32 extends along the row direction DH to the position corresponding to the fourth data line DL(4), and is connected to the fifth adapter pad DLP5 located in the second metal layer M2 through the second metallized via V2. The fifth adapter pad DLP5 is transferred to the sixth adapter pad DLP6 located in the third metal layer M3 through the third metallized via V3. The sixth adapter pad DLP6 is transferred to the fourth data line DL(4) through the fourth metallized via V4.

[0164] The driving voltage channel connected to the third transistor unit MU3 also includes the third sub-transformer DL33 located in the fourth metal layer M4. The second driving voltage transformer DL2, the third sub-transformer DL33, and the second data line DL(2) are directly connected in sequence.

[0165] The driving voltage channel connected to the fourth transistor unit MU4 also includes the fourth sub-transformer DL34 located in the fourth metal layer M4. The second driving voltage transformer DL2, the fourth sub-transformer DL34, and the fifth data line DL(5) are directly connected in sequence.

[0166] The drive voltage channel connected to the fifth transistor unit MU5 also includes the seventh adapter pad DLP7, the eighth adapter pad DLP8, the fifth sub-adapter pad DL35, the ninth adapter pad DLP9, and the tenth adapter pad DLP10, which are connected sequentially starting from the second adapter line DL2 of the drive voltage. The second adapter line DL2 of the driving voltage is connected to the seventh adapter pad DLP7 located in the third metal layer M3 through the fourth metallized via V4 at the end of the adapter area BA. The seventh adapter pad DLP7 is connected to the eighth adapter pad DLP8 located in the second metal layer M2 through the third metallized via V3. The eighth adapter pad DLP8 is connected to the fifth sub-adapter line DL35 located in the first metal layer M1 through the second metallized via V2. The fifth sub-adapter line DL35 is connected to the end of the third data line DL(3) and then connected to the ninth adapter pad DLP9 located in the second metal layer M2 through the second metallized via V2. The ninth adapter pad DLP9 is connected to the tenth adapter pad DLP10 located in the third metal layer M3 through the third metallized via V3. The tenth adapter pad DLP10 is connected to the third data line DL(3) located in the fourth metal layer M4 through the fourth metallized via V4.

[0167] The driving voltage channel connected to the sixth transistor unit MU6 also includes the sixth sub-transformer DL36 located on the fourth metal layer M4. The second driving voltage transformer DL2, the sixth sub-transformer DL36, and the sixth data line DL(6) are directly connected in sequence.

[0168] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A driving substrate, comprising a display area and a decomposition circuit area; the display area is provided with data lines for applying data voltage to a pixel driving circuit; the decomposition circuit area includes a first decomposition circuit sub-region and a second decomposition circuit sub-region located on the side of the first decomposition circuit sub-region away from the display area; In the first decomposition circuit subregion, the driving substrate is provided with a plurality of multiple decomposition circuits arranged along the row direction, each multiple decomposition circuit including a plurality of transistor units; the first terminal of each transistor in the same multiple decomposition circuit is electrically connected to the same source signal line, and the second terminal of each transistor in the same transistor unit is electrically connected to the same data line. The second decomposition circuit subregion has multiple gating signal lines that correspond one-to-one with multiple transistor units in the multiplex decomposition circuit and extend along the row direction. The gate of each transistor in the transistor unit is electrically connected to the corresponding gating signal line.

2. The drive substrate according to claim 1, wherein The dimension of the multiplexing circuit along the column direction is the first dimension; the distance between the edge of the gating signal line closest to the display area and the edge of the gating signal line furthest from the display area is the second dimension; the second dimension is greater than the first dimension.

3. The drive substrate according to claim 2, wherein The width of the strobe signal line is greater than half the width of the channel region of the transistor in the multiplexing circuit.

4. The drive substrate according to claim 1, wherein The driving substrate includes a transistor layer and multiple metal layers stacked sequentially; the transistor layer and the first metal layer are electrically connected through metallized vias, and two adjacent metal layers are electrically connected through metallized vias. In the second decomposition circuit subregion, the driving substrate is provided with a first transfer line for gating signals corresponding to each transistor unit. The first transfer line for gating signals extends along the column direction and is electrically connected to the gate of each transistor in the corresponding transistor unit. There is at least one metal layer between the metal layer where the first adapter wire of the strobe signal is located and the metal layer where the strobe signal line is located.

5. The drive substrate according to claim 4, wherein The first adapter wire for the gating signal is arranged to overlap with each of the gating signal lines.

6. The drive substrate according to claim 4, wherein A fourth selector signal adapter is provided between the first selector signal adapter and the electrically connected selector signal line. The first selector signal adapter is electrically connected to the corresponding selector signal line through the fourth selector signal adapter. When the metal layer where the fourth selector signal adapter is located is adjacent to the metal layer where the first selector signal adapter is located, the first selector signal adapter and the fourth selector signal adapter are electrically connected to each other through at least two columns of metallized vias. Each column of metallized vias includes at least three metallized vias arranged sequentially along the column direction.

7. The drive substrate according to claim 4, wherein The first metal layer has a second gating signal adapter line in the first decomposition circuit subregion that corresponds one-to-one with each transistor unit. The second gating signal adapter line is electrically connected to the gate of each transistor in the corresponding transistor unit through a metallized via. The second adapter wire for the strobe signal has a via portion for connection with a metallized via and a trace portion for connection with the via portion; the width of the trace portion of the second adapter wire for the strobe signal is smaller than the width of the first adapter wire for the strobe signal.

8. The drive substrate according to claim 1, wherein The driving substrate includes a transistor layer and multiple metal layers stacked sequentially; the transistor layer is electrically connected to the first metal layer through metallized vias, and adjacent metal layers are electrically connected to each other through metallized vias. In the second decomposition circuit subregion, the driving substrate is provided with a source signal first adapter line extending along the column direction. One end of the source signal first adapter line is electrically connected to the source signal line, and the other end is electrically connected to the first electrode of each transistor of at least one transistor unit. There is at least one metal layer between the metal layer where the first adapter line of the source signal is located and the metal layer where the strobe signal line is located.

9. The drive substrate according to claim 1, wherein The transistor unit includes multiple transistors connected in parallel, each transistor being arranged sequentially along the column direction, and the channel length direction of each transistor being the row direction; The driving substrate has a first driving voltage adapter line that corresponds one-to-one with the transistor unit and extends along the column direction in the first decomposition circuit subregion. The first driving voltage adapter line is electrically connected to the second electrode of each transistor in the transistor unit and is also electrically connected to the data line.

10. The drive substrate according to claim 1, wherein The multiplexing circuit includes multiple transistor unit groups, and each transistor unit group includes two adjacent transistor units. The driving substrate has a source signal second adapter wire in the first decomposition circuit subregion that corresponds one-to-one with the transistor unit group. The source signal second adapter wire is electrically connected to the first electrode of each transistor in the corresponding transistor unit group.

11. The drive substrate according to claim 10, wherein The driving substrate includes a data line group that corresponds one-to-one with at least a portion of the transistor unit groups. The data line group includes two non-adjacent data lines, and the pixel driving circuit driven by the two data lines of the data line group is used to drive sub-pixels of the same color. One data line of the data line group is electrically connected to the second electrode of each transistor in a transistor unit of the corresponding transistor unit group, and the other data line of the data line group is electrically connected to the second electrode of each transistor in another transistor unit of the corresponding transistor unit group.

12. The drive substrate according to any one of claims 1 to 11, wherein The first decomposition circuit subregion has a ring-shaped back gate structure, and each of the multiplex decomposition circuits is located within the space surrounded by the back gate structure. The gating signal line is located on the side of the back grid structure away from the display area.

13. The drive substrate according to claim 12, wherein, The driving substrate includes a semiconductor substrate and multiple metal layers stacked sequentially. The back gate structure includes an annular back gate doped region located on the semiconductor substrate and a back gate trace located on the first metal layer. The back gate trace is electrically connected to the back gate doped region through a metallized via. The driving substrate is further provided with a metal structure that spans the back gate structure, and the metal layer where the metal structure spanning the back gate structure is located is spaced apart from the first metal layer by at least one metal layer.

14. A display panel comprising the driving substrate according to any one of claims 1 to 13.

15. A display device comprising the display panel of claim 14.

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