Heterojunction semiconductor device

Abstract

The present application relates to a heterojunction semiconductor device, comprising: a substrate; a channel layer located on the substrate; a barrier layer located on the channel layer; a gate structure located on the barrier layer; a source electrode located on the barrier layer; a drain electrode located on the barrier layer, wherein the gate structure is located between the source electrode and the drain electrode; and a stacked semiconductor, which comprises a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer form a target heterojunction at the junction therebetween, the stacked semiconductor is located between the gate structure and the drain electrode, and the target heterojunction is electrically connected to the drain electrode. The target heterojunction of the stacked semiconductor of the present invention serves as an electrically conductive channel to guide the potential of the drain electrode toward the gate structure, thereby achieving the effect of alleviating the dynamic resistance phenomenon.

Description

Heterojunction semiconductor devices Cross-references to related applications

[0001] This patent application claims priority to Chinese Patent Application No. 202411963827.2, filed on December 27, 2024, entitled "Heterojunction Semiconductor Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to semiconductor devices, and more particularly to a heterojunction semiconductor device. Background Technology

[0003] Third-generation semiconductors, also known as wide-bandgap semiconductors, have characteristics such as wide bandgap, high breakdown electric field, high electron mobility, and high thermal conductivity. Among them, heterojunction semiconductor devices have advantages over silicon devices, such as low on-resistance and fast response speed, making them suitable for use in high-frequency and high-temperature power circuits.

[0004] Taking the common AlGaN / GaN (AlGaN / GaN) heterojunction transistor as an example, due to spontaneous polarization and piezoelectric polarization, a two-dimensional electron gas (2DEG) with high mobility and high electron saturation velocity is generated on the upper surface of GaN (i.e., near the interface between GaN and AlGaN), which normally behaves as a depletion-mode device. By using p-GaN (p-type doped gallium nitride) material as the gate of the device, enhancement-mode devices can be realized.

[0005] Traditional heterojunction high electron mobility transistors (HEMTs) have long suffered from a significant trapping effect due to limitations in epitaxial structure and growth processes. Specifically, when a high voltage is applied to the drain of a heterojunction semiconductor device, the high electric field induces electrons at the channel to be trapped at the interface, resulting in a decrease in the current during device conduction and an increase in on-resistance. Simultaneously, when the drain is subjected to a high voltage, the high electric field at the drain electrode corner induces hot carrier injection, further exacerbating the dynamic resistance phenomenon. Summary of the Invention

[0006] Therefore, it is necessary to provide a heterojunction semiconductor device that can alleviate the dynamic resistance phenomenon.

[0007] A heterojunction semiconductor device includes: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a gate structure on the barrier layer; a source electrode on the barrier layer; a drain electrode on the barrier layer; the gate structure being located between the source electrode and the drain electrode; and a stacked semiconductor including a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer form a target heterojunction at their junction; the stacked semiconductor being located between the gate structure and the drain electrode, and the target heterojunction being electrically connected to the drain electrode.

[0008] The aforementioned heterojunction semiconductor device has a stacked semiconductor between the gate structure and the drain electrode. The target heterojunction formed therein serves as a conductive channel, guiding the potential of the drain electrode toward the gate structure. This adjusts the distribution of electric field lines when the drain electrode is subjected to voltage, which can mitigate the electric field peak at the corner of the drain electrode, reduce hot carrier injection, and weaken the trapping effect of interface traps on channel electrons, thereby alleviating the dynamic resistance phenomenon.

[0009] In one embodiment, the source electrode forms an ohmic contact with the barrier layer; the drain electrode forms an ohmic contact with the barrier layer.

[0010] In one embodiment, the material of the first semiconductor layer is different from that of the second semiconductor layer, and both the first semiconductor layer and the second semiconductor layer are made of III-V group compounds.

[0011] In one embodiment, the material of the stacked semiconductor includes any two of gallium nitride, aluminum gallium nitride, gallium indium arsenide, aluminum gallium arsenide, and indium aluminum arsenide, or any combination of different components and doping of one material.

[0012] In one embodiment, the heterojunction semiconductor device further includes a source field plate electrically connected to the source electrode, the source field plate extending from the source electrode over the gate structure.

[0013] In one embodiment, the heterojunction semiconductor device further includes: a first passivation layer located on the barrier layer and covering the surface of the barrier layer away from the channel layer; and a second passivation layer located on the first passivation layer and covering the gate structure, source electrode, drain electrode, source field plate, and stacked semiconductor, wherein the source field plate and the gate structure are separated by the second passivation layer.

[0014] In one embodiment, the bottom of the first semiconductor layer and the top of the barrier layer are separated by the first passivation layer.

[0015] In one embodiment, the first passivation layer is not disposed between the bottom of the first semiconductor layer and the top of the barrier layer.

[0016] In one embodiment, the first semiconductor layer and / or the second semiconductor layer is a stepped structure of at least two layers.

[0017] In one embodiment, the stepped structure is high on the side near the gate structure and low on the side near the drain electrode.

[0018] In one embodiment, the gate structure includes a P-type semiconductor cap located on the barrier layer and a gate electrode located on the P-type semiconductor cap.

[0019] In one embodiment, the gate electrode forms an ohmic contact or a Schottky contact with the P-type semiconductor cap.

[0020] In one embodiment, the material of the P-type semiconductor cap includes any one or more combinations of P-type gallium nitride (GaN), P-type aluminum nitride (AlN), P-type aluminum gallium nitride (AlGaN), P-type indium gallium nitride (InGaN), P-type aluminum indium gallium nitride (AlInGaN), and P-type aluminum indium nitride (AlInN).

[0021] In one embodiment, the substrate includes a substrate and a buffer layer on the substrate.

[0022] In one embodiment, the substrate further includes a nucleation layer located between the substrate and the buffer layer.

[0023] In one embodiment, the substrate is any one or a combination of at least two of Si, SiC, and sapphire.

[0024] In one embodiment, the heterojunction semiconductor device is a high electron mobility transistor. Attached Figure Description

[0025] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0026] Figure 1 is a schematic diagram of the structure of a heterojunction semiconductor device in one embodiment of this application.

[0027] Figure 2 is a schematic diagram of a heterojunction semiconductor device as a comparative example.

[0028] Figure 3 is a simulation comparison diagram of the heterojunction semiconductor devices shown in Figure 1 and Figure 2 under a high electric field.

[0029] Figure 4 is a schematic diagram of the structure of a heterojunction semiconductor device in another embodiment of this application.

[0030] Figure 5 is a schematic diagram of the structure of a heterojunction semiconductor device in another embodiment of this application. Detailed Implementation

[0031] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0033] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0034] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0036] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0037] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0038] Figure 1 is a schematic diagram of a heterojunction semiconductor device according to an embodiment of this application, including a substrate 110, a channel layer 120, a barrier layer 130, a source electrode 142, a drain electrode 144, a gate structure 150, and a stacked semiconductor 160. The channel layer 120 is located on the substrate 110. The barrier layer 130 is located on the channel layer 120. The source electrode 142, drain electrode 144, and gate structure 150 are located on the barrier layer 130. The source electrode 142 and the barrier layer 130 form an ohmic contact, and the drain electrode 144 and the barrier layer 130 form an ohmic contact. The gate structure 150 is located between the source electrode 142 and the drain electrode 144. The stacked semiconductor 160 is located on the barrier layer 130 and includes a first semiconductor layer 162 and a second semiconductor layer 164 located on the first semiconductor layer 162. The first semiconductor layer 162 is located on the barrier layer 130. The first semiconductor layer 162 and the second semiconductor layer 164 form a target heterojunction at their junction, thereby serving as a conductive channel. The stacked semiconductor 160 is located between the gate structure 150 and the drain electrode 144, and the target heterojunction is electrically connected to the drain electrode 144.

[0039] The aforementioned heterojunction semiconductor device has a stacked semiconductor 160 disposed between the gate structure 150 and the drain electrode 144. The target heterojunction formed therein serves as a conductive channel, guiding the potential of the drain electrode 144 toward the gate structure 150. This adjusts the distribution of electric field lines when the drain electrode 144 is subjected to voltage, thus mitigating the electric field peak at the corner of the drain electrode, reducing hot carrier injection, and weakening the trapping effect of interface traps on channel electrons. This also helps to alleviate the dynamic resistance phenomenon (i.e., to alleviate the phenomenon of increased on-resistance of the device when a high voltage is applied to the drain electrode 144).

[0040] Specifically, the stacked semiconductor 160 can achieve horizontal and vertical electric field modulation without changing the basic electrical characteristics of the device, reducing hot carrier injection caused by electric field line accumulation. Depending on the material used, the stacked semiconductor 160 can form a two-dimensional electron gas layer or a two-dimensional hole gas layer between the first semiconductor layer 162 and the second semiconductor layer 164. In the embodiment of forming a two-dimensional hole gas layer, when the drain electrode 144 is subjected to a high voltage, holes are injected into the conductive channel, releasing the trapped electrons. In the embodiment of forming a two-dimensional electron gas layer, when the drain electrode 144 is subjected to a high voltage, the two-dimensional electron gas has a shielding effect on the channel electrons, which can reduce the trapping effect of interface traps on the channel electrons. That is, in addition to the two-dimensional electron gas channel formed between the barrier layer 130 and the channel layer 120, the first semiconductor layer 162 and the second semiconductor layer 164 also form an additional two-dimensional electron gas or two-dimensional hole gas channel to extract the potential and modulate the electric field distribution of the drain electrode 144. The two-dimensional electron gas or two-dimensional hole gas formed by the multilayer semiconductor 160 modulates the electric field distribution in the horizontal and vertical directions, reducing the peak electric field of the drain electrode 144. The two-dimensional electron gas or two-dimensional hole gas formed by the multilayer semiconductor 160 can also reduce the trapping of channel electrons by traps, enhancing device stability.

[0041] In one embodiment of this application, the material of the first semiconductor layer 162 is different from that of the second semiconductor layer 164, and both the first semiconductor layer 162 and the second semiconductor layer 164 are made of group III-V compounds. Group III-V compounds refer to compounds formed by elements of group III and group V in the periodic table. In one embodiment of this application, the material of the stacked semiconductor 160 includes any two of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and indium aluminum arsenide (InAlAs), or any combination of different components and doping of any one material. That is, the first semiconductor layer 162 is one of the above materials, and the second semiconductor layer 164 is another of the above materials; or the first semiconductor layer 162 and the second semiconductor layer 164 are the same material, but with different components and / or doping. The materials of both the first semiconductor layer 162 and the second semiconductor layer 164 are group III-V compounds, which is compatible with traditional heterojunction semiconductor process structures. The materials of the first semiconductor layer 162 and the second semiconductor layer 164 can be the same as the materials of the channel layer 120 and the barrier layer 130.

[0042] In one embodiment of this application, the gate structure 150 includes a P-type semiconductor cap 152 located on the barrier layer 130 and a gate electrode 154 located on the P-type semiconductor cap 152. The gate electrode 154 forms an ohmic contact or a Schottky contact with the P-type semiconductor cap 152.

[0043] In one embodiment of this application, the material of the P-type semiconductor cap 152 includes any one or more combinations of P-type gallium nitride (GaN), P-type aluminum nitride (AlN), P-type aluminum gallium nitride (AlGaN), P-type indium gallium nitride (InGaN), P-type aluminum indium gallium nitride (AlInGaN), and P-type aluminum indium nitride (AlInN).

[0044] In one embodiment of this application, the heterojunction semiconductor device further includes a source field plate 143 electrically connected to the source electrode 142. The source field plate 143 extends from the source electrode 142 over the gate structure 150.

[0045] In one embodiment of this application, the heterojunction semiconductor device further includes a first passivation layer 172 and a second passivation layer 174. The first passivation layer 172 is located on the barrier layer 130 and covers the surface of the barrier layer 130 away from the channel layer 120 (i.e., the upper surface of the barrier layer 130). The second passivation layer 174 is located on the first passivation layer 172 and covers the gate structure 150, the source electrode 142, the drain electrode 144, the source field plate 143, and the stacked semiconductor 160. The source field plate 143 and the gate structure 150 are separated by the second passivation layer 174.

[0046] In one embodiment of this application, the substrate 110 includes a substrate 112 and a buffer layer 116 located on the substrate 112.

[0047] In one embodiment of this application, the substrate 112 is made of any one or a combination of at least two of Si, SiC and sapphire.

[0048] By selecting a material with suitable energy levels for the buffer layer 116, the energy level matching between the channel layer 120 and the substrate 112 can be adjusted, thereby optimizing the electronic transport characteristics of the transistor. Simultaneously, by selecting appropriate buffer layer materials and thicknesses, the carrier concentration of the heterojunction formed at the interface between the channel layer 120 and the barrier layer 130 can be adjusted, further optimizing the transistor's conductivity characteristics.

[0049] In the embodiment shown in FIG1, the substrate 110 further includes a nucleation layer 114 located between the substrate 112 and the buffer layer 116. The main function of the nucleation layer 114 is to control the nucleation process of material growth and promote more uniform, orderly and consistent growth of material on the substrate 112.

[0050] In one embodiment of this application, the heterojunction semiconductor device is a high electron mobility transistor (HEMT).

[0051] Figure 2 is a schematic diagram of a heterojunction semiconductor device as a comparative example. The difference between this device and the one shown in Figure 1 is the absence of the stacked semiconductor 160. Figure 3 is a simulation comparison diagram of the heterojunction semiconductor devices shown in Figures 1 and 2 under a high electric field (Vds = 350V). In Figure 3, the horizontal axis X represents the horizontal position, and the vertical axis Y represents the electric field value. The solid line 101 represents the simulation curve of the heterojunction semiconductor device provided in the embodiment of the present invention, and the dashed line 102 represents the simulation curve of the heterojunction semiconductor device provided in the comparative example. In Figure 3, X = 0 represents the edge position of the device's gate electrode facing the drain electrode, and X = 1.0 μm represents the edge position of the device's drain electrode facing the gate electrode. The boxes indicated by the arrows enlarge the horizontal and vertical axes (the horizontal axis is enlarged by a larger proportion than the vertical axis). As shown in Figure 3, compared to the heterojunction semiconductor device shown in Figure 2, the electric field near the drain electrode of the heterojunction semiconductor device shown in Figure 1 shifts towards the edge of the stacked semiconductor 160 when Vds = 350V blocking, and the peak electric field of the drain electrode decreases by approximately 0.3 × 10⁻⁶. 6 V / cm.

[0052] In the embodiment shown in FIG1, the bottom of the first semiconductor layer 162 and the top of the barrier layer 130 are separated by a first passivation layer 172.

[0053] Figure 4 is a schematic diagram of a heterojunction semiconductor device according to another embodiment of this application, which also includes a substrate 110, a channel layer 120, a barrier layer 130, a source electrode 142, a source field plate 143, a drain electrode 144, a gate structure 150, a multilayer semiconductor 160, a first passivation layer 172, and a second passivation layer 174. The substrate 110 includes a substrate 112, a nucleation layer 114 on the substrate 112, and a buffer layer 116 on the nucleation layer 114. The gate structure 150 includes a P-type semiconductor cap 152 on the barrier layer 130 and a gate electrode 154 on the P-type semiconductor cap 152. The multilayer semiconductor 160 includes a first semiconductor layer 162 and a second semiconductor layer 164 on the first semiconductor layer 162. The barrier layer 130 is located on the channel layer 120. The source electrode 142, the drain electrode 144, and the gate structure 150 are located on the barrier layer 130. Source electrode 142 forms an ohmic contact with barrier layer 130. Drain electrode 144 forms an ohmic contact with barrier layer 130. Gate structure 150 is located between source electrode 142 and drain electrode 144. Stacked semiconductor 160 is located on barrier layer 130. First semiconductor layer 162 and second semiconductor layer 164 form a target heterojunction at their junction, thereby serving as a conductive channel. Stacked semiconductor 160 is located between gate structure 150 and drain electrode 144, and the target heterojunction is electrically connected to drain electrode 144. Source field plate 143 is electrically connected to source electrode 142 and extends from source electrode 142 to above gate structure 150. First passivation layer 172 is located on barrier layer 130, covering the surface of barrier layer 130 away from channel layer 120 (i.e., the upper surface of barrier layer 130). The second passivation layer 174 is located on the first passivation layer 172 and covers the gate structure 150, the source electrode 142, the drain electrode 144, the source field plate 143 and the stacked semiconductor 160. The source field plate 143 and the gate structure 150 are separated by the second passivation layer 174.

[0054] The main difference between the embodiment shown in Figure 4 and the embodiment shown in Figure 1 is that a first passivation layer 172 is not disposed between the bottom of the first semiconductor layer 162 and the top of the barrier layer 130. The bottom of the first semiconductor layer 162 is in direct contact with the top of the barrier layer 130.

[0055] In one embodiment of this application, the first semiconductor layer 162 and / or the second semiconductor layer 164 are at least two-layer stepped structures. The stepped structure is high on the side near the gate structure 150 and low on the side near the drain electrode 144. That is, the steps extend upward in a stepped manner in the direction from the drain electrode 144 to the gate structure 150.

[0056] Figure 5 is a schematic diagram of a heterojunction semiconductor device in another embodiment of this application, which also includes a substrate 110, a channel layer 120, a barrier layer 130, a source electrode 142, a source field plate 143, a drain electrode 144, a gate structure 150, a multilayer semiconductor 160, a first passivation layer 172, and a second passivation layer 174. The substrate 110 includes a substrate 112, a nucleation layer 114 on the substrate 112, and a buffer layer 116 on the nucleation layer 114. The gate structure 150 includes a P-type semiconductor cap 152 on the barrier layer 130 and a gate electrode 154 on the P-type semiconductor cap 152. The multilayer semiconductor 160 includes a first semiconductor layer 162 and a second semiconductor layer 164 on the first semiconductor layer 162. The barrier layer 130 is located on the channel layer 120. The source electrode 142, the drain electrode 144, and the gate structure 150 are located on the barrier layer 130. Source electrode 142 forms an ohmic contact with barrier layer 130. Drain electrode 144 forms an ohmic contact with barrier layer 130. Gate structure 150 is located between source electrode 142 and drain electrode 144. Stacked semiconductor 160 is located on barrier layer 130. First semiconductor layer 162 and second semiconductor layer 164 form a target heterojunction at their junction, thereby serving as a conductive channel. Stacked semiconductor 160 is located between gate structure 150 and drain electrode 144, and the target heterojunction is electrically connected to drain electrode 144. Source field plate 143 is electrically connected to source electrode 142 and extends from source electrode 142 to above gate structure 150. First passivation layer 172 is located on barrier layer 130, covering the surface of barrier layer 130 away from channel layer 120 (i.e., the upper surface of barrier layer 130). The second passivation layer 174 is located on the first passivation layer 172 and covers the gate structure 150, the source electrode 142, the drain electrode 144, the source field plate 143 and the stacked semiconductor 160. The source field plate 143 and the gate structure 150 are separated by the second passivation layer 174.

[0057] The main difference between the embodiment shown in Figure 5 and the embodiment shown in Figure 1 is that the first semiconductor layer 162 and the second semiconductor layer 164 are two-layer stepped structures. This stepped structure is higher on the side near the gate structure 150 and lower on the side near the drain electrode 144; that is, the steps extend upwards in a stepped manner from the drain electrode 144 towards the gate structure 150. The stepped structure can be designed in conjunction with the gate and source field plates to achieve better results. The higher step structure near the gate structure 150 and lower step structure near the drain electrode 144 can prevent electric field lines from accumulating on the gate structure 150 side. In another embodiment of this application, the stepped structure is lower on the side near the gate structure 150 and higher on the side near the drain electrode 144; that is, the steps extend downwards in a stepped manner from the drain electrode 144 towards the gate structure 150.

[0058] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0059] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A heterojunction semiconductor device, characterized in that, include: Base; The channel layer is located on the substrate; A barrier layer is located on the channel layer; A gate structure is located on the barrier layer; The source electrode is located on the barrier layer; The drain electrode is located on the barrier layer; The gate structure is located between the source electrode and the drain electrode; A multilayer semiconductor includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer form a target heterojunction at the junction; The stacked semiconductor is located between the gate structure and the drain electrode, and the target heterojunction is electrically connected to the drain electrode.

2. The heterojunction semiconductor device according to claim 1, characterized in that, The source electrode forms an ohmic contact with the barrier layer; the drain electrode forms an ohmic contact with the barrier layer.

3. The heterojunction semiconductor device according to claim 1, characterized in that, The material of the first semiconductor layer is different from that of the second semiconductor layer, and both the first semiconductor layer and the second semiconductor layer are made of III-V group compounds.

4. The heterojunction semiconductor device according to claim 3, characterized in that, The material of the stacked semiconductor includes any two of gallium nitride, aluminum gallium nitride, gallium indium arsenide, aluminum gallium arsenide, and indium aluminum arsenide, or any combination of different components and doping of any one of the materials.

5. The heterojunction semiconductor device according to claim 1, characterized in that, It also includes a source field plate electrically connected to the source electrode, the source field plate extending from the source electrode to above the gate structure.

6. The heterojunction semiconductor device according to claim 5, characterized in that, Also includes: A first passivation layer is located on the barrier layer and covers the surface of the barrier layer away from the channel layer; A second passivation layer is located on the first passivation layer and covers the gate structure, source electrode, drain electrode, source field plate and stacked semiconductor. The source field plate and the gate structure are separated by the second passivation layer.

7. The heterojunction semiconductor device according to claim 6, characterized in that, The bottom of the first semiconductor layer and the top of the barrier layer are separated by the first passivation layer, or the first passivation layer is not disposed between the bottom of the first semiconductor layer and the top of the barrier layer.

8. The heterojunction semiconductor device according to claim 1, characterized in that, The first semiconductor layer and / or the second semiconductor layer are at least two-layer stepped structures, wherein the stepped structure is high on the side near the gate structure and low on the side near the drain electrode.

9. The heterojunction semiconductor device according to claim 1, characterized in that, The gate structure includes a P-type semiconductor cap located on the barrier layer and a gate electrode located on the P-type semiconductor cap.

10. The heterojunction semiconductor device according to claim 9, characterized in that, The gate electrode forms an ohmic contact or a Schottky contact with the P-type semiconductor cap.

11. The heterojunction semiconductor device according to claim 9, characterized in that, The material of the P-type semiconductor cap includes any one or more combinations of P-type gallium nitride (GaN), P-type aluminum nitride (AlN), P-type aluminum gallium nitride (AlGaN), P-type indium gallium nitride (InGaN), P-type aluminum indium gallium nitride (AlInGaN), and P-type aluminum indium nitride (AlInN).

12. The heterojunction semiconductor device according to claim 1, characterized in that, The substrate includes: Substrate; Nucleation layer, located on the substrate; A buffer layer is located on the nucleation layer.

13. The heterojunction semiconductor device according to claim 1, characterized in that, The substrate is made of any one or a combination of at least two of Si, SiC and sapphire.

14. The heterojunction semiconductor device according to any one of claims 1-13, characterized in that, The heterojunction semiconductor device is a high electron mobility transistor.

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