Photoelectric device array structure and preparation method therefor
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- INNOVISION TECHNOLOGY (ZHEJIANG) CO LTD
- Filing Date
- 2026-02-11
- Publication Date
- 2026-07-02
Smart Images
Figure CN2026078666_02072026_PF_FP_ABST
Abstract
Description
Optoelectronic device array structure and its fabrication method
[0001] Priority information: This application claims priority to Chinese patent application No. CN202411915684.8, filed on December 24, 2024. Technical Field
[0002] This application relates to the field of semiconductor technology, and in particular to an optoelectronic device array structure and its fabrication method. Background Technology
[0003] Optoelectronic device array structures (such as Micro LED) are the core chips of AR (Augmented Reality) / VR (Virtual Reality) devices. Compared with technologies such as LCOS (Liquid Crystal on Silicon) and OLED (Organic Light Emitting Diode), optoelectronic device array structures are considered the best solution due to their advantages such as high resolution, low power consumption, high brightness, and long lifespan.
[0004] Optoelectronic device array structures are generally fabricated from compound pixels and driving wafers. The compound pixel includes a first semiconductor layer, an active layer, and a second semiconductor layer. To form contacts in the semiconductor layers, a transparent conductive film is typically fabricated on the surface of the first semiconductor layer as a first semiconductor contact layer. Bonding structures are then fabricated on this transparent conductive film and the driving wafer, respectively, to complete the bonding integration of the compound pixel and the driving wafer.
[0005] While transparent conductive films have high transmittance, they cannot achieve complete transparency, resulting in optical losses and hindering optimal reflection. Furthermore, the thickness of these films is limited; when the film is too thin, the resistance is high, while a thicker transparent conductive oxide film improves resistance and reduces etching anomalies, but lowers reflectivity. Therefore, the conflicting effects of transparent conductive film thickness on brightness and voltage prevent optoelectronic device array structures from achieving optimal device performance.
[0006] Application content
[0007] The purpose of this application is to provide an optoelectronic device array structure and its fabrication method, which can greatly reduce light loss between pixel units and reflective mirror metal layers when there is no transparent conductive film or the transparent conductive film is extremely thin, thereby achieving optimal brightness improvement.
[0008] To achieve the above-mentioned objectives, this application proposes the following technical solution:
[0009] On the one hand, a method for fabricating an optoelectronic device array structure is provided, the method comprising:
[0010] The driving wafer and the compound pixel are bonded together through bonding structures on their respective surfaces to form a bonded device. A mirror layer and a first semiconductor layer are stacked on the side of the bonding structure corresponding to the compound pixel that is away from the driving wafer.
[0011] The compound pixels in the bonded device are pixelated by etching a portion of the first semiconductor layer into the compound pixels, leaving another portion of the first semiconductor layer intact, resulting in a plurality of pixel units that are continuous on the first semiconductor layer, each pixel unit forming an electrical connection with a first electrode contact in the driving wafer.
[0012] Pixel isolation is performed on multiple consecutive pixel units, and a reflective cavity structure is fabricated around the pixel units. The reflective cavity structure is connected to the outer edge of the first semiconductor layer, the mirror layer, and the bonding structure in the pixel units.
[0013] A second conductive electrode is fabricated on top of the pixel unit after pixel isolation, and the second conductive electrode forms an electrical connection with the second electrode contact in the driving wafer.
[0014] In one possible implementation, before performing pixel isolation on a plurality of consecutive pixel units, the method further includes:
[0015] An insulating dielectric is deposited on the outer surface of multiple consecutive pixel units to prepare a passivation layer;
[0016] An insulating dielectric is deposited again on the surface of the passivation layer to prepare the sidewall structure.
[0017] In one possible implementation, the step of pixel isolation of a plurality of consecutive pixel units and fabrication of a reflective cavity structure surrounding the pixel units includes:
[0018] The sidewall structure is etched in the first step to preserve the sidewall structure of each pixel unit; the passivation layer, first semiconductor layer, mirror layer and bonding structure between adjacent pixel units are etched in the second step to complete pixel isolation and fabrication of the reflective cavity structure.
[0019] In one possible implementation, the second etching step employs any of the following methods:
[0020] Ion beam etching (IBE) or neutral beam etching (NBE).
[0021] In one possible implementation, after completing the second etching step, the method further includes:
[0022] The isolated pixel unit is filled with an insulating medium to prepare the first insulating layer;
[0023] or,
[0024] A second insulating layer is prepared by covering the isolated pixel unit with an insulating medium film.
[0025] In one possible implementation, after the first insulating layer is fabricated and before the second conductive electrode is fabricated, the method further includes:
[0026] A first metal mesh structure is fabricated in the first insulating layer between adjacent pixel units, the top of the first metal mesh structure is in contact with the second conductive electrode, and the bottom of the first metal mesh structure is higher than the surface of the driving wafer.
[0027] In one possible implementation, fabricating a second conductive electrode on top of the pixel unit after pixel isolation includes:
[0028] An opening is made at the top of the pixel unit to expose the second semiconductor layer of the pixel unit;
[0029] A conductive film is deposited on top of each pixel unit to form a second conductive electrode, which connects the second semiconductor layer exposed in each pixel unit.
[0030] In one possible implementation, the method further includes, prior to forming the second conductive electrode:
[0031] A connected metal-filled structure is prepared between the second conductive electrode and the second electrode contact.
[0032] In one possible implementation, during the fabrication of the pixel unit, the method further includes:
[0033] Redundant structures are simultaneously fabricated around the outer periphery of the pixel unit.
[0034] In one possible implementation, the method further includes:
[0035] A second metal mesh structure is fabricated on top of the second conductive electrode.
[0036] In one possible implementation, the preparation process of the compound pixel includes:
[0037] The mirror layer is directly fabricated on the first semiconductor layer of the compound pixel.
[0038] On the other hand, a photoelectric device array structure is provided, which is fabricated by the photoelectric device array intermediate structure as described above, and the photoelectric device array structure includes: a driving wafer and a compound pixel;
[0039] The compound pixel and the driving wafer are respectively provided with bonding structures, and the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer, and the side surface of the bonding structure corresponding to the compound pixel away from the driving wafer is in contact with the mirror layer in the compound pixel.
[0040] The compound pixel includes a plurality of mutually isolated pixel units, each of which is electrically connected to a first electrode contact in the driving wafer;
[0041] The pixel unit is surrounded by a reflective cavity structure. The reflective cavity structure is connected to the outer edge of the first semiconductor layer, the mirror layer, and the bonding structure in the pixel unit. The first semiconductor layer includes at least a stacked first part layer and a second part layer. The first part layer is in contact with the mirror layer. The projection of the second part layer on the driving wafer is within the projection of the first part layer on the driving wafer.
[0042] A second conductive electrode is provided on the top of the pixel unit, and the second conductive electrode forms an electrical connection with the second electrode contact in the driving wafer.
[0043] In one possible implementation, a passivation layer is attached to the outer surface of the pixel unit;
[0044] The reflective cavity structure is also connected to the outer edge of the passivation layer.
[0045] In one possible implementation, a sidewall structure is spaced between the reflective cavity structure and the passivation layer on the sidewall surface of the pixel unit.
[0046] In one possible implementation, the entire outer periphery of the pixel unit is filled with a first insulating layer;
[0047] or,
[0048] The outer periphery of the pixel unit is covered with a second insulating layer in the form of a thin film.
[0049] In one possible implementation, the first insulating layer is filled with a first metal mesh structure, the top of the first metal mesh structure being in contact with the second conductive electrode, and the bottom of the first metal mesh structure being higher than the surface of the driving wafer.
[0050] In one possible implementation, a connecting metal filling structure is provided between the second conductive electrode and the second electrode contact.
[0051] In one possible implementation, a second metal mesh structure is further disposed above the top of the second conductive electrode.
[0052] In one possible implementation, at least one second electrode contact is disposed inside the pixel region of the driving wafer.
[0053] In one possible implementation, a first semiconductor contact layer is provided between the mirror layer and the first semiconductor layer.
[0054] In one possible implementation, the thickness of the first semiconductor contact layer is no greater than 70 nm.
[0055] In one possible implementation, a redundant structure is provided around the outer periphery of the pixel unit.
[0056] In one possible implementation, the distribution width of the redundant structure is not less than the minimum pixel unit size in the pixel region.
[0057] Compared with the prior art, this application has the following beneficial effects:
[0058] A driver wafer and a compound pixel are bonded together using bonding structures on their respective surfaces to form a bonded device. A mirror layer and a first semiconductor layer are stacked on the side of the bonding structure corresponding to the compound pixel that is furthest from the driver wafer. The compound pixel in the bonded device is pixelated by etching a portion of the first semiconductor layer into the compound pixel, leaving the remaining portion intact, resulting in multiple consecutive pixel units on the first semiconductor layer. Each pixel unit is electrically connected to a first electrode contact in the driver wafer. The multiple consecutive pixel units are then pixel-isolated, and a reflective cavity is fabricated surrounding each pixel unit. The structure connects the reflective cavity structure to the outer edge of the first semiconductor layer, the reflective mirror layer, and the bonding structure in the pixel unit. A second conductive electrode is fabricated on top of the pixel unit after pixel isolation, and the second conductive electrode forms an electrical connection with the second electrode contact in the driving wafer. Thus, even with a bottom reflective mirror layer in the device, the electrical connection is enhanced by the retained portion of the first semiconductor layer and the reflective cavity structure. This solves the electrical connection problem when there is no transparent conductive film or the transparent conductive film is extremely thin, as well as the leakage problem when the pixel is etched into the metal. At the same time, it greatly reduces the light loss between the compound and the reflective mirror metal, achieving the best brightness improvement. Attached Figure Description
[0059] Figure 1 is a flowchart of a method for fabricating an optoelectronic device array structure provided in an embodiment of this application;
[0060] Figure 2 is a schematic diagram of the structure of a compound pixel provided in an embodiment of this application;
[0061] Figure 3 is a schematic diagram of a driving wafer structure provided in an embodiment of this application;
[0062] Figure 4 is a schematic diagram of the structure of a bonded device provided in an embodiment of this application;
[0063] Figure 5 is a schematic diagram of the structure of a pixelated device provided in an embodiment of this application;
[0064] Figure 6 is a schematic diagram of the structure of a pixel-isolated device provided in an embodiment of this application;
[0065] Figure 7 is a schematic diagram of another pixelated device provided in an embodiment of this application;
[0066] Figure 8 is a schematic diagram of the structure of a device after the insulation layer is prepared according to an embodiment of this application;
[0067] Figure 9 is a schematic diagram of the structure of another device after the preparation of an insulating layer provided in an embodiment of this application;
[0068] Figure 10 is a schematic diagram of the structure of a device after opening preparation provided in an embodiment of this application;
[0069] Figure 11 is a schematic diagram of the structure of a device after the fabrication of a second conductive electrode provided in an embodiment of this application;
[0070] Figure 12 is a schematic diagram of an optoelectronic device array structure with a first metal mesh structure and a metal filling structure provided in an embodiment of this application.
[0071] Figure 13 is a schematic diagram of a photoelectric device array structure with a metal-filled structure provided in an embodiment of this application;
[0072] Figure 14 is a schematic diagram of a photoelectric device array structure with a second electrode contact within a pixel provided in an embodiment of this application.
[0073] Figure 15 is a schematic diagram of another optoelectronic device array structure with a second electrode contact within a pixel provided in an embodiment of this application.
[0074] Figure 16 is a schematic diagram of an optoelectronic device array structure with optical enhancement structure provided in an embodiment of this application;
[0075] Figure 17 is a schematic diagram of another optoelectronic device array structure with optical enhancement structure provided in the embodiment of this application;
[0076] Figure 18 is a schematic diagram of a discontinuous bonding structure provided in an embodiment of this application.
[0077] Reference numerals: 100-Driver wafer, 110-First electrode contact, 120-Second electrode contact, 200-Compound pixel, 210-Pixel unit, 211-Binding structure, 212-Mirror layer, 213-First semiconductor layer, 214-Active layer, 215-Second semiconductor layer, 216-Substrate, 220-Reflective cavity structure, 230-Passivation layer, 240-Sidewall structure, 251-First insulating layer, 252-Second insulating layer, 261-First metal mesh structure, 262-Metal filling structure, 270-Redundancy structure, 280-Second conductive electrode, 290-Microlens. Detailed Implementation
[0078] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0079] In the description of this application, it should be understood that the terms "vertical," "upper," "lower," "top," "side," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0080] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0081] In the embodiments of this application, by partially retaining the first semiconductor layer and the electrical enhancement connection of the reflective cavity structure on the sidewall during compound pixelation, the electrical connection problem and the leakage problem of pixel etching to metal when there is no transparent conductive film or the transparent conductive film is extremely thin are solved. When there is no transparent conductive film or the transparent conductive film is extremely thin, the light loss between the pixel unit and the metal of the reflective mirror layer is greatly reduced, and the best brightness improvement is achieved.
[0082] The fabrication method of the device structure proposed in this application will be described below.
[0083] As shown in Figure 1, the fabrication method of the optoelectronic device array structure may include the following steps:
[0084] Step S1: The driving wafer and the compound pixel are bonded and integrated through the bonding structure on their respective surfaces to form a bonded device. A mirror layer and a first semiconductor layer are stacked on the side of the bonding structure corresponding to the compound pixel that is away from the driving wafer.
[0085] Specifically, as shown in Figures 2 and 3, bonding structures 211 are prepared on the compound pixel 200 and the driving wafer 100. The bonding structures 211 include Au, Cu, AuSn, CuSn, etc.
[0086] The bonding structure 211 can be a patterned discontinuous metal layer. The bonding structure 211 can be continuous only in the pixel region (the area used for pixel unit fabrication), but discontinuous in the non-pixel regions. The non-pixel regions are filled with an insulating medium for support. The insulating medium can be one or more of media such as SiO2, Si3N4, and PI. This patterned discontinuous metal layer can achieve better bonding warpage and metal cost control. For example, referring to Figure 18, the bonding structure 211 on the surface of the driving wafer 100 and the bonding structure 211 on the surface of the compound pixel 200 are discontinuous metal layers.
[0087] As shown in Figure 2, a mirror layer 212 can be stacked on top of the bonding structure 211 at the compound pixel 200. The mirror layer 212 is used to reflect light entering the bottom of the compound pixel 200. The mirror layer 212 includes metal layers such as Ag, Al, Ni / Ag, Ni / Al, Ag / Al, Ag / Ni / Au, Al / Ni / Au, Ir / Ag, AuBe / Ag, Cr / Pt, and Cr / Rh. Furthermore, an adhesion barrier layer can be disposed between the mirror layer 212 and the bonding structure 211. The adhesion barrier layer includes one or more of Ti, Ni, Pt, Cr, TiN, and TaN.
[0088] If necessary, a transparent oxide, such as ITO or ZnO, can be inserted between the mirror layer and the first semiconductor layer as a first semiconductor contact layer to reduce the difficulty of ohmic contact of the first semiconductor layer. The thickness of the transparent oxide is in the range of 0 to 70 nm.
[0089] An adhesion barrier layer may be disposed between the bonding structure at the driving wafer end and the driving wafer. The bonding structure includes Au, Cu, AuSn, CuSn, etc. The adhesion barrier layer includes one or more of Ti, Ni, Pt, Cr, TiN, TaN, etc.
[0090] An example of a partial cross-section of a single chip showing the fabrication of a compound pixel with a bonded structure and a driving wafer is shown below:
[0091] In one embodiment, the reflective layer at the compound pixel end is a double-layer structure of 10nm ITO and 100nm Al, the adhesion barrier layer is 50nm Ni, 50nm Cr and 50nm Pt, and the bonding structure is a stack of 100nm Au and 100nm Sn.
[0092] In one embodiment, the adhesion barrier layer at the drive wafer end is 50nm Cr and 50nm Pt, and the bonding structure is a stack of 100nm Au and 100nm Sn.
[0093] Furthermore, as shown in Figure 4, after the bonding integration between the two wafer surfaces is completed through the bonding structure 211, the substrate 216 on the surface of the compound pixel 200 can be removed.
[0094] In one possible implementation, the fabrication process of the compound pixel includes: directly fabricating a mirror layer on the first semiconductor layer of the compound pixel. That is, instead of fabricating a transparent conductive film as a first semiconductor contact layer on the surface of the first semiconductor layer, the mirror layer can be fabricated directly on it, thereby avoiding optical losses caused by the first semiconductor contact layer. It is understood that, besides not fabricating the first semiconductor contact layer, a first semiconductor contact layer with a thickness of no more than 70 nm can also be fabricated, minimizing the impact of an excessively thick first semiconductor contact layer on the optical performance of the device.
[0095] Step S2: Pixelate the compound pixel in the bonded device by etching a portion of the first semiconductor layer into the compound pixel, leaving the other portion of the first semiconductor layer intact, to obtain a plurality of continuous pixel units on the first semiconductor layer, each pixel unit forming an electrical connection with a first electrode contact in the driving wafer.
[0096] Specifically, as shown in Figure 5, the compound pixel is patterned using a pixel array etching process. For example, the number of pixel units 210 obtained by etching is not less than three. Each pixel unit 210 forms an electrical connection with the first electrode contact 110 in the driving wafer 100. During the patterning etching, the structure of the compound pixel is not completely isolated, retaining a portion of the first semiconductor layer 213 with a thickness of 30nm to 400nm. This thickness range ensures that the active layer 214 is completely disconnected. It is understood that the figure only illustrates the one-to-one correspondence between pixel units 210 and first electrode contacts 110. Each pixel unit 210 may also correspond to multiple first electrode contacts 110.
[0097] Understandably, during this pixelation process, retaining part of the first semiconductor layer can prevent over-etching into the metal during pixel patterning, which could lead to metal deposition, leakage, and other device failures.
[0098] Step S3: Perform pixel isolation on multiple consecutive pixel units and prepare a reflective cavity structure around the pixel unit. The reflective cavity structure is connected to the outer edge of the first semiconductor layer, the mirror layer, and the bonding structure in the pixel unit.
[0099] Specifically, as shown in Figure 6, pixel isolation is further performed on the continuous pixel units 210 in the first semiconductor layer 213 to completely isolate the structure of the compound pixel, so as to obtain each pixel unit 210 that is completely isolated. During the pixel isolation process, a reflective cavity structure 220 is prepared around each pixel unit 210. The reflective cavity structure 220 is connected to the outer edge of the first semiconductor layer 213, the reflective mirror layer 212, and the bonding structure 211 in the pixel unit 210.
[0100] It is understandable that the reflective cavity structure is a cylindrical cavity structure formed by pixel units. The light waves emitted by the pixel units can be reflected back and forth in it, thereby providing positive optical feedback and greatly improving the luminous efficiency of the device.
[0101] In one possible implementation, before pixel isolation of multiple consecutive pixel units, the following steps are included: depositing an insulating dielectric on the outer surface of the multiple consecutive pixel units to prepare a passivation layer; and depositing an insulating dielectric again on the surface of the passivation layer to prepare a sidewall structure.
[0102] Specifically, following the structure shown in Figure 5 and preceding the structure shown in Figure 6, as shown in Figure 7, a passivation layer 230 and a sidewall structure 240 are further fabricated on the pixel unit 210 after the active layer 214 has been completed. The passivation layer 230 is used to passivate and protect the pixel unit 210, and the sidewall structure 240 is used to provide support for the subsequent formation of the reflective cavity structure 220. The passivation layer 230 includes a single layer or stack of dielectric layers such as aluminum oxide, silicon oxide, and silicon nitride. The sidewall structure 240 includes a single layer or stack of dielectric layers such as aluminum oxide, silicon oxide, and silicon nitride.
[0103] In one embodiment, compound pixels are patterned and etched using a silicon nitride hard mask to retain a 100nm first semiconductor layer, and then passivation is performed to form a passivation layer. The passivation layer can be a dielectric layer of silicon oxide, silicon oxide, or silicon nitride, and the thickness of the passivation layer is between 10nm and 200nm.
[0104] After the passivation layer and sidewall structure are formed, step S3 can further include: first etching the sidewall structure to retain the sidewall structure of each pixel unit; second etching the passivation layer, first semiconductor layer, mirror layer and bonding structure that are continuous between adjacent pixel units to complete the preparation of pixel isolation and reflective cavity structure.
[0105] The second etching step employs any one of the following methods: IBE or NBE.
[0106] Specifically, a sidewall etching process is used to etch the upper surface of the pixel unit and the sidewall structure between pixel units, retaining only the sidewall structure of each pixel unit's sidewall portion. After completing the sidewall etching, an etching scheme such as IBE or NBE is used to fabricate a reflective cavity structure connected to the sidewalls of the bottom layer of the pixel unit, including the first semiconductor layer. This reflective cavity structure can achieve electrical enhancement. It is understood that, due to the above fabrication process, the specific materials of the reflective cavity structure are the same as those used in the passivation layer, first semiconductor layer, mirror layer, and metal portions of the bonding structure during the second etching step.
[0107] Furthermore, after completing the second etching step, the following steps are also included: filling the entire surface of the isolated pixel unit with an insulating medium to prepare a first insulating layer; or covering the isolated pixel unit with a film layer of insulating medium to prepare a second insulating layer.
[0108] Specifically, an insulating layer is prepared on the device after pixel isolation is completed. The insulating layer can be a full-surface filler, forming the first insulating layer 251 as shown in Figure 8, or it can be a non-filled film layer covering the surface, forming the second insulating layer 252 as shown in Figure 9. The aforementioned first insulating layer 251 or second insulating layer 252 includes one or a combination of silicon oxide, aluminum oxide, silicon nitride, and aluminum nitride, and this application does not limit it.
[0109] Step S4: On top of the pixel unit after pixel isolation, a second conductive electrode is prepared, and the second conductive electrode forms an electrical connection with the second electrode contact in the driving wafer.
[0110] In one possible implementation, step S4 may specifically include: making an opening at the top of the pixel unit to expose the second semiconductor layer of the pixel unit; depositing a conductive film on the top of each pixel unit to form a second conductive electrode, the second conductive electrode connecting the exposed second semiconductor layers of each pixel unit.
[0111] Specifically, as shown in Figure 10, the top of the pixel unit 210 is an opening for the contact fabrication of the second conductive electrode 280. Subsequently, the second conductive electrode 280 can be formed on the outer surface of each pixel unit 210 by coating. The structure after fabricating the second conductive electrode 280 as shown in Figure 8 can be shown in Figure 11.
[0112] In one possible implementation, the following steps are also included: a first metal mesh structure is prepared in a first insulating layer between adjacent pixel units, the top of the first metal mesh structure is in contact with a second conductive electrode, and the bottom of the first metal mesh structure is higher than the surface of the driving wafer.
[0113] Specifically, as shown in Figure 12, in order to achieve electrical enhancement of the second conductive electrode 280, a first metal mesh structure 261 is fabricated below the second conductive electrode 280. The first metal mesh structure 261 can be an alloy or stack of metallic materials, such as alloys of Al, AlCu, AlNi, etc., Al / TiN, AlCu / TiN stacks, stacks of metals such as Al / Ni / Ti / Au, or alloys or stacks of metals such as Au / Ge / Ni / Au.
[0114] In one possible implementation, the following step is also included: preparing a connected metal-filled structure between the second conductive electrode and the second electrode contact.
[0115] Specifically, as shown in Figure 12 or Figure 13, in order to achieve the electrical connection of the second conductive electrode 280, metal filling is performed between the second conductive electrode 280 and the second electrode contact 120 in the driving wafer 100 to prepare a metal filling structure 262 connecting the two. The metal filling structure 262 is made of a metallic material, such as Al / Ti / Cu, Al / TiN / Cu, Al / Ni / Cu, Al / NiV / Cu, Al / Ta / Cu, or Al / TaN / Cu. Cu can also be replaced with W, and Al can be omitted from the above structures. This application does not limit the specific type of metallic material.
[0116] It is understood that the number of second electrode contacts 120 can be one or multiple as shown in Figure 14 or Figure 15. In addition to the second electrode contacts 120 outside the pixel area, one or more second electrode contacts 120 are also provided within the pixel area. The second electrode contacts 120 within the pixel area can directly contact the second conductive electrode 280, or each second electrode contact 120 can be provided with a metal filling structure 262 connected to the second conductive electrode 280, and the second electrode contacts 120 contact the second conductive electrode 280 through the metal filling structure 262.
[0117] In one possible implementation, the following step is also included: during the fabrication of the pixel unit, redundant structures are simultaneously fabricated around the pixel unit.
[0118] The redundant structure is a structure fabricated simultaneously with the pixel unit. Unlike the pixel unit, the redundant structure does not need to contact the first electrode contact in the driving wafer, and the size of the redundant structure can be different from that of the pixel unit.
[0119] Specifically, as shown in Figures 2 to 15, a portion of the compound pixels are retained between the peripheral common cathode and the pixel area to form a redundant structure 270, resulting in a higher fill density. This improves some steps and density requirements in subsequent semiconductor processes, such as resist tailing and chemical mechanical polishing (CMP). The redundant structure 270 can be a pixel array redundancy or a compound dam structure surrounding the pixel array. The distribution width of the redundant structure 270 is not less than the minimum pixel unit size in the pixel area. For example, the distribution width of the redundant structure 270 is not less than 10 μm.
[0120] In one possible implementation, the following step is also included: fabricating a second metal mesh structure on top of the second conductive electrode.
[0121] Specifically, to achieve electrical enhancement of the second conductive electrode, a second metal mesh structure is fabricated above the second conductive electrode. The second metal mesh structure can be an alloy or stack of metallic materials, such as alloys of Al, AlCu, and AlNi, Al / TiN or AlCu / TiN stacks, stacks of metals such as Al / Ni / Ti / Au, or alloys or stacks of metals such as Au / Ge / Ni / Au.
[0122] In one possible implementation, optical enhancement structures such as microlenses and metasurfaces are fabricated on the final structure to achieve optical enhancement or collimation. As shown in Figures 16 and 17, microlenses 290 are fabricated as optical enhancement structures. Microlenses 290 can be hemispherical or semi-rugby-shaped. Redundant microlenses 290 are fabricated around the pixel array to achieve diffuse reflection around the pixel array and reduce optical anomalies, such as "ghosting" caused by excessive reflection in the optical module.
[0123] In summary, the method for fabricating the optoelectronic device array structure provided in this application integrates a driving wafer and a compound pixel by bonding them together through bonding structures on their respective surfaces to form a bonded device. A mirror layer and a first semiconductor layer are stacked on the side of the bonding structure corresponding to the compound pixel that is furthest from the driving wafer. The compound pixel in the bonded device is pixelated by etching a portion of the first semiconductor layer into the compound pixel, leaving the remaining portion of the first semiconductor layer intact, resulting in multiple consecutive pixel units on the first semiconductor layer. Each pixel unit forms an electrical connection with a first electrode contact in the driving wafer. Pixel isolation is then performed on the multiple consecutive pixel units, and... A reflective cavity structure is fabricated around the pixel unit, and the reflective cavity structure is connected to the outer edge of the first semiconductor layer, the mirror layer, and the bonding structure in the pixel unit. A second conductive electrode is fabricated on top of the pixel unit after pixel isolation, and the second conductive electrode forms an electrical connection with the second electrode contact in the driving wafer. Thus, even with a bottom mirror layer in the device, the electrical connection is enhanced by the retained portion of the first semiconductor layer and the reflective cavity structure. This solves the electrical connection problem when there is no transparent conductive film or the transparent conductive film is extremely thin, as well as the leakage problem when the pixel is etched into the metal. At the same time, it greatly reduces the light loss between the compound and the mirror metal, achieving the best brightness improvement.
[0124] As shown in FIG5, this application also provides an intermediate structure for an optoelectronic device array, which includes a driving wafer 100 and a compound pixel.
[0125] In this compound pixel, bonding structures 211 are respectively disposed on the surface of the driving wafer 100, and the bonding structure 211 corresponding to the compound pixel is in contact with the bonding structure 211 corresponding to the driving wafer 100. Furthermore, the side of the bonding structure 211 corresponding to the compound pixel away from the driving wafer 100 is in contact with the mirror layer 212 in the compound pixel. The compound pixel includes multiple pixel units 210, which are continuous on a first semiconductor layer 213 in the compound pixel. The first semiconductor layer 213 is disposed on the side of the mirror layer 212 away from the driving wafer 100. Each pixel unit 210 forms an electrical connection with a first electrode contact 110 in the driving wafer 100.
[0126] The driving wafer 100 can be an active design combining one or more of the following: thin-film transistor (TFT), low-temperature polysilicon (LTPS), CMOS integrated circuit, high-mobility transistor (HEMT).
[0127] The material of the compound pixel corresponding to pixel unit 210 can be as follows:
[0128] Taking the Micro-LED field as an example, the materials of some compound pixels involved in the embodiments of this application are shown in the table below. In some practical applications, the compound film layers are more complex, or there is cross-use of materials. Typically, they mainly include P-type contacts, N-type contacts, and active layers and other functional layers sandwiched between them:
[0129] The compound contacts are divided into P-type contacts and N-type contacts, which contact the P-contact layer and the N-contact layer, respectively. The barrier layer, confinement layer, or waveguide layer corresponding to the P-type contact and the barrier layer, confinement layer, or waveguide layer corresponding to the N-type contact can correspond to the first semiconductor layer 213 and the second semiconductor layer 215, respectively. In the embodiments, the P-type contact materials used include single layers or stacks of transparent metal oxides such as ITO, IZO, and ZnO, or single layers or stacks of metals such as Ni, Cr, Au, Ag, Zn, Be, and Al, or alloys, or stacks of transparent metal oxides and metals; the N-type contact materials used include single layers or stacks of transparent metal oxides such as ITO, IZO, and ZnO, or single layers or stacks of metals such as Ni, Cr, Ti, Au, Ge, and Al, or alloys, or stacks of transparent metal oxides and metals. The semiconductor contact layer can be deposited using methods such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), and ALD (Atomic Layer Deposition).
[0130] In one possible implementation, a first semiconductor contact layer is disposed between the mirror layer 212 and the first semiconductor layer 213, and the thickness of the first semiconductor contact layer is no greater than 70 nm. By thinning the first semiconductor layer, the impact of excessive thickness of the first semiconductor contact layer on the optical performance of the device is avoided.
[0131] In summary, the optoelectronic device intermediate array structure provided in this application includes a driving wafer and a compound pixel. Bonding structures are respectively disposed on the surfaces of the compound pixel and the driving wafer, and the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer. Furthermore, the side of the bonding structure corresponding to the compound pixel away from the driving wafer is in contact with a mirror layer in the compound pixel. The compound pixel includes multiple pixel units, which are continuous on a first semiconductor layer within the compound pixel. The first semiconductor layer is disposed on the side of the mirror layer away from the driving wafer, and each pixel unit forms an electrical connection with a first electrode contact in the driving wafer. Thus, by retaining a portion of the first semiconductor layer, the problem of over-etching to metal during pixel patterning, leading to metal deposition and leakage current, and device failure, is avoided.
[0132] Furthermore, based on the aforementioned intermediate structure of the optoelectronic device array, the final optoelectronic device array structure can be further fabricated.
[0133] In this application, as shown in Figure 11 or Figure 14, an optoelectronic device array structure is also provided, which includes a driving wafer 100 and a compound pixel.
[0134] In this compound pixel, bonding structures 211 are respectively disposed on the surface of the driving wafer 100, and the bonding structure 211 corresponding to the compound pixel is in contact with the bonding structure 211 corresponding to the driving wafer 100. The side of the bonding structure 211 corresponding to the compound pixel away from the driving wafer 100 is in contact with the mirror layer 212 in the compound pixel. The compound pixel includes multiple pixel units 210, each pixel unit 210 forming an electrical connection with a first electrode contact 110 in the driving wafer 100. A reflective cavity structure 220 surrounds the pixel unit 210, and the reflective cavity structure 220 is connected to the outer edge of the first semiconductor layer 213, the mirror layer 212, and the bonding structure 211 in the pixel unit 210. The first semiconductor layer 213 includes at least a stacked first partial layer and a second partial layer. The first partial layer is in contact with the mirror layer 212, and the projection of the second partial layer onto the driving wafer 100 is within the projection of the first partial layer onto the driving wafer 100. A second conductive electrode 280 is provided on the top of the pixel unit 210, and the second conductive electrode 280 forms an electrical connection with the second electrode contact 120 in the driving wafer 100.
[0135] Furthermore, a passivation layer 230 is attached to the outer surface of the pixel unit 210; the reflective cavity structure 220 is also connected to the outer edge of the passivation layer 230. The passivation layer 230 includes a single layer or stack of dielectric layers such as aluminum oxide, silicon oxide, and silicon nitride.
[0136] Furthermore, a sidewall structure 240 is spaced between the reflective cavity structure 220 and the passivation layer 230 on the sidewall surface of the pixel unit 210. The sidewall structure 240 includes a single layer or stack of dielectric layers such as aluminum oxide, silicon oxide, and silicon nitride.
[0137] Furthermore, as shown in FIG11, the entire outer periphery of the pixel unit 210 is filled with a first insulating layer 251; or, as shown in FIG14, the outer periphery of the pixel unit 210 is covered with a thin film-like second insulating layer 252. The first insulating layer 251 or the second insulating layer 252 comprises one or a combination of silicon oxide, aluminum oxide, silicon nitride, and aluminum nitride, and this application does not impose any limitations on this.
[0138] Furthermore, as shown in Figure 12, the first insulating layer 251 is filled with a first metal mesh structure 261. The top of the first metal mesh structure 261 is in contact with the second conductive electrode 280, and the bottom of the first metal mesh structure 261 is higher than the surface of the driving wafer 100, thereby enhancing the electrical connection through this first metal mesh structure 261. The first metal mesh structure 261 can be an alloy or stack of metallic materials, such as alloys of Al, AlCu, and AlNi, Al / TiN or AlCu / TiN stacks, Al / Ni / Ti / Au stacks, or alloys or stacks of Au / Ge / Ni / Au.
[0139] Furthermore, as shown in Figure 13, a connecting metal filling structure 262 is provided between the second conductive electrode 280 and the second electrode contact 120 to enhance the electrical connection. The metal filling structure 262 is made of a metallic material, such as Al / Ti / Cu, Al / TiN / Cu, Al / Ni / Cu, Al / NiV / Cu, Al / Ta / Cu, or Al / TaN / Cu. Cu can also be replaced with W, and Al can be omitted from the above structures. This application does not limit the specific type of metallic material.
[0140] Furthermore, a second metal mesh structure is provided above the top of the second conductive electrode 280. The second metal mesh structure can be an alloy or stack of metallic materials, such as alloys of Al, AlCu, AlNi, etc., Al / TiN, AlCu / TiN stacks, stacks of metals such as Al / Ni / Ti / Au, or alloys or stacks of metals such as Au / Ge / Ni / Au.
[0141] Furthermore, as shown in Figure 14, at least one second electrode contact 120 is provided inside the pixel area of the driving wafer 100 to enhance the electrical connection.
[0142] Furthermore, a first semiconductor contact layer is provided between the reflector layer 212 and the first semiconductor layer 213. To avoid the first semiconductor contact layer being too thick, the thickness of the first semiconductor contact layer is no more than 70 nm.
[0143] Furthermore, a redundant structure 270 is provided around the outer periphery of the pixel unit 210. In addition, the distribution width of the redundant structure 270 is not less than the minimum size of the pixel unit in the pixel region.
[0144] In summary, the optoelectronic device array structure provided in this application includes a driving wafer and a compound pixel. Bonding structures are respectively disposed on the surfaces of the compound pixel and the driving wafer, and the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer. Furthermore, the side of the bonding structure corresponding to the compound pixel away from the driving wafer is in contact with a mirror layer in the compound pixel. The compound pixel includes multiple pixel units, each pixel unit forming an electrical connection with a first electrode contact in the driving wafer. A reflective cavity structure surrounds the outer periphery of the pixel unit, and the reflective cavity structure is connected to the outer edge of the first semiconductor layer, the mirror layer, and the bonding structure in the pixel unit. The body layer includes at least a stacked first part layer and a second part layer. The first part layer is in contact with the mirror layer, and the projection of the second part layer on the driving wafer is within the projection of the first part layer on the driving wafer. A second conductive electrode is provided on the top of the pixel unit, and the second conductive electrode forms an electrical connection with the second electrode contact in the driving wafer. Thus, even with a bottom mirror layer in the device, the electrical connection is enhanced by the retained portion of the first semiconductor layer and the reflective cavity structure. This solves the electrical connection problem when there is no transparent conductive film or the transparent conductive film is extremely thin, as well as the leakage problem when the pixel is etched into the metal. At the same time, it greatly reduces the light loss between the compound and the mirror metal, achieving the best brightness improvement.
[0145] All the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application. That is, any number of embodiments can be combined to meet the needs of different application scenarios. All of them are within the protection scope of this application and will not be described in detail here.
[0146] It should be noted that the above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for fabricating an optoelectronic device array structure, wherein, The method includes: The driving wafer and the compound pixel are bonded together through bonding structures on their respective surfaces to form a bonded device. A mirror layer and a first semiconductor layer are stacked on the side of the bonding structure corresponding to the compound pixel that is away from the driving wafer. The compound pixels in the bonded device are pixelated by etching a portion of the first semiconductor layer into the compound pixels, leaving another portion of the first semiconductor layer intact, resulting in a plurality of pixel units that are continuous on the first semiconductor layer, each pixel unit forming an electrical connection with a first electrode contact in the driving wafer. Pixel isolation is performed on multiple consecutive pixel units, and a reflective cavity structure is fabricated around the pixel units. The reflective cavity structure is connected to the outer edge of the first semiconductor layer, the mirror layer, and the bonding structure in the pixel units. A second conductive electrode is fabricated on top of the pixel unit after pixel isolation, and the second conductive electrode forms an electrical connection with the second electrode contact in the driving wafer.
2. The method according to claim 1, wherein, Before performing pixel isolation on a plurality of consecutive pixel units, the method further includes: An insulating dielectric is deposited on the outer surface of multiple consecutive pixel units to prepare a passivation layer; An insulating dielectric is deposited again on the surface of the passivation layer to prepare the sidewall structure.
3. The method according to claim 2, wherein, The step of pixel isolation of multiple consecutive pixel units and fabrication of a reflective cavity structure surrounding the pixel units includes: The sidewall structure is etched in the first step to preserve the sidewall structure of each pixel unit sidewall portion; A second etching step is performed on the passivation layer, the first semiconductor layer, the mirror layer, and the bonding structure that are continuous between adjacent pixel units to complete pixel isolation and the fabrication of the reflective cavity structure.
4. The method according to claim 3, wherein, The second etching step employs any of the following methods: IBE or NBE.
5. The method according to claim 3, wherein, After completing the second etching step, the method further includes: The isolated pixel unit is filled with an insulating medium to prepare the first insulating layer; or, A second insulating layer is prepared by covering the isolated pixel unit with an insulating medium film.
6. The method according to claim 5, wherein, After the first insulating layer is prepared and before the second conductive electrode is prepared, the method further includes: A first metal mesh structure is fabricated in the first insulating layer between adjacent pixel units, the top of the first metal mesh structure is in contact with the second conductive electrode, and the bottom of the first metal mesh structure is higher than the surface of the driving wafer.
7. The method according to claim 1, wherein, The step of fabricating a second conductive electrode on top of the pixel unit after pixel isolation includes: An opening is made at the top of the pixel unit to expose the second semiconductor layer of the pixel unit; A conductive film is deposited on top of each pixel unit to form a second conductive electrode, which connects the second semiconductor layer exposed in each pixel unit.
8. The method according to claim 7, wherein, Before forming the second conductive electrode, the method further includes: A connected metal-filled structure is prepared between the second conductive electrode and the second electrode contact.
9. The method according to claim 1, wherein, In the process of preparing the pixel unit, the method further includes: Redundant structures are simultaneously fabricated around the outer periphery of the pixel unit.
10. The method according to claim 1, wherein, The method further includes: A second metal mesh structure is fabricated on top of the second conductive electrode.
11. The method according to claim 1, wherein, The preparation process of the compound pixel includes: The mirror layer is directly fabricated on the first semiconductor layer of the compound pixel.
12. An array structure for optoelectronic devices, wherein, The optoelectronic device array structure includes: a driving wafer and compound pixels; The compound pixel and the driving wafer are respectively provided with bonding structures, and the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer, and the side surface of the bonding structure corresponding to the compound pixel away from the driving wafer is in contact with the mirror layer in the compound pixel. The compound pixel includes a plurality of mutually isolated pixel units, each of which is electrically connected to a first electrode contact in the driving wafer; The pixel unit is surrounded by a reflective cavity structure. The reflective cavity structure is connected to the outer edge of the first semiconductor layer, the mirror layer, and the bonding structure in the pixel unit. The first semiconductor layer includes at least a stacked first part layer and a second part layer. The first part layer is in contact with the mirror layer. The projection of the second part layer on the driving wafer is within the projection of the first part layer on the driving wafer. A second conductive electrode is provided on the top of the pixel unit, and the second conductive electrode forms an electrical connection with the second electrode contact in the driving wafer.
13. The optoelectronic device array structure according to claim 12, wherein, A passivation layer is attached to the outer surface of the pixel unit; The reflective cavity structure is also connected to the outer edge of the passivation layer.
14. The optoelectronic device array structure according to claim 13, wherein, A sidewall structure is spaced between the reflective cavity structure and the passivation layer on the sidewall surface of the pixel unit.
15. The optoelectronic device array structure according to claim 12, wherein, The entire outer periphery of the pixel unit is filled with a first insulating layer; or, The outer periphery of the pixel unit is covered with a second insulating layer in the form of a thin film.
16. The optoelectronic device array structure according to claim 15, wherein, The first insulating layer is filled with a first metal mesh structure, the top of the first metal mesh structure is in contact with the second conductive electrode, and the bottom of the first metal mesh structure is higher than the surface of the driving wafer.
17. The optoelectronic device array structure according to claim 12, wherein, A connecting metal filling structure is provided between the second conductive electrode and the second electrode contact.
18. The optoelectronic device array structure according to claim 12, wherein, A second metal mesh structure is also provided on the top of the second conductive electrode.
19. The optoelectronic device array structure according to claim 12, wherein, At least one second electrode contact is disposed inside the pixel region of the driving wafer.
20. The optoelectronic device array structure according to claim 12, wherein, A first semiconductor contact layer is provided between the reflector layer and the first semiconductor layer.
21. The optoelectronic device array structure according to claim 20, wherein, The thickness of the first semiconductor contact layer is no greater than 70 nm.
22. The optoelectronic device array structure according to claim 12, wherein, The pixel unit is surrounded by a redundant structure.
23. The optoelectronic device array structure according to claim 22, wherein, The distribution width of the redundant structure is not less than the minimum pixel unit size in the pixel region.