Optoelectronic component

The modified PIN junction structure with a laterally displaced P-doped layer and photonic crystal waveguide addresses the challenge of high capacitance in optoelectronic components, achieving high-frequency operation and simplified manufacturing with reduced optical losses.

WO2026139582A1PCT designated stage Publication Date: 2026-07-02NCODIN +3
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
NCODIN
Filing Date
2025-12-23
Publication Date
2026-07-02

AI Technical Summary

Technical Problem

Existing optoelectronic components, such as photodetectors and electro-optical modulators, face challenges in achieving high integration density and operating at high frequencies due to their large capacitance and resistance, which are difficult to manufacture and require complex fabrication techniques.

Method used

The optoelectronic component is designed with a modified PIN junction structure where the P-doped layer is laterally displaced, minimizing capacitance by substituting it with an intrinsic layer, thereby reducing the facing N and P surfaces, and incorporating a one-dimensional or two-dimensional photonic crystal waveguide to confine light.

Benefits of technology

This design achieves a significant reduction in capacitance by more than an order of magnitude, enabling detection and modulation beyond 1 GHz with reduced optical losses and simpler manufacturing, using a high load resistance.

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  • Figure EP2025088940_02072026_PF_FP_ABST
    Figure EP2025088940_02072026_PF_FP_ABST
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Abstract

The invention relates to an optoelectronic component (1, 21, 41) comprising: • a substrate; • an arrangement of three layers extending in a stacking direction perpendicular to the plane of the substrate, the arrangement comprising: • a first semiconductor layer (2, 22, 42) deposited on the substrate; • a second semiconductor layer (3, 23, 43), referred to as an active layer, deposited on the first semiconductor layer (2, 22, 42); • a third N-doped semiconductor layer (4, 24, 44), referred to as an N-doped layer, deposited on the active layer (3, 23, 43); the first semiconductor layer (2, 22, 42) being a layer divided into at least two regions: • an intrinsic region (5, 25, 45); • a P-doped region (6, 26, 46); the N-doped layer (4, 24, 44) and the active layer (3, 23, 43) being arranged so as to at least partially cover the intrinsic region (5, 25, 45), at least one electrical contact (9, 29, 47) being arranged on the P-doped region (6, 26, 46) and at least one electrical contact being arranged on the N-doped layer.
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