Bidirectional amplifier and wireless communication device

Abstract

A bidirectional amplifier (26, 28) includes FETs (35-37) having a symmetrical structure, and complex conjugate matching circuits (39) that are symmetrical and block a DC component. The FETs (35-37) are connected in series with the complex conjugate matching circuits (39) interposed between the FETs.

Description

Bidirectional Amplifier and Wireless Communication Device

[0001] The present disclosure relates to a bidirectional amplifier and a wireless communication device.

[0002] A wireless communication device generally has a transmission path and a reception path, and these paths are independent of each other. In particular, in a wireless communication device such as a mobile phone that performs time-division communication, the antenna is often shared for transmission and reception. In this case, transmission / reception switching using a switch is often adopted. In addition, in the transmission path and the reception path, an amplifier for amplifying not only an intermediate frequency band signal but also a radio frequency band signal is provided. When including signals up to the local oscillation system frequency band, a maximum of six signal amplifiers are required.

[0003] In recent years, the use of a high-frequency band of 100 GHz or higher has been considered as a signal frequency band used by a wireless communication device, and multi-stage signal amplifiers are required. For example, the gain per stage of an amplifier using a semiconductor is 5 dB or less in a signal frequency band exceeding 100 GHz, and in this frequency band, three or more stages of amplifiers are required. In addition, the development of a phased array antenna or the like in which antenna elements are arranged at intervals of less than one wavelength in the radio frequency band on the same plane has progressed, and the demand for miniaturization of wireless communication devices has become even stronger.

[0004] For example, Patent Document 1 describes a wireless communication device provided with an amplifier having bidirectionality for transmission and reception (hereinafter referred to as a bidirectional amplifier) instead of providing amplifiers in the transmission path and the reception path. By providing this bidirectional amplifier, it is possible to significantly reduce the components of the circuit in the wireless communication device.

[0005] Japanese Patent Publication No. Hei 9-505450

[0006] Conventional bidirectional amplifiers, as described in Patent Document 1, have a problem in that when the number of amplifier stages is increased to obtain the desired gain, the bias voltage must be increased in proportion to the number of stages, and the bias voltage may exceed the withstand voltage of the elements. When a bias voltage exceeding the withstand voltage of the elements is applied, bidirectional amplifiers require that when voltage control is performed to reverse the amplification direction, a voltage that does not exceed the withstand voltage is applied to each component constituting the amplifier. For this reason, a control circuit is required to control the voltage when switching the amplification direction.

[0007] This disclosure aims to solve the above-mentioned problems and to provide a bidirectional amplifier that can suppress the application of voltages exceeding the element's withstand voltage.

[0008] The bidirectional amplifier according to this disclosure comprises a plurality of transistors having a symmetrical structure and a matching circuit having symmetry and blocking the DC component, wherein the plurality of transistors are connected in series between the transistors via a complex conjugate matching circuit.

[0009] According to this disclosure, since the DC component of the voltage applied to each transistor is blocked by the matching circuit, even if the applied voltage is dynamically changed, the bidirectional amplifier according to this disclosure can suppress the application of a voltage exceeding the element withstand voltage.

[0010] This is a circuit diagram showing an example configuration of a conventional wireless communication device. This is a circuit diagram showing an example configuration of a wireless communication device using a bidirectional amplifier. This is a circuit diagram showing an example configuration of a bidirectional amplifier according to Embodiment 1. This is a Smith chart showing the input / output impedance frequency characteristics of a gate-grounded FET in the 300 GHz band. This is a circuit diagram showing a modified configuration of the bidirectional amplifier according to Embodiment 1. This is a circuit diagram showing an example configuration of a wireless communication device according to Embodiment 2. This is a circuit diagram showing an example configuration of a bidirectional amplifier according to Embodiment 2. This is a circuit diagram showing a modified configuration of the bidirectional amplifier according to Embodiment 2. This is a circuit diagram showing an example configuration of a wireless communication device according to Embodiment 3. This is a circuit diagram showing an example configuration of a bidirectional amplifier according to Embodiment 3. This is an equivalent circuit diagram showing a transformer with a turns ratio of 1:1. This is a circuit diagram showing a modified configuration of the bidirectional amplifier according to Embodiment 3.

[0011] Embodiment 1. The wireless communication device according to Embodiment 1 is equipped with a bidirectional amplifier. In general wireless communication devices, separate amplifiers are required for transmission and reception, but by incorporating a bidirectional amplifier, both transmission and reception functions can be realized with a single amplifier. As a result, the wireless communication device according to Embodiment 1 has a simplified circuit and the number of required components can be reduced.

[0012] Figure 1 is a circuit diagram showing an example configuration of a conventional wireless communication device 1. The wireless communication device 1 has separate amplification stages for transmission and reception. In Figure 1, the wireless communication device 1 transmits and receives signals via a wireless transmitting and receiving antenna 2. The wireless communication device 1 receives an intermediate frequency signal via an input terminal 3 and outputs an intermediate frequency signal to the outside of the device via an output terminal 4.

[0013] The wireless transceiver antenna 2 converts the transmit electrical signal into an electromagnetic wave and transmits it, and receives the electromagnetic wave and converts it into a received electrical signal. The intermediate frequency signal input to the input terminal 3 is used to generate the transmit electrical signal. The intermediate frequency signal output from the output terminal 4 is generated from the received electrical signal.

[0014] As shown in Figure 1, the wireless communication device 1 includes a transmit / receive switch 5, a local oscillator frequency oscillator 6, a transmitting local oscillator frequency amplifier 7, a receiving local oscillator frequency amplifier 8, a transmitting intermediate frequency amplifier 9, a transmitting upconversion mixer 10, a transmitting radio frequency band amplifier 11, a receiving intermediate frequency amplifier 12, a receiving downconversion mixer 13, and a receiving radio frequency band amplifier 14.

[0015] The transmit / receive switch 5 is a device for switching the wireless transmit / receive antenna 2 between transmission and reception. During transmission, the transmit / receive switch 5 connects the signal from the transmitting system to the wireless transmit / receive antenna 2, and during reception, it connects the wireless transmit / receive antenna 2 to the receiving system to receive electromagnetic waves in space.

[0016] The local oscillator frequency generator 6 is a device that oscillates the local oscillator frequency. The local oscillator frequency varies depending on the communication protocol or frequency band, such as the center frequency of the transmitted signal or the local oscillation frequency of the received signal. The transmitting local oscillator frequency amplifier 7 amplifies the local oscillator frequency signal oscillated by the local oscillator frequency generator 6 and outputs the amplified local oscillator frequency signal to the transmitting upconversion mixer 10. The receiving local oscillator frequency amplifier 8 amplifies the local oscillator frequency signal oscillated by the local oscillator frequency generator 6 and outputs the amplified local oscillator frequency signal to the receiving downconversion mixer 13.

[0017] The transmitting intermediate frequency amplifier 9 amplifies the transmitting intermediate frequency signal input to the input terminal 3 and outputs the amplified intermediate frequency signal to the transmitting upconversion mixer 10. The transmitting upconversion mixer 10 generates a transmitting signal with the intermediate frequency converted to a higher frequency by mixing the local oscillator frequency signal amplified by the transmitting local oscillator frequency amplifier 7 and the intermediate frequency signal amplified by the transmitting intermediate frequency amplifier 9. The transmitting radio frequency band amplifier 11 amplifies the transmitting signal generated by the transmitting upconversion mixer 10 and outputs the amplified transmitting signal to the transmit / receive switch 5.

[0018] The receiving intermediate frequency amplifier 12 amplifies the intermediate frequency signal output from the receiving down-conversion mixer 13 and outputs the amplified intermediate frequency signal to the output terminal 4. The receiving down-conversion mixer 13 generates a received intermediate frequency signal converted to an intermediate frequency lower than the radio frequency of the received signal by mixing the received signal amplified by the receiving radio frequency band amplifier 14 and the local oscillator frequency signal amplified by the receiving local oscillator frequency amplifier 8. The receiving radio frequency band amplifier 14 amplifies the received signal received by the radio transmitting and receiving antenna 2 and outputs the amplified received signal to the receiving down-conversion mixer 13.

[0019] In the wireless communication device 1, the transmitting amplification stage consists of a transmitting intermediate frequency amplifier 9 and a transmitting radio frequency band amplifier 11, while the receiving amplification stage consists of a receiving intermediate frequency amplifier 12 and a receiving radio frequency band amplifier 14. Because the wireless communication device 1 requires two amplification stages, the overall miniaturization of the device is limited.

[0020] On the other hand, the wireless communication device according to Embodiment 1 can perform both transmission and reception functions with a single amplifier by including a bidirectional amplifier. Figure 2 is a circuit diagram showing an example of the configuration of the wireless communication device 21 according to Embodiment 1. The wireless communication device 1 includes a bidirectional amplifier. In Figure 2, the wireless communication device 21 transmits and receives signals via the wireless transmitting and receiving antenna 22. The wireless communication device 21 receives an intermediate frequency signal via the input / output terminal 23 and outputs an intermediate frequency signal to the outside of the device.

[0021] The wireless transceiver antenna 22 converts the transmit electrical signal into electromagnetic waves and transmits it, and receives the electromagnetic waves and converts them into a received electrical signal. The transmission intermediate frequency signal input to the input / output terminal 23 is used to generate the transmit electrical signal. The received intermediate frequency signal output from the input / output terminal 23 is generated from the received electrical signal.

[0022] As shown in Figure 2, the wireless communication device 21 includes a local oscillator frequency oscillator 24, a local oscillator frequency amplifier 25, an intermediate frequency band bidirectional amplifier 26, a radio frequency band bidirectional amplifier 28, and a transmit / receive frequency converter 27. The local oscillator frequency oscillator 24 is a device that emits the local oscillator frequency. The local oscillator frequency varies depending on the communication protocol or frequency band, such as the center frequency of the transmitted signal or the local oscillation frequency of the received signal.

[0023] The local oscillator frequency amplifier 25 amplifies the local oscillator frequency signal oscillated by the local oscillator frequency oscillator 24 and outputs the amplified local oscillator frequency signal to the transmit / receive frequency converter 27. The intermediate frequency band bidirectional amplifier 26 and the radio frequency band bidirectional amplifier 28 are bidirectional amplifiers according to Embodiment 1, and have the ability to amplify signals in both input and output directions, enabling both transmission and reception functions to be realized with a single amplifier.

[0024] The intermediate frequency band bidirectional amplifier 26 is a transmitting and receiving intermediate frequency amplifier that amplifies the transmitting intermediate frequency signal input to the input / output terminal 23, and further amplifies the received intermediate frequency signal that has been converted from radio frequency to intermediate frequency by the transmitting / receiving frequency converter 27. The radio frequency band bidirectional amplifier 28 is a transmitting and receiving radio frequency amplifier that amplifies the transmitting signal that has been converted to a radio frequency signal higher than the intermediate frequency by the transmitting / receiving frequency converter 27, and further amplifies the radio received signal that has been received by the radio transmitting / receiving antenna 22.

[0025] The transmit / receive frequency converter 27 generates a transmit signal by converting the intermediate frequency to a higher frequency by mixing the local oscillator frequency signal amplified by the local oscillator frequency amplifier 25 and the intermediate frequency signal amplified by the intermediate frequency band bidirectional amplifier 26. Furthermore, the transmit / receive frequency converter 27 generates a received intermediate frequency signal converted to an intermediate frequency lower than the radio frequency of the received signal by mixing the received signal amplified by the radio frequency band bidirectional amplifier 28 and the local oscillator frequency signal amplified by the local oscillator frequency amplifier 25.

[0026] The wireless communication device 21 can achieve the same functions as the wireless communication device 1 using only components such as a local oscillator frequency oscillator 24, a local oscillator frequency amplifier 25, an intermediate frequency band bidirectional amplifier 26, a radio frequency band bidirectional amplifier 28, and a transmit / receive frequency converter 27. However, in a typical bidirectional amplifier, if the number of amplifier stages is increased, the output signal may exceed the bias voltage of the previous stage, and the bias voltage may exceed the withstand voltage of the element.

[0027] Therefore, the intermediate frequency band bidirectional amplifier 26 and the radio frequency band bidirectional amplifier 28 according to Embodiment 1 use a complex conjugate matching circuit that blocks DC and has a symmetrical structure, allowing the bias voltage applied to each FET to be controlled independently. This suppresses the application of voltages exceeding the element withstand voltage even when the amplifiers are connected in multiple stages. The intermediate frequency band bidirectional amplifier 26 and the radio frequency band bidirectional amplifier 28 will be described in detail below.

[0028] Figure 3 is a circuit diagram showing an example configuration of an intermediate frequency band bidirectional amplifier 26 and a radio frequency band bidirectional amplifier 28 according to Embodiment 1. The intermediate frequency band bidirectional amplifier 26 and the radio frequency band bidirectional amplifier 28, for example, amplify the signal input to the input / output terminal 30 and output the amplified signal from the input / output terminal 31. The intermediate frequency band bidirectional amplifier 26 and the radio frequency band bidirectional amplifier 28 also amplify the signal input to the input / output terminal 31 and output the amplified signal from the input / output terminal 30. In the intermediate frequency band bidirectional amplifier 26 and the radio frequency band bidirectional amplifier 28, a bias voltage is applied from the bias voltage application terminal 32 and the bias voltage application terminal 33, and a gate voltage is applied from the gate voltage application terminal 34. The bias voltage application terminal 32 is a first bias voltage application terminal to which the bias voltage of terminal B, described later, is applied, and the bias voltage application terminal 33 is a second bias voltage application terminal to which the bias voltage of terminal A, described later, is applied.

[0029] As shown in Figure 3, the intermediate frequency band bidirectional amplifier 26 and the radio frequency band bidirectional amplifier 28 include field-effect transistors (hereinafter referred to as FETs) 35-37, a variable matching circuit 38, a variable matching circuit 40, a complex conjugate matching circuit 39, an AC blocking element 41, an AC blocking element 42, an AC blocking element 43, and a capacitive element 44. FETs 35-37 are connected in series between the FETs via the complex conjugate matching circuit 39. Specifically, the complex conjugate matching circuit 39 is connected in series between terminal B1 of FET 35 and terminal A2 of FET 36, and the complex conjugate matching circuit 39 is connected in series between terminal B2 of FET 36 and source terminal A3 of FET 37. The capacitive element 44 is a stabilized capacitive element connected to the gate terminals of FETs 35-37 and the AC blocking element 43, with the other end grounded. The AC blocking element 43 blocks the AC component to the gate terminal. The capacitive element 44 appropriately stabilizes the DC component applied to the gate terminal of the FET. Although the example shows the gate terminal of the FET being grounded via the capacitive element 44, it is not limited to this case. In other words, the gate terminal is grounded to stabilize the gate potential, and grounding includes not only grounding to the ground potential but also fixing it to a specific reference potential.

[0030] In Figure 3, FETs 35 to 37 are transistors with a symmetrical structure and identical structure. A symmetrical structure of an FET is a transistor structure that uses holes (p-type semiconductor) or electrons (n-type semiconductor) to form the channel. FETs 35 to 37 may have different parameters, as long as they are FETs with a symmetrical structure. In this case, the complex conjugate matching circuit 39 loaded between the FETs must also be designed individually.

[0031] A variable matching circuit 38 is installed between the input / output terminal 30 and terminal A1 of the FET 35, which is capable of bidirectional matching by adjusting the element parameters in accordance with the reversal of the amplification direction. The input / output terminal 30 is the first input / output terminal, and the variable matching circuit 38 is the first variable matching circuit. A variable matching circuit 40 is installed between the input / output terminal 31 and terminal B3 of the FET 37, which is capable of bidirectional matching by adjusting the element parameters in accordance with the reversal of the amplification direction. The input / output terminal 31 is the second input / output terminal, and the variable matching circuit 40 is the second variable matching circuit.

[0032] For example, when a FET with a symmetrical structure operates as a common-gate amplifier, the input impedance and output impedance of the FET may differ significantly. Figure 4 is a Smith chart showing the input / output impedance frequency characteristics of FETs 35-37, which are common-gate FETs, in the 300 GHz band. As shown in Figure 4, the input impedance frequency characteristics 50 and output impedance frequency characteristics 51 of the common-gate FET differ significantly. To complex conjugate match the input impedance and output impedance of the FET, it is necessary to load a matching element at the input terminal of the FET and shift the input impedance to the complex conjugate frequency characteristics 52 of the output impedance.

[0033] (Input / Output terminal 30 → Input / Output terminal 31) For example, in the intermediate frequency band bidirectional amplifier 26 and the radio frequency band bidirectional amplifier 28, the direction in which input / output terminal 30 is the input and input / output terminal 31 is the output is called the "forward direction," and the direction in which input / output terminal 31 is the input and input / output terminal 30 is the output is called the "reverse direction." Each transistor in the bidirectional amplifier, such as an FET, has three terminals A, B, and G. In gate-grounded mode, terminals A and B are used for signal input and output, and terminal G is the terminal to which the ground voltage is applied. If the transistor is an FET with a voltage rating of 1V, in the forward direction, terminal A is applied with the lowest voltage, such as 0V, and functions as the source terminal; terminal B is applied with the highest voltage, such as 1V, and functions as the drain terminal; and terminal G is grounded at 0.5V and functions as the gate terminal. Furthermore, in the reverse direction, which will be described later, the highest voltage, such as 1V, is applied to terminal A and functions as a terminal, the lowest voltage, such as 0V, is applied to terminal B and functions as a source terminal, and terminal G is grounded to a voltage such as 0.5V and functions as a gate terminal. When the directionality is determined in the forward direction, it is necessary to apply a high voltage to terminal B of FETs 35 to 37. AC blocking elements 41 are mounted in series between terminal B1 of FET 35, terminal B2 of FET 36, and terminal B3 of FET 37 and the bias voltage application terminal 32. The AC blocking element 41 is a first AC blocking element, and generally, a transmission line with an electrical length of one-quarter wavelength that provides a sufficiently high impedance in the signal frequency band to be amplified is used.

[0034] Furthermore, a DC stabilizing capacitor element may be connected in parallel to the bias voltage application terminal 32 to stabilize the DC component. Although not shown in the diagram, this DC stabilizing capacitor element has one terminal connected to the bias voltage application terminal 32 and the other terminal grounded.

[0035] When the direction is determined such that input / output terminal 30 is the input and input / output terminal 31 is the output, a low voltage needs to be applied to terminal A of FETs 35 to 37. AC blocking elements 42 are mounted in series between terminal A1 of FET 35, terminal A2 of FET 36, and terminal A3 of FET 37 and the bias voltage application terminal 33. The AC blocking element 42 is a second AC blocking element, and generally, a transmission line with an electrical length of one-quarter wavelength that provides a sufficiently high impedance in the signal frequency band to be amplified is used.

[0036] Furthermore, a DC stabilizing capacitor element may be connected in parallel to the bias voltage application terminal 33 to stabilize the DC component. Although not shown in the diagram, this DC stabilizing capacitor element has one terminal connected to the bias voltage application terminal 33 and the other terminal grounded.

[0037] AC blocking elements 43 are connected in series between terminal G1 of FET 35, terminal G2 of FET 36, and terminal G3 of FET 37 and the gate voltage application terminal 34. The AC blocking elements 43 are third AC blocking elements, and generally, a transmission line with an electrical length of one-quarter wavelength that provides a sufficiently high impedance in the signal frequency band to be amplified is used.

[0038] Furthermore, a DC stabilizing capacitor element may be connected in parallel to the gate voltage application terminal 34 to stabilize the DC component. Although not shown in the figure, this DC stabilizing capacitor element has one terminal connected to the gate voltage application terminal 34 and the other terminal grounded.

[0039] Note that the voltage applied to each gate terminal of FETs 35 to 37 shown in Figure 3 is configured to be the same voltage. However, this is not the only option, and each gate voltage may be controlled individually.

[0040] For example, the following describes a case where a signal input to input / output terminal 30 is amplified and output from input / output terminal 31, and FETs with a component withstand voltage of 1.0V are used as FETs 35-37. In this case, the voltage applied to terminals A1, A2, and A3 of FETs 35-37 must be low voltage, and the voltage applied to terminals B1, B2, and B3 of the output side FETs 35-37 must be high voltage. For this reason, for example, a voltage of 1.0V is applied to the bias voltage application terminal 32, the voltage applied to the bias voltage application terminal 33 is set to 0V, and 0.5V is applied to the gate voltage application terminal 34. At this time, terminals A1, A2, and A3 operate as source terminals, and terminals B1, B2, and B3 operate as terminals.

[0041] In FET 35, 0V is applied to input terminal A1 via AC blocking element 42, 1.0V is applied to output terminal B1 via AC blocking element 41, and 0.5V is applied to gate terminal G1 via AC blocking element 43. As a result, FET 35 functions as a gate-grounded amplifier element in which gate terminal G1 is stabilized in the signal frequency band by AC blocking element 43.

[0042] Similarly, in FET 36, 0V is applied to input terminal A2 via AC blocking element 42, 1.0V is applied to output terminal B2 via AC blocking element 41, and 0.5V is applied to gate terminal G2 via AC blocking element 43. As a result, FET 36 functions as a gate-grounded amplifier element in which gate terminal G2 is stabilized in the signal frequency band by AC blocking element 43.

[0043] In FET 37, 0V is applied to input terminal A3 via AC blocking element 42, 1.0V is applied to output terminal B3 via AC blocking element 41, and 0.5V is applied to gate terminal G3 via AC blocking element 43. FET 37 functions as a gate-grounded amplifier element with its gate terminal G3 stabilized in the signal frequency band by AC blocking element 43.

[0044] In FET35, the impedance of input / output terminal 30 is matched by variable matching circuit 38. The impedance of input / output terminal 30 is generally 50 Ω. A complex conjugate matching circuit 39 is loaded between FET35 and FET36. The complex conjugate matching circuit 39 complex conjugate matches the impedance of terminal B1 of FET35 and the impedance of terminal A2 of FET36 while blocking the DC components of the voltage of 1.0 V applied to terminal B1 of FET35 and the voltage of 0 V applied to terminal B2 of FET36.

[0045] Similarly, a complex conjugate matching circuit 39 is also loaded between FET36 and FET37. The complex conjugate matching circuit 39 complex conjugate matches the impedance of terminal B2 of FET36 and the impedance of terminal A3 of FET37 while blocking the DC components of the voltage of 1.0 V applied to terminal B2 of FET36 and the voltage of 0 V applied to terminal A3 of FET37. In FET37, the impedance of input / output terminal 31 is matched by variable matching circuit 40. The impedance of input / output terminal 31 is generally 50 Ω.

[0046] (Input / output terminal 31 → input / output terminal 30) When the signal amplification directions of bidirectional amplifiers 26 and 28 are reversed, that is, for the "reverse direction" where a signal is input to input / output terminal 31 and output from input / output terminal 30, an explanation will be given. In this case, the voltages applied to terminals B1, B2, and B3 of FETs 35 to 37 are low voltages and function as source terminals, and the voltages applied to terminals A3, A2, and A1 of FETs 35 to 37 are high voltages and need to function as drain terminals. Therefore, for example, a voltage of 0 V is applied to bias voltage application terminal 32, the voltage applied to bias voltage application terminal 33 is 1.0 V, and a voltage of 0.5 V is applied to gate voltage application terminal 34.

[0047] In FET37, 0V is applied to terminal B3 serving as an input terminal via AC cutoff element 41, 1.0V is applied to terminal A3 serving as an output terminal via AC cutoff element 42, and 0.5V is applied to gate terminal G3 via AC cutoff element 43. As a result, FET37 functions as a gate-grounded amplifier element in which gate terminal G3 is stabilized in the signal frequency band by AC cutoff element 43.

[0048] Similarly, in FET36, 0V is applied to terminal B2 serving as an input terminal via AC cutoff element 41, 1.0V is applied to terminal A2 serving as an output terminal via AC cutoff element 42, and 0.5V is applied to gate terminal G2 via AC cutoff element 43. As a result, FET36 functions as a gate-grounded amplifier element in which gate terminal G2 is stabilized in the signal frequency band by AC cutoff element 43.

[0049] In FET35, 0V is applied to terminal B1 serving as an input terminal via AC cutoff element 41, 1.0V is applied to terminal A1 serving as an output terminal via AC cutoff element 42, and 0.5V is applied to gate terminal G1 via AC cutoff element 43. As a result, FET35 functions as a gate-grounded amplifier element in which gate terminal G1 is stabilized in the signal frequency band by AC cutoff element 43.

[0050] In FET37, the impedance of input / output terminal 31 is matched by variable matching circuit 40. The impedance of input / output terminal 31 is generally 50Ω. A complex conjugate matching circuit 39 is loaded between FET37 and FET36. Complex conjugate matching circuit 39 complex conjugate matches the impedance of terminal B2 of FET36 and the impedance of terminal A3 of FET37 while blocking the DC components of the voltage 0V applied to terminal B2 of FET36 and the voltage 1.0V applied to terminal A3 of FET37.

[0051] Similarly, a complex conjugate matching circuit 39 is installed between FET 36 and FET 35. The complex conjugate matching circuit 39 blocks the DC component of the voltage 0V applied to terminal B1 of FET 35 and the voltage 1.0V applied to terminal A2 of FET 36, while complex conjugate matching the impedance of terminal B1 of FET 35 and the impedance of terminal A2 of FET 36. In FET 35, the impedance of the input / output terminal 30 is matched by a variable matching circuit 38. The impedance of the input / output terminal 30 is generally 50Ω.

[0052] The complex conjugate matching circuit 39 mounted between the FETs blocks the DC component and has a symmetrical structure. Therefore, even when the orientation is determined such that input / output terminal 30 is the input and input / output terminal 31 is the output, or when the orientation is determined such that input / output terminal 31 is the input and input / output terminal 30 is the output, complex conjugate matching between the FETs is achieved and the same frequency characteristics can be obtained. The voltages applied to FETs 35 to 37 are separated by the complex conjugate matching circuit 39 and remain below the element withstand voltage of 1.0V. Therefore, even if the voltage applied to FETs 35 to 37 is dynamically changed, exceeding the element withstand voltage is suppressed.

[0053] In the bidirectional amplifier described in Patent Document 1, if the number of amplifier stages is increased to obtain the desired gain, the bias voltage must be increased in proportion to the number of stages. Furthermore, in the bidirectional amplifier described in Patent Document 1, the types of gate voltages and intermediate voltages applied to the amplifier increase with the number of stages. This leads to the problem of the voltage control circuit becoming more complex and larger. Moreover, in the bidirectional amplifier described in Patent Document 1, a bias voltage near the element withstand voltage must be applied to each stage in order to maximize the performance of the amplifier. Therefore, in the bidirectional amplifier described in Patent Document 1, if the amplifier is configured with multiple stages, the bias voltage applied to the entire amplifier inevitably exceeds the element withstand voltage. When such a voltage exceeding the element withstand voltage is applied, it is necessary to control the voltage during power-on, power-off, and reversal of the amplification direction so as not to exceed the element withstand voltage, and a control circuit for sequentially switching the voltage must be provided.

[0054] In contrast, the bidirectional amplifiers 26 and 28 can independently control the bias voltage applied to the FETs 35 to 37 by the complex conjugate matching circuit 39. This makes it possible to operate the entire amplifier with a bias voltage below the element withstand voltage, even when multiple amplifiers are connected in stages. Furthermore, since the voltage control during power-on / off and reversal of amplification is below the element withstand voltage, a complex control circuit is unnecessary.

[0055] (Differential Amplification) Next, a modified example of the bidirectional amplifiers 26 and 28 according to Embodiment 1 will be described. Figure 5 is a circuit diagram showing the configuration of a modified example of the bidirectional amplifiers 26 and 28, in which the FETs connected in series via the complex conjugate matching circuit 39D are differential transistors. In Figure 5, the modified bidirectional amplifiers 26 and 28 amplify the signal input to the input / output terminal 30 and amplify the signal output from the input / output terminal 31, similar to the circuit in Figure 3. The bidirectional amplifiers 26 and 28 also amplify the signal input to the input / output terminal 31 and output the amplified signal from the input / output terminal 30. In addition, in the bidirectional amplifiers 26 and 28, a bias voltage is applied from the bias voltage application terminals 32 and 33, and a gate voltage is applied from the gate voltage application terminal 34.

[0056] As shown in Figure 5, the bidirectional amplifiers 26 and 28 include differential transistors 35D to 37D, a variable matching circuit 38D, a variable matching circuit 40D, and a complex conjugate matching circuit 39D. The differential transistors 35D to 37D are connected in series between them via the complex conjugate matching circuit 39D. Specifically, the complex conjugate matching circuit 39D is connected in series between terminals B1a and B1b of differential transistor 35D and terminals A2a and A2b of differential transistor 37D, and the complex conjugate matching circuit 39D is connected in series between terminals B2a and B2b of differential transistor 36D and terminals A3a and A3b of differential transistor 37D.

[0057] Furthermore, a variable matching circuit 38D capable of bidirectional matching by adjusting element parameters in accordance with the reversal of the amplification direction may be installed between the input / output terminal 30 and the differential transistor 35D. In addition, a variable matching circuit 40D capable of bidirectional matching by adjusting element parameters in accordance with the reversal of the amplification direction may be installed between the input / output terminal 31 and the differential transistor 37D.

[0058] The differential transistor 35D is composed of FET 35a and FET 35b, with terminal G1a of FET 35a and terminal G1b of FET 35b connected. Terminal A1a of FET 35a and terminal A1b of FET 35b are connected to the input / output terminal 30 via the variable matching circuit 38D. Terminal B1a of FET 35a and terminal B1b of FET 35b are connected to the complex conjugate matching circuit 39D. Similarly, the differential transistor 36D is composed of FET 36a and FET 36b, with gate terminal G2a of FET 36a and gate terminal G2b of FET 36b connected. Terminal A2a of FET 36a and terminal A2b of FET 36b are connected to terminal B1a of FET 35a and terminal B1b of FET 35b via the complex conjugate matching circuit 39D. Terminal B2a of FET 36a and terminal B2b of FET 36b are connected to the complex conjugate matching circuit 39D. Similarly, the differential transistor 37D is composed of FET 37a and FET 37b, with the gate terminal G3a of FET 37a and the gate terminal G3b of FET 37b being connected. Terminal A3a of FET 37a and terminal A3b of FET 37b are connected to terminal B2a of FET 36a and terminal B2b of FET 36b via the complex conjugate matching circuit 39D. Terminal B3a of FET 37a and terminal B3b of FET 37b are connected to the input / output terminal 31 via the variable matching circuit 40D.

[0059] In a differential transistor, the two FETs operate symmetrically, so common-phase AC components are canceled at the output terminal. On the other hand, in a single FET, a stabilizing capacitor (capacitor element 44) is required to stabilize the DC at the gate terminal. Thus, in a differential transistor, the cancellation of common-phase AC components is achieved by its structure, and as shown in Figure 5, the capacitor element 44 and the AC blocking element 43 can be omitted compared to the configuration in Figure 3. This makes it possible to reduce the circuit size of the bidirectional amplifiers 26 and 28.

[0060] As described above, the bidirectional amplifiers 26 and 28 according to Embodiment 1 include FETs 35 to 37 or 35D to 37D having a symmetrical structure, and a complex conjugate matching circuit 39 or 39D having symmetry and blocking the DC component. The FETs 35 to 37 or 35D to 37D are connected in series between the FETs via the complex conjugate matching circuit 39 or 39D. Since the voltage applied to each FET is separated by the complex conjugate matching circuit 39 or 39D, the bidirectional amplifiers 26 and 28 can suppress the application of voltages exceeding the element withstand voltage even when the applied voltage is dynamically changed.

[0061] Furthermore, in the bidirectional amplifiers 26 and 28 according to Embodiment 1, the FETs 35 to 37 have a gate terminal G and two terminals A and B. In one bidirectional direction, one of the two terminals functions as a drain terminal and the other terminal functions as a source terminal. In the other bidirectional direction, one of the two terminals functions as a source terminal and the other terminal functions as a drain terminal. The amplifier includes an AC blocking element 41 connected to one of the two terminals and a bias voltage application terminal 32 to block the AC component in the signal frequency band, an AC blocking element 42 connected to the other terminal and a bias voltage application terminal 33 to block the AC component in the signal frequency band, and an AC blocking element 43 connected to a grounded gate terminal and a gate voltage application terminal 34 to block the AC component in the signal frequency band. The AC blocking elements 41, 42, and 43 can block the AC component applied to each terminal of the FET.

[0062] The bidirectional amplifiers 26 and 28 according to Embodiment 1 include a DC stabilized capacitor element with one end connected to a bias voltage application terminal 32 and the other end grounded, a DC stabilized capacitor element with one end connected to a bias voltage application terminal 33 and the other end grounded, and a DC stabilized capacitor element with one end connected to a gate voltage application terminal 34 and the other end grounded. This allows for appropriate stabilization of the DC component applied to each terminal of the FET.

[0063] In the bidirectional amplifiers 26 and 28 according to Embodiment 1, the FETs connected in series via the complex conjugate matching circuit 39D are differential transistors 35D to 37D, in which two FETs 35a and 35b, 36a and 36b, and 37a and 37b are connected. The capacitive element 44 and the AC blocking element 43 can be omitted. This makes it possible to reduce the circuit size of the bidirectional amplifiers 26 and 28.

[0064] The bidirectional amplifiers 26 and 28 according to Embodiment 1 include a variable matching circuit 38 or 38D connected to the input / output terminal 30 for matching with the outside of the amplifier, and a variable matching circuit 40 or 40D connected to the input / output terminal 31 for matching with the outside of the amplifier. Terminal A of the FET 35 or differential transistor 35D located at one end of the series is connected to the input / output terminal 30 via the variable matching circuit 38 or 38D, and terminal B of the FET 37 or differential transistor 37D located at the other end of the series is connected to the input / output terminal 31 via the variable matching circuit 40 or 40D. This makes it possible to prevent oscillation due to reflection of high-frequency signals, for example.

[0065] The wireless communication device 21 according to Embodiment 1 includes bidirectional amplifiers 26 and 28, so that the application of a voltage exceeding the element withstand voltage in the amplifier can be suppressed.

[0066] Embodiment 2. Embodiment 2 describes a bidirectional amplifier equipped with a complex conjugate matching circuit composed of inductive elements.

[0067] Figure 6 is a circuit diagram showing an example configuration of a wireless communication device 61 according to Embodiment 2. In Figure 6, the wireless communication device 61 transmits and receives signals via a wireless transmitting and receiving antenna 22. The wireless communication device 61 receives intermediate frequency signals and outputs intermediate frequency signals to the outside of the device via input / output terminals 23. The wireless transmitting and receiving antenna 22 converts the transmit electrical signal into electromagnetic waves and transmits them, and receives the electromagnetic waves and converts them into received electrical signals. The transmission intermediate frequency signal input to the input / output terminals 23 is used to generate the transmit electrical signal. The received intermediate frequency signal output from the input / output terminals 23 is generated from the received electrical signal.

[0068] As shown in Figure 6, the wireless communication device 61 includes a local oscillator frequency oscillator 24, a local oscillator frequency amplifier 25, a bidirectional amplifier 66, a bidirectional amplifier 68, and a transmit / receive frequency converter 27. The local oscillator frequency oscillator 24 is a device that emits the local oscillator frequency. The local oscillator frequency varies depending on the communication protocol or frequency band, such as the center frequency of the transmitted signal or the local oscillation frequency of the received signal.

[0069] The local oscillator frequency amplifier 25 amplifies the local oscillator frequency signal oscillated by the local oscillator frequency oscillator 24 and outputs the amplified local oscillator frequency signal to the transmit / receive frequency converter 27. The bidirectional amplifiers 66 and 68 are bidirectional amplifiers according to Embodiment 2, and have the ability to amplify signals in both input and output directions, enabling both transmission and reception functions to be realized with a single amplifier.

[0070] The bidirectional amplifier 66 is a transceiver intermediate frequency amplifier that amplifies the intermediate frequency signal for transmission input to the input / output terminal 23, and further amplifies the received intermediate frequency signal that has been converted from radio frequency to intermediate frequency by the transceiver frequency converter 27. The bidirectional amplifier 68 is a transceiver radio frequency amplifier that amplifies the transmission signal that has been converted to a radio frequency signal higher than the intermediate frequency by the transceiver frequency converter 27, and further amplifies the radio received signal that has been received by the radio transceiver antenna 22.

[0071] The transmit / receive frequency converter 27 generates a transmit signal by converting the intermediate frequency to a higher frequency by mixing the local oscillator frequency signal amplified by the local oscillator frequency amplifier 25 and the intermediate frequency signal amplified by the bidirectional amplifier 66. Furthermore, the transmit / receive frequency converter 27 generates a received intermediate frequency signal converted to an intermediate frequency lower than the radio frequency of the received signal by mixing the received signal amplified by the bidirectional amplifier 68 and the local oscillator frequency signal amplified by the local oscillator frequency amplifier 25.

[0072] The bidirectional amplifiers 66 and 68 according to Embodiment 2 can independently control the bias voltage applied to the FETs by a complex conjugate matching circuit, thereby suppressing the application of voltages exceeding the element withstand voltage even when multiple amplifiers are connected in stages. The bidirectional amplifiers 66 and 68 will be described in detail below.

[0073] Figure 7 is a circuit diagram showing an example configuration of bidirectional amplifiers 66 and 68 according to Embodiment 2. The bidirectional amplifiers 66 and 68 amplify the signal input to the input / output terminal 30 and output it from the input / output terminal 31. The bidirectional amplifiers 66 and 68 also amplify the signal input to the input / output terminal 31 and output the amplified signal from the input / output terminal 30. In the bidirectional amplifiers 66 and 68, a bias voltage is applied from the bias voltage application terminal 32, a bias voltage is applied from the bias voltage application terminal 33, and a gate voltage is applied from the gate voltage application terminal 34.

[0074] As shown in Figure 7, the bidirectional amplifiers 66 and 68 include FETs 35 to 37, a variable matching circuit 38, a variable matching circuit 40, a complex conjugate matching circuit 70, an AC blocking element 41, an AC blocking element 42, a capacitive element 44, and an AC blocking element 43. The capacitive element 44 is a stabilized capacitive element with one end connected to the connection point between the gate terminal of the FET and the AC blocking element 43, and the other end grounded. The AC blocking element 43 blocks the AC component to the gate terminal. The capacitive element 44 appropriately stabilizes the DC component applied to the gate terminal of the FET.

[0075] A variable matching circuit 38 is installed between the input / output terminal 30 and terminal A1 of FET 35, which allows for bidirectional matching by adjusting the element parameters in accordance with the reversal of the amplification direction. A variable matching circuit 40 is installed between the input / output terminal 31 and terminal B3 of FET 37, which allows for bidirectional matching by adjusting the element parameters in accordance with the reversal of the amplification direction.

[0076] FETs 35 to 37 are connected in series between them via a complex conjugate matching circuit 70. Specifically, the complex conjugate matching circuit 70 is connected in series between terminal B1 of FET 35 and terminal A2 of FET 36, and the complex conjugate matching circuit 70 is connected in series between terminal D2 of FET 36 and terminal A3 of FET 37.

[0077] The complex conjugate matching circuit 70 is comprised of an inductive element 71, an inductive element 73, and a capacitive element 72. In the complex conjugate matching circuit 70 provided between FET 35 and FET 36, the inductive element 71 is a first inductive reactance element with one terminal connected to terminal B1 of FET 35 and the other terminal connected to the bias voltage application terminal 32. In the complex conjugate matching circuit 70 provided between FET 36 and FET 37, the inductive element 71 is a first inductive reactance element with one terminal connected to terminal B2 of FET 36 and the other terminal connected to the bias voltage application terminal 32.

[0078] In the complex conjugate matching circuit 70 provided between FET 35 and FET 36, the inductive element 73 is a second inductive reactance element with one terminal connected to terminal A2 of FET 36 and the other terminal connected to the bias voltage application terminal 33. Also, in the complex conjugate matching circuit 70 provided between FET 36 and FET 37, the inductive element 73 is a second inductive reactance element with one terminal connected to terminal A3 of FET 37 and the other terminal connected to the bias voltage application terminal 33.

[0079] Furthermore, the capacitive element 72 is provided between one terminal of the inductive element 71 and one terminal of the inductive element 73, and is a DC blocking element that blocks DC current. The complex conjugate matching circuit 70 is a circuit with a symmetrical structure in which the inductive element 71 is connected to one end of the capacitive element 72 and the inductive element 73 is connected to the other end.

[0080] Furthermore, a capacitive element may be provided between the other end of the inductive element 71 and the bias voltage application terminal 32. Although not shown in the figure, this capacitive element has one end connected to the connection point between the inductive element 71 and the bias voltage application terminal 32, and the other end is grounded. Additionally, a capacitive element may be provided between the other end of the inductive element 73 and the bias voltage application terminal 33. Although not shown in the figure, this capacitive element has one end connected to the connection point between the inductive element 73 and the bias voltage application terminal 33, and the other end is grounded.

[0081] The inductive elements 71 and 73 also function as the AC interruption elements 41 and 42, which are power supply lines, as shown in Embodiment 1. Therefore, the voltage application terminals connected to the ends of the inductive elements 71 and 73 that are not on the FET side may be loaded with the capacitive elements described above in order to make them low impedance in the signal frequency band. In addition, the element constants of the inductive elements 71 and 73 may be different as long as the complex conjugate matching circuit 70 has a symmetrical structure.

[0082] As described above, the complex conjugate matching circuit 70 has a symmetrical structure, and the DC component is blocked by the capacitive element 72. Therefore, complex conjugate matching between the FETs is maintained even if the direction of the signal being amplified is reversed. As a result, the bidirectional amplifiers 66 and 68 can obtain the same frequency characteristics even if the direction of the signal being amplified is reversed.

[0083] Furthermore, the bias voltages applied to FETs 35-37 by the complex conjugate matching circuit 70 can be controlled independently. In addition, the inductive elements 71 and 73, together with the capacitive element 72, also function as the AC interruption elements 41 and 43 of the power supply line shown in Embodiment 1, thus reducing the number of elements in the circuit. The complex conjugate matching circuit 70 has a symmetrical structure, and complex conjugate matching between FETs is achieved even if the signal direction is reversed. For this reason, the transmitting / receiving intermediate frequency amplifier and the transmitting / receiving radio frequency amplifier in the wireless communication device 61 can be operated as bidirectional amplifiers.

[0084] Furthermore, a capacitive element for stabilizing the DC component may be mounted in parallel to the bias voltage application terminal 32. Although not shown in the figure, this capacitive element has one terminal connected to the AC interruption element 41 and the other terminal grounded. Additionally, a capacitive element for stabilizing the DC component may be mounted in parallel to the bias voltage application terminal 33. Although not shown in the figure, this capacitive element has one terminal connected to the AC interruption element 42 and the other terminal grounded. Furthermore, a capacitive element for stabilizing the DC component may be mounted in parallel to the gate voltage application terminal 34. Although not shown in the figure, this capacitive element has one terminal connected to the AC interruption element 43 and the other terminal grounded.

[0085] (Differential Amplification) Next, a modified example of the bidirectional amplifiers 66 and 68 according to Embodiment 2 will be described. Figure 8 is a circuit diagram showing the configuration of a modified example of the bidirectional amplifiers 66 and 68, in which the FETs connected in series via the complex conjugate matching circuit 70D are differential transistors. In Figure 8, the modified bidirectional amplifiers 66 and 68 amplify the signal input to the input / output terminal 30 and amplify the signal output from the input / output terminal 31, similar to the circuit in Figure 7. Furthermore, the bidirectional amplifiers 66 and 68 amplify the signal input to the input / output terminal 31 and amplify the signal output from the input / output terminal 30. In addition, in the bidirectional amplifiers 66 and 68, a DC voltage is applied from the bias voltage application terminals 32 and 33, and a gate voltage is applied from the gate voltage application terminal 34.

[0086] As shown in Figure 8, the bidirectional amplifiers 66 and 68 include differential transistors 35D to 37D, a variable matching circuit 38D, a variable matching circuit 40D, a complex conjugate matching circuit 70D, an AC blocking element 41, and an AC blocking element 42. The differential transistors 35D to 37D are connected in series between them via the complex conjugate matching circuit 70D. Specifically, the complex conjugate matching circuit 70D is connected in series between terminals B1a and B1b of differential transistor 35D and terminals A2a and A2b of differential transistor 36D, and the complex conjugate matching circuit 70D is connected in series between terminals B2a and B2b of differential transistor 36D and terminals A3a and A3b of differential transistor 37D.

[0087] A variable matching circuit 38D is installed between the input / output terminal 30 and the differential transistor 35D, which allows for bidirectional matching by adjusting the element parameters in accordance with the reversal of the amplification direction. A variable matching circuit 40D is installed between the input / output terminal 31 and the differential transistor 37D, which allows for bidirectional matching by adjusting the element parameters in accordance with the reversal of the amplification direction.

[0088] As shown in Figure 8, the complex conjugate matching circuit 70D is configured with inductive elements 71a, 71b, 73a, 73b, capacitive elements 72a and 72b. Inductive elements 71a and 71b are first inductive reactance elements connected in series between differential input / output lines, with their connection points connected to the bias voltage application terminal 32. Inductive elements 73a and 73b are second inductive reactance elements connected in series between differential input / output lines, with their connection points connected to the bias voltage application terminal 33. Capacitive element 72a is mounted between the connection points of inductive element 71a and inductive element 73a on one of the differential input / output lines. Similarly, capacitive element 72b is mounted between the connection points of inductive element 71b and inductive element 73b on the other of the differential input / output lines.

[0089] The differential transistor 35D is composed of FET 35a and FET 35b, with the gate terminal G1a of FET 35a and the gate terminal G1b of FET 35b connected to each other. Terminals A1a of FET 35a and A1b of FET 35b are connected to the input / output terminals 30 via the variable matching circuit 38D. Terminal B1a of FET 35a is connected to the inductive element 73a in the complex conjugate matching circuit 70D, and terminal B1b of FET 36b is connected to the inductive element 71b in the complex conjugate matching circuit 70D.

[0090] The differential transistor 36D is composed of FET 36a and FET 36b, with the gate terminal G2a of FET 36a and the gate terminal G2b of FET 36b connected. Terminal A2a of FET 36a is connected to the inductive element 73a in the complex conjugate matching circuit 70D, and terminal A2b of FET 36b is connected to the inductive element 73b in the complex conjugate matching circuit 70D. Terminal B2a of FET 36a is connected to the inductive element 71a in the complex conjugate matching circuit 70D, and terminal B2b of FET 36b is connected to the inductive element 71b in the complex conjugate matching circuit 70D.

[0091] The differential transistor 37D is composed of FET 37a and FET 37b, with the gate terminal G3a of FET 37a and the gate terminal G3b of FET 37b connected. Terminal A3a of FET 37a is connected to the inductive element 73a in the complex conjugate matching circuit 70D, and terminal A3b of FET 37b is connected to the inductive element 73b in the complex conjugate matching circuit 70D. Terminal B3a of FET 37a and terminal B3b of FET 37b are connected to the input / output terminal 31 via the variable matching circuit 40D.

[0092] In differential transistors 35D, 36D, and 37D, the common-mode components appearing at both inputs are canceled, and the differential component, which is the difference between the two inputs, is amplified. Thus, because the structure of the differential transistor achieves the cancellation of common-mode AC components, the capacitive element 44 and the AC blocking element 43 can be omitted compared to the configuration in Figure 7, as shown in Figure 8. This makes it possible to reduce the circuit size of the bidirectional amplifiers 66 and 68.

[0093] As described above, in the bidirectional amplifiers 66 and 68 according to Embodiment 2, the complex conjugate matching circuit 70 includes an inductive element 71 connected to one of the two terminals of one FET between the FETs and the bias voltage application terminal 32, an inductive element 73 connected to the other of the two terminals of one FET between the FETs and the bias voltage application terminal 33, and a capacitive element 72 connected between the inductive element 71 and the inductive element 73 to block the DC component. Since the voltage applied to each FET is separated by the complex conjugate matching circuit 70, even if the applied voltage is dynamically changed, the bidirectional amplifiers 66 and 68 can suppress the application of a voltage exceeding the element withstand voltage.

[0094] Furthermore, in the bidirectional amplifiers 66 and 68 according to Embodiment 2, the FETs 35 to 37 have a gate terminal G and two terminals A and B, with one terminal functioning as the drain terminal and the other as the source terminal on one side of the bidirectional circuit, and one terminal functioning as the source terminal and the other as the drain terminal on the other side of the bidirectional circuit. The amplifier may also include an AC blocking element 41 connected to one of the two terminals and a bias voltage application terminal 32 to block the AC component in the signal frequency band, an AC blocking element 42 connected to the other terminal and a bias voltage application terminal 33 to block the AC component in the signal frequency band, and an AC blocking element 43 connected to a grounded gate terminal and a gate voltage application terminal 34 to block the AC component in the signal frequency band. The AC blocking elements 41, 42 and 43 can block the AC component applied to each terminal of the FET.

[0095] The bidirectional amplifiers 66 and 68 according to Embodiment 2 may include a DC stabilizing capacitor element with one end connected to the bias voltage application terminal 32 and the other end grounded, a DC stabilizing capacitor element with one end connected to the bias voltage application terminal 33 and the other end grounded, and a DC stabilizing capacitor element with one end connected to the gate voltage application terminal 34 and the other end grounded. This allows for appropriate stabilization of the DC component applied to each terminal of the FET.

[0096] In the bidirectional amplifiers 66 and 68 according to Embodiment 2, the FETs connected in series via the complex conjugate matching circuit 70D are differential transistors 35D to 37D, in which two FETs 35a and 35b, 36a and 36b, and 37a and 37b are connected. The capacitive element 44 and the AC blocking element 43 can be omitted. This makes it possible to reduce the circuit size of the bidirectional amplifiers 66 and 68.

[0097] The bidirectional amplifiers 66 and 68 according to Embodiment 2 include a variable matching circuit 38 or 38D connected to the input / output terminal 30 for matching with the outside of the amplifier, and a variable matching circuit 40 or 40D connected to the input / output terminal 31 for matching with the outside of the amplifier. Terminal A of the FET 35 or differential transistor 35D located at one end of the series is connected to the input / output terminal 30 via the variable matching circuit 38 or 38D, and terminal B of the FET 37 or differential transistor 37D located at the other end of the series is connected to the input / output terminal 31 via the variable matching circuit 40 or 40D. This makes it possible to prevent oscillation due to reflection of high-frequency signals, for example.

[0098] The wireless communication device 1A according to Embodiment 2 includes bidirectional amplifiers 66 and 68, which can suppress the application of voltages exceeding the element withstand voltage in the amplifiers.

[0099] Embodiment 3. Embodiment 3 describes a bidirectional amplifier equipped with a complex conjugate matching circuit composed of transformers.

[0100] Figure 9 is a circuit diagram showing an example configuration of a wireless communication device 91 according to Embodiment 3. In Figure 9, the wireless communication device 91 transmits and receives signals via a wireless transmitting and receiving antenna 22. The wireless communication device 91 receives intermediate frequency signals and outputs intermediate frequency signals to the outside of the device via input / output terminals 23. The wireless transmitting and receiving antenna 22 converts the transmit electrical signal into electromagnetic waves and transmits them, and receives the electromagnetic waves and converts them into received electrical signals. The transmission intermediate frequency signal input to the input / output terminals 23 is used to generate the transmit electrical signal. The received intermediate frequency signal output from the input / output terminals 23 is generated from the received electrical signal.

[0101] As shown in Figure 9, the wireless communication device 91 includes a local oscillator frequency oscillator 24, a local oscillator frequency amplifier 25, a bidirectional amplifier 96, a bidirectional amplifier 98, and a transmit / receive frequency converter 27. The local oscillator frequency oscillator 24 is a device that emits the local oscillator frequency. The local oscillator frequency varies depending on the communication protocol or frequency band, such as the center frequency of the transmitted signal or the local oscillation frequency of the received signal.

[0102] The local oscillator frequency amplifier 25 amplifies the local oscillator frequency signal oscillated by the local oscillator frequency oscillator 24 and outputs the amplified local oscillator frequency signal to the transmit / receive frequency converter 27. The bidirectional amplifiers 96 and 98 are bidirectional amplifiers according to Embodiment 3, and have the ability to amplify signals in both input and output directions, enabling both transmission and reception functions to be realized with a single amplifier.

[0103] The bidirectional amplifier 96 is a transceiver intermediate frequency amplifier that amplifies the intermediate frequency signal for transmission input to the input / output terminal 23, and further amplifies the received intermediate frequency signal that has been converted from a radio frequency to an intermediate frequency by the transceiver frequency converter 27. The bidirectional amplifier 98 is a transceiver radio frequency amplifier that amplifies the transmission signal that has been converted to a radio frequency signal higher than the intermediate frequency by the transceiver frequency converter 27, and further amplifies the radio received signal that has been received by the radio transceiver antenna 22.

[0104] The transmit / receive frequency converter 27 generates a transmit signal by converting the intermediate frequency to a higher frequency by mixing the local oscillator frequency signal amplified by the local oscillator frequency amplifier 25 and the intermediate frequency signal amplified by the bidirectional amplifier 96. Furthermore, the transmit / receive frequency converter 27 generates a received intermediate frequency signal converted to an intermediate frequency lower than the radio frequency of the received signal by mixing the received signal amplified by the bidirectional amplifier 98 and the local oscillator frequency signal amplified by the local oscillator frequency amplifier 25.

[0105] The bidirectional amplifiers 96 and 98 according to Embodiment 3 can independently control the bias voltage applied to the FETs by a complex conjugate matching circuit, thereby suppressing the application of voltages exceeding the element withstand voltage even when multiple amplifiers are connected in stages. The bidirectional amplifiers 96 and 98 will be described in detail below.

[0106] Figure 10 is a circuit diagram showing an example configuration of bidirectional amplifiers 96 and 98 according to Embodiment 3. The bidirectional amplifiers 96 and 98 amplify the signal input to the input / output terminal 30 and amplify the signal output from the input / output terminal 31. In addition, the bidirectional amplifiers 96 and 98 amplify the signal input to the input / output terminal 31 and amplify the signal output from the input / output terminal 30. In the bidirectional amplifiers 96 and 98, a bias voltage is applied from the bias voltage application terminal 32, a bias voltage is applied from the bias voltage application terminal 33, and a gate voltage is applied from the gate voltage application terminal 34.

[0107] As shown in Figure 10, the bidirectional amplifiers 96 and 98 include FETs 35 to 37, a variable matching circuit 38, a variable matching circuit 40, a transformer 100, an AC blocking element 41, an AC blocking element 43, a capacitive element 44, and another AC blocking element 43. The capacitive element 44 is a stabilized capacitive element with one end connected to the connection point between the gate terminal of the FET and the AC blocking element 43, and the other end grounded. The AC blocking element 43 blocks the AC component to the gate terminal. The capacitive element 44 appropriately stabilizes the DC component applied to the gate terminal of the FET.

[0108] A variable matching circuit 38 is installed between the input / output terminal 30 and terminal A1 of FET 35, which allows for bidirectional matching by adjusting the element parameters in accordance with the reversal of the amplification direction. A variable matching circuit 40 is installed between the input / output terminal 31 and terminal B3 of FET 37, which allows for bidirectional matching by adjusting the element parameters in accordance with the reversal of the amplification direction.

[0109] FETs 35 to 37 are connected in series between them via a transformer 100. Specifically, the transformer 100 is connected in series between terminal B1 of FET 35 and terminal A2 of FET 36, and the transformer 100 is connected in series between terminal B2 of FET 36 and terminal A3 of FET 37.

[0110] The transformer 100 is a transformer with a symmetrical structure and functions as a complex conjugate matching circuit. For example, the transformer 100 has a coupling coefficient k, which indicates the degree of coupling between the magnetic fluxes of the primary and secondary sides, and a turns ratio of 1:1. Because the transformer 100 utilizes electromagnetic field coupling between inductors, the DC component between the input and output is structurally blocked.

[0111] Figure 11 is an equivalent circuit diagram showing a transformer 100 with a turns ratio of 1:1. As shown in Figure 11, a transformer 100 with a turns ratio of 1:1 is represented by an equivalent circuit including a primary winding leakage inductance 110, a secondary winding leakage inductance 111, and a primary inductance 112. In this circuit, the primary winding leakage inductance 110 and the secondary winding leakage inductance 111 are symmetrical and equivalent. Because of this symmetrical structure, even if the input and output directions are reversed, the transformer 100 can function similarly in each direction. On the other hand, if the turns ratio of the transformer is n:1, the symmetry is broken and therefore it is not adopted as a transformer 100.

[0112] Generally, among the matching elements used in amplifiers, inductors, which are inductive elements, need to avoid electromagnetic coupling between inductors. For this reason, the elements need to be placed at a certain distance apart. For example, in the bidirectional amplifiers 66 and 68 shown in Figure 6, the inductive elements 71 and 73 need to be placed apart to avoid electromagnetic coupling between them, which tends to make the amplifiers larger.

[0113] On the other hand, the transformer 100 is an element that utilizes electromagnetic field coupling, and it is possible to stack inductive matching elements on the output and input sides of the amplifier. Therefore, by using the transformer 100, not only can the number of capacitive elements 72 in the complex conjugate matching circuit 70 be reduced, but the matching elements can also be miniaturized. This, in turn, greatly contributes to the miniaturization of the amplifier.

[0114] The bias voltages applied to FETs 35-37 by the transformer 100 can be controlled independently. Furthermore, the transformer 100 has a symmetrical structure, and complex conjugate matching between FETs is maintained even when the signal direction is reversed. Therefore, the transmitting / receiving intermediate frequency amplifier and the transmitting / receiving radio frequency amplifier in the wireless communication device 91 can be operated as bidirectional amplifiers.

[0115] Furthermore, a capacitive element for stabilizing the DC component may be mounted in parallel to the bias voltage application terminal 32. Although not shown in the figure, this capacitive element has one terminal connected to the AC interruption element 41 and the other terminal grounded. Additionally, a capacitive element for stabilizing the DC component may be mounted in parallel to the bias voltage application terminal 33. Although not shown in the figure, this capacitive element has one terminal connected to the AC interruption element 42 and the other terminal grounded. Furthermore, a capacitive element for stabilizing the DC component may be mounted in parallel to the gate voltage application terminal 34. Although not shown in the figure, this capacitive element has one terminal connected to the AC interruption element 43 and the other terminal grounded.

[0116] (Differential Amplification) Next, a modified example of the bidirectional amplifiers 96 and 98 according to Embodiment 3 will be described. Figure 12 is a circuit diagram showing the configuration of a modified example of the bidirectional amplifiers 96 and 98, in which the FETs connected in series via the transformer 100D are differential transistors. In Figure 12, the modified bidirectional amplifiers 96 and 98 amplify the signal input to the input / output terminal 30 and amplify the signal output from the input / output terminal 31, similar to the circuit in Figure 10. The bidirectional amplifiers 96 and 98 also amplify the signal input to the input / output terminal 31 and output the amplified signal from the input / output terminal 30. In addition, in the bidirectional amplifiers 96 and 98, a bias voltage is applied from the bias voltage application terminal 32 and a gate voltage is applied from the gate voltage application terminal 34.

[0117] As shown in Figure 12, the bidirectional amplifiers 96 and 98 include differential transistors 35D to 37D, a variable matching circuit 38D, a variable matching circuit 40D, a transformer 100D, an AC interruption element 41, and an AC interruption element 42. The differential transistors 35D to 37D are connected in series between them via the transformer 100D. Specifically, the transformer 100D is connected in series between terminals B1a and B1b of differential transistor 35D and terminals A2a and A2b of differential transistor 36D, and the transformer 100D is connected in series between terminals B2a and B2b of differential transistor 36D and terminals A3a and A3b of differential transistor 37D.

[0118] A variable matching circuit 40D is installed between the input / output terminal 30 and the differential transistor 35D, which allows for bidirectional matching by adjusting the element parameters in accordance with the reversal of the amplification direction. A variable matching circuit 40D is installed between the input / output terminal 31 and the differential transistor 37D, which allows for bidirectional matching by adjusting the element parameters in accordance with the reversal of the amplification direction.

[0119] As shown in Figure 12, the transformer 100D is configured with two windings. The winding connected to terminal A of the differential transistor has its center tap connected to the bias voltage application terminal 32. The winding connected to terminal B of the differential transistor has its center tap connected to the bias voltage application terminal 33.

[0120] The differential transistor 35D is composed of FET 35a and FET 35b, with the gate terminal G1a of FET 35a and the gate terminal G1b of FET 35b connected to each other. Terminals A1a of FET 35a and A1b of FET 35b are connected to the input / output terminal 30 via a variable matching circuit 38D. Terminals B1a of FET 35a and B1b of FET 35b are connected to one of the windings of the transformer 100D, which is located to the right of the differential transistor 35D in Figure 12.

[0121] The differential transistor 36D is composed of FET 36a and FET 36b, with the gate terminal G2a of FET 36a and the gate terminal G2b of FET 36b connected. Terminals A2a of FET 36a and A2b of FET 36b are connected to the other winding of the transformer 100D, which is located to the left of the differential transistor 36D in Figure 12. Terminal B2a of FET 36a and terminal B2b of FET 36b are connected to one of the windings of the transformer 100D, which is located to the right of the differential transistor 36D in Figure 12.

[0122] The differential transistor 37D is composed of FET 37a and FET 37b, with the gate terminal G3a of FET 37a and the gate terminal G3b of FET 37b connected to each other. Terminals A3a of FET 37a and A3b of FET 37b are connected to the other winding of the transformer 100D located to the left of the differential transistor 37D in Figure 12. In addition, terminal B3a of FET 37a and terminal B3b of FET 37b are connected to the input / output terminal 31 via the variable matching circuit 40D.

[0123] In differential transistors 35D, 36D, and 37D, the common-mode components appearing at both inputs are canceled, and the differential component, which is the difference between the two inputs, is amplified. On the other hand, a single FET requires a stabilizing capacitor (capacitor 44) at the gate terminal. Thus, because the common-mode component cancellation is achieved in differential transistors by their structure, the capacitor 44 and AC blocking element 43 can be omitted compared to the configuration in Figure 10, as shown in Figure 12. This makes it possible to reduce the circuit size of the bidirectional amplifiers 96 and 98.

[0124] As described above, in the bidirectional amplifiers 96 and 98 according to Embodiment 3, the complex conjugate matching circuit is a transformer 100 having a symmetrical structure. Since the voltage applied to each FET is separated by the transformer 100, even if the applied voltage is dynamically changed, the bidirectional amplifiers 96 and 98 can suppress the application of voltages exceeding the element withstand voltage.

[0125] Furthermore, in the bidirectional amplifiers 96 and 98 according to Embodiment 3, the FETs 35 to 37 have a gate terminal G and two terminals A and B, with one terminal functioning as the drain terminal and the other as the source terminal on one side of the bidirectional operation, and one terminal functioning as the source terminal and the other as the drain terminal on the other side of the bidirectional operation. The amplifier may also include an AC blocking element 41 connected to one of the two terminals and a bias voltage application terminal 32 to block the AC component in the signal frequency band, an AC blocking element 42 connected to the other terminal and a bias voltage application terminal 33 to block the AC component in the signal frequency band, and an AC blocking element 43 connected to a grounded gate terminal and a gate voltage application terminal 34 to block the AC component in the signal frequency band. The AC blocking elements 41, 42 and 43 can block the AC component applied to each terminal of the FET.

[0126] The bidirectional amplifiers 96 and 98 according to Embodiment 3 include a DC stabilizing capacitor element with one end connected to a bias voltage application terminal 32 and the other end grounded, a DC stabilizing capacitor element with one end connected to a bias voltage application terminal 33 and the other end grounded, and a DC stabilizing capacitor element with one end connected to a gate voltage application terminal 34 and the other end grounded. This allows for appropriate stabilization of the DC component applied to each terminal of the FET.

[0127] In the bidirectional amplifiers 96 and 98 according to Embodiment 3, the FETs connected in series via the transformer 100D are differential transistors 35D to 37D, in which two FETs 35a and 35b, 36a and 36b, and 37a and 37b are connected. The AC blocking elements 41, 42, 44, and 43 can be omitted. This makes it possible to reduce the circuit size of the bidirectional amplifiers 96 and 98.

[0128] The bidirectional amplifiers 96 and 98 according to Embodiment 3 include a variable matching circuit 38 or 38D connected to the input / output terminal 30 for matching with the outside of the amplifier, and a variable matching circuit 40 or 40D connected to the input / output terminal 31 for matching with the outside of the amplifier. Terminal A1, A1a, or A1b of the FET 35 or differential transistor 35D located at one end of the series is connected to the input / output terminal 30 via the variable matching circuit 38 or 38D, and terminal B1, B1a, or B1b of the FET 37 or differential transistor 37D located at the other end of the series is connected to the input / output terminal 31 via the variable matching circuit 40 or 40D. This makes it possible to prevent oscillation due to reflection of high-frequency signals, for example.

[0129] The wireless communication device 91 according to Embodiment 3 includes bidirectional amplifiers 96 and 98, so that the application of a voltage exceeding the element withstand voltage in the amplifier can be suppressed.

[0130] Furthermore, it is possible to combine each embodiment, modify any component of each embodiment, or omit any component in each embodiment.

[0131] The bidirectional amplifier described herein can be used, for example, in wireless communication devices.

[0132] 1, 21, 61, 91 Wireless communication device, 2, 22 Wireless transceiver antenna, 3 Input terminal, 4 Output terminal, 5 Transceiver switch, 6 Local oscillator frequency oscillator, 7 Transmit local oscillator frequency amplifier, 8 Receive local oscillator frequency amplifier, 9 Transmit intermediate frequency amplifier, 10 Transmit upconversion mixer, 11 Transmit radio frequency band amplifier, 12 Receive intermediate frequency amplifier, 13 Receive downconversion mixer, 14 Receive radio frequency band amplifier, 23, 30, 31 Input / output terminals, 25 Local oscillator frequency amplifier, 26, 28, 66, 68, 96, 98 Bidirectional amplifier, 27 Transceiver frequency converter, 32, 33 Bias voltage application terminal, 34 Gate voltage application terminal, 35, 36, 37 FET, 35D, 36D, 37D Differential transistor, 38, 40, 38D, 40D Variable matching circuits, 39, 39D, 70, 70D Complex conjugate matching circuits, 41, 42, 43 AC blocking elements, 44 Capacitive elements, 50 Input impedance frequency characteristics, 51 Output impedance frequency characteristics, 52 Output impedance complex conjugate frequency characteristics, 71, 73, 71a, 73a, 71b, 73b Inductive elements, 100, 100D Transformers, 110 Primary winding leakage inductance, 111 Secondary winding leakage inductance, 112 Primary inductance.

Claims

1. A bidirectional amplifier comprising a plurality of transistors having a symmetrical structure and a matching circuit having symmetry and blocking DC components, wherein the plurality of transistors are connected in series between the transistors via the matching circuit.

2. The bidirectional amplifier according to claim 1, characterized in that the transistor has a gate terminal and two terminals, where on one side of the bidirectional direction, one terminal of the two terminals functions as a drain terminal and the other terminal of the two terminals functions as a source terminal, where on the other side of the bidirectional direction, one terminal of the two terminals functions as a source terminal and the other terminal of the two terminals functions as a drain terminal, a first AC blocking element connected to one terminal of the two terminals and a first bias voltage application terminal to block the AC component of the signal frequency band, a second AC blocking element connected to the other terminal of the two terminals and a second bias voltage application terminal to block the AC component of the signal frequency band, and a third AC blocking element connected to a grounded gate terminal and a gate voltage application terminal to block the AC component of the signal frequency band.

3. The bidirectional amplifier according to claim 1, wherein the transistor has a gate terminal and two terminals, where in one direction, one of the two terminals functions as a drain terminal and the other terminal functions as a source terminal, and in the other direction, one of the two terminals functions as a source terminal and the other terminal functions as a drain terminal, and the matching circuit comprises a first inductive reactance element connected to one of the two terminals of one of the transistors between the transistors and a first bias voltage application terminal, a second inductive reactance element connected to the other terminal of the two terminals of one of the transistors between the transistors and a second bias voltage application terminal, and a capacitive element connected between the first inductive reactance element and the second inductive reactance element to block the DC component.

4. The bidirectional amplifier according to claim 1, characterized in that the matching circuit is a transformer having the symmetry described above.

5. The bidirectional amplifier according to claim 1, characterized in that the transistor comprises a gate terminal, two terminals, one of which functions as a drain terminal and the other as a source terminal on one side of the bidirectional direction, one of which functions as a source terminal and the other as a drain terminal on the other side of the bidirectional direction, a first bias voltage application terminal connected to one of the two terminals, a second bias voltage application terminal connected to the other of the two terminals, a gate voltage application terminal connected to the gate terminal, a DC stabilized capacitor element with one end connected to the first bias voltage application terminal and the other end grounded, a DC stabilized capacitor element with one end connected to the second bias voltage application terminal and the other end grounded, and a DC stabilized capacitor element with one end connected to the gate voltage application terminal and the other end grounded.

6. The bidirectional amplifier according to any one of claims 1 to 4, characterized in that the transistor connected in series via the matching circuit is a differential transistor formed by connecting two of the transistors.

7. The bidirectional amplifier according to any one of claims 1 to 6, wherein the transistor has a gate terminal and two terminals, one of which functions as a drain terminal and the other as a source terminal on one side of the bidirectional connection, one of which functions as a source terminal and the other as a drain terminal on the other side of the bidirectional connection, and comprises a first variable matching circuit connected to a first input / output terminal for matching with the outside of the amplifier, and a second variable matching circuit connected to a second input / output terminal for matching with the outside of the amplifier, wherein one of the two terminals of the transistor located at one end of the series connection is connected to the first input / output terminal via the first variable matching circuit, and the other terminal of the two terminals of the transistor located at the other end of the series connection is connected to the second input / output terminal via the second variable matching circuit.

8. A wireless communication device comprising a bidirectional amplifier according to any one of claims 1 to 7.

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