Ranging device and ranging system

Abstract

The present disclosure pertains to a ranging device and a ranging system with which it is possible to reduce the number of wires and improve the dynamic range of light intensity vs count. This ranging device comprises a pulse width modulation part that generates and outputs a pulse signal. Said signal is obtained by combining photon detection signals using a plurality of pixels, and is represented in terms of the pulse width by the reaction time of the initially reacted pixel from among the plurality of pixels in a transmission unit and by the pixel number and / or pixel position of the reacted pixels. The technology of the present disclosure can be applied to, for example, a ranging system that detects the distance to a subject in the depth direction by a direct ToF method.

Description

Distance Measuring Device and Distance Measuring System

[0001] The present disclosure relates to a distance measuring device and a distance measuring system, and particularly to a distance measuring device and a distance measuring system that can reduce the number of wirings and improve the dynamic range of the light amount versus count.

[0002] A direct ToF (Time-of-Flight) type distance measuring device measures the distance to the object to be measured by measuring the time until the reflected light of the irradiated light is received by the object to be measured. For the pixels of the direct ToF type distance measuring device, for example, a SPAD (Single Photon Avalanche Diode) is used as a light detection element. The distance measuring device is provided with a TDC that measures the time until the light detection element detects light and reacts, and a histogram generation unit that generates a histogram based on the measured time.

[0003] In a direct ToF type distance measuring device, if pixels and TDCs are provided one-to-one, it becomes impossible to handle multi-pixels. Therefore, there is a device that reduces the number of wirings and TDCs by binning the detection signals of multiple pixels with an OR circuit (see, for example, Patent Document 1).

[0004] When binning the detection signals of multiple pixels with an OR circuit, if multiple pixels in the binning unit detect light simultaneously, the count disappears, distortion occurs in the histogram, or the dynamic range of the light amount versus count decreases. In contrast, Patent Document 2 proposes a configuration for avoiding count disappearance.

[0005] [[ID=十五]]International Publication No. 2022-541879, US Patent Application Publication No. 2020 / 0400792

[0006] However, the configuration of Patent Document 2 requires a clock signal supply and output wiring for detecting the number of simultaneous reactions, resulting in additional wiring.

[0007] The present disclosure has been made in view of such a situation, and aims to reduce the number of wirings and improve the dynamic range of the light amount versus count.

[0008] The distance measuring device according to the first aspect of this disclosure includes a pulse width modulation unit that generates and outputs a pulse signal in which the detection signals of photons are aggregated by a plurality of pixels, and the pulse width represents at least one of the reaction time of the first pixel to react among the plurality of pixels of the transmission unit and the number of pixels or the pixel position of the reacting pixel.

[0009] A distance measuring system according to a second aspect of the present disclosure comprises an illumination device that emits illumination light and a distance measuring device that receives reflected light from an object, wherein the distance measuring device comprises a pixel array in which a plurality of pixels including photodetectors are arranged in a matrix, and a pulse width modulation unit that generates and outputs a pulse signal in which the detection signals of the plurality of pixels are combined, and the pulse width represents the reaction time of the first pixel to react among the plurality of pixels of the transmission unit and at least one of the number of pixels or the pixel position of the reacted pixel.

[0010] In the first and second aspects of this disclosure, a pulse signal is generated and output, which is a signal obtained by combining the photon detection signals of multiple pixels, wherein the pulse width represents at least one of the reaction time of the first pixel to react among the multiple pixels of the transmission unit and the number of pixels or the pixel position of the reacting pixel.

[0011] The distance measuring device and distance measuring system may be a standalone device or a module incorporated into another device.

[0012] This is a block diagram illustrating a schematic configuration example of the distance measuring system according to this disclosure. This is a diagram illustrating the operation of a pixel. This is a diagram illustrating an overview of the operation of the distance measuring device. This is a diagram illustrating an overview of the operation of the distance measuring device. This is a diagram showing a first circuit implementation example of the distance measuring device. This is a diagram showing a second circuit implementation example of the distance measuring device. This is a plan view showing an example of the arrangement of the pulse width modulation unit. This is a plan view showing an example of signal wiring for transmitting a width-modulated pulse signal. This is a diagram illustrating histogram generation in units exceeding macro pixels. This is a block diagram illustrating a detailed configuration example of the pulse width modulation unit, demodulation unit, and MP histogram generation unit. This is a diagram showing a more detailed circuit configuration example of the pulse width modulation unit. This is a timing chart illustrating the operation of the pulse width modulation unit. This is a diagram showing a detailed circuit configuration example of the pulse width detection circuit and the response number conversion circuit. This is a timing chart illustrating the operation of the pulse width detection circuit and the response number conversion circuit. This is a block diagram illustrating a configuration example of the edge detection type MP histogram generation unit. This is a block diagram illustrating a configuration example of the level detection type MP histogram generation unit. This is a diagram illustrating the effect of the distance measuring device. This is a block diagram illustrating a second configuration example of the pulse width modulation unit. This is a diagram showing the truth table of the combination circuit in Figure 18. This is a block diagram illustrating a third configuration example of the pulse width modulation unit. This figure shows the truth table of the combinational circuit shown in Figure 20. This figure illustrates the schematic configuration when the reaction pixel position is output using a width-modulated pulse signal. This block diagram shows a detailed configuration example of the pulse width modulation unit, demodulation unit, and MP histogram generation unit according to the second embodiment. This figure shows an example of a width-modulated pulse signal that transmits the reaction pixel position. This figure shows a detailed circuit configuration example of the pulse width detection circuit and the reaction position conversion circuit. This is a timing chart that explains the operation of the pulse width detection circuit and the reaction position conversion circuit. This figure explains the processing of the MP histogram generation unit. This block diagram shows an example of the schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of the external information detection unit and the imaging unit.

[0013] Hereinafter, embodiments for carrying out the technology of this disclosure (hereinafter referred to as "embodiments") will be described with reference to the attached drawings. In this specification and drawings, components having substantially the same functional configuration will be denoted by the same reference numerals, and redundant explanations will be omitted. The explanation will be given in the following order: 1. Example of distance measuring system configuration 2. Example of schematic pixel configuration 3. Overview of the operation of the distance measuring device 4. Example of circuit implementation of the distance measuring device 5. Example of pulse width modulation unit arrangement 6. Histogram generation of multiple pixel units exceeding macro pixels 7. Detailed configuration of the distance measuring device 8. Effects of the distance measuring device 9. Second example of pulse width modulation unit configuration 10. Third example of pulse width modulation unit configuration 11. Transmission of reaction pixel position 12. Detailed configuration of the distance measuring device according to the second embodiment 13. Example of application to a moving object

[0014] In the following explanation, "Hi" represents a voltage equivalent to "1" in logic, and "Lo" represents a voltage equivalent to "0" in logic, and "Low" represents a voltage equivalent to "0". Furthermore, the definitions of directions such as up / down and left / right in the following explanation are merely for the sake of explanation and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up / down will be converted to left / right and read accordingly, and if it is rotated 180° and observed, up / down will be inverted and read accordingly.

[0015] <1. Example of Distance Measurement System Configuration> Figure 1 is a block diagram showing an example of the schematic configuration of the distance measurement system according to this disclosure.

[0016] The distance measuring system 1 shown in Figure 1 is a sensor system that measures the distance to an object OBJ using the direct ToF method (hereinafter referred to as the dToF method). This distance measuring system 1 can be mounted on, for example, an in-vehicle LiDAR. The distance measuring system 1 comprises an overall control unit 10, an illumination device 20, and a distance measuring device 30.

[0017] The overall control unit 10 controls the lighting device 20 and the distance measuring device 30, for example, according to a pre-programmed set of instructions. The overall control unit 10 may be incorporated as part of the lighting device 20 or the distance measuring device 30.

[0018] The illumination device 20 has a light source such as a laser light source or an LED (Light Emitting Diode) and irradiates light toward the object OBJ. The illumination device 20 emits an optical pulse signal L1 in the frequency band of near-infrared light as the irradiated light. The light source may also be a surface light source such as a VCSEL (Vertical Cavity Surface Emitting Laser).

[0019] The distance measuring device 30 receives a reflected pulse signal L2, which is reflected light from an object OBJ after an optical pulse signal L1 from the illumination device 20 is irradiated onto the object OBJ, and calculates the distance to the object OBJ. The distance measuring device 30 includes a clock generation unit 41, a control unit 42, an illumination timing control unit 43, a drive circuit 44, a pixel array 45, a distance measuring control unit 46, a distance measuring processing unit 47, and an output unit 48.

[0020] The clock generation unit 41 generates a clock signal Vclk to synchronize the lighting device 20 and the distance measuring device 30 based on a reference clock signal supplied from an external source, and supplies it to the control unit 42.

[0021] The control unit 42 synchronizes the light emission timing control unit 43 and the distance measurement control unit 46 based on the clock signal Vclk supplied from the clock generation unit 41 and instructions from the overall control unit 10.

[0022] The light emission timing control unit 43 generates a light emission control signal indicating the light emission timing according to the light emission trigger signal supplied from the control unit 42. The light emission control signal is supplied to the lighting device 20 and also to the distance measurement processing unit 47. The lighting device 20 emits an optical pulse signal L1 according to the light emission control signal from the light emission timing control unit 43.

[0023] The drive circuit 44 includes a shift register and an address decoder, and drives each pixel 50 of the pixel array 45, either all pixels simultaneously or in columns. The drive circuit 44 drives each pixel 50 in synchronization with the timing at which the light emission timing control unit 43 transmits a light emission instruction.

[0024] The pixel array 45 has a plurality of pixels 50 arranged in a matrix. The pixels 50 receive a reflected pulse signal L2, which is the light pulse signal L1 from the illumination device 20 reflected by the object OBJ. As will be described in detail with reference to Figure 2, the pixels 50 have, for example, a SPAD (Single Photon Avalanche Diode) as a photodetector element. The pixels 50 that receive the reflected pulse signal L2 generate a detection signal, and the detection signal output from the pixels 50 is supplied to the distance measurement processing unit 47.

[0025] The distance measurement control unit 46 controls the distance measurement processing unit 47 in synchronization with the light emission timing control unit 43, under the control of the control unit 42. Based on instructions from the control unit 42, the distance measurement control unit 46 controls the operation of the distance measurement processing unit 47, causing the distance measurement processing unit 47 to generate distance information based on the detection signals output from each pixel 50 of the pixel array 45.

[0026] The distance measurement processing unit 47 performs distance measurement calculations using the dToF method based on detection signals output from each pixel 50 of the pixel array 45. The distance measurement processing unit 47 includes a TDC unit 61, a histogram generation unit 62, and a signal processing unit 63.

[0027] The TDC unit 61 measures the time difference from a reference timing (for example, the timing when the light emission control signal is input from the light emission timing control unit 43) to the time when the detection signal is input from the pixel array 45, and generates digital information indicating the measured time difference. In other words, based on the light emission control signal and the detection signal, the TDC unit 61 generates time information indicating the time of flight from when the illumination light is emitted from the lighting device 20, when that light is reflected by the object OBJ, and when it enters each pixel 50.

[0028] The histogram generation unit 62 generates a histogram based on the time information generated by the TDC unit 61. Here, the histogram generation unit 62 counts the time information based on the unit time d set by the distance measurement control unit 46 and generates a histogram. The unit time d may be, for example, the time width assigned to one bin in the histogram. Alternatively, the unit time d may be, for example, the same time width as the sampling period for reading the detection signal from each pixel 50 of the pixel array 45.

[0029] The signal processing unit 63 performs predetermined calculations based on the histogram data generated by the histogram generation unit 62 to calculate distance information. For example, the signal processing unit 63 creates an approximate histogram curve based on the histogram data. The signal processing unit 63 can detect the peak of the approximate histogram curve and determine the distance D to the object OBJ based on the detected peak.

[0030] The distance information calculated by the distance measurement processing unit 47 is supplied to the output unit 48. The output unit 48 converts the distance information from the distance measurement processing unit 47 into an output format according to a predetermined interface, such as MIPI (Mobile Industry Processor Interface), and outputs it externally as output data.

[0031] <2. Schematic Example of Pixel Configuration> Figure 2 is a diagram illustrating the operation of pixel 50.

[0032] The pixel 50 comprises a photodetector 81, a quench resistor 82, a selection transistor 83, and an inverter 84. The quench resistor 82 is composed of, for example, a PMOS transistor, and the selection transistor 83 is composed of, for example, an NMOS transistor.

[0033] The photodetector element 81 converts incident light (photons) into an electrical signal by photoelectric conversion and outputs a pulse corresponding to the incident photon. For example, a single-photon avalanche diode (SPAD) is used as the photodetector element 81. When a large negative voltage that generates avalanche multiplication is applied to the cathode of an SPAD, avalanche multiplication occurs in response to the incident of one photon, and a large current flows. By utilizing this characteristic of the SPAD, the incident of one photon can be detected with high sensitivity. In the pixel 50, the occurrence of avalanche multiplication in response to the incident photon and the flow of a large current is appropriately referred to as the photodetector element 81 reacting, or the pixel 50 reacting.

[0034] In Figure 2, the photodetector 81 has its cathode connected to the drain of a quench resistor 82, and its anode connected to a voltage source that provides a negative voltage (-Vop) corresponding to the breakdown voltage Vbd of the photodetector 81. The source of the quench resistor 82 is connected to the power supply voltage Ve. The quench voltage V_QCH is input to the gate of the quench resistor 82. The quench resistor 82 is a current source that outputs a current from its drain corresponding to the power supply voltage Ve and the quench voltage V_QCH. With this configuration, a reverse bias is applied to the photodetector 81. The photocurrent flows from the cathode to the anode of the photodetector 81.

[0035] More specifically, when a photon is incident on the photodetector 81 with a power supply voltage Ve applied to the cathode and the voltage between the cathode and anode being Ve + Vop, avalanche multiplication is initiated, causing a current to flow from the cathode to the anode, resulting in a voltage drop in the photodetector 81. This voltage drop causes the voltage between the cathode and anode of the photodetector 81 to drop to voltage Vop, at which point avalanche multiplication stops (quenching operation). Subsequently, the photodetector 81 is charged by the current from the quench resistor 82 (recharge current), and the state of the photodetector 81 returns to the state before the photon was incident (recharge operation).

[0036] The voltage Vca, taken from the connection point between the drain of the quench resistor 82 and the cathode of the photodetector element 81, is input to the inverter 84. The inverter 84 performs a threshold determination on the input voltage Vca based on the threshold voltage Vth, and inverts the output signal PFout each time the voltage Vca exceeds the threshold voltage Vth in either the positive or negative direction.

[0037] More specifically, the inverter 84 inverts the signal PFout to Hi (High) at a first timing when the voltage Vca crosses the threshold voltage Vth in response to the voltage drop due to avalanche multiplication in response to the incidence of photons on the photodetector element 81. Next, the photodetector element 81 is charged by the recharge operation and the voltage Vca rises. At a second timing when this rising voltage Vca crosses the threshold voltage Vth, the inverter 84 inverts the signal PFout again to Lo (Low). In this way, the photodetector element 81 of the pixel 50 outputs a Hi pulse with a time width between the first timing and the second timing in response to the incidence of photons. This signal PFout corresponds to the detection signal explained in Figure 1 and will be referred to as the detection signal PFout below.

[0038] The drain of the selection transistor 83 is connected to the connection point between the drain of the quench resistor 82 and the cathode of the photodetector 81, and the source of the selection transistor 83 is connected to a voltage Vg. The voltage Vg may be the GND voltage (0V) or a negative voltage. The gate of the selection transistor 83 is connected to a drive circuit 44, and the selection control voltage V_SEL supplied to the gate from the drive circuit 44 controls the selection transistor 83 to be on or off.

[0039] Pixel 50 operates as follows, for example. When the selection transistor 83 is controlled to the off state, the power supply voltage Ve is supplied to the cathode of the photodetector element 81. Therefore, when a photon is incident on the photodetector element 81, a voltage drop occurs as described above, and a detection signal PFout corresponding to the detection of the photon is output from pixel 50. When pixel 50 is in a state in which it outputs a pulse in response to the detection of a photon, pixel 50 is said to be an active pixel. On the other hand, when the selection transistor 83 is controlled to the on state, a voltage Vg is applied to the cathode of the photodetector element 81, and no voltage exceeding the breakdown voltage Vbd is applied to the photodetector element 81. Therefore, even when a photon is incident on the photodetector element 81, no pulse is output from pixel 50. When pixel 50 is in a state in which it does not output a pulse even when a photon is incident on it, pixel 50 is said to be an inactive pixel.

[0040]

[0040] Next, referring to FIGS. 3 and 4, an outline of the operation of the distance measuring device 30 will be described.

[0041]

[0041] The distance measuring device 30 generates one histogram based on the detection signals PFout of a plurality of pixels 50. A unit of a plurality of pixels that generate this one histogram is referred to as a macro pixel MP. In the present embodiment, the macro pixel MP is described as being composed of 4 pixels of 2×2. However, of course, the macro pixel MP may be composed of other numbers of pixels.

[0042]

[0042] First, referring to FIG. 3, a basic method (hereinafter referred to as the basic method) before applying the method adopted by the distance measuring device 30 will be described.

[0043]

[0043] When each pixel 50 of 2×2 constituting the macro pixel MP receives the reflected light that has been reflected by the object OBJ and incident, as described with reference to FIG. 2, it outputs a detection signal PFout. Each pixel 50 is connected to a TDC 91 on a one-to-one basis, and the detection signal PFout output from each pixel 50 is output to the corresponding TDC 91. The TDC 91 counts the time from when the illumination device 20 emits the irradiation light until the reflected light is received, and outputs the count value to the integration unit 92 as a ToF value. The ToF value corresponds to the reaction time of the pixel 50 where the photodetection element 81 has reacted. The integration unit 92 outputs the ToF values supplied from each of the 2×2 pixels 50 constituting the macro pixel MP to the MP histogram generation unit 93. The MP histogram generation unit 93 generates a histogram in units of the macro pixel MP by counting up the frequency values of the bins corresponding to the supplied ToF values.

[0044]

[0044] As described above, in the basic method, since the pixel 50 and the TDC 91 are provided on a one-to-one basis, when increasing the number of pixels of the pixel array 45 or miniaturizing the pixel 50, it becomes difficult to connect the wiring connecting the pixel 50 and the TDC 91 and to arrange the TDC 91.

[0045]

[0045] Next, referring to FIG. 4, the method adopted by the distance measuring device 30 (hereinafter referred to as the present method) will be described.

[0046] The ranging device 30 includes a pulse width modulation unit 101 for each macro pixel MP, and corresponding to the pulse width modulation unit 101, a demodulation unit 102 and an MP histogram generation unit 103 are provided.

[0047] As shown in the middle row of FIG. 4, the pulse width modulation unit 101 is a signal obtained by collecting the detection signal PFout of reflected light (photons) in units of macro pixels MP. Among the plurality of pixels of the macro pixel MP, the reaction time of the pixel 50 at which the photodetector 81 first reacts and the number of pixels of the pixel 50 at which the photodetector 81 reacts (hereinafter also referred to as the reaction number) are used as reaction information, and a width modulation pulse signal WMPFout is generated by pulse width modulation (PWM) so as to represent it by the pulse width and output.

[0048] As shown in the upper row of FIG. 4, the width modulation pulse signal WMPFout is supplied to a demodulation unit 102 provided corresponding to the pulse width modulation unit 101. The demodulation unit 102 includes a TDC 111 and a demodulation circuit 112, and demodulates the width modulation pulse signal WMPFout into the reaction time and reaction number of the macro pixel MP. The TDC 111 acquires the reaction time of the pixel 50 at which the photodetector 81 first reacts from the rising edge of the width modulation pulse signal WMPFout. The demodulation circuit 112 detects the reaction number of the pixel 50 from the pulse width of the width modulation pulse signal WMPFout. The TDC 111 is the same circuit as the basic type TDC 91, and outputs the ToF value, which is the reaction time of the first-reacted pixel 50, to the MP histogram generation unit 103. The demodulation circuit 112 outputs the reaction number of the pixel 50 detected from the width modulation pulse signal WMPFout to the MP histogram generation unit 103.

[0049] The MP histogram generation unit 103 generates a histogram in units of macro pixels MP according to the reaction time (ToF value) and the reaction number. There are two methods for the MP histogram generation unit 103 to generate a histogram, namely the edge detection method and the level detection method shown in the lower row of FIG. 4, and a histogram can be generated by a desired detection method with setting information or the like. The edge detection method is a method of adding (counting up) the frequency value by the reaction number to the bin of the ToF value of the reaction time. The level detection method is a method of adding (counting up) the frequency value by 1 to each bin of the number of bins corresponding to the reaction number from the bin of the ToF value of the reaction time.

[0050] According to the method adopted by the distance measuring device 30, macro pixels MP are transmission units that transmit width-modulated pulse signals WMPFout to TDC 111, and the wiring that transmits the width-modulated pulse signals WMPFout is on a macro pixel MP basis, not on a pixel basis, so the number of wires can be reduced compared to the basic method. Since TDC 111 is provided in accordance with the wiring that transmits the width-modulated pulse signals WMPFout, the number of TDC 111 can also be reduced.

[0051] <4. Circuit Implementation Example of Distance Measuring Device> Figure 5 shows a first circuit implementation example of the distance measuring device 30.

[0052] As shown in Figure 5, the distance measuring device 30 can be configured in which the pixel array 45, the distance measuring processing unit 47, and other components are arranged on a single semiconductor substrate 140.

[0053] Alternatively, the distance measuring device 30 may be configured as a laminated structure in which a first semiconductor substrate 141 and a second semiconductor substrate 142 are stacked, as shown in Figure 6. Figure 6 is a diagram showing a second circuit implementation example of the distance measuring device 30. Multiple photodetectors 81 for each pixel 50 are arranged in a matrix on the first semiconductor substrate 141. The second semiconductor substrate 142 is provided with, for example, a quench resistor 82 for each pixel 50, a selection transistor 83, an inverter 84, and a pulse width modulation unit 101, TDC 111, and demodulation circuit 112 provided for each macro pixel MP. Peripheral circuits such as a clock generation unit 41 and a control unit 42 are also provided on the second semiconductor substrate 142. The first semiconductor substrate 141 and the second semiconductor substrate 142 are electrically connected, for example, by a Cu-Cu connection 143.

[0054] In the second semiconductor substrate 142, the quench resistor 82, the selection transistor 83, and the inverter 84 are provided in the lower layer (below the pixel) of the corresponding photodetector element 81 pixel 50 on the first semiconductor substrate 141. The pulse width modulation unit 101 is also provided in the lower layer (below the pixel) of the corresponding macro pixel MP, so that the macro pixel MP and the corresponding pulse width modulation unit 101 are superimposed in a plan view.

[0055] Furthermore, the arrangement of circuits on the first semiconductor substrate 141 and the second semiconductor substrate 142 is not limited to the example described above, and can be arranged arbitrarily. For example, the quench resistor 82, selection transistor 83, and inverter 84 for each pixel 50 may be placed on the first semiconductor substrate 141 instead of the second semiconductor substrate 142.

[0056] Furthermore, when the distance measuring device 30 is made of a stacked structure of multiple semiconductor substrates, it may be made of three or more layers instead of the two layers described above.

[0057] <5. Example of arrangement of pulse width modulation unit> Figure 7 is a plan view showing an example of the arrangement of the pulse width modulation unit 101.

[0058] The pulse width modulation unit 101 is positioned in the center of the corresponding macro pixel MP in a plan view, and is arranged in a staggered pattern with a position shift of one pixel in the vertical and horizontal directions from the nearest other pulse width modulation unit 101. Focusing on a predetermined pixel 50 in the pixel array 45, the pixel 50 belongs to two macro pixels MP: a first macro pixel MP-A and a second macro pixel MP-B. Each pixel 50 outputs a detection signal PFout to the two pulse width modulation units 101, the first pulse width modulation unit 101-A and the second pulse width modulation unit 101-B. The first pulse width modulation unit 101-A is the pulse width modulation unit 101 corresponding to the first macro pixel MP-A, and the second pulse width modulation unit 101-B is the pulse width modulation unit 101 corresponding to the second macro pixel MP-B.

[0059] Figure 8 is a plan view showing an example of signal wiring for transmitting a width-modulated pulse signal WMPFout.

[0060] The signal wiring 181 connects the pulse width modulation unit 101 and the TDC 111 and transmits the width-modulated pulse signal WMPFout. As shown in Figure 8, six signal wirings 181-1 to 181-6 are arranged in one row of the pixel array 45. As a result, for example, of the six horizontally adjacent pulse width modulation units 101-A, the first three pulse width modulation units 101-A output the width-modulated pulse signal WMPFout to the TDC 111 using the signal wirings 181-1, 3, and 5 in the upper row of the macro pixels MP where the pulse width modulation units 101-A are located, and the latter three pulse width modulation units 101-A output the width-modulated pulse signal WMPFout to the TDC 111 using the signal wirings 181-1, 3, and 5 in the lower row of the macro pixels MP where the pulse width modulation units 101-A are located. For six horizontally adjacent pulse width modulation units 101-B, the first three pulse width modulation units 101-B output the width-modulated pulse signal WMPFout to the TDC 111 using the signal wirings 181-2, 4, and 6 in the upper row of the macro pixels MP where the pulse width modulation units 101-B are located, while the latter three pulse width modulation units 101-B output the width-modulated pulse signal WMPFout to the TDC 111 using the signal wirings 181-2, 4, and 6 in the lower row of the macro pixels MP where the pulse width modulation units 101-B are located. Viewed on a pixel-by-pixel basis, the signal wirings 181-1 to 181-6 arranged in one row allow for the simultaneous reading of width-modulated pulse signals WMPFout for 12 pixels in the horizontal direction. When reading the width-modulated pulse signals WMPFout for all pixel rows of the pixel array 45, all pixel rows can be read sequentially in units of 12 pixel rows.

[0061] <6. Generating histograms in units of multiple pixels beyond macro pixels> The MP histogram generation unit 103 generates histograms in units of macro pixels MP, that is, in units of 2x2 4 pixels. However, histograms in units of multiple pixels beyond macro pixels MP can be generated by the signal processing unit 63, which is located downstream of the MP histogram generation unit 103, by aggregating the histogram data from multiple MP histogram generation units 103.

[0062] Figure 9 shows an example of generating histogram data in 6-pixel units and calculating the distance to the object OBJ.

[0063] In Figure 9, the illumination light emitted from the lighting device 20 is treated as spot light rather than surface light, and the macro pixels MP' corresponding to the spot light are used as the histogram generation unit. Each macro pixel MP' consists of 6 pixels in a 2x3 arrangement. In Figure 9, the dashed macro pixel MP'-1 corresponds to one predetermined spot light from among multiple spot lights emitted as illumination light, and the dashed macro pixel MP'-2 corresponds to another spot light. Macro pixel MP'-1 consists of 4 pixels of macro pixel MP-A1 and 2 pixels of macro pixel MP-A2. Macro pixel MP'-2 consists of 2 pixels of macro pixel MP-A3 and 4 pixels of macro pixel MP-A4. Each pixel 50 constituting macro pixels MP'-1 and MP'-2 is controlled as an active pixel, while the other grayed-out pixels 50 are controlled as inactive pixels.

[0064] The pulse width modulation unit 101-A1 generates a width-modulated pulse signal WMPFout corresponding to the reaction time and number of reactions of the four pixels of macro pixels MP-A1, and outputs it to the TDC 111-A1 and the demodulation circuit 112-A1 (not shown) via the signal wiring 181-1. The pulse width modulation unit 101-A2 generates a width-modulated pulse signal WMPFout corresponding to the reaction time and number of reactions of the two pixels of macro pixels MP-A2, and outputs it to the TDC 111-A2 and the demodulation circuit 112-A2 (not shown) via the signal wiring 181-3.

[0065] The MP histogram generation unit 103-A1 generates a histogram corresponding to the four pixels of macro pixel MP-A1. The MP histogram generation unit 103-A2 generates a histogram corresponding to the two pixels of macro pixel MP-A2. The signal processing unit 63 generates histogram data corresponding to macro pixel MP'-1 by summing the histogram data from the MP histogram generation unit 103-A1 and the histogram data from the MP histogram generation unit 103-A2.

[0066] The pulse width modulation unit 101-A3 generates a width-modulated pulse signal WMPFout corresponding to the reaction time and number of reactions of two pixels of macro pixels MP-A3, and outputs it to TDC 111-A3 and demodulation circuit 112-A3 (not shown) via signal wiring 181-1. The pulse width modulation unit 101-A4 generates a width-modulated pulse signal WMPFout corresponding to the reaction time and number of reactions of four pixels of macro pixels MP-A4, and outputs it to TDC 111-A4 and demodulation circuit 112-A4 (not shown) via signal wiring 181-3.

[0067] The MP histogram generation unit 103-A3 generates a histogram corresponding to two pixels of macro pixel MP-A3. The MP histogram generation unit 103-A4 generates a histogram corresponding to four pixels of macro pixel MP-A4. The signal processing unit 63 generates histogram data corresponding to macro pixel MP'-2 by summing the histogram data from the MP histogram generation unit 103-A3 and the histogram data from the MP histogram generation unit 103-A4.

[0068] As described above, the signal processing unit 63 generates a histogram in which multiple pixel units exceeding four pixels are defined as macro pixels MP' by summing the histogram data from the first MP histogram generation unit 103 (for example, the pulse width modulation unit 101-A1) and the histogram data from the second MP histogram generation unit 103 (for example, the pulse width modulation unit 101-A2), and the distance to the object OBJ can be calculated.

[0069] The grayed-out TDC 111 and MP histogram generation unit 103 correspond to inactive pixels, and the counting and histogram creation processes are stopped.

[0070] <7. Detailed Configuration of the Distancing Device> <Example of Detailed Configuration of Pulse Width Modulation Unit, Demodulation Unit, and MP Histogram Generation Unit> Figure 10 is a block diagram showing an example of the detailed configuration of the pulse width modulation unit 101, demodulation unit 102, and MP histogram generation unit 103, which are provided in correspondence with macro pixels MP.

[0071] The pulse width modulation unit 101 includes a binning circuit 201, a reaction information holding circuit 202, and a modulation circuit 203.

[0072] The binning circuit 201 outputs a binned signal ORout to the modulation circuit 203, which is obtained by binning (combining) the detection signals PFout of multiple pixels 50 of the macro pixels MP. The binning circuit 201 is composed of an OR circuit (logical disjunction circuit) 211, as will be described later in Figure 11.

[0073] The reaction information holding circuit 202 has an SR latch circuit 221 for each pixel 50 that constitutes the macro pixel MP. Therefore, the reaction information holding circuit 202 has four SR latch circuits 221. The reaction information holding circuit 202 detects and holds reaction information when multiple pixels 50 within the macro pixel MP react. The reaction information held by the reaction information holding circuit 202 is output to the modulation circuit 203 for each pixel 50.

[0074] The modulation circuit 203 includes a pulse width changing circuit 231 and a delay generation circuit 232. The pulse width changing circuit 231 generates and outputs a width-modulated pulse signal WMPFout, whose pulse width is changed according to the delay time generated by the delay generation circuit 232. The delay generation circuit 232 generates a delay time according to the response information and outputs it to the pulse width changing circuit 231.

[0075] The pulse width changing circuit 231 has an FF circuit (flip-flop circuit) 241, which generates and outputs a width-modulated pulse signal WMPFout, which is modified from the binning signal ORout from the binning circuit 201 to a pulse width corresponding to the number of responses of macro pixels MP. The binning signal ORout from the binning circuit 201 is supplied to the CLK input of the FF circuit 241, and a Hi is supplied to the Set input of the FF circuit 241. The delay signal DLYOUT, which is the output of the delay generation circuit 232, is supplied to the Reset input of the FF circuit 241. The FF circuit 241 outputs a width-modulated pulse signal WMPFout from its Q output, which is Hi with the binning signal ORout from the binning circuit 201 and Lo (Lo reset) with the Lo delay signal DLYOUT from the delay generation circuit 232.

[0076] The delay generation circuit 232 generates a delayed signal DLYOUT, which delays the timing of when it becomes Hi according to the output results of the four SR latch circuits 221 of the reaction information holding circuit 202, and outputs it to the FF circuit 241 of the pulse width changing circuit 231.

[0077] The demodulation unit 102 includes a TDC 111 and a demodulation circuit 112. The demodulation circuit 112 includes a pulse width detection circuit 271 and a response number conversion circuit 272. The width-modulated pulse signal WMPFout output from the pulse width changing circuit 231 is supplied to the TDC 111 and the demodulation circuit 112.

[0078] The TDC 111 generates a time code (ToF value), which is a count value corresponding to the time from when the illumination device 20 emits light until it receives reflected light, and outputs it to the MP histogram generation unit 103. The time code is a count value corresponding to the rising edge of the width modulated pulse signal WMPFout, and corresponds to the reaction time of the first pixel 50 to react among the multiple pixels 50 constituting the macro pixel MP.

[0079] The pulse width detection circuit 271 detects the time width from the rising edge to the falling edge of the width-modulated pulse signal WMPFout, i.e., the pulse width of the width-modulated pulse signal WMPFout, and outputs it to the response number conversion circuit 272. The response number conversion circuit 272 converts the pulse width detected by the response number conversion circuit 272 into data (binary value) corresponding to the response number and outputs it to the MP histogram generation unit 103.

[0080] The MP histogram generation unit 103 includes an address decoder 281 and a plurality of ripple counters 282. The number of ripple counters 282 corresponds to the number of bins in the histogram to be generated.

[0081] The address decoder 281 functions as a bin selector that selects the bin number corresponding to the time code. If the histogram generation method is edge detection, the address decoder 281 increments the ripple counter 282 of the bin corresponding to the time code by a number corresponding to the number of responses. If the histogram generation method is level detection, the address decoder 281 increments the ripple counter 282 of each bin, starting with the bin corresponding to the time code, by one, for a number of bins corresponding to the number of responses.

[0082] <Detailed Circuit Configuration Example of Pulse Width Modulation Unit> Figure 11 shows a more detailed circuit configuration example of the pulse width modulation unit 101.

[0083] In the explanations from Figure 11 onward, the four pixels 50 constituting the macro pixel MP will be described separately as pixels 50A to 50D as needed. In addition, the detection signals PFout output by pixels 50A to 50D constituting the macro pixel MP may be described separately as detection signals PFout1 to PFout4.

[0084] The binning circuit 201 has OR circuits 211-1 to 211-3, which calculate the logical OR of the detection signals PFout output by pixels 50A to 50D and output a binning signal ORout. OR circuit 211-1 calculates the logical OR of the detection signal PFout1 of pixel 50A and the detection signal PFout2 of pixel 50B and outputs the calculation result to OR circuit 211-3. OR circuit 211-2 calculates the logical OR of the detection signal PFout3 of pixel 50C and the detection signal PFout4 of pixel 50D and outputs the calculation result to OR circuit 211-3. OR circuit 211-3 calculates the logical OR of the outputs of OR circuit 211-1 and OR circuit 211-2 and outputs the binning signal ORout, which is the calculation result, to the FF circuit 241 of the pulse width changing circuit 231. The rising edge of the binning signal ORout corresponds to the response time of the first pixel 50 to respond among pixels 50A to 50D.

[0085] The reaction information holding circuit 202 has SR latch circuits 221A to 221D corresponding to pixels 50A to 50D of the macro pixels MP. Each SR latch circuit 221 detects and holds reaction information when the corresponding pixel 50 reacts. Each SR latch circuit 221 generates a latch signal DLY that holds Hi for a predetermined period from the moment the detection signal PFout of the corresponding pixel 50 becomes Hi, and outputs it to the delay generation circuit 232. Specifically, SR latch circuit 221A generates a latch signal DLY1 that detects and holds the reaction information of pixel 50A and outputs it to the delay generation circuit 232. SR latch circuit 221B generates a latch signal DLY2 that detects and holds the reaction information of pixel 50B and outputs it to the delay generation circuit 232. SR latch circuit 221C generates a latch signal DLY3 that detects and holds the reaction information of pixel 50C and outputs it to the delay generation circuit 232. The SR latch circuit 221D generates a latch signal DLY4 that detects and holds the response information of the pixel 50D, and outputs it to the delay generation circuit 232. The period during which the latch signal DLY holds Hi is the period until a Lo delay signal DLYOUT' is supplied from the delay element 316 of the modulation circuit 203 to the Reset input of the SR latch circuit 221. The delay signal DLYOUT' is a signal obtained by delaying the delay signal DLYOUT, which is the output of the delay generation circuit 232, by a predetermined time.

[0086] The delay generation circuit 232 includes a current source 301, MOS transistors 302, MOS transistors 311A ​​to 311D, capacitive elements 312A to 312D, inverter 313, MOS transistor 314, and inverter 315. MOS transistors 302, 311A ​​to 311D, and 314 are composed of, for example, N-type MOS transistors (MOS FETs).

[0087] The current source 301 is a current source that supplies a constant current I to the capacitive elements 312A to 312D. The MOS transistor 302 is a transistor that switches the current supply to the capacitive elements 312A to 312D on and off. The gate of the MOS transistor 302 is supplied with the width-modulated pulse signal WMPFout, which is the output of the FF circuit 241, and current can be supplied to the capacitive elements 312A to 312D while the width-modulated pulse signal WMPFout is high.

[0088] MOS transistors 311A ​​to 311D are transistors that control the connection (on / off) with capacitive elements 312A to 312D. A latch signal DLY1 from the SR latch circuit 221A is supplied to the gate of MOS transistor 311A, and MOS transistor 311A ​​is turned on when pixel 50A reacts. A latch signal DLY2 from the SR latch circuit 221B is supplied to the gate of MOS transistor 311B, and MOS transistor 311B is turned on when pixel 50B reacts. A latch signal DLY3 from the SR latch circuit 221C is supplied to the gate of MOS transistor 311C, and MOS transistor 311C is turned on when pixel 50C reacts. A latch signal DLY4 from the SR latch circuit 221D is supplied to the gate of MOS transistor 311D, and MOS transistor 311D is turned on when pixel 50D reacts. Therefore, the capacitive elements 312A to 312D are charged by a constant current I from the current source 301 in a number corresponding to the number of pixels that reacted in the macro pixels MP. The capacitance C of the capacitive elements 312A to 312D is the same.

[0089] The inverter 313 generates a low delay signal DLYOUT when the input voltage VPWM, corresponding to the charging of capacitive elements 312A to 312D, exceeds the threshold voltage Vth1, and outputs it to the Reset input of the FF circuit 241 and to the delay element 316.

[0090] The gate of the MOS transistor 314 is supplied with the output of the inverter 315. The inverter 315 receives the width-modulated pulse signal WMPFout, which is the output of the FF circuit 241. The MOS transistor 314 turns on when the width-modulated pulse signal WMPFout switches from Hi to Lo, and resets the charge of the capacitive elements 312A to 312D.

[0091] <Timing Chart of Pulse Width Modulation Unit> The operation of the pulse width modulation unit 101 will be explained with reference to the timing chart in Figure 12. Figure 12 shows the operation according to the number of reactions of the four pixels 50A to 50D that constitute the macro pixel MP. For the sake of explanation, we will assume that when there is one reaction, pixel 50A reacts; when there are two reactions, pixels 50A and 50B react; and when there are three reactions, pixels 50A to 50C react. However, the combination of pixels 50 that react within the macro pixel MP does not matter.

[0092] First, we will explain the case where only pixel 50A reacts, and there is one reaction within the macro pixel MP.

[0093] Pixel 50A reacts and outputs a Hi detection signal PFout1. The SR latch circuit 221A outputs a Hi latch signal DLY1 in response to the rising edge of the detection signal PFout1. The Hi latch signal DLY1 turns on the MOS transistor 311A ​​of the delay generation circuit 232, and the capacitive element 312A is charged with a constant current I from the current source 301. When the input voltage VPWM corresponding to the charge of the capacitive element 312A exceeds the threshold voltage Vth1, the inverter 313 generates a Lo delay signal DLYOUT and resets the FF circuit 241. As a result, the width modulated pulse signal WMPFout, which is the output of the FF circuit 241, becomes Lo. After a predetermined time of the Lo delay signal DLYOUT (after the delay time of the delay element 316), the latch signal DLY1 of the SR latch circuit 221A is also reset to Lo. The time it takes for the capacitive element 312A to charge and for the input voltage VPWM of the inverter 313 to exceed the threshold voltage Vth1, in other words, the pulse width of the width-modulated pulse signal WMPFout, is determined by C・Vth1 / I (hereinafter referred to as modulation width 1). The charging time of the capacitive element 312A becomes the delay time generated by the delay generation circuit 232.

[0094] Next, we will explain the case where there are two reactions within a macro pixel MP, and pixel 50A reacts first, followed by pixel 50B.

[0095] Pixel 50A reacts and outputs a Hi detection signal PFout1. The SR latch circuit 221A outputs a Hi latch signal DLY1 in response to the rising edge of the detection signal PFout1. Subsequently, when pixel 50B reacts, the SR latch circuit 221B outputs a Hi latch signal DLY2 in response to the rising edge of the detection signal PFout2. The Hi latch signal DLY1 turns on the MOS transistor 311A ​​of the delay generation circuit 232, and then the Hi latch signal DLY2 turns on the MOS transistor 311B of the delay generation circuit 232. With MOS transistors 311A ​​and 311B turned on, capacitive elements 312A and 312B are charged by a constant current I from the current source 301. When the input voltage VPWM corresponding to the charging of capacitive elements 312A and 312B exceeds the threshold voltage Vth1, the inverter 313 generates a Lo delay signal DLYOUT and resets the FF circuit 241. As a result, the width-modulated pulse signal WMPFout, which is the output of the FF circuit 241, becomes low. After a predetermined time of the low delay signal DLYOUT, the latch signals DLY1 and DLY2 of the SR latch circuits 221A and 221B are also reset to low. The time it takes for the capacitive elements 312A and 312B to charge and for the input voltage VPWM of the inverter 313 to exceed the threshold voltage Vth1, in other words, the pulse width of the width-modulated pulse signal WMPFout, is determined by 2C・Vth1 / I, and becomes twice the width of modulation width 1 (hereinafter referred to as modulation width 2). The charging time of the capacitive elements 312A and 312B becomes the delay time generated by the delay generation circuit 232.

[0096] Next, we will explain the case where there are three reactions within a macro pixel MP, and the three pixels react in the order of pixels 50A, 50B, and 50C.

[0097] In response to the Hi detection signals PFout1, PFout2, and PFout3 output by pixels 50A, 50B, and 50C, the SR latch circuits 221A, 221B, and 221C output Hi latch signals DLY1, DLY2, and DLY3. The Hi latch signals DLY1, DLY2, and DLY3 sequentially turn on the MOS transistors 311A, 311B, and 311C of the delay generation circuit 232, and the capacitive elements 312A, 312B, and 312C are charged by a constant current I from the current source 301. When the input voltage VPWM corresponding to the charging of the capacitive elements 312A, 312B, and 312C exceeds the threshold voltage Vth1, the inverter 313 generates a Lo delay signal DLYOUT and resets the FF circuit 241. As a result, the width-modulated pulse signal WMPFout, which is the output of the FF circuit 241, becomes Lo. After a predetermined time has elapsed since the delay signal DLYOUT was set to Lo, the latch signals DLY1, DLY2, and DLY3 are also reset to Lo. The time it takes for the capacitive elements 312A to 312C to charge and for the input voltage VPWM of the inverter 313 to exceed the threshold voltage Vth1, in other words, the pulse width of the width-modulated pulse signal WMPFout, is determined by 3C・Vth1 / I, which is three times the width of modulation width 1 (hereinafter referred to as modulation width 3). The charging time of the capacitive elements 312A to 312C becomes the delay time generated by the delay generation circuit 232.

[0098] Next, we will explain the case where there are four reactions within a macro pixel MP, and the four pixels react in the order of pixels 50A, 50B, 50C, and 50D.

[0099] In response to the detection signals PFout1 to PFout4 that pixels 50A to 50D output, the SR latch circuits 221A to 221D output high latch signals DLY1 to DLY4. The high latch signals DLY1 to DLY4 sequentially turn on the MOS transistors 311A ​​to 331D of the delay generation circuit 232, and the capacitive elements 312A to 312D are charged by a constant current I from the current source 301. When the input voltage VPWM corresponding to the charging of the capacitive elements 312A to 312D exceeds the threshold voltage Vth1, the inverter 313 generates a low delay signal DLYOUT and resets the FF circuit 241. As a result, the width-modulated pulse signal WMPFout, which is the output of the FF circuit 241, becomes low. After a predetermined time of the low delay signal DLYOUT, the latch signals DLY1 to DLY4 are also reset to low. The time it takes for the input voltage VPWM of the inverter 313 to exceed the threshold voltage Vth1 while the capacitive elements 312A to 312D are charged, in other words, the pulse width of the width-modulated pulse signal WMPFout is determined by 4C・Vth1 / I, which is four times the width of modulation width 1 (hereinafter referred to as modulation width 4). The charging time of the capacitive elements 312A to 312D becomes the delay time generated by the delay generation circuit 232.

[0100] When multiple pixels 50 react in a macro pixel MP, regardless of the order or combination in which the multiple pixels of the macro pixel MP react, if there are two reactions, the pulse width of the width-modulated pulse signal WMPFout is determined by 2C・Vth1 / I; if there are three reactions, the pulse width of the width-modulated pulse signal WMPFout is determined by 3C・Vth1 / I; and if there are four reactions, the pulse width of the width-modulated pulse signal WMPFout is determined by 4C・Vth1 / I. In other words, the capacitance C increases in proportion to the number of reactions of pixels 50 in the macro pixel MP, and it is charged with a constant current I, so the charging time until the input voltage VPWM exceeds the threshold voltage Vth1 is proportional to the number of reactions of pixels 50 in the macro pixel MP. As a result, the pulse width modulation unit 101 can generate and output a width-modulated pulse signal WMPFout with a pulse width proportional to the number of reactions of pixels 50.

[0101] <Detailed Circuit Configuration Example of Pulse Width Detection Circuit and Response Number Conversion Circuit> Figure 13 shows a detailed circuit configuration example of the pulse width detection circuit 271 and the response number conversion circuit 272 of the demodulation circuit 112.

[0102] The pulse width detection circuit 271 is constructed by connecting four stages of blocks, each consisting of an EXOR circuit 351, a delay generation circuit 352, an inverter 353, and an FF circuit (flip-flop circuit) 354. The EXOR circuit 351, delay generation circuit 352, inverter 353, and FF circuit 354 in each stage are distinguished by assigning the labels A, B, C, and D to them in order from the input side of the width-modulated pulse signal WMPFout.

[0103] The EXOR circuit 351A calculates the exclusive OR (EXOR) of the width-modulated pulse signal WMPFout from the pulse width modulation unit 101 and the output of the FF circuit 354A, and outputs the calculation result to the delay generation circuit 352A.

[0104] The delay generation circuit 352A includes a current source 371A, MOS transistors 372A and 373A, a capacitive element 374A, inverters 375A and 376A, and MOS transistors 377A to 379A. The MOS transistors 372A, 373A, 377A to 379A are composed of, for example, N-type MOS transistors (MOS FETs).

[0105] The delay generation circuit 352A charges the capacitive element 374A with a constant current I from the current source 371A when the output of the EXOR circuit 351A is Hi, and outputs a Lo signal when it exceeds the threshold voltage Vth2 of the inverter 375A. The delay generation circuit 352A is composed of a replica circuit of the delay generation circuit 232 of the pulse width modulation unit 101. Specifically, the current source 371A corresponds to the current source 301 of the delay generation circuit 232, the MOS transistors 372A and 373A correspond to the MOS transistors 302 and 311A ​​of the delay generation circuit 232, the capacitive element 374A corresponds to the capacitive element 312A of the delay generation circuit 232, and the inverter 375A corresponds to the inverter 313 of the delay generation circuit 232. The inverter 376A corresponds to the inverter 315 of the delay generation circuit 232, and the MOS transistors 377A to 379A correspond to the MOS transistor 314 of the delay generation circuit 232. By configuring the delay generation circuit 352A as a replica circuit of the modulation-side delay generation circuit 232, a correlation is established between the modulation and demodulation sides in terms of voltage and temperature fluctuations, making the modulation and demodulation operation more robust.

[0106] Inverter 353A outputs an inverted signal, which is the output signal of inverter 375A from delay generation circuit 352A, to the CLK input of inverter 375A.

[0107] The FF circuit 354A outputs a high signal from its Q output when the output signal of inverter 353A is high. The width modulated pulse signal WMPFout is input to the Reset input of the FF circuit 354A, and when the width modulated pulse signal WMPFout becomes low, the output of the FF circuit 354A is reset (low reset).

[0108] The second stage EXOR circuit 351B calculates the exclusive OR (EXOR) of the output of the first stage FF circuit 354A and the output of the FF circuit 354B, and outputs the result to the delay generation circuit 352B. The operation of the second stage delay generation circuit 352B, inverter 353B, and FF circuit 354B is the same as that of the first stage delay generation circuit 352A, inverter 353A, and FF circuit 354A. The third and fourth stages are the same as the second stage.

[0109] The reaction number conversion circuit 272 includes an inverter 401, EXOR circuits 411A to 411E, and FF circuits (flip-flop circuits) 412A to 412E.

[0110] The inverter 401 outputs the inverted signal of the width-modulated pulse signal WMPFout from the pulse width modulation unit 101 to the CLK input of the FF circuits 412A to 412E. The EXOR circuits 411A to 411E calculate the exclusive OR (EXOR) of the two inputs and output the calculation result to the Set input of the FF circuits 412A to 412E. An enable signal EN, which controls the on / off state of demodulation operation, is supplied to the Reset input of the EXOR circuits 411A to 411E, for example from the distance measurement control unit 46. When demodulation operation is to start, a Hi enable signal EN is input.

[0111] The EXOR circuit 411A calculates the exclusive OR (EXOR) of the always-high signal and the output of the FF circuit 354A, and outputs the calculation result to the Set input of the FF circuit 412A. When the FF circuit 412A receives a high signal from the EXOR circuit 411A, it outputs a high signal from its Q output. The CLK input of the EXOR circuit 411A receives the inverted signal of the width-modulated pulse signal WMPFout, and the EXOR circuit 411A is reset when the next width-modulated pulse signal WMPFout, after counting the number of responses, becomes low.

[0112] EXOR circuit 411B performs an exclusive OR (EXOR) operation between the output of FF circuit 354A and the output of FF circuit 354B, and outputs the result to the Set input of FF circuit 412B. When a Hi signal is input to FF circuit 412B from EXOR circuit 411B, FF circuit 412B outputs a Hi signal from its Q output. The same applies to EXOR circuits 411C to 411E and FF circuits 412C to 412E, so their explanation is omitted. FF circuits 412A to 412D correspond to response numbers "1", "2", "3", and "4" from the FF circuit 354A side, and FF circuit 412E is an error detection circuit.

[0113] The FF circuits 354A to 354D of the pulse width detection circuit 271 output a Hi or Lo signal corresponding to the pulse width of the width-modulated pulse signal WMPFout. The response number conversion circuit 272 converts the pulse width detected by the pulse width detection circuit 271 into a binary value as data indicating the number of responses and outputs it to the MP histogram generation unit 103. Specifically, if the number of responses for a macro pixel MP is one, the FF circuits 412A to 412D output Hi(1), Lo(0), Lo(0), Lo(0) from the FF circuit 412A side. If the number of responses for a macro pixel MP is two, the FF circuits 412A to 412D output Lo(0), Hi(1), Lo(0), Lo(0) from the FF circuit 412A side. When there are three macro pixel MPs, FF circuits 412A to 412D output Lo(0), Lo(0), Hi(1), and Lo(0) from FF circuit 412A. When there are four macro pixel MPs, FF circuits 412A to 412D output Lo(0), Lo(0), Lo(0), and Hi(1) from FF circuit 412A.

[0114] <Timing Chart of Pulse Width Detection Circuit and Response Number Conversion Circuit> The operation of the pulse width detection circuit 271 and the response number conversion circuit 272 of the demodulation circuit 112 will be explained with reference to the timing chart in Figure 14. Figure 14 shows the operation according to the response number of the four pixels 50A to 50D that constitute the macro pixel MP. For the sake of explanation, we will assume that when there is one response, pixel 50A responds; when there are two responses, pixels 50A and 50B respond; and when there are three responses, pixels 50A to 50C respond, but the combination of pixels 50 that respond within the macro pixel MP does not matter.

[0115] First, we will explain the case where only pixel 50A responds and a modulated pulse signal WMPFout with a modulation width of 1 is input.

[0116] In the pulse width detection circuit 271, after a time interval of modulation width 1 has elapsed from the rising edge of the width-modulated pulse signal WMPFout with modulation width 1, the falling edge of the width-modulated pulse signal WMPFout resets the FF circuits 354A to 354D, so the FF circuits 354A to 354D maintain a Lo output. In the response number conversion circuit 272, since one of the inputs to the EXOR circuit 411A is always Hi, the FF circuits 412A to 412D output Hi(1), Lo(0), Lo(0), Lo(0) from the FF circuit 354A side. When the next width-modulated pulse signal WMPFout is input and becomes Lo, the FF circuits 412A to 412D are reset.

[0117] Next, we will describe the case where pixels 50A and 50B react and a width-modulated pulse signal WMPFout with a modulation width of 2 is input.

[0118] In the pulse width detection circuit 271, after a time interval of modulation width 1 has elapsed from the rising edge of the width-modulated pulse signal WMPFout with modulation width 2, the output of the delay generation circuit 352A becomes Hi, and the FF circuit 354A outputs a Hi signal. Due to the Hi signal output of the FF circuit 354A, only the EXOR circuit 411B among the EXOR circuits 411A to 411D outputs a Hi signal, so the FF circuits 412A to 412D output Lo(0), Hi(1), Lo(0), Lo(0) from the FF circuit 354A side. When the next width-modulated pulse signal WMPFout is input and becomes Lo, the FF circuits 412A to 412D are reset.

[0119] Next, we will explain the case where pixels 50A to 50C react and a modulated pulse signal WMPFout with a modulation width of 3 is input.

[0120] In the pulse width detection circuit 271, FF circuit 354A outputs a Hi signal after a time interval of 1 modulation width from the rising edge of the width-modulated pulse signal WMPFout with a modulation width of 3. Furthermore, FF circuit 354B outputs a Hi signal after a time interval of 2 modulation widths from the rising edge of the width-modulated pulse signal WMPFout. Due to the Hi signal output from FF circuits 354A and 354B, only EXOR circuit 411C among EXOR circuits 411A to 411D outputs a Hi signal, so FF circuits 412A to 412D output Lo(0), Lo(0), Hi(1), Lo(0) from the FF circuit 354A side. When the next width-modulated pulse signal WMPFout is input and becomes Lo, FF circuits 412A to 412D are reset.

[0121] Next, we will explain the case where pixels 50A to 50D react and a modulated pulse signal WMPFout with a modulation width of 4 is input.

[0122] In the pulse width detection circuit 271, FF circuit 354A outputs a Hi signal after a time interval of 1 modulation width from the rising edge of the width-modulated pulse signal WMPFout with modulation width 4. Furthermore, FF circuit 354B outputs a Hi signal after a time interval of 2 modulation widths from the rising edge of the width-modulated pulse signal WMPFout, and FF circuit 354C outputs a Hi signal after a time interval of 3 modulation widths from the rising edge of the width-modulated pulse signal WMPFout. Due to the Hi signal output from FF circuits 354A to 354C, only EXOR circuit 411D outputs a Hi signal among EXOR circuits 411A to 411D, so FF circuits 412A to 412D output Lo(0), Lo(0), Lo(0), and Hi(1) from the FF circuit 354A side. When the next width-modulated pulse signal WMPFout is input and becomes Lo, FF circuits 412A to 412D are reset.

[0123] <Detailed Configuration Example of MP Histogram Generation Unit (Edge Detection Method)> Figure 15A is a block diagram showing an example configuration of the MP histogram generation unit 103 when the histogram generation method is the edge detection method.

[0124] The MP histogram generation unit 103 consists of an address decoder 281 and a number of ripple counters 282 corresponding to the number of bins in the histogram. For example, if the histogram consists of N bins, then N ripple counters 282, numbered 282-0 to 282-(N-1), are provided.

[0125] The address decoder 281 selects a bin number corresponding to the time code and increments the frequency value of the ripple counter 282-n (where n is an integer between 0 and N-1, inclusive) corresponding to the selected bin number by the number of responses.

[0126] Figure 15B shows an example where the frequency value of the ripple counter 282-5 is increased by "+3" when the time code is "5" and the number of responses is "3".

[0127] <Detailed Configuration Example of MP Histogram Generation Unit (Level Detection Method)> Figure 16A is a block diagram showing an example configuration of the MP histogram generation unit 103 when the histogram generation method is the level detection method.

[0128] The MP histogram generation unit 103 consists of an address decoder 281 and a number of ripple counters 282 corresponding to the number of bins in the histogram. For example, if the histogram consists of N bins, then N ripple counters 282, numbered 282-0 to 282-(N-1), are provided.

[0129] The address decoder 281 selects a bin number corresponding to the time code, and using the selected bin number as the first bin, it counts up the frequency value of the ripple counter 282, which corresponds to the number of responses.

[0130] Figure 16B shows an example where the frequency values ​​of ripple counters 282-5, 6, and 7 are each increased by "+1" when the time code is "5" and the number of responses is "3".

[0131] <8. Effects of the Distance Measuring Device> The effects of the distance measuring device 30 will be explained with reference to Figure 17.

[0132] Figure 17 shows a comparison of the count rates between this method and the 4-pixel OR method. The 4-pixel OR method is a method disclosed in prior art document Patent Document 1, which reduces the number of wires and TDCs by binning the detection signals PFout of four pixels with an OR circuit.

[0133] In Figure 17, the horizontal axis represents the incident photon rate per pixel [cps (counts per second)], and the vertical axis represents the count rate per pixel [cps].

[0134] If the dead time for pixel 50 is 5 nsec, the saturation count rate is calculated by the reciprocal of 5 nsec, resulting in 200 M [cps]. In the 4-pixel OR method, under high light conditions, the probability of multiple pixels reacting almost simultaneously increases, leading to count loss, and the count rate per pixel saturates at 50 M [cps]. In contrast, this method does not miss simultaneous reactions of multiple pixels constituting the macro pixel MP, allowing the count rate to be increased up to the saturation count rate of 200 M [cps]. Therefore, this method reduces the number of wires and improves the dynamic range of light intensity versus count by transmitting a width-modulated pulse signal WMPFout per macro pixel MP.

[0135] <9. Second Configuration Example of Pulse Width Modulation Unit> Next, with respect to the pulse width modulation unit 101, configurations different from those described in Figures 11 and 12 will be described with reference to Figures 18 to 21. The configuration of the pulse width modulation unit 101 described in Figures 11 and 12 will be referred to as the first configuration example, and the second and third configuration examples of the pulse width modulation unit 101 will be described below.

[0136] Figure 18 is a block diagram showing a second configuration example of the pulse width modulation unit 101.

[0137] In Figure 18, parts common to the pulse width modulation unit 101 described in Figures 11 and 12 are denoted by the same reference numerals, and explanations of those parts are omitted as appropriate. In the second configuration example of Figure 18, the binning circuit 201 and the reaction information holding circuit 202 are the same as in the first configuration example, but the configuration of the modulation circuit 203 differs from that of the first configuration example.

[0138] The modulation circuit 203 includes a pulse width modulation circuit 451, a combinational circuit 452, and an inverter 453.

[0139] The pulse width modulation circuit 451 includes a waveform shaping circuit 471, switches 472 to 474, delay elements 475 to 477, and OR circuits (logical disjunction circuits) 481-1 to 481-3.

[0140] The waveform shaping circuit 471 shapes the binning signal ORout from the binning circuit 201 into a pulse signal ORout' with a constant pulse width, specifically a modulation width of 1, and outputs it. Switches 472 to 474 control their connection (on / off) according to the switch control signals DLY2', DLY3', and DLY4', which are outputs from the combinational circuit 452. Delay elements 475 to 477 each delay the input signal by a time width equal to the modulation width of 1.

[0141] OR circuits 481-1 to 481-3 generate and output a width-modulated pulse signal WMPFout by performing a logical OR operation on the output signal (pulse signal ORout') of the waveform shaping circuit 471 and the output signals DLY2OUT to DLY4OUT from the waveform shaping circuit 471 via delay elements 475 to 477. Specifically, OR circuit 481-1 calculates the logical OR of the output signal DLY4OUT of the delay element 477 and the output signal DLY3OUT of the delay element 476, and outputs the calculation result to OR circuit 481-3. OR circuit 481-2 calculates the logical OR of the output signal DLY2OUT of the delay element 475 and the pulse signal ORout' output by the waveform shaping circuit 471, and outputs the calculation result to OR circuit 481-3. OR circuit 481-3 calculates the logical OR of the outputs of OR circuit 481-1 and OR circuit 481-2, and outputs the calculation result as a width-modulated pulse signal WMPFout. The width-modulated pulse signal WMPFout is output not only to the demodulation unit 102 but also to the inverter 453 in the modulation circuit 203. The output of the inverter 453 is supplied to the Reset input of each SR latch circuit 221 in the reaction information holding circuit 202.

[0142] The combination circuit 452 generates switch control signals DLY2', DLY3', and DLY4' according to the combination result of the latch signals DLY1, DLY2, DLY3, and DLY4 from the reaction information holding circuit 202, and outputs them to switches 472 to 474.

[0143] Figure 19 shows the truth table for the combinational circuit 452 that generates the switch control signals DLY2', DLY3', and DLY4'.

[0144] If the latch signals DLY1, DLY2, DLY3, and DLY4 determine that the number of responses of pixel 50 of the macro pixel MP is 1, the combinational circuit 452 outputs a "Lo" signal for all switch control signals DLY2', DLY3', and DLY4'. If the number of responses of pixel 50 of the macro pixel MP is determined to be 2, the combinational circuit 452 outputs a "Hi" signal for switch control signal DLY2' and a "Lo" signal for switch control signals DLY3' and DLY4'. If the number of responses of pixel 50 of the macro pixel MP is determined to be 3, the combinational circuit 452 outputs a "Hi" signal for switch control signals DLY2' and DLY3' and a "Lo" signal for switch control signal DLY4'. If the number of responses of pixel 50 of the macro pixel MP is determined to be 4, the combinational circuit 452 outputs a "Hi" signal for all switch control signals DLY2', DLY3', and DLY4'.

[0145] <10. Third Configuration Example of Pulse Width Modulation Unit> Figure 20 is a block diagram showing a third configuration example of the pulse width modulation unit 101.

[0146] In Figure 20, parts common to the pulse width modulation unit 101 described in Figures 11 and 12 are denoted by the same reference numerals, and explanations of those parts are omitted as appropriate. In the third configuration example of Figure 20, the binning circuit 201 and the reaction information holding circuit 202 are the same as in the first configuration example, but the configuration of the modulation circuit 203 differs from that of the first configuration example.

[0147] The modulation circuit 203 includes a pulse width modulation circuit 501, a combination circuit 502, and an inverter 503.

[0148] The pulse width modulation circuit 501 includes delay elements 521 to 524, a selector (selection circuit) 525, an AND circuit (logic AND circuit) 526, and an FF circuit (flip-flop circuit) 527.

[0149] Each of the delay elements 521 to 524 delays the input signal by a time width equal to the modulation width 1. The selector 525 selects one of the inputs SEL1 to SEL4 based on the selection control signal DLYSEL output from the combination circuit 452, and outputs the selected signal as the output signal DLYOUT. The outputs from the delay elements 521 to 524 are input to inputs SEL1 to SEL4, and the output signals of the delay elements 521 to 524 are signals with different delay amounts relative to the binning signal ORout, which is the output of the binning circuit 201. The AND circuit 526 calculates the logical AND of the output signal DLYOUT from the selector 525 and the width-modulated pulse signal WMPFout, which is the output of the FF circuit 527, and outputs the calculation result to the Reset input of the FF circuit 527.

[0150] The FF circuit 527 uses the binning signal ORout, which is the output of the binning circuit 201, and the output signal DLYOUT from the selector 525 to generate and output a width-modulated pulse signal WMPFout, which has been modified to have a pulse width corresponding to the number of responses of macro pixels MP. The binning signal ORout from the binning circuit 201 is supplied to the CLK input of the FF circuit 527, and the Set input of the FF circuit 527 is supplied with an inverted signal of the width-modulated pulse signal WMPFout from the inverter 503. The FF circuit 527 generates a width-modulated pulse signal WMPFout that becomes Hi with the binning signal ORout from the binning circuit 201 and becomes Lo (Hi reset) with the Hi output from the AND circuit 526, and outputs it from the Q output.

[0151] The combination circuit 502 generates a selection control signal DLYSEL according to the combination result of the latch signals DLY1, DLY2, DLY3, and DLY4 from the reaction information holding circuit 202, and outputs it to the selector 525.

[0152] Figure 21 is a truth table for the combinational circuit 502 that generates the selection control signal DLYSEL.

[0153] If the latch signals DLY1, DLY2, DLY3, and DLY4 determine that the number of responses of the macro pixel MP (pixel 50) is 1, the combinational circuit 502 outputs a selection control signal DLYSEL to select SEL1. If the number of responses of the macro pixel MP (pixel 50) is determined to be 2, the combinational circuit 502 outputs a selection control signal DLYSEL to select SEL2. If the number of responses of the macro pixel MP (pixel 50) is determined to be 3, the combinational circuit 502 outputs a selection control signal DLYSEL to select SEL3. If the number of responses of the macro pixel MP (pixel 50) is determined to be 4, the combinational circuit 502 outputs a selection control signal DLYSEL to select SEL4.

[0154] <11. Transmission of Reacting Pixel Position> In the above-described embodiment, the distance measuring device 30 generated and output a width-modulated pulse signal WMPFout, which represents the reaction time of the first reacting pixel 50 in the macro pixel MP and the number of reacting pixels 50 in terms of pulse width. The above-described embodiment is referred to as the first embodiment of the distance measuring device 30.

[0155] The distance measuring device 30 can also express the position information of the pixels 50 within the macro pixels MP as response information in terms of pulse width and output it. Below, an embodiment of the distance measuring device 30 in which the position information of the responded pixels 50 is expressed and output as a width-modulated pulse signal WMPFout (hereinafter also referred to as the second embodiment) will be described.

[0156] Figure 22 illustrates a schematic configuration when outputting a pulse-width modulated pulse signal WMPFout, in which the position information of pixel 50 is represented by the pulse width as response information. In Figures 22 and later, parts common to the configuration described above are denoted by the same reference numerals, and explanations of those parts are omitted as appropriate.

[0157] As shown in the lower part of Figure 22, the pulse width modulation unit 101P generates and outputs a pulse width modulated pulse signal WMPFout, which is pulse width modulated (PWM) so that the reaction time of the first pixel 50 to be reacted to by the photodetector 81 within the macro pixel MP is represented by the rising edge of the pulse, and the position information of the pixel 50 to which the photodetector 81 reacted is represented as reaction information in the pulse width. In other words, the pulse width of the pulse width modulated pulse signal WMPFout differs depending on the pixel position of the reacted pixel 50 within the macro pixel MP.

[0158] The demodulation unit 102P includes a TDC 111 and a demodulation circuit 112P. The demodulation circuit 112P detects the pixel position of the reacted pixel 50 from the pulse width of the width-modulated pulse signal WMPFout. The demodulation circuit 112P outputs the reacted pixel position (reacted pixel position) to the MP histogram generation unit 103P.

[0159] The MP histogram generation unit 103P includes a selector 601 and pixel histogram generation units 602A to 602D. The selector 601 outputs a time code to the pixel histogram generation units 602A to 602D corresponding to the reacted pixels 50A to 50D, based on the reacted pixel position supplied from the demodulation circuit 112P. Each of the pixel histogram generation units 602A to 602D corresponds to the pixels 50A to 50D of the macro pixels MP and generates a pixel-level histogram based on the supplied time code.

[0160] <12. Detailed Configuration of the Distancing Device According to the Second Embodiment> <Detailed Configuration Example of Pulse Width Modulation Unit, Demodulation Unit, and MP Histogram Generation Unit> Figure 23 is a block diagram showing a detailed configuration example of the pulse width modulation unit 101P, demodulation unit 102P, and MP histogram generation unit 103P according to the second embodiment.

[0161] For the sake of simplicity, Figures 23 and beyond will describe the case where the macro pixel MP consists of two pixels, pixel 50A and pixel 50B.

[0162] The pulse width modulation unit 101P includes a binning circuit 201, a reaction information holding circuit 202, and a modulation circuit 203. In the modulation circuit 203, the delay generation circuit 232 in the first embodiment has been changed to a delay generation circuit 232P. The delay generation circuit 232 in the first embodiment generated a delay according to the number of reactions, but the delay generation circuit 232P generates a delay according to the pixel position. The detailed circuit configuration is omitted, but in the delay generation circuit 232P, the capacitances of the capacitive elements 312A and 312B corresponding to pixels 50A and 50B are different. For example, the capacitance C of the capacitive element 312A corresponding to pixel 50A A If this is the capacitance C, then the capacitance C of the capacitive element 312B corresponding to pixel 50B is B is, capacity C A It is said to have 1.5 times the capacity (1.5C).

[0163] Figure 24 shows an example of a width-modulated pulse signal WMPFout when pixels 50A and 50B react.

[0164] When pixel 50A reacts, the pulse width of the width-modulated pulse signal WMPFout is determined by C・Vth1 / I. When pixel 50B reacts, the pulse width of the width-modulated pulse signal WMPFout is determined by 1.5C・Vth1 / I. When both pixels 50A and 50B react, the pulse width of the width-modulated pulse signal WMPFout is determined by (1+1.5)C・Vth1 / I. By detecting the position of the reacted pixel based on the pulse width of the width-modulated pulse signal WMPFout, the number of reacted pixels 50 within the macro pixel MP can also be detected.

[0165] Returning to Figure 23, in the demodulation unit 102P, the pulse width detection circuit 271 and the reaction number conversion circuit 272 in the first embodiment have been changed to a pulse width detection circuit 271P and a reaction position conversion circuit 272P.

[0166] <Detailed Circuit Configuration Example of Pulse Width Detection Circuit and Reaction Position Conversion Circuit> Figure 25 shows a detailed circuit configuration example of the pulse width detection circuit 271P and the reaction position conversion circuit 272P.

[0167] In the first embodiment, since the macro pixels MP consisted of four pixels, the EXOR circuit 351, delay generation circuit 352, inverter 353, and FF circuit 354 were connected in four stages. However, in Figure 25, the configuration has been changed to a two-stage connection to correspond to a configuration where the macro pixels MP consist of two pixels. Since the delay generation circuits 352A and 352B are replica circuits of the delay generation circuit 232 of the pulse width modulation unit 101, the capacitance of the capacitive element 374A of the delay generation circuit 352A is set to C, and the capacitance of the capacitive element 374A of the delay generation circuit 352B is set to 1.5C.

[0168] The reaction position conversion circuit 272P is the same as the reaction number conversion circuit 272 of the first embodiment, except that the blocks of the EXOR circuit 411 and FF circuit 412 are changed to three stages to correspond to the fact that the macro pixels MP are composed of two pixels. The FF circuit 412 for error detection is omitted.

[0169] <Timing chart of pulse width detection circuit and reaction position conversion circuit> Figure 26 is a timing chart illustrating the operation of the pulse width detection circuit 271P and the reaction position conversion circuit 272P.

[0170] The operation of the pulse width detection circuit 271P and the reaction position conversion circuit 272P is the same as that of the first embodiment described in Figure 14, so a detailed explanation will be omitted. The reaction position conversion circuit 272P converts the pulse width detected by the pulse width detection circuit 271P into a binary value as data indicating the pixel position and outputs it to the MP histogram generation unit 103P. Specifically, when the reaction pixel position is only pixel 50A, the FF circuits 412A to 412C of the reaction position conversion circuit 272P output Hi(1), Lo(0), Lo(0) from the FF circuit 412A side. When the reaction pixel position is only pixel 50B, the FF circuits 412A to 412C of the reaction position conversion circuit 272P output Lo(0), Hi(1), Lo(0) from the FF circuit 412A side. When the reaction pixel positions are pixels 50A and 50B, the FF circuits 412A to 412C of the reaction position conversion circuit 272P output Lo(0), Lo(0), and Hi(1) from the FF circuit 412A side.

[0171] Returning to Figure 23, the MP histogram generation unit 103P includes an MP histogram generation circuit 611, a pixel ratio histogram generation circuit 612, a peak detection circuit 613, and a pixel unit histogram generation unit 614.

[0172] The MP histogram generation circuit 611 generates a macro pixel unit histogram, which is a histogram of macro pixel MP units (first histogram) corresponding to the time code supplied from TDC 111. The pixel ratio histogram generation circuit 612 uses the time code supplied from TDC 111 and the reaction pixel position supplied from the reaction position conversion circuit 272P to generate a pixel ratio histogram, which is a histogram of the ratio of reaction pixel positions (second histogram).

[0173] The peak detection circuit 613 detects the peak bin of the histogram for each of the 50 macro pixels MP (pixels 50A, 50B) based on the pixel ratio histogram. The detected peak bins for each of the 50 pixels are supplied to the pixel-unit histogram generation unit 614.

[0174] The pixel-unit histogram generation unit 614 generates a histogram for each pixel 50 of the macro pixels MP by extracting multiple bins around the peak bin for each pixel 50 of the macro pixels MP from the macro pixel-unit histogram. Based on the generated histogram for each pixel 50, the pixel-unit histogram generation unit 614 calculates the distance D to the object OBJ for each pixel 50.

[0175] Figure 27 is a diagram illustrating the processing of the MP histogram generation unit 103P.

[0176] The MP histogram generation circuit 611 has a counter corresponding to the number of bins and counts up the frequency value of the bin corresponding to the time code. The macro pixel unit histogram generated by the MP histogram generation circuit 611 includes the histogram of pixel 50A, which is a constituent pixel of the macro pixel MP, and the histogram of pixel 50B.

[0177] The pixel ratio histogram generation circuit 612 has an up / down counter corresponding to the number of bins, and its initial value is set to the midpoint of the number of bits in the up / down counter (for example, 5 bits). The pixel ratio histogram generation circuit 612 increases the frequency value of the bin corresponding to the time code by 1 if the responding pixel is pixel 50A, and decreases it by 1 if it is pixel 50B. If the responding pixel is both pixels 50A and 50B, the frequency value is not changed.

[0178] The peak detection circuit 613 detects the peak bin of the histogram for every 50 pixels (pixels 50A, 50B) of the macro pixels MP, based on the pixel ratio histogram generated by the pixel ratio histogram generation circuit 612.

[0179] The pixel-unit histogram generation unit 614 generates histograms for each of the macro pixels MP by extracting histograms with, for example, ±3 bins, centered on the peaks for each pixel 50 detected by the peak detection circuit 613, from the macro pixel-unit histogram generated by the MP histogram generation circuit 611. The pixel-unit histogram generation unit 614 then determines the centroid bin position of the generated histogram for each pixel 50 and calculates the distance D to the object OBJ for each pixel 50 based on the centroid bin position.

[0180] The pixel ratio histogram generation circuit 612 and the peak detection circuit 613 correspond to the selector 601 in Figure 22, while the MP histogram generation circuit 611 and the pixel unit histogram generation unit 614 correspond to the pixel histogram generation units 602A to 602D in Figure 22. The number of bits for the frequency values ​​in the macro pixel unit histogram is increased to, for example, 16 bits, in order to improve the distance measurement accuracy. On the other hand, the pixel ratio histogram only needs to have enough bits to distinguish the count priority of the pixel position, so a small number of bits, for example, 5 bits, is sufficient. Therefore, the circuit area can be reduced compared to the case where a histogram generation circuit is provided for each constituent pixel of the macro pixel MP.

[0181] <13. Examples of Application to Mobile Devices> The technology relating to this disclosure (this technology) can be applied to various products. For example, the technology relating to this disclosure may be realized as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0182] Figure 28 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0183] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 28, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0184] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0185] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0186] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0187] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0188] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0189] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0190] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0191] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0192] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 28, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0193] Figure 29 shows an example of the installation position of the imaging unit 12031.

[0194] In Figure 29, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0195] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0196] Figure 29 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0197] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0198] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0199] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0200] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0201] The above describes an example of a vehicle control system to which the technology described herein can be applied. The technology described herein can be applied to the imaging unit 12031, etc., among the configurations described above. Specifically, for example, the distance measuring system 1 in Figure 1 can be applied to the imaging unit 12031. The imaging unit 12031 is, for example, a LIDAR and is used to detect objects around the vehicle 12100 and the distance to those objects. By applying the technology described herein to the imaging unit 12031, the detection accuracy of objects around the vehicle 12100 and the distance to those objects is improved. As a result, for example, collision warnings for the vehicle can be issued at an appropriate time, making it possible to prevent traffic accidents.

[0202] In this specification, a system refers to a collection of multiple components (devices, modules (parts), etc.), regardless of whether all components are located in the same enclosure. Therefore, multiple devices housed in separate enclosures and connected via a network, and a single device containing multiple modules within a single enclosure, are both considered systems.

[0203] Furthermore, the embodiments of the technology disclosed herein are not limited to those described above, and various modifications are possible without departing from the gist of the technology disclosed herein.

[0204] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0205] Furthermore, the technology disclosed herein may employ the following configurations: (1) A distance measuring device comprising a pulse width modulation unit that generates and outputs a pulse signal in which the detection signals of photons are aggregated by multiple pixels, and the pulse width represents at least one of the reaction time of the first pixel to react among the multiple pixels of the transmission unit and the number of pixels or the pixel position of the reacting pixel. (2) The distance measuring device according to (1), wherein the pulse width modulation unit comprises a binning circuit for binning the detection signals of the multiple pixels of the transmission unit, a reaction information holding circuit for holding the number of pixels or the pixel position of the transmission unit, a delay generation circuit for generating a delay time according to the number of pixels or the pixel position, and a pulse width changing circuit for generating and outputting the pulse signal with the pulse width changed according to the delay time. (3) The distance measuring device according to (2), wherein the reaction information holding circuit has a latch circuit for latching the detection signal for each pixel. (4) The distance measuring device according to any one of (2) to (3), wherein the delay generation circuit comprises a current source, a capacitive element provided for each pixel of the transmission unit, and a transistor that controls the connection between the capacitive element and the current source, and the delay time is the time until a number of the capacitive elements corresponding to the number of pixels or the pixel position are charged. (5) The distance measuring device according to any one of (2) to (4), wherein the pulse width changing circuit is composed of a flip-flop circuit and outputs the pulse signal which becomes Hi with the detection signal from the binning circuit and Lo with the signal from the delay generation circuit. (6) The distance measuring device according to any one of (1) to (5), further comprising a TDC that acquires the reaction time from the rising edge of the pulse signal, and a demodulation circuit that detects at least one of the number of pixels or the pixel position from the pulse width of the pulse signal. (7) The distance measuring device according to (6), wherein the demodulation circuit comprises a pulse width detection circuit that detects the pulse width of the pulse signal and a conversion circuit that converts the detected pulse width into a binary value corresponding to the number of pixels or the pixel position. (8) The distance measuring device according to any one of (6) to (7), further comprising a histogram generation unit that generates a histogram corresponding to the reaction time acquired by the TDC and the number of pixels or the pixel position.(9) The distance measuring device according to (8), wherein the demodulation circuit detects the number of pixels from the pulse width, and the histogram generation unit adds a value corresponding to the number of pixels to the bin of the reaction time. (10) The distance measuring device according to any one of (8) to (9), wherein the demodulation circuit detects the number of pixels from the pulse width, and the histogram generation unit adds a value to each of the bins corresponding to the number of pixels, with the bin of the reaction time being the first. (11) The distance measuring device according to any one of (8) to (10), wherein the demodulation circuit detects the pixel position from the pulse width, and the histogram generation unit generates a first histogram corresponding to the reaction time acquired at the TDC and a second histogram corresponding to the pixel position. (12) The distance measuring device according to (11), wherein the histogram generation unit extracts a histogram for each pixel of the transmission unit from the first histogram based on the second histogram and calculates the distance for each pixel. (13) The distance measuring device according to any one of (1) to (12), wherein the pulse width modulation unit comprises a binning circuit for binning the detection signals of multiple pixels of the transmission unit, a reaction information holding circuit for holding the number of pixels or the pixel positions of the transmission unit, a combination circuit for generating a signal corresponding to the number of pixels or the pixel positions, a switch for controlling the connection with a delay element according to the signal generated by the combination circuit, and a logical OR circuit for generating and outputting the pulse signal by logical ORing the output signal of the binning circuit and the signal from the binning circuit via the delay element. (14) The distance measuring device according to any one of (1) to (13), wherein the pulse width modulation unit comprises: a binning circuit for binning the detection signals of multiple pixels of the transmission unit; a reaction information holding circuit for holding the number of pixels or the pixel positions of the transmission unit; a combination circuit for generating a signal corresponding to the number of pixels or the pixel positions; a selector for selecting one of a plurality of signals with different delay amounts relative to the output signal of the binning circuit, according to the signal generated by the combination circuit; and a flip-flop circuit for generating and outputting the pulse signal using the output signal of the binning circuit and the output signal of the selector.(15) The distance measuring device according to any one of (1) to (14), wherein the transmission unit consists of 2x2 4 pixels, and the pulse width modulation unit is located in the center of the 4 pixels in a plan view. (16) The distance measuring device according to (15), wherein the pulse width modulation unit is arranged in a staggered configuration with the nearest pulse width modulation unit shifted by 1 pixel in the horizontal and vertical directions. (17) The distance measuring device according to any one of (15) to (16), wherein the wiring connecting the pulse width modulation unit and the TDC is arranged in a row of 6 wires. (18) The distance measuring device according to any one of (15) to (17), wherein the pixels output the detection signal to two of the pulse width modulation units. (19) A distance measuring device according to any one of (1) to (18), further comprising: a pixel array in which a plurality of pixels are arranged in a matrix; a drive circuit for controlling each pixel of the pixel array to be an active pixel or an inactive pixel; a histogram generation unit for generating a histogram of the transmission unit using the reaction time and the number of pixels or the pixel position; and a signal processing unit for summing the histogram data of the first histogram generation unit corresponding to the first pulse width modulation unit and the histogram data of the second histogram generation unit corresponding to the second pulse width modulation unit. (20) A distance measuring system comprising: an illumination device that emits illumination light; and a distance measuring device that receives reflected light from an object, wherein the distance measuring device comprises: a pixel array in which a plurality of pixels including a photodetector are arranged in a matrix; and a pulse width modulation unit that generates and outputs a pulse signal in which the detection signals of the photons are aggregated by the plurality of pixels, and the pulse width represents at least one of the reaction time of the first pixel to react among the plurality of pixels of the transmission unit and the number of pixels or the pixel position of the reacted pixel.

[0206] 1 Distance measuring system, 20 Illumination device, 30 Distance measuring device, 44 Drive circuit, 45 Pixel array, 46 Distance measuring control unit, 47 Distance measuring processing unit, 48 Output unit, 50 Pixel, 61 TDC unit, 62 Histogram generation unit, 63 Signal processing unit, 81 Photodetector element, 82 Quench resistor, 83 Select transistor, 84 Inverter, 92 Integration unit, 93 MP histogram generation unit, 101, 101P Pulse width modulation unit, 102, 102P Demodulation unit, 103, 103P MP histogram generation unit, 112, 112P Demodulation circuit, 140 Semiconductor substrate, 141 First semiconductor substrate, 142 Second semiconductor substrate, 143 Cu connection, 181 Signal wiring, 181-1 to 6 Signal wiring, 201 Binning circuit, 202 Reaction information holding circuit, 203 Modulation circuit, 211-1 to 3 OR circuits, 221A to 221D SR latch circuits, 231 Pulse width changing circuit, 232 Delay generation circuit, 232P Delay generation circuit, 241 FF circuit, 271, 271P Pulse width detection circuit, 272 Reaction number conversion circuit, 272P Reaction position conversion circuit, 281 Address decoder, 282 Ripple counter, 301 Current source, 302 MOS transistor, 311A ​​to 311D MOS transistor, 312A to 312D Capacitive element, 313 Inverter, 314 MOS transistor, 315 Inverter, 316 Delay element, 351A to 351D EXOR circuit, 352A to 352D Delay generation circuit, 353A-353D inverter, 354A-354D FF circuit, 371A current source, 372A, 373A MOS transistor, 374A, 374B capacitive element, 375A, 376A inverter, 377A-379A MOS transistor, 401 inverter, 411A-411E EXOR circuit, 412A-412E FF circuit, 451 pulse width modulation circuit, 452 combination circuit, 453 inverter, 471 waveform shaping circuit, 472-474 switch, 475-477 delay element, 481-1-3 OR circuit, 501 pulse width modulation circuit, 502 combination circuit, 503 inverter, 521-524 delay element, 525 selector, 526 AND gate, 527 FF gate,601 Selector, 602A Pixel histogram generation unit, 611 MP histogram generation circuit, 612 Pixel ratio histogram generation circuit, 613 Peak detection circuit, 614 Pixel unit histogram generation unit,

Claims

1. A ranging device comprising a pulse width modulation unit that generates and outputs a pulse signal in which the detection signals of photons are combined by multiple pixels, and the pulse width represents at least one of the reaction time of the first pixel to react among the multiple pixels of the transmission unit and the number of pixels or the pixel position of the reacting pixel.

2. The distance measuring device according to claim 1, wherein the pulse width modulation unit comprises a binning circuit for binning the detection signals of multiple pixels of the transmission unit; a reaction information holding circuit for holding the number of pixels or the pixel positions of the transmission unit; a delay generation circuit for generating a delay time corresponding to the number of pixels or the pixel positions; and a pulse width changing circuit for generating and outputting the pulse signal with the pulse width changed according to the delay time.

3. The distance measuring device according to claim 2, wherein the reaction information holding circuit has a latch circuit for latching the detection signal for each pixel.

4. The distance measuring device according to claim 2, wherein the delay generation circuit comprises a current source, a capacitive element provided for each pixel of the transmission unit, and a transistor that controls the connection between the capacitive element and the current source, and the delay time is the time it takes to charge a number of the capacitive elements corresponding to the number of pixels or the pixel positions.

5. The distance measuring device according to claim 2, wherein the pulse width changing circuit is composed of a flip-flop circuit and outputs the pulse signal which becomes Hi in response to the detection signal from the binning circuit and Lo in response to the signal from the delay generation circuit.

6. The distance measuring device according to claim 1, further comprising: a TDC for acquiring the reaction time from the rising edge of the pulse signal; and a demodulation circuit for detecting at least one of the number of pixels or the pixel position from the pulse width of the pulse signal.

7. The distance measuring device according to claim 6, wherein the demodulation circuit comprises a pulse width detection circuit for detecting the pulse width of the pulse signal and a conversion circuit for converting the detected pulse width into a binary value corresponding to the number of pixels or the pixel position.

8. The distance measuring device according to claim 6, further comprising a histogram generation unit that generates a histogram corresponding to the reaction time acquired by the TDC and the number of pixels or the pixel position.

9. The distance measuring device according to claim 8, wherein, when the demodulation circuit detects the number of pixels from the pulse width, the histogram generation unit adds a value corresponding to the number of pixels to the bin of the reaction time.

10. When the demodulation circuit detects the number of pixels from the pulse width, the histogram generation unit adds a value to each bin corresponding to the number of pixels, with the bin for the reaction time being the first bin. The distance measuring device according to claim 8.

11. When the demodulation circuit detects the pixel position from the pulse width, the histogram generation unit generates a first histogram corresponding to the reaction time acquired at the TDC and a second histogram corresponding to the pixel position, as described in claim 8.

12. The distance measuring device according to claim 11, wherein the histogram generation unit extracts a histogram for each pixel of the transmission unit from the first histogram based on the second histogram and calculates the distance for each pixel.

13. The distance measuring device according to claim 1, wherein the pulse width modulation unit comprises a binning circuit for binning the detection signals of multiple pixels of the transmission unit; a reaction information holding circuit for holding the number of pixels or the pixel positions of the transmission unit; a combination circuit for generating a signal corresponding to the number of pixels or the pixel positions; a switch for controlling the connection with a delay element according to the signal generated by the combination circuit; and a logical OR circuit for generating and outputting the pulse signal by performing a logical OR operation between the output signal of the binning circuit and the signal from the binning circuit via the delay element.

14. The distance measuring device according to claim 1, wherein the pulse width modulation unit comprises: a binning circuit for binning the detection signals of multiple pixels of the transmission unit; a reaction information holding circuit for holding the number of pixels or the pixel positions of the transmission unit; a combination circuit for generating a signal corresponding to the number of pixels or the pixel positions; a selector for selecting one of a plurality of signals with different delay amounts relative to the output signal of the binning circuit, according to the signal generated by the combination circuit; and a flip-flop circuit for generating and outputting the pulse signal using the output signal of the binning circuit and the output signal of the selector.

15. The distance measuring device according to claim 1, wherein the transmission unit consists of four 2x2 pixels, and the pulse width modulation unit is located in the center of the four pixels in a plan view.

16. The distance measuring device according to claim 15, wherein the pulse width modulation units are arranged in a staggered configuration with a position shift of one pixel in the horizontal and vertical directions from the nearest other pulse width modulation units.

17. The distance measuring device according to claim 15, wherein the wiring connecting the pulse width modulation unit and the TDC has six wires in one row.

18. The distance measuring device according to claim 15, wherein the pixel outputs the detection signal to two pulse width modulation units.

19. The distance measuring device according to claim 1, further comprising: a pixel array in which a plurality of pixels are arranged in a matrix; a drive circuit for controlling each pixel of the pixel array to be an active pixel or an inactive pixel; a histogram generation unit for generating a histogram of the transmission unit using the reaction time and the number of pixels or the pixel position; and a signal processing unit for summing the histogram data of the first histogram generation unit corresponding to the first pulse width modulation unit and the histogram data of the second histogram generation unit corresponding to the second pulse width modulation unit.

20. A distance measuring system comprising: an illumination device that emits illumination light; and a distance measuring device that receives reflected light from an object, wherein the distance measuring device comprises: a pixel array in which a plurality of pixels including a photodetector are arranged in a matrix; and a pulse width modulation unit that generates and outputs a pulse signal in which the detection signals of the plurality of pixels are combined, and the pulse width represents at least one of the reaction time of the first pixel to react among the plurality of pixels of the transmission unit and the number of pixels or the pixel position of the reacted pixel.

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