Chip resistor and method for manufacturing chip resistor

Abstract

This ceramic substrate has a support surface. The ceramic substrate comprises: a base material that is a sintered body of ceramic particles (A); and a covering that is a sintered body of ceramic particles (B). The support surface has a covered portion and a margin portion. The margin portion has a first margin portion and a second margin portion. The first margin portion and the second margin portion are respectively disposed on the support surface at end portions on both sides in one direction along the support surface so as to sandwich the covered portion. A first electrode is disposed on the support surface so as to cover the first margin portion. A second electrode is disposed on the support surface so as to cover the second margin portion.

Description

Chip Resistor and Method for Manufacturing Chip Resistor

[0001] The present disclosure relates to a chip resistor used in various electronic devices and a method for manufacturing the chip resistor.

[0002] Patent Document 1 discloses a technique in which a small amount of silica glass is contained in an alumina substrate itself, a glass coat is formed on the entire surface of the alumina substrate, and an upper electrode, a resistor, etc. are formed on the glass coat.

[0003] Japanese Unexamined Patent Application Publication No. 2017-168749

[0004] A chip resistor according to one aspect of the present disclosure includes a ceramic substrate, a first electrode and a second electrode disposed on the ceramic substrate, and a resistor that electrically connects the first electrode and the second electrode. The ceramic substrate has a support surface. The ceramic substrate includes a base material that is a sintered body of ceramic particles (A) and a covering that is a sintered body of ceramic particles (B) and covers a part of the base material on the support surface. The support surface has a covering portion where the covering is disposed and a margin portion where the covering is not disposed. The margin portion has a first margin portion and a second margin portion. The first margin portion and the second margin portion are disposed on both ends of the support surface along one direction along the support surface so as to sandwich the covering portion. The first electrode is disposed on the support surface so as to cover the first margin portion. The second electrode is disposed on the support surface so as to cover the second margin portion. At least a part of the covering portion is disposed in a region on the support surface sandwiched between the first electrode and the second electrode, and the first margin portion and the second margin portion are not disposed. The resistor is disposed so as to cover the region and is electrically connected to the first electrode and the second electrode.

[0005] The method for manufacturing a chip resistor according to the present disclosure is a method for manufacturing a chip resistor, comprising: preparing a large substrate having a main surface provided with a plurality of substrate forming portions arranged in a matrix, the main surface of the large substrate, by arranging the coating, which is a sintered body of ceramic particles (A), on each of the substrate forming portions to form the coating portion and the margin portion; manufacturing the first electrode, the second electrode, and the resistor on each of the substrate forming portions; and cutting the large substrate at the boundary between the substrate forming portions.

[0006] According to this disclosure, it is possible to provide a chip resistor and a method for manufacturing a chip resistor that can suppress electrode defects in a chip resistor in which electrodes and resistors are arranged on a ceramic substrate, which is a ceramic substrate coated with a ceramic coating.

[0007] Figure 1 is a schematic cross-sectional view of a chip resistor according to the present disclosure, viewed from the front, along the X1-X1 cutting line in Figure 2. Figure 2 is a schematic plan view of a chip resistor according to the present disclosure, viewed from above. Figure 3 is a schematic plan view of a large substrate in the coating placement process of a chip resistor according to the present disclosure, viewed from above. Figure 4 is a schematic cross-sectional view of a large substrate in the coating placement process of a chip resistor according to the present disclosure, viewed from the X2-X2 cutting line in Figure 3. Figure 5 is a schematic plan view of the first divided piece in the first dividing process of a chip resistor according to the present disclosure, viewed from above. Figure 6 is a schematic cross-sectional view of the first divided piece in the first dividing process of a chip resistor according to the present disclosure, viewed from the front, along the X3-X3 cutting line in Figure 5. Figure 7 is a schematic plan view of the second divided piece in the second dividing process of a chip resistor according to the present disclosure, viewed from above. Figure 8 is a schematic cross-sectional view of the second divided piece of the chip resistor in the second division process according to the embodiment of this disclosure, viewed from the front, along the X4-X4 cutting line in Figure 7. Figure 9 is a diagram showing another example of a schematic cross-sectional view of the chip resistor according to the embodiment of this disclosure, viewed from the front.

[0008] 1. Overview Embodiments of this disclosure will be described with reference to the figures. Note that the embodiments described below are only a part of the various embodiments of this disclosure. Furthermore, the embodiments described below can be modified in various ways depending on the design, etc., as long as the objectives of this disclosure are achieved. The figures referred to below are schematic diagrams, and the dimensional ratios of the components in the figures do not necessarily reflect the actual dimensional ratios. The arrows indicating direction in the drawings (arrows indicating the up / down direction, front / back direction, and left / right direction) are not intended to define the direction in which the chip resistor 10 is used, but are merely included to make the explanation easier to understand and do not have any actual meaning. In this disclosure, viewing along the up / down direction is called a plan view, viewing along the front / back direction is called a front view, and viewing along the left / right direction is called a side view. In the embodiments, the up / down direction, front / back direction, and left / right direction are perpendicular to each other.

[0009] On the surface of the ceramic substrate 1 of the chip resistor 10 on which the resistor 5 is placed, a coating 3, which is a sintered body of ceramic particles (B), is placed for purposes such as improving the smoothness of the ceramic substrate 1. According to the inventor's research, when the coating 3 is placed over the entire surface on which the coating 3 is placed, chipping or peeling of the coating 3 occurs near the edge of the ceramic substrate 1, and as a result, this chipping or peeling of the coating 3 can cause damage to the electrodes 4 of the chip resistor 10. Therefore, as a result of diligent research and development, the inventor has invented a chip resistor 10 that is less prone to damage to the electrodes 4.

[0010] The chip resistor 10 according to this embodiment comprises a ceramic substrate 1, a first electrode 41 and a second electrode 42 arranged on the ceramic substrate 1, and a resistor 5 that electrically connects the first electrode 41 and the second electrode 42. The ceramic substrate 1 has a support surface 8. The ceramic substrate 1 comprises a base material 2 which is a sintered body of ceramic particles (A), and a covering 3 which is a sintered body of ceramic particles (B) that covers a part of the base material 2 on the support surface 8. The support surface 8 has a covering portion 81 on which the covering 3 is arranged, and a margin portion 82 on which the covering 3 is not arranged. The margin portion 82 has a first margin portion 821 and a second margin portion 822. The first margin portion 821 and the second margin portion 822 are each arranged on the support surface 8, at both ends in one direction along the support surface 8, sandwiching the covering portion 81. The first electrode 41 is arranged on the support surface 8 so as to cover the first margin portion 821. The second electrode 42 is positioned on the support surface 8 so as to cover the second margin portion 822. At least a portion of the covering portion 81 is positioned in the region on the support surface 8 sandwiched between the first electrode 41 and the second electrode 42, while the first margin portion 821 and the second margin portion 822 are not positioned there. The resistor 5 is positioned to cover the region and is electrically connected to the first electrode 41 and the second electrode 42. In this embodiment, when the support surface 8 has a margin portion 82 where the covering 3 is not positioned, the covering 3 is not positioned at both ends in one direction along the support surface 8. Therefore, chipping or peeling of the covering 3 is less likely to occur near both ends in one direction along the support surface 8, and thus damage to the first electrode 41 and the second electrode 42 of the chip resistor 10 can be suppressed.

[0011] 2. The chip resistor 10 in the detailed embodiment will be described with reference to the drawings.

[0012] 2.1 The specific components of the chip resistor 10 according to the configuration embodiment will be described.

[0013] (Ceramic Substrate) The chip resistor 10 comprises a ceramic substrate 1. The ceramic substrate 1 has a support surface 8, a main surface 12 opposite to the support surface 8, and two side surfaces 13 and 14 connecting the support surface 8 and the main surface 12. The support surface 8 and the main surface 12 are surfaces visible when the chip resistor 10 is viewed from above, and they face each other in the direction along the vertical direction. The two side surfaces 13 and 14 are surfaces visible when the chip resistor 10 is viewed from the side, and they face each other in the direction along the horizontal direction. The shape of the ceramic substrate 1 is rectangular when the chip resistor 10 is viewed from above. The thickness of the ceramic substrate 1 is, for example, 100 μm or more and 600 μm or less. As already mentioned, the ceramic substrate 1 has a support surface 8. The support surface 8 has a covering portion 81 on which the covering 3 is placed, and a margin portion 82 on which the covering 3 is not placed. The surface roughness of the coated portion 81 is smaller than the surface roughness of the coated portion 81 when it is not coated by the coating 3. That is, the surface roughness of the coated portion 81 is smaller than the surface roughness of the base material 2 in the portion coated by the coating 3. In this embodiment, the margin portion 82 has a first margin portion 821 and a second margin portion 822 at both ends in the left-right direction along the support surface 8. Each of the first margin portion 821 and the second margin portion 822 has a constant width in the left-right direction and extends in the front-back direction. The minimum left-right length of each of the first margin portion 821 and the second margin portion 822 is 30 μm. On the other hand, the maximum left-right length of each of the first margin portion 821 and the second margin portion 822 varies depending on the size of the chip resistor 10, and is preferably the value obtained by subtracting 30 μm from the left-right lengths of the first electrode 41 and the second electrode 42, respectively. In this case, electrode defects in the chip resistor 10 can be suppressed. Preferably, the length of the first margin portion 821 in the left-right direction and the length of the second margin portion 822 in the left-right direction are the same. Furthermore, in this embodiment, the margin portion 82 has a third margin portion 823 and a fourth margin portion 824 at both ends in the front-rear direction along the support surface 8. Each of the third margin portion 823 and the fourth margin portion 824 has a certain width in the front-rear direction and extends in the left-right direction. The minimum value of the front-rear length of each of the third margin portion 823 and the fourth margin portion 824 is 30 μm.In this case, defects such as damage to the protective film 6 are suppressed, thereby increasing the reliability of the chip resistor 10. The first margin portion 821 and the second margin portion 822 are each positioned on the support surface 8, at both ends in the left-right direction along the support surface 8, so as to sandwich the covering portion 81. The third margin portion 823 and the fourth margin portion 824 are each positioned on the support surface 8, at both ends in the front-rear direction along the support surface 8, so as to sandwich the covering portion 81. In other words, the margin portions 82 are positioned along the outer circumference of the support surface 8, surrounding the covering 3. To put it another way, the area enclosed by the first margin portion 821, the second margin portion 822, the third margin portion 823, and the fourth margin portion 824 is the covering portion 81, and the covering 3 is positioned on this covering portion 81.

[0014] Further explanation will be given regarding the specific components of the ceramic substrate 1. The ceramic substrate 1 comprises a base material 2. The base material 2 is a sintered body of ceramic particles (A). The ceramic particles (A) include, for example, at least one selected from the group consisting of alumina particles and aluminum nitride particles. It is preferable that the ceramic particles (A) include alumina particles. In other words, it is preferable that the base material 2 is an alumina sintered body substrate. It is preferable that the content of alumina particles in the total ceramic particles (A) is 96% by mass or more. In other words, it is preferable that the content of the sintered body of alumina particles in the total base material 2 is 96% by mass or more. In this case, the thermal conductivity of the ceramic substrate 1 can be improved. This also improves the thermal conductivity of the chip resistor 10. The upper limit of the content of alumina particles in the total ceramic particles (A) is, for example, 100% by mass.

[0015] In this embodiment, each of the end faces 21 on the first margin portion 821 side and 22 on the second margin portion 822 side of the base material 2 is on the support surface 8 side and has tapered portions 211 and 221 that inclin inward as they face the support surface 8 side. In other words, each of the two end faces 21 and 22 in the left-right direction is bent and each is composed of two surfaces. The tapered portion 211 is bent toward the end face 22 of the base material 2. The tapered portion 221 is bent toward the end face 21 of the base material 2. In this embodiment, each of the end faces 23 on the third margin portion 823 side and 24 on the fourth margin portion 824 side of the base material 2 is on the support surface 8 side and has tapered portions 223 and 224 that inclin inward as they face the support surface 8 side. In other words, each of the two end faces 23 and 24 in the front-rear direction is bent and each is composed of two surfaces. The tapered portion 223 is bent toward the end face 24 of the base material 2. The tapered portion 224 is bent toward the end face 23 of the base material 2.

[0016] The ceramic substrate 1 has a covering 3. The covering 3 covers a portion of the base material 2 on the support surface 8. The covering 3 may be a continuous surface or a discontinuous surface. The thickness of the covering 3 is, for example, 1 μm or more and 30 μm or less. As already mentioned, the surface roughness of the covering portion 81 is smaller than the surface roughness of the covering portion 81 when it is not covered by the covering 3. In other words, the surface of the base material 2 may have minute irregularities, but the covering 3 covers the surface of the base material 2 in a way that fills these irregularities, thereby increasing the smoothness of the surface of the ceramic substrate 1. This increases the electrostatic discharge (ESD) resistance of the chip resistor 10. To explain in more detail, the surface of the base material 2 may have minute irregularities, such as recesses with intricate shapes on the inner side or protrusions with shapes that protrude from the surface. As a result, the surface smoothness of the base material 2 may not be sufficiently obtained, and as a result, the ESD resistance of the chip resistor 10 may not be sufficiently ensured. In contrast, in this embodiment, a coating 3, which is a sintered body of ceramic particles (B), is placed on the support surface 8 of the base material 2. As a result, the surface of the ceramic substrate 1 can be smoothed because the irregularities on the surface of the base material 2 are covered by the coating 3. Consequently, the ESD resistance of the chip resistor 10 can be sufficiently ensured.

[0017] The coating 3 is a sintered body of ceramic particles (B). Ceramic particles (B) include, for example, alumina particles, boehmite (AlOOH), zirconium oxide (ZrO). ２ ), silicon dioxide (SiO ２ It includes at least one selected from the group consisting of ), magnesium oxide (MgO), calcium oxide (CaO), and aluminum nitride (AlN). Among these, alumina particles are preferred. Examples of alumina particles include α-alumina particles, β-alumina particles, and γ-alumina particles, but among these, α-alumina particles are particularly preferred. In this case, the ESD resistance of the chip resistor 10 tends to increase. Furthermore, it is preferable that the ceramic particles (B) contain both alumina particles and boehmite. In this case, the boehmite can improve the sinterability of the alumina particles, thus further increasing the ESD resistance of the chip resistor 10.

[0018] It is preferable that the average particle diameter of ceramic particles (B) is smaller than the average particle diameter of ceramic particles (A). In this case, even if the shape of the minute irregularities on the substrate 2 has an intricate shape on the inner side, the coating 3 can be positioned so as to sufficiently fill the irregularities. This makes it less likely for gaps to form between the substrate 2 and the coating 3. This further improves the ESD resistance of the chip resistor 10. The average particle diameter of ceramic particles (A) is, for example, 0.5 μm or more and 8.0 μm or less. The average particle diameter of ceramic particles (B) is, for example, 30 nm or more and 1000 nm or less. The ratio of the average particle diameter of ceramic particles (B) to the average particle diameter of ceramic particles (A) is, for example, 1 / 3 or less. If the relationship between the average particle diameter of ceramic particles (A), the average particle diameter of ceramic particles (B), or their ratio is within the above range, the ESD resistance of the chip resistor 10 can be further improved. Furthermore, it is preferable that the maximum particle size of the ceramic particles (B) is 1500 nm or less. In this case, the thermal conductivity and smoothness of the ceramic substrate 1 can be further improved. As a result, the thermal conductivity and ESD resistance of the chip resistor 10 can be further improved.

[0019] (Electrodes) The chip resistor 10 is equipped with electrodes 4. In this embodiment, the chip resistor 10 is equipped with a first electrode 41 and a second electrode 42 arranged on a ceramic substrate 1. The first electrode 41 is positioned on the support surface 8 so as to cover the first margin portion 821. The second electrode 42 is positioned on the support surface 8 so as to cover the second margin portion 822. At least a portion of the covering portion 81 is positioned in the area between the first electrode 41 and the second electrode 42 on the support surface 8, and the first margin portion 821 and the second margin portion 822 are not positioned in that area. In other words, when the chip resistor 10 is viewed from above, the first electrode 41 is positioned so as to straddle the boundary between the covering portion 81 and the first margin portion 821. When the chip resistor 10 is viewed from above, the second electrode 42 is positioned so as to straddle the boundary between the covering portion 81 and the second margin portion 822.

[0020] Each of the first electrode 41 and the second electrode 42 is composed of multiple electrodes. In this embodiment, the first electrode 41 has a first surface electrode 411, a first resurface electrode 416, a first back surface electrode 412, a first end surface electrode 413, a first intermediate electrode 414, and a first external electrode 415. The second electrode 42 has a second surface electrode 421, a second resurface electrode 426, a second back surface electrode 422, a second end surface electrode 423, a second intermediate electrode 424, and a second external electrode 425.

[0021] Each of the first surface electrode 411 and the second surface electrode 421 is positioned on the support surface 8 of the ceramic substrate 1 and is electrically connected to the resistor 5. Each of the first surface electrode 411 and the second surface electrode 421 may be in contact with a location on the ceramic substrate 1 other than the support surface 8. For example, each of the first surface electrode 411 and the second surface electrode 421 may be in direct contact with a portion of the left and right end faces 21 and 22 of the base material 2. Each of the first surface electrode 411 and the second surface electrode 421 may be composed of a metal, a metal alloy, or a resin composition containing a metal. In this embodiment, each of the first surface electrode 411 and the second surface electrode 421 is composed of an Au-based alloy. Each of the first surface electrode 411 and the second surface electrode 421 can be formed from a thin-film conductor obtained by a thin-film process. When the first surface electrode 411 is said to be positioned on the support surface 8, it means that the first surface electrode 411 is positioned so as to be in direct contact with the support surface 8, or that the first surface electrode 411 is positioned on the support surface 8 via an element different from the first surface electrode 411. When the second surface electrode 421 is said to be positioned on the support surface 8, it means that the second surface electrode 421 is positioned so as to be in direct contact with the support surface 8, or that the second surface electrode 421 is positioned on the support surface 8 via an element different from the second surface electrode 421.

[0022] Each of the first surface electrode 416 and the second surface electrode 426 is positioned on the first surface electrode 411 and the second surface electrode 421, respectively. Each of the first surface electrode 416 and the second surface electrode 426 may be composed of a metal, a metal alloy, or a resin composition containing a metal. In this embodiment, each of the first surface electrode 416 and the second surface electrode 426 is composed of a conductive paste containing resin and Ag.

[0023] Each of the first back electrode 412 and the second back electrode 422 is positioned on the main surface 12 of the ceramic substrate 1. Each of the first back electrode 412 and the second back electrode 422 may be composed of a metal, a metal alloy, or a resin composition containing a metal. In the embodiment, each of the first back electrode 412 and the second back electrode 422 is composed of a conductive paste containing resin and Ag. When the first back electrode 412 is positioned on the main surface 12, it means that the first back electrode 412 is positioned so as to be in direct contact with the main surface 12, or that the first back electrode 412 is positioned on the main surface 12 via an element different from the first back electrode 412. When the second back electrode 422 is positioned on the main surface 12, it means that the second back electrode 422 is positioned so as to be in direct contact with the main surface 12, or that the second back electrode 422 is positioned on the main surface 12 via an element different from the second back electrode 422.

[0024] The first end electrode 413 is in contact with a portion of the first surface electrode 411, a portion of the first resurface electrode 416, and a portion of the first back electrode 412. The second end electrode 423 is in contact with a portion of the second surface electrode 421, a portion of the second resurface electrode 426, and a portion of the second back electrode 422. Each of the first end electrode 413 and the second end electrode 423 may be made of metal, a metal alloy, or a resin composition containing metal. In this embodiment, each of the first end electrode 413 and the second end electrode 423 is made of a conductive paste containing resin and Ag. Note that when we say that the first end electrode 413 is positioned on the side surface 13, we mean that the first end electrode 413 is positioned so as to be in direct contact with the side surface 13, or that the first end electrode 413 is positioned on the side surface 13 via an element different from the first end electrode 413. The arrangement of the second end face electrode 423 on the side surface 13 means that the second end face electrode 423 is arranged so as to be in direct contact with the side surface 14, or that the second end face electrode 423 is arranged on the side surface 14 via an element different from the second end face electrode 423. The end face 21 on the first margin portion 821 side and the end face 22 on the second margin portion 822 side of the base material 2 are the portion on the support surface 8 side and have a tapered portion 211 that slopes inward as it approaches the support surface 8 side. However, there is no gap between the first end face electrode 413 and the second end face electrode 423 and the base material 2, and the first end face electrode 413 and the second end face electrode 423 are arranged on the side surfaces 13 and 14 of the ceramic substrate 1, respectively.

[0025] The first intermediate electrode 414 covers the first surface electrode 411, the first resurface electrode 416, the first back surface electrode 412, and the first end surface electrode 413, and also covers a portion of the protective film 6. The second intermediate electrode 424 covers the second surface electrode 421, the second resurface electrode 426, the second back surface electrode 422, and the second end surface electrode 423, and also covers a portion of the protective film 6. Each of the first intermediate electrode 414 and the second intermediate electrode 424 is made of Ni plating.

[0026] The first external electrode 415 covers the first intermediate electrode 414. The second external electrode 425 covers the second intermediate electrode 424. Both the first external electrode 415 and the second external electrode 425 are made of Sn plating.

[0027] (Resistor) The chip resistor 10 includes a resistor 5 that electrically connects the first electrode 41 and the second electrode 42. More specifically, the resistor 5 is positioned to cover the area on the support surface 8 sandwiched between the first electrode 41 and the second electrode 42, and is electrically connected to the first electrode 41 and the second electrode 42. The resistor 5 is positioned on the support surface 8 of the ceramic substrate 1. More specifically, a covering portion 81 is positioned on the support surface 8, and the resistor 5 is positioned on the covering 3 positioned on the covering portion 81. The resistor 5 may have elements other than the first electrode 41 and the second surface electrode 421 and the resistor 5 interposed between the first electrode 41 and the second electrode 42 and the resistor 5, provided that the advantages of the enhanced smoothness of the support surface 8 are not impaired, but it is preferable that the first electrode 41 and the second electrode 42 and the resistor 5 are in direct contact. In this embodiment, a part of the resistor 5 is in direct contact with the first surface electrode 411 and the second surface electrode 421, overlapping with them. The thickness of the resistor 5 is, for example, 10 nm to 1000 nm. The resistor 5 may be made of a metal or a metal alloy. In this embodiment, the resistor 5 is made of a NiCr alloy. The resistor 5 can be formed from a thin film conductor obtained by a thin film process.

[0028] (Protective film) In this embodiment, the chip resistor 10 further comprises a protective film 6 that covers a portion of the first electrode 41, a portion of the second electrode 42, and the resistor 5. The protective film 6 can be formed from an epoxy resin composition containing, for example, an epoxy resin, an inorganic filler, and a pigment.

[0029] (Inorganic protective film) In this embodiment, the chip resistor 10 further comprises an inorganic protective film 7 interposed between the resistor 5 and the protective film 6. The inorganic protective film 7 is composed of a metal oxide. The metal oxide is, for example, magnesium oxide (MgO) or aluminum oxide (Al ２ O ３ ), silicon dioxide (SiO ２ ), nickel oxide (Ni ３ O ４ ) and zirconium oxide (ZrO ２It contains at least one selected from the group consisting of ) etc.

[0030] 2.2 Manufacturing Method A method for manufacturing a chip resistor 10 according to an embodiment will be described. The method for manufacturing a chip resistor 10 includes preparing a large substrate 200 which is a sintered body of ceramic particles (A) and has a main surface 203 on which a plurality of substrate forming parts 20 arranged in a matrix are provided, forming a coating part 81 and a margin part 82 by placing a coating 3 which is a sintered body of ceramic particles (A) on each of the substrate forming parts 20 on the main surface 203 of the large substrate 200, manufacturing a first electrode 41, a second electrode 42 and a resistor 5 on each of the substrate forming parts 20, and cutting the large substrate 200 at the boundary between the substrate forming parts 20. Note that the first electrode 41 of one substrate forming part 20 and the second electrode 42 of the other substrate forming part 20 are connected in the direction in which the first electrode 41 and the second electrode 42 are aligned. Then, when the large substrate 200 is divided, the first electrode 41 of one substrate forming section 20 and the second electrode 42 of the other substrate forming section 20 are separated.

[0031] A detailed explanation will be given regarding the manufacturing method of the chip resistor 10 according to this embodiment.

[0032] First, a large base material 200 is prepared. The large base material 200 is made from the material of the base material 2, and multiple base materials 2 are made from the large base material 200. The large base material 200 has one main surface 203. The main surface 203 is the surface of the large base material 200 on which the covering 3 is placed. The large base material 200 has multiple base material forming sections 20 arranged in a matrix. In other words, the base material forming sections 20 are arranged in a matrix to constitute the main surface 203 of the large base material 200. The base material forming section 20 is a design region corresponding to the support surface 8 in the ceramic substrate 1 which has base materials 2 made from the large base material 200.

[0033] Furthermore, the large substrate 200 has a dividing groove 201 that opens to the main surface 203 and extends in a direction perpendicular to the direction in which the first electrode 41 and the second electrode 42 are aligned, at the boundary between the substrate forming portions 20 in a direction perpendicular to the direction in which the first electrode 41 and the second electrode 42 are aligned. The shape of the dividing groove 201, when viewed from a direction perpendicular to the direction in which the first electrode 41 and the second electrode 42 are aligned, is wedge-shaped so that the large substrate 200 can be easily cut with the dividing groove 201 as the boundary (see Figure 4). In addition, the large substrate 200 has a dividing groove 202 that opens to the main surface 203 and extends in a direction perpendicular to the direction in which the first electrode 41 and the second electrode 42 are aligned, at the boundary between the substrate forming portions 20 in a direction perpendicular to the direction in which the first electrode 41 and the second electrode 42 are aligned. When viewed from the direction in which the first electrode 41 and the second electrode 42 of the dividing groove 202 are aligned, the shape is wedge-shaped, so that the large base material 200 can be easily cut with the dividing groove 202 as the boundary.

[0034] Next, on the main surface 203 of the large substrate 200, a coating 3, which is a sintered body of ceramic particles (B), is placed on each of the substrate forming parts 20 to form a coating part 81 and a margin part 82 (see Figures 3 and 4). A mask 300 is placed so as to overlap the upper and lower sides of the large substrate 200. The mask 300 has open openings 301 and closed non-opening parts 302. The shape of the openings 301 is rectangular. Multiple openings 301 are spaced apart along the front-to-back and left-to-right directions, that is, arranged in a matrix. By applying a coating liquid containing ceramic particles (B) (hereinafter also referred to as coating liquid (X)) through such a mask 300 with multiple openings 301 arranged in a matrix, the coating liquid (X) can be applied to the parts of the large substrate 200 that overlap with the openings 301 in the vertical direction, that is, on the substrate forming parts 20. Then, after the applied coating liquid (X) is dried and then fired, the coatings 3 can be placed on each of the substrate forming parts 20. The method of applying the coating liquid (X) onto the large substrate 200 via the mask 300 is not particularly limited, but examples include application using a squeegee and application by printing. Application by printing includes, for example, screen printing. Furthermore, from the viewpoint of easily demonstrating the effects of the obtained chip resistor 10 embodiment, it is preferable that the coatings 3 are not placed in the dividing grooves 201 and 202. For this reason, the mask 300 is positioned so that the opening 301 of the mask 300 and the dividing grooves 201 and 202 of the large substrate 200 do not overlap in the vertical direction.

[0035] Furthermore, a margin portion 82 is formed at this time, for example, by setting the minimum length in the left-right direction of the first margin portion 821 and the second margin portion 822 to 30 μm, or by setting the maximum length in the left-right direction of the first margin portion 821 and the second margin portion 822 to the value obtained by subtracting 30 μm from the left-right lengths of the first electrode 41 and the second electrode 42, and then applying the coating liquid (X) onto the large substrate 200. In this way, even without increasing the precision of the alignment between the mask 300 and the large substrate 200, the coating 3 of the manufactured chip resistor 10 is less likely to be placed at the left-right edges of the support surface 8. This can suppress electrode defects in the manufactured chip resistor 10.

[0036] Furthermore, the coating liquid (X) can be applied to the large substrate 200 such that the minimum length of the third margin portion 823 and the fourth margin portion 824 in the front-to-back direction is 30 μm. In this way, even without increasing the precision of the alignment between the mask 300 and the large substrate 200, the coating 3 on the manufactured chip resistor 10 is less likely to be positioned at the front-to-back ends of the support surface 8. As a result, defects in the protective film 6 on the manufactured chip resistor 10 are suppressed, and the reliability of the chip resistor 10 is increased.

[0037] Next, the first electrode 41, the second electrode 42, and the resistor 5 are fabricated on each of the substrate forming sections 20. In this embodiment, in addition to the first electrode 41, the second electrode 42, and the resistor 5, a protective film 6 and an inorganic protective film 7 are further fabricated on each of the substrate forming sections 20.

[0038] First, the first surface electrode 411 and the second surface electrode 421 are formed on the main surface 203 of the large substrate 200. Specifically, a thin film conductor containing an Au-based alloy is formed on each of the substrate forming portions 20 of the large substrate 200 by a thin film process such as sputtering. Then, by removing the unnecessary portion of the thin film conductor by a photolithography process, the first surface electrode 411 and the second surface electrode 421 can be formed on each of the substrate forming portions 20. Once the first surface electrode 411 and the second surface electrode 421 are formed in this way, when the large substrate 200 is viewed from above, the first surface electrode 411 and the second surface electrode 421 can be positioned on each of the substrate forming portions 20 so that each of the coverings 3 is sandwiched between the first surface electrode 411 and the second surface electrode 421. When the large substrate 200 is divided into divided pieces 101, the first electrode 41 of one substrate forming section 20 and the second electrode 42 of the other substrate forming section 20 are formed in such a way that they are separated in the direction in which the first electrode 41 and the second electrode 42 are aligned. Therefore, the first surface electrode 411 of one substrate forming section 20 and the second surface electrode 421 of the other substrate forming section 20 are separated simultaneously when the large substrate 200 is divided.

[0039] Next, resistors 5 are formed on the main surface 203 of the large substrate 200. Specifically, thin film conductors containing a NiCr alloy are formed on each of the coverings 3 by a thin-film process such as sputtering. Then, the resistors 5 can be formed by removing the unnecessary parts of the thin film conductors by a photolithography process. Once the resistors 5 are formed in this way, when the large substrate 200 is viewed from above, the resistors 5 can be arranged on each of the coverings 3 such that each resistor 5 is interposed between the first surface electrode 411 and the second surface electrode 421 in the left-right direction.

[0040] Next, an inorganic protective film 7 is formed to protect the resistors 5. The inorganic protective film 7 can be formed by sputtering metal oxide onto the resistors 5, which are placed on each of the substrate forming sections 20, thereby depositing the metal oxide onto the resistors 5. Once the inorganic protective film 7 is formed in this way, it can be placed on each of the resistors 5.

[0041] Subsequently, first re-surface electrodes 416 and second re-surface electrodes 426 are formed on each of the first surface electrode 411 and the second surface electrode 421. Specifically, a conductive paste containing resin and Ag is applied so as to cover a part of each of the first surface electrode 411 and the second surface electrode 421. Then, by heating and curing this, the first re-surface electrodes 416 and the second re-surface electrodes 426 can be respectively formed on each of the first surface electrode 411 and the second surface electrode 421. By forming the first re-surface electrodes 416 and the second re-surface electrodes 426 in this way, when the large-sized substrate 200 is viewed in plan view, each of the resistors 5 in the left-right direction can be arranged on each of the first surface electrode 411 and the second surface electrode 421 in such a manner that they are sandwiched by the first re-surface electrodes 416 and the second re-surface electrodes 426. When the large-sized substrate 200 is divided into the divided pieces 101, at the same time, the first electrode 41 of one substrate forming portion 20 and the second electrode 42 of the other substrate forming portion 20 adjacent to each other in the direction in which the first electrode 41 and the second electrode 42 are arranged are formed so as to be divided. Therefore, the first re-surface electrode 416 of one substrate forming portion 20 and the second re-surface electrode 426 of the other substrate forming portion 20 adjacent to each other in the direction in which the first electrode 41 and the second electrode 42 are arranged are divided at the same time when the large-sized substrate 200 is divided.

[0042] Subsequently, a first back electrode 412 and a second back electrode 422 are formed on the surface of the large-sized substrate 200 opposite to the main surface 203. A conductive paste containing resin and Ag is applied to the surface of the large-sized substrate 200 opposite to the main surface 203. Then, by heating and curing this, the first back electrode 412 and the second back electrode 422 can be formed. By forming the first back electrode 412 and the second back electrode 422 in this way, when the large-sized substrate 200 is viewed in plan view, each of the resistors 5 in the left-right direction is interposed between the first back electrode 412 and the second back electrode 422, and the first back electrode 412 and the second back electrode 422 can be arranged on the surface of the large-sized substrate 200 opposite to the main surface 203. When the large-sized substrate 200 is divided into divided pieces 101, simultaneously, the first electrode 41 of one substrate forming portion 20 and the second electrode 42 of the adjacent substrate forming portion 20 adjacent in the direction in which the first electrode 41 and the second electrode 42 are aligned are formed so as to be divided. Therefore, the first back electrode 412 of one substrate forming portion 20 and the second back electrode 422 of the other substrate forming portion 20 of the substrate forming portions 20 adjacent in the direction in which the first electrode 41 and the second electrode 42 are aligned are divided simultaneously when the large-sized substrate 200 is divided.

[0043] Then, a protective film 6 is formed on the inorganic protective film 7. The protective film 6 can be formed by applying an epoxy resin composition on the inorganic protective film 7 and heating and curing this. By forming the protective film 6 in this way, the protective film 6 can be arranged on each of the inorganic protective films 7.

[0044] Subsequently, the large-sized substrate 200 is cut along the direction along the front-back direction among the boundaries between the substrate forming portions 20 (see FIG. 5). As already described, in the embodiment, the large-sized substrate 200 has a dividing groove 201 along the front-back direction. By dividing the large-sized substrate 200 into strip shapes along the dividing groove 201, the divided pieces 101 can be produced. The shape of the dividing groove 201 of the large-sized substrate 200 when viewed from the front-back direction is a wedge shape, and if the large-sized substrate 200 is bent with the dividing groove 201 as a boundary, the large-sized substrate 200 can be easily cut.

[0045] The divided piece 101 has components added in a step prior to the formation of the divided piece 101 (see Figure 6). That is, the divided piece 101 has a plurality of base material forming sections 20 arranged in the front-to-back direction. The divided piece 101 has a covering 3 on each of the base material forming sections 20. The divided piece 101 has a first surface electrode 411 and a second surface electrode 421 on each of the base material forming sections 20. The first surface electrode 411 and the second surface electrode 421 are arranged to cover a part of the covering 3 and to cover the left-right end of one surface of the divided piece 101 where the covering 3 is not placed. The divided piece 101 has a resistor 5 on each of the base material forming sections 20. The resistor 5 is placed on the covering 3. The divided piece 101 has an inorganic protective film 7 on each of the base material forming sections 20. The inorganic protective film 7 is placed on the resistor 5. Each divided piece 101 is provided with a first surface electrode 416 and a second surface electrode 426 on each of the base material forming portions 20. Each of the first surface electrode 416 and the second surface electrode 426 is positioned on the first surface electrode 411 and the second surface electrode 421, respectively. Each divided piece 101 is provided with a protective film 6 on each of the base material forming portions 20. The protective film 6 is positioned on a part of the second surface electrode 421 and on the inorganic protective film 7. On the side of the divided piece 101 opposite to the side on which the covering 3 is positioned, a first back surface electrode 412 and a second back surface electrode 422 are provided. A divided piece 101 having such a configuration can be manufactured.

[0046] Next, a first end face electrode 431 and a second end face electrode 432 are formed on the divided piece 101. A conductive paste containing resin and Ag is applied to each of the left and right side surfaces 131 and 141 of the divided piece 101. Then, by heating and curing this paste, the first end face electrode 431 and the second end face electrode 432 can be formed on each of the side surfaces 131 and 141, respectively. Once the first end face electrode 431 and the second end face electrode 432 are formed in this way, the first end face electrode 431 and the second end face electrode 432 can be positioned on each of the left and right side surfaces 131 and 141 of the divided piece 101, respectively.

[0047] Next, the divided piece 101 is cut along the left-right direction of the boundary between the base material forming sections 20 (see Figure 7). As already mentioned, in this embodiment, the large base material 200 has a dividing groove 202 that runs along the left-right direction. The divided piece 102 can be produced by dividing the divided piece 101 into smaller pieces along the dividing groove 202. When viewed from the left-right direction, the dividing groove 202 of the large base material 200 has a wedge shape, and the large base material 200 can be easily cut by bending it along the dividing groove 202.

[0048] The divided piece 102 according to this embodiment includes a configuration added in a step prior to the formation of the divided piece 102 (see Figure 8). The divided piece 102 comprises a base material 2. The divided piece 102 comprises a covering 3 on the base material 2. The divided piece 102 comprises a first surface electrode 411 and a second surface electrode 421 on the base material 2. The first surface electrode 411 and the second surface electrode 421 are arranged to cover a part of the covering 3 and to cover the left and right ends of one surface of the divided piece 102 where the covering 3 is not placed. The divided piece 102 comprises a resistor 5 on the base material 2. The resistor 5 is placed on the covering 3. The divided piece 102 comprises an inorganic protective film 7 on the base material 2. The inorganic protective film 7 is placed on the resistor 5. The divided piece 102 comprises a first resurface electrode 416 and a second resurface electrode 426 on the base material 2. The first surface electrode 416 and the second surface electrode 426 are each positioned on the first surface electrode 411 and the second surface electrode 421, respectively. The segmented piece 102 has a protective film 6 on the substrate 2. The protective film 6 is positioned on a part of the second surface electrode 421 and on the inorganic protective film 7. The segmented piece 102 has a first back surface electrode 412 and a second back surface electrode 422 on the side opposite to the side on which the covering 3 is positioned. The segmented piece 102 has a first end surface electrode 413 and a second end surface electrode 423 on each of its sides 132 and 142, respectively. A segmented piece 102 having such a configuration can be manufactured.

[0049] Next, a first intermediate electrode 414 and a second intermediate electrode 424 are formed on the divided piece 102. Ni plating is applied to each of the side surfaces 132 and 142 of the divided piece 102. This allows the first intermediate electrode 414 and the second intermediate electrode 424 to be formed on each of the side surfaces 132 and 142, respectively. Then, a first external electrode 415 and a second external electrode 425 are formed on the divided piece 102. Sn plating is applied to each of the side surfaces 132 and 142 of the divided piece 102. This allows the first external electrode 415 and the second external electrode 425 to be formed on each of the side surfaces 132 and 142, respectively.

[0050] By following the procedure described above, the chip resistor 10 according to the embodiment can be manufactured. Note that the method described above is merely one example of a method for manufacturing the chip resistor 10 according to the embodiment, and any other method may be used.

[0051] 2.3 Summary A chip resistor 10 and its manufacturing method according to an embodiment have been described. In this embodiment, when the support surface 8 has a margin portion 82 where the covering material 3 is not placed, the covering material 3 is not placed at both ends in one direction along the support surface 8. In other words, when the large base material 200 is cut and divided, the covering material 3 is not placed at the cutting location, so when dividing, chipping or peeling of the covering material 3 is less likely to occur near both ends in one direction along the support surface 8, thereby suppressing damage to the first electrode 41 and the second electrode 42 in the chip resistor 10. Note that if the support surface 8 has a margin portion 82 where the covering material 3 is not placed, the end faces 21 and 22 of the base material 2 used in the chip resistor 10 do not need to have tapered portions 211 and 221, respectively (see Figure 9). Also, when manufacturing such a chip resistor 10, the large base material 200 does not need to be provided with a dividing groove 201 or a dividing groove 202. When dividing a large substrate 200 that does not have a dividing groove 201 or a dividing groove 202 into divided pieces 101, or when dividing a divided piece 101 into divided pieces 102, a dicing method using a dicing saw or the like can be applied. Furthermore, in the embodiment, the margin portion 82 had a third margin portion 823 and a fourth margin portion 824, but the margin portion 82 does not have to have a third margin portion 823 and a fourth margin portion 824. In this case, the covering material 3 is placed at both ends in the front-rear direction along the support surface 8. However, the covering material 3 is not placed at both ends in the left-right direction along the support surface 8. Therefore, chipping or peeling of the covering material 3 near both ends in the left-right direction along the support surface 8 can be sufficiently suppressed, and thus damage to the first electrode 41 and the second electrode 42 of the chip resistor 10 can be suppressed.

[0052] 3. Embodiments As is clear from the embodiments described above, this disclosure includes the following embodiments. Hereafter, reference numerals are enclosed in parentheses solely to indicate their correspondence with the embodiments.

[0053] A chip resistor (10) according to a first aspect of the present disclosure comprises a ceramic substrate (1), a first electrode (41) and a second electrode (42) disposed on the ceramic substrate (1), and a resistor (5) that electrically connects the first electrode (41) and the second electrode (42). The ceramic substrate (1) has a support surface (8). The ceramic substrate (1) comprises a base material (2) which is a sintered body of ceramic particles (A), and a covering (3) which is a sintered body of ceramic particles (B) that covers a part of the base material (2) on the support surface (8). The support surface (8) has a covering portion (81) on which the covering (3) is disposed, and a margin portion (82) on which the covering (3) is not disposed. The margin portion (82) has a first margin portion (821) and a second margin portion (822). The first margin portion (821) and the second margin portion (822) are each positioned on the support surface (8) at both ends in one direction along the support surface (8), sandwiching the covering portion (81). The first electrode (41) is positioned on the support surface (8) so as to cover the first margin portion (821). The second electrode (42) is positioned on the support surface (8) so as to cover the second margin portion (822). At least a portion of the covering portion (81) is positioned in the region on the support surface (8) sandwiched between the first electrode (41) and the second electrode (42), and the first margin portion (821) and the second margin portion (822) are not positioned in this region. The resistor (5) is positioned to cover the region and is electrically connected to the first electrode (41) and the second electrode (42).

[0054] In the first embodiment, the chip resistor (10) according to a second aspect of the present disclosure has a surface roughness of the coating portion (81) that is smaller than the surface roughness of the coating portion (81) when it is not covered with the coating material (3).

[0055] In the third aspect of the present disclosure, the chip resistor (10) is configured such that, in the first or second aspect, the average particle diameter of the ceramic particles (B) is smaller than the average particle diameter of the ceramic particles (A).

[0056] In a fourth aspect of the present disclosure, the chip resistor (10) is configured such that, in any one of the first to third embodiments, the margin portion (82) is arranged along the outer circumference of the support surface (8) and surrounds the covering (3).

[0057] A chip resistor (10) according to a fifth aspect of the present disclosure, in any one of the first to fourth aspects, has a tapered portion (211, 221) on the end face (21) on the first margin portion (821) side and a tapered portion (22) on the end face (22) on the second margin portion (822) side of the substrate (2), which is on the support surface (8) side and is inclined to be more inward towards the support surface (8) side.

[0058] A method for manufacturing a chip resistor (10) according to the sixth aspect of this disclosure is a method for manufacturing a chip resistor (10) according to any one of the first to fifth aspects, comprising: preparing a large substrate (200) having a main surface (203) provided with a plurality of substrate forming portions (20) arranged in a matrix, which is a sintered body of ceramic particles (A); forming a coating portion (81) and a margin portion (82) by arranging a coating (3) which is a sintered body of ceramic particles (A) on each of the substrate forming portions (20) on the main surface (203) of the large substrate (200); manufacturing a first electrode (41), a second electrode (42), and a resistor (5) on each of the substrate forming portions (20); and cutting the large substrate (200) at the boundary between the substrate forming portions (20).

[0059] A chip resistor (10) according to a seventh aspect of the present disclosure, in the sixth aspect, the large substrate (200) has a dividing groove (201) that opens to the main surface (203) and extends in a direction perpendicular to the direction in which the first electrode (41) and the second electrode (42) are aligned, at the boundary between the substrate forming portions (20) in a direction perpendicular to the direction in which the first electrode (41) and the second electrode (42) are aligned.

[0060] 1 Ceramic substrate 2 Base material 3 Covering material 5 Resistor 8 Support surface 10 Chip resistor 12 Main surface 21, 22 End surface 20 Base material forming part 41 First electrode 42 Second electrode 81 Covering part 82 Margin part 101 Divided piece 200 Large base material 201 Dividing groove 203 Main surface 211, 221 Tapered part 821 First margin part 822 Second margin part

Claims

1. The device comprises a ceramic substrate, a first electrode and a second electrode disposed on the ceramic substrate, and a resistor electrically connecting the first electrode and the second electrode, wherein the ceramic substrate has a support surface, the ceramic substrate comprises a base material which is a sintered body of ceramic particles (A), and a covering which is a sintered body of ceramic particles (B) and covers a part of the base material on the support surface, the support surface has a covering portion where the covering is disposed and a margin portion where the covering is not disposed, the margin portion has a first margin portion and a second margin portion, the first margin portion and the second margin portion are each disposed on the support surface at both ends in one direction along the support surface so as to sandwich the covering portion, the first electrode is disposed on the support surface so as to cover the first margin portion, the second electrode is disposed on the support surface so as to cover the second margin portion A chip resistor wherein at least a portion of the covering portion is disposed in the region sandwiched between the first electrode and the second electrode on the support surface, and the first margin portion and the second margin portion are not disposed therein, and the resistor is disposed to cover the region and is electrically connected to the first electrode and the second electrode.

2. The chip resistor according to claim 1, wherein the surface roughness of the coated portion is smaller than the surface roughness of the coated portion when it is not covered with the coating.

3. The chip resistor according to claim 1, wherein the average particle diameter of the ceramic particles (B) is smaller than the average particle diameter of the ceramic particles (A).

4. The chip resistor according to claim 1, wherein the margin portion is arranged along the outer circumference of the support surface so as to surround the covering.

5. The chip resistor according to claim 1, wherein each of the end faces of the substrate on the first margin side and the end face on the second margin side has a tapered portion that is on the support surface side and is inclined to be more inward towards the support surface side.

6. A method for manufacturing a chip resistor according to claim 1, comprising: preparing a large substrate having a main surface provided with a plurality of substrate forming portions arranged in a matrix, the main surface of which is a sintered body of ceramic particles (A); forming the coating portion and the margin portion by arranging the coating, which is a sintered body of ceramic particles (A), on each of the substrate forming portions on the main surface of the large substrate; manufacturing the first electrode, the second electrode, and the resistor on each of the substrate forming portions; and cutting the large substrate at the boundary between the substrate forming portions.

7. The method for manufacturing a chip resistor according to claim 6, wherein the large substrate has a division groove that opens to the main surface and is long in a direction perpendicular to the direction in which the first electrode and the second electrode are aligned, at the boundary between the substrate forming portions in a direction perpendicular to the direction in which the first electrode and the second electrode are aligned.

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