Light-emitting device and light-emitting module comprising same

Abstract

The present invention provides a light-emitting device comprising a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein: the active layer includes a multi-quantum well structure of alternately disposed well layers and barrier layers; the peak wavelength of an emission light emitted from the active layer is 620 nm to 640 nm; and the ratio of the peak wavelength to a thickness (nm) from a barrier layer adjacent to the second conductive semiconductor layer up to the second conductive semiconductor layer has a value between 3.4 and 3.8.

Description

Light-emitting element and light-emitting module including the same

[0001] The present invention relates to a light-emitting element and a light-emitting module including the same.

[0002] A light-emitting diode (LED) is a light-emitting device that emits light when current is applied. Recently, light-emitting diodes are being used in various fields such as display devices, automotive lamps, and general lighting. Furthermore, light-emitting diodes have the advantages of a long lifespan, low power consumption, and fast response speed. By fully utilizing these advantages, they are rapidly replacing existing light sources. For example, a display device using light-emitting diodes can be obtained by forming structures of red (Red, R), green (Green, G), and blue (Blue, B) light-emitting diodes (LEDs) that are individually grown on a final substrate.

[0003] Specifically, the light-emitting diode is formed by growing epitaxial layers on a substrate and includes an N-type semiconductor layer, a P-type semiconductor layer, and an active layer interposed between them. An N-electrode pad is formed on the N-type semiconductor layer and a P-electrode pad is formed on the P-type semiconductor layer, so that the light-emitting diode is electrically connected to an external power source through the electrode pads and driven. At this time, current can flow from the P-electrode pad through the semiconductor layers to the N-electrode pad, and light generated through the recombination of electrons and holes in the active layer can be emitted.

[0004] The purpose of the present invention is to provide a light-emitting element capable of emitting high-efficiency red light and a light-emitting module including the same.

[0005] The purpose of the present invention is to provide a light-emitting device that emits red light using a single InGaN-based material and a light-emitting module including the same.

[0006] The present invention aims to provide a light-emitting device suitable for a monolithic integrated structure that forms all red, green, and blue (RGB) pixels at the chip level, and a light-emitting module including the same, by implementing a red light-emitting device using the same substrate as the blue and green light-emitting devices using InGaN-based materials.

[0007] The purpose of the present invention is to provide a light-emitting element capable of realizing a high-quality white LED without a separate color conversion material or a complex chip transfer process through the monolithic integration described above, and a light-emitting module including the same.

[0008] The present invention aims to provide a light-emitting device in which lattice mismatch and resulting strain occurring in the active layer are relieved, and a light-emitting module including the same.

[0009] The present invention aims to provide a high-efficiency long-wavelength red light-emitting device with improved internal quantum efficiency (IQE) and external quantum efficiency (EQE) by relieving strain to suppress the generation of crystal defects, and a light-emitting module including the same.

[0010] The purpose of the present invention is to provide a light-emitting element having low efficiency droop even at high driving currents and high light output and high luminosity characteristics, and a light-emitting module including the same.

[0011] The purpose of the present invention is to provide a light-emitting element with excellent thermal stability and long-term reliability, and a light-emitting module including the same.

[0012] The present invention aims to provide a light-emitting device and a light-emitting module including the same, which can simplify the manufacturing process and reduce production costs by enabling all RGB pixels to be formed in a single epitaxial growth process.

[0013] One embodiment of the present invention discloses a light-emitting device comprising a first conductivity semiconductor layer, a second conductivity semiconductor layer, and an active layer disposed between the first conductivity semiconductor layer and the second conductivity semiconductor layer.

[0014] In one embodiment, the active layer may include a multiple quantum well structure of well layers and barrier layers arranged alternately.

[0015] In one embodiment, the difference between the In composition (%) of the well layer and the In composition (%) of the second conductivity semiconductor layer may be 20% or more.

[0016] In one embodiment, the second conductivity semiconductor layer may include a buffer line to relieve lattice stress with the well layer.

[0017] In one embodiment, the buffer line may extend from one side of the second conductivity semiconductor layer toward the other side, having a slope with respect to the thickness direction of the second conductivity semiconductor layer.

[0018] In one embodiment, the ratio of the peak wavelength to the thickness (nm) of the well layer may have a value between 135 and 256.

[0019] In one embodiment, the first conductivity type semiconductor layer may be a semiconductor layer doped with an n-type dopant, and the second conductivity type semiconductor layer may be a semiconductor layer doped with a p-type dopant.

[0020] In one embodiment, the light-emitting element may further include a pre-deformed layer disposed between the first conductive semiconductor layer and the active layer.

[0021] In one embodiment, the ratio of the peak wavelength to the thickness (nm) of the pre-deformed layer may have a value between 0.8 and 1.

[0022] In one embodiment, the pre-deformation layer may include a first pre-deformation layer comprising GaN disposed on one surface of the first conductive semiconductor layer, a second pre-deformation layer comprising InGaN disposed on one surface of the first pre-deformation layer, and a superlattice pre-deformation layer disposed on one surface of the second pre-deformation layer.

[0023] In one embodiment, the first pre-deformation layer may include a first-1 pre-deformation layer and a first-2 pre-deformation layer having a thinner thickness than the first-1 pre-deformation layer.

[0024] In one embodiment, the first pre-deformed layer may be Si-doped.

[0025] In one embodiment, the In composition of the second pre-deformed layer may have a value between 1% and 10%.

[0026] In one embodiment, the superlattice pre-deformation layer may include a plurality of pairs in which InGaN and GaN are alternately stacked.

[0027] In one embodiment, the In composition of the superlattice pre-deformation layer may be smaller than or equal to the In composition of the second pre-deformation layer.

[0028] In one embodiment, the active layer may further include a cap layer containing Al disposed between the well layer and the barrier layer.

[0029] In one embodiment, the cap layer may include a first cap layer comprising AlN disposed on one surface of the well layer and a second cap layer comprising AlGaN disposed on one surface of the first cap layer.

[0030] In one embodiment, the first conductivity semiconductor layer may include a first-1 conductivity semiconductor layer comprising GaN, a first-2 conductivity semiconductor layer disposed on one surface of the first-1 conductivity semiconductor layer comprising Al, and a first-3 conductivity semiconductor layer disposed on one surface of the first-2 conductivity semiconductor layer comprising GaN.

[0031] In one embodiment, the second conductivity type semiconductor layer may include a second-1 conductivity type semiconductor layer comprising GaN, a second-2 conductivity type semiconductor layer disposed on one surface of the second-1 conductivity type semiconductor layer comprising Al, and a second-3 conductivity type semiconductor layer disposed on one surface of the second-2 conductivity type semiconductor layer comprising GaN.

[0032] Another embodiment of the present invention discloses a light-emitting device comprising a first conductivity semiconductor layer, a second conductivity semiconductor layer, and an active layer disposed between the first conductivity semiconductor layer and the second conductivity semiconductor layer, wherein the active layer comprises a multiple quantum well structure of well layers and barrier layers disposed alternately, the main wavelength of the emitted light from the active layer is 610 nm to 630 nm, and the ratio of the main wavelength to the thickness (nm) from the barrier layer adjacent to the second conductivity semiconductor layer to the second conductivity semiconductor layer has a value between 3.4 and 3.8.

[0033] In one embodiment, the difference between the In composition (%) of the well layer and the In composition (%) of the second conductivity semiconductor layer may be 20% or more.

[0034] In one embodiment, the second conductivity semiconductor layer may include a buffer line to relieve lattice stress with the well layer.

[0035] The present invention can provide a light-emitting element capable of emitting high-efficiency red light and a light-emitting module including the same.

[0036] The present invention can provide a light-emitting device that emits red light using a single InGaN-based material and a light-emitting module including the same.

[0037] The present invention can provide a light-emitting device suitable for a monolithic integrated structure that forms all red, green, and blue (RGB) pixels at the chip level, and a light-emitting module including the same, by implementing a red light-emitting device using the same substrate as the blue and green light-emitting devices using InGaN-based materials.

[0038] The present invention can provide a light-emitting element capable of realizing a high-quality white LED without a separate color conversion material or a complex chip transfer process through the monolithic integration, and a light-emitting module including the same.

[0039] The present invention can provide a light-emitting device in which lattice mismatch and resulting strain occurring in the active layer are relieved, and a light-emitting module including the same.

[0040] The present invention can provide a high-efficiency long-wavelength red light-emitting device with improved internal quantum efficiency (IQE) and external quantum efficiency (EQE) by relaxing strain to suppress the generation of crystal defects, and a light-emitting module including the same.

[0041] The present invention can provide a light-emitting element having low efficiency droop even at high driving currents and high light output and high luminosity characteristics, and a light-emitting module including the same.

[0042] The present invention can provide a light-emitting element with excellent thermal stability and long-term reliability, and a light-emitting module including the same.

[0043] The present invention can provide a light-emitting device and a light-emitting module including the same, which can simplify the manufacturing process and reduce production costs by enabling all RGB pixels to be formed in a single epitaxial growth process.

[0044] FIG. 1 is a cross-sectional view showing a light-emitting element according to one embodiment of the present invention.

[0045] Figure 2 is an enlarged view showing A of Figure 1.

[0046] FIG. 3 is a cross-sectional view showing the first conductivity type semiconductor layer of the light-emitting element of FIG. 1.

[0047] Figure 4 is a cross-sectional view showing a part of the active layer of the light-emitting element of Figure 1.

[0048] FIG. 5 is a cross-sectional view showing the second conductivity type semiconductor layer of the light-emitting element of FIG. 1.

[0049] Figure 6 is a cross-sectional view showing the pre-deformed layer of the light-emitting element of Figure 1.

[0050] FIG. 7 is a cross-sectional view showing a part of a light-emitting element according to another embodiment of the present invention.

[0051] FIG. 8a is a cross-sectional view showing a light-emitting module according to a first embodiment of the present invention.

[0052] Fig. 8b is a variation of Fig. 8a.

[0053] FIG. 9 is a plan view showing a light-emitting module according to a second embodiment of the present invention.

[0054] FIG. 10 is a side view showing a light-emitting module according to a third embodiment of the present invention.

[0055] FIG. 11 is a plan view showing a light-emitting module according to a fourth embodiment of the present invention.

[0056] FIG. 12 is an exploded perspective view showing a light-emitting module according to the fifth embodiment of the present invention.

[0057] FIG. 13 is a cross-sectional view showing a part of a light-emitting module according to the 6th embodiment of the present invention.

[0058] FIG. 14 is a side view showing a part of a light-emitting module according to the seventh embodiment of the present invention.

[0059] In the following description, numerous specific details are described for the purpose of explanation and to provide a complete understanding of the various embodiments or implementations of the present disclosure. As used herein, “Embodiments” and “Implementations” are interchangeable terms indicating non-limiting examples of devices or methods utilizing one or more of the concepts of the invention disclosed herein. However, it will be apparent that various embodiments may be implemented without utilizing these specific details or by utilizing one or more equivalent arrangements. In other examples, known structures and devices are illustrated in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, while various embodiments may differ from one another, they do not need to be exclusive. For example, specific shapes, configurations, and characteristics of an embodiment may be used or implemented in other embodiments without departing from the scope of the concept of the invention.

[0060] Unless otherwise specified, the illustrated embodiments should be understood as providing exemplary features of varying details in some ways in which the concept of the present invention can actually be realized. Therefore, unless otherwise specified, features, components, modules, layers, membranes, panels, regions and / or modes of various embodiments (hereinafter referred to individually or collectively as “elements”) may be combined, separated, interchanged, and / or rearranged differently without departing from the scope of the concept of the present invention.

[0061] The use of cross-hatching and / or shading in the attached drawings is generally provided to clarify the boundaries between adjacent elements. As such, the presence or absence of cross-hatching or shading, unless otherwise specified, does not imply or indicate any preference or requirement regarding the specific material, material properties, dimensions, proportions, commonalities between the exemplified elements, or any other features, attributes, and characteristics of the elements. Additionally, in the attached drawings, the size and relative size of the elements may be exaggerated for clarity and / or illustrative purposes. When embodiments are implemented differently, specific process sequences may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. Also, the same reference numerals indicate the same elements.

[0062] When an element such as a layer is referred to as being "on", "connected to," or "coupled to" another element or layer, said element may be directly on, connected to, or coupled to the other element or layer, or an interposed element or layer may exist. However, when an element or layer is referred to as being "directly on", "directly connected to," or "directly coupled to" another element or layer, no interposed element or layer exists. To this end, the term "connected" may refer to a physical, electrical, and / or fluid connection with or without an interposed element. Furthermore, the DR1-axis, DR2-axis, and DR3-axis are not limited to the three axes of an orthogonal coordinate system, such as the x, y, and z axes, and may be interpreted in a broader sense. For example, the DR1-axis, DR2-axis, and DR3-axis may be perpendicular to each other, or they may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “one or more of X, Y, and Z” and “one or more selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed articles.

[0063] Although terms such as “first,” “second,” etc., may be used herein to describe various forms of elements, these elements shall not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below may be named the second element without departing from the teachings of the present disclosure.

[0064] Spatially relative terms such as “below,” “under,” “immediately below,” “lower,” “above,” “upper,” “upper,” “higher,” and “side” (e.g., as in “side wall”) may be used for descriptive purposes and thereby to describe the relationship between one element and another element(s) as illustrated in the drawings. Spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture in addition to the orientations illustrated in the drawings. For example, if the device in the drawings is inverted, the element described as “below” or “under” another element or feature will be oriented “above” the other element or feature. Therefore, the exemplary term “below” may include both upper and lower orientations. Additionally, the device may be oriented differently (e.g., rotated 90° or oriented in a different orientation), and thus, spatially relative descriptors used herein may also be interpreted accordingly.

[0065] The technical terms used in this specification are intended to describe specific embodiments and are not limiting. The singular form used in this specification also includes the plural form unless the context clearly indicates otherwise. Additionally, the terms “comprising,” “comprising,” “comprising,” and / or “comprising” used in this specification specify the presence of the mentioned features, integers, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms “substantially,” “about,” and other similar terms used in this specification are used to indicate approximation rather than degree, and are used to describe inherent deviations of measured, calculated, and / or provided values ​​that may be recognized by a person of ordinary knowledge in the art.

[0066] Various embodiments are described below with reference to cross-sectional and / or exploded drawings, which are schematic examples of idealized embodiments and / or intermediate structures. As such, variations from the shapes in the drawings may be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of specific illustrated regions, but should be interpreted to include, for example, variations in shape resulting from manufacturing. In this way, the regions illustrated in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus are not intended to have a limiting meaning.

[0067] As is customary in the art, some embodiments may be illustrated and described in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, wiring circuits, memory elements, and wiring connections, formed using semiconductor-based manufacturing technology or other manufacturing technology. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor for performing other functions (e.g., one or more programmed processors and associated circuits). Additionally, each of the blocks, units, and / or modules of some embodiments may be physically separated into two or more interacting and individual blocks, units, and / or modules without departing from the scope of the concept of the present invention. Additionally, the blocks, units, and / or modules of some embodiments may be physically combined into more complex blocks, units, and / or modules without departing from the scope of the concept of the present invention.

[0068] Unless otherwise defined, all terms used herein (including technical or scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with that meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification.

[0069] Hereinafter, the light-emitting element of the present invention and the light-emitting module including the same will be described in detail with reference to the drawings.

[0070] FIG. 1 illustrates a semiconductor layer (EP) of a light-emitting element (100) according to one embodiment of the present invention, wherein the semiconductor layer (EP) may include a first conductivity type semiconductor layer (110), a second conductivity type semiconductor layer (130), and an active layer (120) disposed between the first conductivity type semiconductor layer (110) and the second conductivity type semiconductor layer (130).

[0071] The first conductivity type semiconductor layer (110) may include a phosphide or nitride-based semiconductor such as (Al, Ga, In)P or (Al, Ga, In)N and may be disposed on a substrate (101).

[0072] Here, the substrate (101) is not limited to any substrate capable of growing or placing a semiconductor, and may include heterogeneous substrates such as, for example, a sapphire substrate, a silicon substrate, a silicon carbide substrate, or a spinel substrate, and may also include homogeneous substrates such as a gallium nitride substrate or an aluminum nitride substrate. One surface of the substrate (101) may be a flat surface, or it may be patterned to form irregularities or protrusions (P). The substrate (101) may be removed after the semiconductor layer is formed, or the semiconductor layer may be bonded to the substrate (101).

[0073] For example, the first conductivity type semiconductor layer (110) is a semiconductor layer doped with a first conductivity type dopant, such as the first conductivity type semiconductor layer (110) being an In layer doped with Si as the first conductivity type dopant. x Al y Ga (1-x-y) N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) or In x Al y Ga (1-x-y) P can be formed into layers (0≤x≤1, 0≤y≤1, 0≤x+y≤1).

[0074] Additionally, the first conductivity type semiconductor layer (110) may be doped as n-type by including one or more impurities such as Si, C, Ge, Sn, Te, Pb, etc. However, it is not limited thereto, and the first conductivity type semiconductor layer (110) may be doped as the opposite conductivity type by including a p-type dopant. The doping concentration of the first conductivity type dopant is 1×10 18 atoms / cm 3 Up to 1x10 20 atoms / cm 3 It could be.

[0075] The first conductivity semiconductor layer (110) may be composed of a single layer or may include a plurality of layers. The first conductivity semiconductor layer (110) may further include a core layer and a buffer layer. Additionally, the first conductivity semiconductor layer (110) may further include a superlattice layer. The superlattice layer may be formed on top of the first conductivity semiconductor layer (110). Furthermore, the first conductivity semiconductor layer (110) may additionally include a contact layer, a modulation doping layer, an electron injection layer, etc.

[0076] As an example, referring to FIG. 3, the first conductivity semiconductor layer (110) is a semiconductor layer doped with an n-type dopant and may include a first-1 conductivity semiconductor layer (112), a first-2 conductivity semiconductor layer (114, 116) disposed on one side of the first-1 conductivity semiconductor layer (112) and having a bandgap energy higher than that of the first-1 conductivity semiconductor layer (112), and a first-3 conductivity semiconductor layer (118) disposed on one side of the first-2 conductivity semiconductor layer (114, 116) and having a bandgap energy lower than that of the first-2 conductivity semiconductor layer (114, 116).

[0077] For example, the first conductivity type semiconductor layer (110) may include a first-1 conductivity type semiconductor layer (112) containing GaN, a first-2 conductivity type semiconductor layer (114, 116) disposed on one side of the first-1 conductivity type semiconductor layer (112) and containing Al, and a first-3 conductivity type semiconductor layer (118) disposed on one side of the first-2 conductivity type semiconductor layer (114, 116) and containing GaN.

[0078] The thickness of the first-1 conductivity type semiconductor layer (112) may be between 2500 nm and 3500 nm. The doping concentration of the first conductivity type dopant of the first-1 conductivity type semiconductor layer (112) is 1X10 20 atoms / cm 3 Up to 2x10 20 atoms / cm 3 It could be.

[0079] The first-2 conductivity type semiconductor layer (114, 116) may be disposed on one surface of the first-1 conductivity type semiconductor layer (112) and may be a layer containing Al. Additionally, the first-2 conductivity type semiconductor layer (114, 116) may be doped with a first conductivity type dopant, but is not limited thereto.

[0080] The first and second conductivity type semiconductor layers (114, 116) may be provided in multiple numbers. For example, FIG. 3 illustrates an example in which the first and second conductivity type semiconductor layers (114, 116) are composed of two layers, but the present invention is not limited thereto.

[0081] One of the first and second conductivity semiconductor layers (114, 116) may include a first layer (114) having a relatively higher bandgap energy, and the other may include a second layer (116) having a relatively lower bandgap energy. For example, the first layer (114) may be an AlN layer, and the second layer (116) may be an AlGaN layer.

[0082] The first layer (114) may be disposed on one side of the first-1 conductivity type semiconductor layer (112). The first layer (114) may further include Ga. The first layer (114) is Al x G (1-x) N can have a composition of (0 < x ≤ 1).

[0083] The thickness of the first layer (114) may be between 2 nm and 3 nm.

[0084] The Al composition of the first layer (114) may be 20% or more. The doping concentration of the first conductive type dopant of the first layer (114) is 1×10 19 atoms / cm 3 It may be less than or equal to this.

[0085] The second layer (116) may be disposed on one side of the first layer (114). The second layer (116) is Al x G (1-x) It may have a composition of N (0 < x < 1). The second layer (116) may further include In.

[0086] The thickness of the second layer (116) may be thicker than the thickness of the first layer (114) for strain control. For example, the thickness of the second layer (116) may be between 15 nm and 30 nm.

[0087] The Al composition of the second layer (116) may be less than the Al composition of the first layer (114). Additionally, the second layer (116) may have a gradient structure in which the Al composition gradually varies depending on the position.

[0088] The doping concentration of the first conductive type dopant of the second layer (116) is 1X10 19 atoms / cm 3 It may be less than or equal to this.

[0089] The first layer (114) and the second layer (116) can form a single pair, and multiple pairs can be stacked sequentially.

[0090] The first-third conductivity type semiconductor layer (118) is disposed on one side of the first-second conductivity type semiconductor layer (114, 116) and may include GaN. For example, the first-third conductivity type semiconductor layer (118) may be disposed on one side of the second layer (116).

[0091] The thickness of the first-third conductivity type semiconductor layer (118) may be between 1.5 μm and 2.0 μm. The doping concentration of the first conductivity type dopant of the first-third conductivity type semiconductor layer (118) is 1 x 10 20 atoms / cm 3 It may be less than or equal to this.

[0092] The second conductivity semiconductor layer (130) may include a phosphide-based or nitride-based semiconductor such as (Al, Ga, In)P or (Al, Ga, In)N and may be grown using techniques such as MOCVD, MBE, or HVPE. The second conductivity semiconductor layer (130) may be doped with a second conductivity dopant having a conductivity opposite to that of the first conductivity semiconductor layer (130). For example, the second conductivity semiconductor layer (130) may be doped to a p-type by including an impurity such as Mg. The second conductivity semiconductor layer (130) may be, for example, In x Al y Ga (1-x-y) N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) or In x Al y Ga (1-x-y) P can be formed as (0≤x≤1, 0≤y≤1, 0≤x+y≤1).

[0093] In addition, the second conductivity type semiconductor layer (130) is p-In x Al y Ga (1-x-y) N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) or p-In x Al y Ga (1-x-y) It may be composed of a single layer having a composition such as P (0≤x≤1, 0≤y≤1, 0≤x+y≤1) or may include multiple layers. Additionally, the second conductivity semiconductor layer (130) may further include a layer containing Al internally. Additionally, the second conductivity semiconductor layer (130) may further include a superlattice layer. Additionally, the second conductivity semiconductor layer (130) may further include a second conductivity contact layer.

[0094] As an example, referring to FIG. 5, the second conductivity semiconductor layer (130) may include a second-first conductivity semiconductor layer (132) containing GaN or GaP, which is a semiconductor layer doped with a p-type dopant; a second-second conductivity semiconductor layer (134, 136) disposed on one side of the second-first conductivity semiconductor layer (132) and having a bandgap energy greater than that of the second-first conductivity semiconductor layer (132); and a second-third conductivity semiconductor layer (138) disposed on one side of the second-second conductivity semiconductor layer (134, 136) and containing GaN or GaP.

[0095] The thickness of the above 2-1 conductivity type semiconductor layer (132) may be between 10 nm and 25 nm. The doping concentration of the second conductivity type dopant of the above 2-1 conductivity type semiconductor layer (132) is 1 x 10 20 atoms / cm 3 Up to 2x10 20 atoms / cm 3 It could be.

[0096] The above-mentioned second-2 conductivity type semiconductor layer (134, 136) is disposed on one surface of the second-1 conductivity type semiconductor layer (132) and may be an Al(Ga)N layer containing Al. Additionally, the above-mentioned second-2 conductivity type semiconductor layer (134, 136) may be doped with a second conductivity type dopant, but is not limited thereto.

[0097] The above second-second conductivity type semiconductor layer (134, 136) may be provided in multiple numbers. For example, FIG. 5 illustrates an example in which the above second-second conductivity type semiconductor layer (134, 136) is composed of two first layers (134) and second layers (136), but the present invention is not limited thereto.

[0098] The first layer (134) above may be an AlN layer, and the second layer (136) above may be an AlGaN layer.

[0099] The first layer (134) may be disposed on one side of the second-1 conductivity type semiconductor layer (132). The first layer (134) may further include Ga. The first layer (134) is Al x G (1-x) N (0 < x ≤ 1) or Al x G (1-x) P can have a composition of (0<x≤1).

[0100] The thickness of the first layer (134) may be between 2 nm and 5 nm.

[0101] The Al composition of the first layer (134) may be 20% or more. The doping concentration of the second conductivity type dopant of the first layer (134) is 1×10 19 atoms / cm 3 It may be less than or equal to this.

[0102] The second layer (136) may be disposed on one side of the first layer (134). The second layer (136) is Al x G (1-x) N (0 < x < 1) or Al x G (1-x) It may have a composition of P (0 < x < 1). The second layer (136) may further include In.

[0103] The thickness of the second layer (136) may be thicker than the thickness of the first layer (134) for strain control. For example, the thickness of the second layer (136) may be between 15 nm and 30 nm.

[0104] The Al composition of the second layer (136) may be less than the Al composition of the first layer (134). Additionally, the second layer (136) may have a gradient structure in which the Al composition gradually varies depending on the position.

[0105] The doping concentration of the second conductive type dopant of the second layer (136) is 1X10 19 atoms / cm 3 It may be less than or equal to this.

[0106] The first layer (134) and the second layer (136) can form a single pair, and multiple pairs can be stacked sequentially.

[0107] The second-third conductivity type semiconductor layer (138) is disposed on one side of the second-second conductivity type semiconductor layer (134, 136) and may include GaN or GaP. For example, the second-third conductivity type semiconductor layer (138) may be disposed on one side of the second layer (136).

[0108] The second-third conductivity type semiconductor layer (138) may include a plurality of layers. For example, the second-third conductivity type semiconductor layer (138) may include a first layer (138a) and a contact layer (138b). For example, the first layer (138a) may be a p-GaN layer.

[0109] The thickness of the first layer (138a) may be between 50 nm and 200 nm. The doping concentration of the second conductivity type dopant of the first layer (138a) is 5×10 19 atoms / cm 3 Up to 1x10 20 atoms / cm 3 It can be between.

[0110] The thickness of the contact layer (138b) may be between 10 nm and 20 nm. The doping concentration of the second conductivity type dopant of the contact layer (138b) is 5 x 10 20 atoms / cm 3 Up to 1x10 21 atoms / cm 3 It can be between.

[0111] The active layer (120) may be a light-emitting layer disposed between the first conductive semiconductor layer (110) and the second conductive semiconductor layer (130). The active layer (120) may be disposed on one surface of the first conductive semiconductor layer (110).

[0112] Referring to FIG. 2, the active layer (120) may include a quantum well (QW) structure comprising at least two barrier layers (128) and at least one well layer (124). Alternatively, the active layer (120) may include a multi-quantum well (MQW) structure of alternating barrier layers (124) and well layers (128). Adjacent barrier layers (124) and well layers (128) may form a pair (P), and the active layer (120) may include a plurality of sequentially stacked pairs (P). Adjacent barrier layers and well layers may form a pair. The active layers (304, 305, 306) may include a plurality of pairs.

[0113] The above well layer (124) and barrier layer (128) are, for example, In x Al y Ga (1-x-y) N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) or In x Al y Ga (1-x-y) It can be formed from a semiconductor material having the composition formula P (0≤x≤1, 0≤y≤1, 0≤x+y≤1).

[0114] The wavelength of light emitted from the active layer (120) can be controlled by controlling the composition ratio of the material constituting the well layer (124). The composition and thickness of the well layer (124) can determine the wavelength of the generated light. In particular, by controlling the composition of the well layer (124), an active layer (120) that generates ultraviolet light, blue light, red light, or green light can be provided. For example, the well layer (124) may contain a high In composition. The difference between the In composition (%) of the well layer (124) and the In composition (%) of the second conductivity semiconductor layer (130) may be 20% or more. Through this, long-wavelength red light can be emitted from the active layer (120). The peak wavelength of the emitted light may be formed between 600 and 650 nm. The main wavelength of the emitted light may be between 590 and 640 nm.

[0115] The first conductivity type semiconductor layer (110), the active layer (120), and the second conductivity type semiconductor layer (130) may be a semiconductor stack and a light-emitting structure that emits light having a preset peak wavelength. That is, the semiconductor stack may emit light such as blue, green, or red. For example, a semiconductor stack that emits red light may have a main wavelength and a peak wavelength within the red wavelength region. Specifically, the semiconductor stack may have a main wavelength and a peak wavelength between 600 nm and 650 nm. The peak wavelength of the red light may be a wavelength longer than the main wavelength.

[0116] Meanwhile, referring to FIG. 4, the active layer (120) may further include a pre-well layer (122) between the first conductivity semiconductor layer (110) and the well layer (124). The pre-well layer (122) may be an InGaN layer with a thickness of 1 nm or less.

[0117] The active layer (120) may further include a cap layer (126) containing Al, which is disposed between the well layer (124) and the barrier layer (128). The cap layer (126) is disposed directly on top of the well layer (124) to enhance the confinement effect of carriers (holes and electrons) and to finely adjust the lattice strain.

[0118] The above cap layer (126) may include a first cap layer (126a) comprising AlN disposed on one side of the well layer (124) and a second cap layer (126b) comprising AlGaN disposed on one side of the first cap layer (126a).

[0119] The thickness of the first cap layer (126a) may be between 1 nm and 2.5 nm. The first cap layer (126a) may be a layer that does not contain Ga. Since AlN has the widest bandgap among the III-nitride series, a very high energy barrier can be formed by placing a thin AlN layer directly above the InGaN well layer (124). The high energy barrier can block leakage current or overflow phenomena in which electrons injected into the well layer (124) escape to the barrier layer (128). In particular, since such electron leakage is a major cause of efficiency degradation in a long-wavelength (red) light-emitting device (100) in which the depth of the well layer (124) is relatively shallow, efficiency can be maximized through the AlN-based first cap layer (126a).

[0120] Additionally, the barrier layer (128) can be grown at a much higher temperature than the well layer (124). At this time, due to the thermally stable first cap layer (126a), the problem of indium (In) in the InGaN well layer (124) decomposing or out-diffusion at high temperatures, which degrades the quality of the well layer (124) and changes the emission wavelength, can be prevented. That is, the first cap layer (126a) can act as a protective film to protect the well layer (124) from high-temperature processes.

[0121] The thickness of the second cap layer (126b) may be between 1 nm and 2.5 nm. The thickness of the second cap layer (126b) may be thicker than the thickness of the first cap layer (126a). While AlN, which is the first cap layer (126a), has a small lattice constant, GaN, which is the barrier layer (128), has a relatively large lattice constant. The second cap layer (126b), formed of AlGaN, can act as an intermediate layer, i.e., a strain buffer layer, that gradually bridges the lattice constants between these two layers. Through this, crystal defects that may occur due to abrupt lattice mismatch between the first cap layer (126a) and the GaN barrier layer (128) can be suppressed, and the stability of the entire epitaxial structure can be improved.

[0122] The above double cap layer (126a, 126b) structure can overcome the structural and electrical limitations of a red InGaN well layer (124) containing a high concentration of indium (In) and improve the efficiency and reliability of the light-emitting device (100) through a functional combination of a first cap layer (126a) responsible for carrier confinement and protection of the well layer (124) and a second cap layer (126b) that relieves lattice strain.

[0123] In addition, the barrier layer (128) may have a stack structure in which a plurality of sub-barrier layers (128a, 128b, 128c) formed under different growth conditions are stacked.

[0124] The plurality of sub-barrier layers (128a, 128b, 128c) can be formed at different growth temperatures and perform functionally separate roles. For example, the barrier layer (128) may include a first sub-barrier layer (GaN Barrier 1, 128a), a second sub-barrier layer (GaN Barrier 2, 128b), and a third sub-barrier layer (GaN Barrier 3, 128c) sequentially disposed on the cap layer (126).

[0125] The well layer (124) containing a high concentration of indium (In) and the cap layer (126) containing Al can be very thermally sensitive. If the entire barrier layer (128) is grown at a high temperature all at once, the heat may cause the indium (In) in the well layer (124) to decompose or out-diffuse, which can severely degrade the quality of the well layer (124). To prevent this, the first sub-barrier layer (128a) can be grown at a relatively low temperature to serve as a protective layer that minimizes thermal damage to the lower well layer (124) and cap layer (126).

[0126] On the other hand, as the GaN layer is grown at a higher temperature, the mobility of the atoms increases, resulting in superior crystallinity and a flatter surface. Superior crystallinity and a flat surface can determine the quality of the next well layer (124) to be grown thereon. Thus, the second and third sub-barrier layers (128b, 128c) can be grown at a higher temperature than the first sub-barrier layer (128a) to improve the crystallinity of the barrier layer (128) itself and provide a high-quality flat surface for the growth of the next well layer (124).

[0127] For optimal strain distribution and structural stability, the thickness of the first sub-barrier layer (128a) may be formed to be thinner than the sum of the thicknesses of the second sub-barrier layer (128b) and the third sub-barrier layer (128c).

[0128] The area from the pre-well layer (122) to the barrier layer (128) may form a single pair (P), and the total thickness of the pair (P) may be between 10 nm and 20 nm. The number of pairs (P) may be between 5 and 12.

[0129] Meanwhile, the light-emitting element (100) of the present invention may contain a very high concentration of indium (In) in the well layer (124) within the active layer (120) to realize red light. This can cause large lattice stress between the active layer (120) and the second conductivity semiconductor layer (130) grown thereon. If this stress is not effectively relieved, it can create serious crystal defects, such as misfit dislocations, directly within the active layer (120), which can significantly reduce the light-emitting efficiency.

[0130] Referring to FIG. 7, in order to solve these problems, the second conductivity semiconductor layer (130) may include a buffer line (BL) to relieve lattice stress with the well layer (124).

[0131] The above buffer line (BL) is a line-shaped structure formed inside the second conductive semiconductor layer (130) and can be formed to effectively relieve and disperse stress energy accumulated in the active layer (120).

[0132] For example, the buffer line (BL) may extend from one side of the second conductivity semiconductor layer (130) toward the other side with an inclination with respect to the thickness direction of the second conductivity semiconductor layer (130).

[0133] The buffer line (BL) has a constant slope in the thickness direction and can start near the interface with the active layer (120) (one side) and extend obliquely or in a curved shape toward the top (other side) of the second conductivity semiconductor layer (130). Through this sloped structure, the length of the buffer line (BL) can be extended and stress energy can be gradually distributed over a wider area. Some of the buffer lines (BL) can extend into the interior of the active layer (120).

[0134] The compressive stress energy generated in the active layer (120) can be released and relieved along the buffer line (BL) as the second conductive semiconductor layer (130) grows. That is, the buffer line (BL) can function as an 'energy outlet' that prevents stress concentration, and through this, the well layer (124) where light is generated can maintain a high-quality state with relatively few defects.

[0135] Meanwhile, the light-emitting element (100) may further include a pre-deformation layer (140) disposed between the first conductive semiconductor layer (110) and the active layer (120). In FIG. 1, the pre-deformation layer (140) may be omitted as an optional configuration.

[0136] The above pre-deformed layer (140) can pre-control and relieve lattice strain so that the active layer (120) to be subsequently grown, particularly the red quantum well layer (124) which contains a high concentration of indium (In) and causes large lattice stress, can grow while maintaining high-quality crystallinity. The above pre-deformed layer (140) may have a stacked structure composed of multiple layers.

[0137] For example, the pre-deformation layer (140) may include a first pre-deformation layer (142) comprising GaN disposed on one side of the first conductive semiconductor layer (110), a second pre-deformation layer (144) comprising InGaN disposed on one side of the first pre-deformation layer (142), and a superlattice pre-deformation layer (146) disposed on one side of the second pre-deformation layer (144). The first pre-deformation layer (142), the second pre-deformation layer (144), and the superlattice pre-deformation layer (146) may be stacked sequentially starting from the first conductive semiconductor layer (110).

[0138] The first pre-deformed layer (142) can provide a stable foundation for subsequent layer growth. The first pre-deformed layer (142) may be doped with a first conductivity type dopant, e.g., Si. The doping concentration is 1 x 10⁻¹⁰ 17 atoms / cm 3 Up to 3x10 18 atoms / cm 3 It could be between.

[0139] The first pre-deformation layer (142) may include a first-1 pre-deformation layer (142a) and a first-2 pre-deformation layer (142b) having a thinner thickness than the first-1 pre-deformation layer (142a).

[0140] The thickness of the first-1 pre-deformed layer (142a) may be between 250 nm and 300 nm. The first-1 pre-deformed layer (142a) may be doped with a first conductive type dopant. The doping concentration is 1 x 10 17 atoms / cm 3 Up to 3x10 18 atoms / cm 3 It could be between.

[0141] The first-2 pre-deformation layer (142b) may be a recovery layer having a thinner thickness than the first-1 pre-deformation layer (142a). The thickness of the first-2 pre-deformation layer (142b) may be between 10 nm and 30 nm.

[0142] The second pre-deformed layer (144) may be a single InGaN layer disposed on one side of the first pre-deformed layer (142). The In composition of the second pre-deformed layer (144) may have a relatively low value between 1% and 10%. The second pre-deformed layer (144) may be doped with a first conductivity type dopant, e.g., Si. The doping concentration is 5×10 17 atoms / cm 3 Up to 3x10 18 atoms / cm 3 It may be between. The second pre-deformed layer (144) may be subjected to modulation doping having a non-uniform first conductivity type dopant concentration distribution.

[0143] The above second pre-deformation layer (144) can gradually introduce strain into the lattice before growing the active layer (120) containing a high concentration of indium.

[0144] The superlattice pre-deformation layer (146) may be a superlattice layer disposed on one side of the second pre-deformation layer (144).

[0145] The superlattice pre-deformation layer (146) may include a plurality of pairs in which InGaN and GaN are alternately stacked. For example, the superlattice pre-deformation layer (146) may include a structure in which an InGaN layer and a GaN layer are alternately stacked in 2 to 4 cycles, but this is exemplary and is not limited thereto.

[0146] The thickness of the superlattice pre-deformed layer (146) may be between 300 nm and 415 nm.

[0147] The In composition of the superlattice pre-deformation layer (146) may be smaller than or equal to the In composition of the second pre-deformation layer (144).

[0148] The superlattice pre-deformation layer (146) can effectively disperse and finely control lattice strain, thereby minimizing the occurrence of crystal defects in the active layer (120) to be grown on top.

[0149] The above pre-deformed layer (140) can gradually accommodate and alleviate lattice stress generated during the growth of a red light-emitting active layer (120) containing a high concentration of indium through a multilayer composite structure. This improves the crystallinity of the active layer (120) and, consequently, maximizes the internal quantum efficiency (IQE) and external quantum efficiency (EQE) of the light-emitting device (100).

[0150] The light-emitting element (100) may include a mesa structure in which a portion of the semiconductor layer is etched. A portion of the upper surface of the first conductive semiconductor layer (110) may be exposed around the mesa.

[0151] The light-emitting element (100) may include a first contact electrode that is in contact with a first conductive semiconductor layer (110) and a second contact electrode that is in contact with a second conductive semiconductor layer (130). The light-emitting element (100) is disposed on one side of a circuit board and may be electrically connected to the circuit board through the first contact electrode and the second contact electrode.

[0152] Meanwhile, the light-emitting element (100) described above is a light-emitting structure in which the well layer (124) contains a high In composition and emits long-wavelength red light, and the peak wavelength of the emitted light from the active layer (120) may be 600 nm to 650 nm.

[0153] At this time, the ratio (λp / T1) of the peak wavelength (λp, nm) to the thickness (T1, nm) from the barrier layer (128) adjacent to the second conductivity semiconductor layer (120) to the second conductivity semiconductor layer (120) may have a value between 3.4 and 3.8.

[0154] The light-emitting element (100) of the present invention emits long-wavelength red light with a peak wavelength range of 620 nm to 640 nm by including a high concentration of indium (In) composition in the well layer (124), and this high concentration of indium can be the main cause of accumulating a significant amount of compressive strain within the active layer (120). The accumulated strain can be controlled and the light-emitting efficiency determined according to the thickness of the second conductivity type semiconductor layer (p-type semiconductor layer, 130) grown on the active layer (120).

[0155] The above thickness (T1) may refer to the total thickness from the upper surface of the barrier layer (128, i.e., the last barrier layer) located at the top of the multiple quantum well (MQW) structure to the upper surface of the second conductive semiconductor layer (130).

[0156] If the second conductivity semiconductor layer (130) is too thin, it may not effectively relieve or disperse the massive strain accumulated in the active layer (120), and crystal defects may occur. Conversely, if the second conductivity semiconductor layer (130) becomes too thick, it may cause another strain problem or degrade crystallinity. Within the thickness-peak wavelength ratio (λp / T1) range of the present invention, the strain of the active layer (120) can be effectively relieved so that crystallinity is maintained.

[0157] Additionally, as the thickness (T1) increases, the total resistance of the second conductivity semiconductor layer (130) increases, causing the hole injection efficiency to decrease and the driving voltage (Vf) of the light-emitting element (100) to increase. Within the thickness-peak wavelength ratio (λp / T1) range of the present invention, a sufficient strain relief effect can be obtained while suppressing an excessive increase in the driving voltage.

[0158] In addition, the second conductivity semiconductor layer (130) may be grown at a relatively low temperature to prevent thermal damage to the active layer (120), and thus its crystallinity may be weak. The thickness (T1) specified in the present invention can secure a high-quality second conductivity semiconductor layer (130) even under such process conditions and effectively form a strain relief structure such as the buffer line.

[0159] According to the thickness-peak wavelength ratio (λp / T1) above, problems such as strain, crystallinity degradation, and electrical characteristics deterioration of a red light-emitting element (100) containing high concentration indium (In) can be improved, and external quantum efficiency (EQE) can be maximized.

[0160] Alternatively, the ratio of the main wavelength (λd) to the thickness (nm) from the barrier layer (128) adjacent to the second conductivity semiconductor layer (130) to the second conductivity semiconductor layer (130) ((λd / T1)) may have a value between 3.4 and 3.8. The main wavelength (λd) may be shorter than the peak wavelength (λp).

[0161] In addition, the ratio (λp / T2) of the peak wavelength (λp) to the thickness (nm, T2) of the well layer (124) may have a value between 135 and 256.

[0162] The peak wavelength (λp) of light emitted from the light-emitting element (100) can be determined by the thickness (T2) of the well layer (124) and the material composition (e.g., indium content). As the thickness (T2) of the well layer (124) increases, the energy level is lowered due to the quantum size effect, allowing for the emission of longer wavelengths of light (red-shift). Therefore, one may consider increasing the thickness (T2) of the well layer (124) simply to obtain red light. However, as the well layer (124) increases, the recombination probability of electrons and holes decreases, which may lower the internal quantum efficiency (IQE), and the degree of shielding of the internal electric field changes depending on the amount of injected current, causing the emission wavelength to fluctuate unstably.

[0163] Therefore, indiscriminately increasing the well layer thickness (T2) for red light significantly reduces efficiency, and conversely, reducing the thickness (T2) requires an excessively high indium (In) composition to obtain the desired red wavelength, which may increase crystal defects.

[0164] The present invention can realize a high-efficiency red light emitting element (100) without excessive efficiency reduction or crystal defects by setting the ratio (λp / T2) between the thickness (T2) of the well layer and the peak wavelength (λp) to between 135 and 256.

[0165] In addition, the ratio of the peak wavelength (λp) to the thickness (nm) of the pre-deformed layer (140) may have a value between 0.8 and 1.

[0166] As described above, the pre-deformed layer (140) may be a layer for pre-accommodating and relieving large lattice stress of an active layer (120) containing high concentration indium (In) to be grown thereon. The total thickness of the pre-deformed layer (140) may affect the stress control capability.

[0167] By limiting the ratio of the peak wavelength (λp) to the thickness (nm) of the pre-deformed layer (140), the crystallinity of the active layer (120) is maximized and high luminescence efficiency can be obtained.

[0168] If the ratio of the peak wavelength (λp) to the thickness (nm) of the pre-deformed layer (140) exceeds 1, the pre-deformed layer (140) is excessively thin, and the thickness of the pre-deformed layer (140) may not be sufficient for the amount of stress generated in the active layer (120) (the longer the wavelength, the greater the stress generated). If the pre-deformed layer is too thin, it may not be able to effectively absorb or disperse the massive stress energy generated during the growth of the active layer (120). Consequently, unbuffered stress may directly create fatal crystal defects, such as misfit dislocations, within the active layer (120). These defects may act as non-radiative recombination centers and severely degrade the internal quantum efficiency (IQE).

[0169] If the ratio of the peak wavelength (λp) to the thickness (nm) of the pre-deformed layer (140) is less than 0.8, the pre-deformed layer (140) is excessively thick, which degrades the quality of the pre-deformed layer (140) itself and may have an adverse effect on the active layer (120), and the thin film growth process time may be prolonged, thereby reducing productivity and increasing manufacturing costs. In addition, an unnecessarily thick pre-deformed layer (140) may cause the driving voltage (Vf) to increase, which may reduce the power efficiency of the light-emitting device (100).

[0170] The light-emitting module according to the present invention may include the light-emitting element (100) described above.

[0171] First, FIG. 8a is a light-emitting module according to a first embodiment of the present invention, and may be a light-emitting package (1000) including at least one light-emitting element (100).

[0172] The light-emitting package (1000) may include at least one light-emitting element (100) and a lead frame (1010) on which the light-emitting element (100) is mounted. The light-emitting element (100) may be electrically connected to an electrode of the lead frame (1010) through a wire (W).

[0173] The lead frame (1010) may be provided with a cavity (C) for mounting the light-emitting element (100). The side wall of the lead frame (1010) forming the cavity (C) forms an inclined surface, and the inclined surface may be a reflective surface that reflects light emitted from the light-emitting element (100).

[0174] The above-described light-emitting package (1000) may further include a molding portion disposed in the cavity (C). The molding portion may be a transparent molding. Or the molding portion may include a wavelength-converting material. Or the molding portion may further include a light-absorbing material, a light-reflecting material, or a light-scattering material.

[0175] Next, the light-emitting package (1000') of FIG. 8b is a modified example of the light-emitting package (1000) of FIG. 8a, and can be configured to be identical or similar to the light-emitting package (1000) of FIG. 8a, except that the light-emitting element (100) is soldered to the lead frame (1010) via bumps in the form of a flip chip.

[0176] Next, FIG. 9 may be a light-emitting module according to a second embodiment of the present invention, comprising at least one light-emitting element (100) and a light-emitting module (2000). The light-emitting module (2000) may include a substrate (2010) and at least one light-emitting element (100) disposed on the substrate (2010).

[0177] The light-emitting module (2000) may include a plurality of light-emitting elements (100). FIG. 9 illustrates an example in which the light-emitting module (2000) includes two light-emitting elements (100), but the present invention is not limited thereto. In FIG. 9, ER illustrates a light-emitting region by a light-emitting element (100).

[0178] Next, FIG. 10 is a light-emitting module according to a third embodiment of the present invention, wherein the light-emitting module may be a lighting device (3000) comprising at least one light-emitting element (100) described above.

[0179] Referring to FIG. 10, the lighting device (3000) may include a diffusion cover (3010), a light source module (3020), and a body part (3030). The body part (3030) may accommodate the light source module (3020), and the diffusion cover (3010) may be placed on the body part (3030) to cover the upper part of the light-emitting device module (3020).

[0180] The body portion (3030) is not limited to a shape that accommodates and supports the light source module (3020) and can supply electrical power to the light source module (3020). For example, as illustrated, the body portion (3030) may include a body case (3031), a power supply unit (3033), a power case (3035), and a power connection portion (3037).

[0181] The power supply unit (3033) is housed within the power case (3035) and electrically connected to the light source module (3020), and may include at least one IC chip. The IC chip can adjust, convert, or control the characteristics of the power supplied to the light source module (3020). The power case (3035) can house and support the power supply unit (3033), and the power case (3035), in which the power supply unit (3033) is fixed inside, can be located inside the body case (3031). The power connection part (3037) is positioned at the bottom of the power case (3035) and can be connected to the power case (3035). Accordingly, the power connection part (3037) is electrically connected to the power supply unit (3033) inside the power case (3035) and can serve as a passage through which external power can be supplied to the power supply unit (3033).

[0182] The light source module (3020) may include a substrate (3023) and at least one light-emitting element (100) disposed on the substrate (3023). The light source module (3020) may be provided on the upper part of a body case (3031) and electrically connected to a power supply (3033).

[0183] The substrate (3023) is not limited to any specific substrate capable of supporting the light-emitting element (100), and, for example, may be a printed circuit board including wiring. The substrate (3023) may have a shape corresponding to a fixing part on the upper part of the body case (3031) so that it can be stably fixed to the body case (3031).

[0184] The diffusion cover (3010) is placed on the light-emitting element (100) and is fixed to the body case (3031) to cover the light-emitting element (100). The diffusion cover (3010) may have a light-transmitting material, and the directional characteristics of the lighting device (3000) can be controlled by adjusting the shape and light transmittance of the diffusion cover (3010). Accordingly, the diffusion cover (3010) can be modified into various shapes depending on the purpose of use and application of the lighting device (3000).

[0185] Next, FIG. 11 is a cross-sectional view of a light-emitting module according to a fourth embodiment of the present invention, wherein the light-emitting module may be a display device (4000) comprising at least one light-emitting element (100) described above.

[0186] The above display device (4000) may include a display panel (4110), a backlight unit that provides light to the display panel (4110), and a panel guide that supports the lower edge of the display panel (4110).

[0187] The above display panel (4110) is not particularly limited and, for example, may be a liquid crystal display panel including a liquid crystal layer. A gate driving PCB that supplies a driving signal to the gate line may be further located at the edge of the display panel (4110). Here, the gate driving PCB may not be configured on a separate PCB but may be formed on a thin-film transistor substrate. The pixels of the display panel (4110) may be LED displays implemented by the light-emitting element (100) of the present invention. If the display panel (4110) is an LED display, the backlight unit described later may be omitted.

[0188] The backlight unit may include a light source module comprising at least one substrate and a plurality of light-emitting elements (100). Furthermore, the backlight unit may further include a bottom cover (4180), a reflective sheet (4170), a diffusion plate (4131), and optical sheets (4130).

[0189] The bottom cover (4180) is open at the top and can accommodate a substrate, a light-emitting element (100), a reflective sheet (4170), a diffusion plate (4131), and optical sheets (4130). Additionally, the bottom cover (4180) can be coupled with a panel guide. The substrate may be positioned below the reflective sheet (4170) and arranged in a form surrounded by the reflective sheet (4170). However, it is not limited thereto, and may be positioned on the reflective sheet (4170) if a reflective material is coated on the surface. Additionally, the substrate may be formed in multiple numbers and arranged in a form where multiple substrates are placed side by side, but is not limited thereto, and may be formed as a single substrate.

[0190] The light-emitting elements (100) can be regularly arranged in a certain pattern on a substrate. Additionally, a lens (4210) is disposed on each light-emitting element (100) to improve the uniformity of the light emitted from the plurality of light-emitting elements (4160).

[0191] The above diffusion plate (4131) and optical sheets (4130) are positioned on the light-emitting element (100). Light emitted from the light-emitting element (100) can be supplied to a display panel (4110) in the form of a surface light source through the diffusion plate (4131) and optical sheets (4130).

[0192] In this way, the light-emitting element (100) according to the embodiments of the present invention can be applied to a direct-type display device (4000) such as the present embodiment.

[0193] Next, FIG. 12 is a cross-sectional view of a light-emitting module according to a fifth embodiment of the present invention, wherein the light-emitting module may be a display device (5000) comprising at least one light-emitting element (100) described above.

[0194] A display device (5000) equipped with a backlight unit according to the fifth embodiment includes a display panel (5210) on which an image is displayed, and a backlight unit disposed on the back surface of the display panel (5210) to irradiate light. Furthermore, the display device (5000) may include a frame that supports the display panel (5210) and accommodates the backlight unit, and a cover (5240, 5280) that surrounds the display panel (5210).

[0195] The display panel (5210) is not specifically limited and, for example, may be a liquid crystal display panel including a liquid crystal layer. A gate driving PCB that supplies a driving signal to the gate line may be further located at the edge of the display panel (5210). Here, the gate driving PCB may not be configured on a separate PCB but may be formed on a thin-film transistor substrate. The display panel (5210) is fixed by covers (5240, 5280) located on its upper and lower parts, and the cover (5280) located on the lower part may be connected to a backlight unit.

[0196] A backlight unit that provides light to a display panel (5210) includes a lower cover (5270) with a portion of its upper surface open, a light source module disposed on one side of the interior of the lower cover (5270), and a light guide plate (5250) positioned parallel to the light source module to convert point light into surface light. Additionally, the backlight unit of the present embodiment may further include optical sheets (5230) positioned on the light guide plate (5250) to diffuse and concentrate light, and a reflective sheet (5260) disposed below the light guide plate (5250) to reflect light traveling in the downward direction of the light guide plate (5250) toward the display panel (35210).

[0197] The light source module includes a substrate (5220) and a plurality of light-emitting elements (100) spaced apart at regular intervals on one surface of the substrate (5220). The substrate (5220) is not limited to supporting the light-emitting elements (100) and being electrically connected to the light-emitting elements (100), and may be, for example, a printed circuit board.

[0198] Light emitted from the light source module can be incident on the light guide plate (5250) and supplied to the display panel (5210) through the optical sheets (5230). Through the light guide plate (5250) and the optical sheets (5230), the point light source emitted from the light-emitting elements (100) can be transformed into a surface light source.

[0199] In this way, the light-emitting element (100) according to the embodiments of the present invention can be applied to an edge-type display device (5000) such as the present embodiment.

[0200] Next, FIG. 13 is a cross-sectional view of a light-emitting module according to a sixth embodiment of the present invention, wherein the light-emitting module may be a head lamp (6000) comprising at least one light-emitting element (100) described above.

[0201] Referring to FIG. 13, the head lamp (6000) may include a lamp body (6070), a substrate (6020), a light-emitting element (100), and a cover lens (6050). Furthermore, the head lamp (6000) may further include a heat dissipation part (6030), a support rack (6060), and a connecting member (6040).

[0202] The substrate (6020) can be fixed by a support rack (6060) and spaced apart on the lamp body (6070). The substrate (6020) is not limited to any specific substrate capable of supporting the light-emitting element (100), and may be, for example, a substrate having a conductive pattern such as a printed circuit board. The light-emitting element (100) is positioned on the substrate (6020) and can be supported and fixed by the substrate (6020). Additionally, the light-emitting element (100) can be electrically connected to an external power source through the conductive pattern of the substrate (6020).

[0203] The cover lens (6050) is positioned on the path along which light emitted from the light-emitting element (100) travels. For example, as illustrated, the cover lens (6050) may be positioned spaced apart from the light-emitting element (100) by a connecting member (6040) and may be positioned in a direction intended to provide light emitted from the light-emitting element (100). The directional angle and / or color of the light emitted outward from the head lamp (6000) can be controlled by the cover lens (6050).

[0204] Meanwhile, the connecting member (6040) may serve as a light guide that secures the cover lens (6050) to the substrate (6020) and surrounds the light-emitting element (100) to provide a light-emitting path (6045). At this time, the connecting member (6040) may be formed of a light-reflective material or coated with a light-reflective material. Meanwhile, the heat dissipation member (6030) may include a heat dissipation fin (6031) and / or a heat dissipation fan (6033) and may dissipate heat generated when the light-emitting element (6010) is operated to the outside.

[0205] Next, FIG. 15 is a cross-sectional view of a light-emitting module according to the seventh embodiment of the present invention, wherein the light-emitting module may include a circuit board (7010) and at least one light-emitting element (100) disposed on one surface of the circuit board (7010).

[0206] The light-emitting module according to an embodiment of the present invention can be configured with various light-emitting devices, such as lighting devices and display devices.

[0207]

[0208] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0209] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

Claims

1. A light-emitting device comprising a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, The above active layer includes a multiple quantum well structure of well layers and barrier layers arranged alternately, and The peak wavelength of the emitted light from the active layer is 620 nm to 640 nm, and A light-emitting device having a ratio of the peak wavelength to the thickness (nm) from the barrier layer adjacent to the second conductivity semiconductor layer to the second conductivity semiconductor layer, a value between 3.4 and 3.

8.

2. In Claim 1, A light-emitting device in which the difference between the In composition (%) of the well layer and the In composition (%) of the second conductivity semiconductor layer is 20% or more.

3. In Claim 2, The above second conductivity type semiconductor layer is a light-emitting device comprising a buffer line for relieving lattice stress with the well layer.

4. In Claim 3, The above buffer line is a light-emitting element that has a slope with respect to the thickness direction of the second conductivity semiconductor layer and extends from one side to the other side of the second conductivity semiconductor layer.

5. In Claim 1, A light-emitting device having a ratio of the peak wavelength to the thickness (nm) of the well layer between a value of 135 and 256.

6. In Claim 1, The first conductivity semiconductor layer is a semiconductor layer doped with an n-type dopant, and the second conductivity semiconductor layer is a semiconductor layer doped with a p-type dopant. A light-emitting device further comprising a pre-deformation layer disposed between the first conductivity type semiconductor layer and the active layer.

7. In Claim 6, A light-emitting device having a ratio of the peak wavelength to the thickness (nm) of the pre-deformed layer of the above-mentioned light-emitting element having a value between 0.8 and 1.

8. In Claim 6, A light-emitting device comprising a first pre-deformation layer disposed on one side of the first conductive semiconductor layer and including a first pre-deformation layer including GaN, a second pre-deformation layer disposed on one side of the first pre-deformation layer and including InGaN, and a superlattice pre-deformation layer disposed on one side of the second pre-deformation layer.

9. In Claim 8, The light-emitting device comprises the first pre-deformation layer, a first-1 pre-deformation layer, and a first-2 pre-deformation layer having a thinner thickness than the first-1 pre-deformation layer.

10. In Claim 8, The above first pre-deformed layer is a Si-doped light-emitting device.

11. In Claim 8, A light-emitting element having an In composition of the second pre-deformed layer having a value between 1% and 10%.

12. In Claim 11 The above superlattice pre-deformation layer is a light-emitting device comprising a plurality of pairs in which InGaN and GaN are alternately stacked.

13. In Claim 12, A light-emitting device in which the In composition of the superlattice pre-deformation layer is smaller than or equal to the In composition of the second pre-deformation layer.

14. In Claim 1, The light-emitting device comprising an active layer disposed between the well layer and the barrier layer, and further including a cap layer containing Al.

15. In Claim 14, A light-emitting device comprising a first cap layer comprising AlN disposed on one side of the well layer and a second cap layer comprising AlGaN disposed on one side of the first cap layer.

16. In Claim 6, A light-emitting device comprising: a first conductivity type semiconductor layer comprising GaN; a first conductivity type semiconductor layer comprising Al disposed on one surface of the first conductivity type semiconductor layer comprising Al; and a first conductivity type semiconductor layer comprising GaN disposed on one surface of the first conductivity type semiconductor layer comprising GaN.

17. In Claim 6, A light-emitting device comprising: a second conductivity type semiconductor layer comprising a second-1 conductivity type semiconductor layer comprising GaN; a second-2 conductivity type semiconductor layer disposed on one surface of the second-1 conductivity type semiconductor layer comprising Al; and a second-3 conductivity type semiconductor layer disposed on one surface of the second-2 conductivity type semiconductor layer comprising GaN.

18. A light-emitting device comprising a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, The above active layer includes a multiple quantum well structure of well layers and barrier layers arranged alternately, and The main wavelength of the emitted light from the above active layer is 610 nm to 630 nm, and A light-emitting device having a ratio of the main wavelength to the thickness (nm) from the barrier layer adjacent to the second conductivity semiconductor layer to the second conductivity semiconductor layer, a value between 3.4 and 3.

8.

19. In Claim 18, A light-emitting device in which the difference between the In composition (%) of the well layer and the In composition (%) of the second conductivity semiconductor layer is 20% or more.

20. In Claim 19, The above second conductivity type semiconductor layer is a light-emitting device comprising a buffer line for relieving lattice stress with the well layer.

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