Display panel and electronic device including same

Abstract

An embodiment of the present invention provides a display panel including a plurality of first areas and a second area surrounding each of the plurality of first areas, wherein the display panel comprises: a pixel circuit layer including a plurality of pixel circuits and insulating layers disposed in each of the plurality of first areas; a plurality of light-emitting diodes disposed on the pixel circuit layer and electrically connected to the plurality of pixel circuits, respectively; a connection line disposed in the second area and electrically connecting pixel circuits disposed adjacent to each other among the plurality of pixel circuits; and an auxiliary pattern disposed to cover both ends of the connection line.

Description

Display panel and electronic device including the same

[0001] The present invention relates to a display panel and an electronic device including the same.

[0002] In general, as display panels that visually display electrical signals advance, various display panels with excellent characteristics such as thinness, lightness, and low power consumption, as well as electronic devices containing them, are being introduced. For example, research and development is actively underway on display panels of various structures, such as flexible display panels that can be folded or rolled into a roll shape, and stretchable display panels, as well as electronic devices containing them.

[0003] Embodiments of the present invention aim to provide a display panel with improved stretchability and capable of realizing an image of excellent quality even when stretched, and an electronic device including the same. However, these objectives are exemplary and do not limit the scope of the present invention.

[0004] One embodiment of the present invention provides a display panel comprising a plurality of first regions and a second region surrounding each of the plurality of first regions, the display panel comprising: a pixel circuit layer comprising a plurality of pixel circuits and insulating layers (e.g., electrical insulating layers) disposed in each of the plurality of first regions; a plurality of light-emitting diodes disposed on the pixel circuit layer and electrically connected to each of the plurality of pixel circuits; a connecting line electrically connecting pixel circuits disposed adjacent to each other among the plurality of pixel circuits; and an auxiliary pattern disposed to cover both ends of the connecting line (e.g., two ends disposed opposite each other).

[0005] In one embodiment, both ends of the connection line and the auxiliary pattern are placed in a first area of ​​one of the plurality of first areas, and a portion of the connection line excluding both ends may be placed in the second area.

[0006] In one embodiment, the modulus of the auxiliary pattern may be greater than the modulus of the connection line.

[0007] In one embodiment, the modulus of the auxiliary pattern may have a value in the range of 10 to 5000 times the modulus of the connection line.

[0008] In one embodiment, a base layer disposed below the pixel circuit layer and covering the lower surface of the connection line and the lower surface of the auxiliary pattern may be further included.

[0009] In one embodiment, with respect to the thickness direction of the pixel circuit layer, the thickness of the auxiliary pattern may be greater than the thickness of the connection line.

[0010] In one embodiment, based on the thickness direction of the pixel circuit layer, the thickness of the auxiliary pattern may be 1.25 times or more the thickness of the connection line.

[0011] In one embodiment, the connecting line extends along a first direction and has a first width along a second direction intersecting the first direction, and the auxiliary pattern has a second width along the second direction, and in a plane, the second width of the auxiliary pattern may be larger than the first width of the connecting line.

[0012] In one embodiment, the second width of the auxiliary pattern may be at least 1.25 times the first width of the connecting line.

[0013] In one embodiment, the connection lines are provided in plurality, and pixel circuits disposed in one of the plurality of first regions are connected to the plurality of connection lines, and the plurality of connection lines may include a plurality of horizontal connection lines extending along a first direction and a plurality of vertical connection lines extending along a second direction intersecting the first direction.

[0014] In one embodiment, the auxiliary patterns are provided in plurality to cover the ends of each of the plurality of connection lines, and the plurality of auxiliary patterns may be spaced apart from each other.

[0015] In one embodiment, one of the auxiliary patterns can cover the ends of two or more of the plurality of connection lines.

[0016] In one embodiment, an auxiliary pattern covering all ends of the plurality of connection lines may be disposed in one of the plurality of first regions.

[0017] In one embodiment, the auxiliary pattern may have a planar mesh pattern in the first region.

[0018] In one embodiment, the auxiliary pattern may have a single continuous shape so as to overlap with the pixel circuit layer on a plane.

[0019] In one embodiment, the auxiliary pattern may extend diagonally between the first direction and the second direction on the first area.

[0020] In one embodiment, one end of the auxiliary pattern covers one end of one of the plurality of horizontal connection lines, and the other end of the auxiliary pattern can cover one end of one of the plurality of vertical connection lines.

[0021] In one embodiment, the auxiliary pattern may extend in the first direction or the second direction to cover the ends of the plurality of connection lines arranged on one side of the first region.

[0022] In one embodiment, the auxiliary patterns are provided in a plurality, some of the plurality of auxiliary patterns cover the end of one of the plurality of connection lines, and the remainder of the plurality of auxiliary patterns can cover the end of two or more of the plurality of connection lines.

[0023] In one embodiment, the auxiliary pattern is extended in the first direction, such that one end of the auxiliary pattern covers the end of one of the plurality of horizontal connecting lines disposed on one side of the first region, and the other end of the auxiliary pattern covers the end of one of the plurality of horizontal connecting lines disposed on the opposite side of the one side.

[0024] Another embodiment of the present invention provides an electronic device comprising: a display panel including a plurality of first regions and a second region surrounding each of the plurality of first regions; and a lower cover having an opening that forms an exterior and exposes a portion of the display panel on a front surface; wherein the display panel comprises: a pixel circuit layer including a plurality of pixel circuits and insulating layers disposed in each of the plurality of first regions; a plurality of light-emitting diodes disposed on the pixel circuit layer and electrically connected to each of the plurality of pixel circuits; a connection line electrically connecting pixel circuits disposed adjacent to each other among the plurality of pixel circuits; and an auxiliary pattern disposed to cover both ends of the connection line.

[0025] According to some embodiments of the present invention, a display panel with improved elasticity and excellent quality image realization and an electronic device including the same can be provided. The aforementioned effects are exemplary and the effects of the present invention are not limited to those described above.

[0026] The attached drawings illustrate embodiments of the contents of the present invention together with the specification and serve to explain the principles of the embodiments of the present invention together with the description.

[0027] FIG. 1a is a schematic perspective view of an electronic device according to one embodiment of the present invention.

[0028] FIG. 1b is a block diagram schematically illustrating an electronic device according to one embodiment of the present invention.

[0029] FIG. 2 is a schematic perspective view of a display panel according to one embodiment of the present invention.

[0030] FIGS. 3A and FIGS. 3B are perspective views showing the display panel of FIG. 2 extended in the first direction.

[0031] FIG. 3c is a perspective view showing the display panel of FIG. 2 extended in a second direction.

[0032] FIG. 3d is a perspective view showing the display panel of FIG. 2 extended in the first direction and the second direction.

[0033] FIG. 3e is a perspective view showing the display panel of FIG. 2 extended in a third direction.

[0034] FIG. 4 is a schematic plan view of a display panel according to one embodiment of the present invention.

[0035] FIG. 5 is a plan view schematically showing the arrangement of pixels of a display panel according to one embodiment of the present invention.

[0036] FIG. 6 is a cross-sectional view schematically showing a part of a display panel according to one embodiment of the present invention.

[0037] FIGS. 7a to 7c are each equivalent circuit diagrams of pixels of a display panel according to an embodiment of the present invention.

[0038] FIGS. 8a to 8d are cross-sectional views schematically showing a light-emitting diode of a display panel according to one embodiment of the present invention.

[0039] FIG. 9 is a schematic plan view showing a part of a display panel according to one embodiment of the present invention.

[0040] FIG. 10 is a schematic plan view showing a part of a display panel according to one embodiment of the present invention.

[0041] FIG. 11 is a cross-sectional view schematically showing a part of a display panel according to one embodiment of the present invention.

[0042] FIG. 12 is a perspective view showing the first line, second line, connecting line, and auxiliary pattern of FIG. 11.

[0043] FIGS. 13a to 13f are each schematic plan views showing parts of a display panel according to embodiments of the present invention.

[0044] FIGS. 14a to 14g are schematic perspective views illustrating embodiments of an electronic device including a display panel according to one embodiment of the present invention.

[0045] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0046] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof may not be repeated.

[0047] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0048] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0049] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0050] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0051] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0052] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0053] In the following embodiments, when it is stated that a membrane, region, component, etc. is connected, it includes not only cases where the membrane, region, or component is directly connected, but also cases where other membranes, regions, or components are interposed between them to form an indirect connection. For example, when it is stated in this specification that a membrane, region, component, etc. is electrically connected, it includes not only cases where the membrane, region, or component, etc. are directly electrically connected, but also cases where other membranes, regions, or components are interposed between them to form an indirect electrical connection.

[0054] FIG. 1a is a schematic perspective view of an electronic device (1) according to one embodiment of the present invention, and FIG. 1b is a schematic block diagram of an electronic device (1) according to one embodiment of the present invention.

[0055] Referring to FIGS. 1a and 1b, an electronic device (1) having a display panel (10) according to one embodiment of the present invention is a device for displaying video or still images, and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs). An electronic device (1) according to one embodiment can be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). An electronic device (1) according to one embodiment can be used as a center information display (CID) placed on the center fascia or dashboard of a vehicle, a room mirror display replacing the side mirror of a vehicle, and a display placed on the back of the front seat for entertainment for the rear seat of a vehicle.

[0056] FIG. 1a illustrates an electronic device (1) according to one embodiment being used as a smartphone. The electronic device (1) may include a display panel (10) and a lower cover (90) disposed below the display panel (10). The electronic device (1) may include a cover window covering the upper surface of the display panel (10).

[0057] The lower cover (90) forms the exterior of the electronic device (1) and may have an opening that exposes a portion of the display panel (10) on the front surface. The lower cover (90) may be assembled with the display panel (10) in a shape where the side corresponding to the display panel (10) is open. The lower cover (90) forms the exterior of the lower surface of the electronic device (1), and a display circuit board, components, a main circuit board, a battery, a driver, etc. may be placed between the display panel (10) and the lower cover (90). The lower cover (90) may include plastic (e.g., polymer), metal, or both plastic (e.g., polymer) and metal.

[0058] The electronic device (1) may include a main processor (510), a wireless communication unit (520), an input unit (530), a sensor unit (540), an output unit (550), an interface unit (560), a memory (570), and / or a power supply unit (580).

[0059] The main processor (510) can control all (or substantially all) functions of the electronic device (1). For example, the main processor (510) can output digital video data through a display circuit board to a data driver so that the display panel (10) displays an image. The main processor (510) can receive detection data from a touch sensor driver. The main processor (510) can determine whether a user touches based on the detection data and execute an action corresponding to the user's direct touch or proximity touch. The main processor (510) may be an application processor, a central processing unit, or a system chip made of an integrated circuit.

[0060] The camera device (531) processes image frames, such as still images or video, obtained by an image sensor in camera mode and outputs them to the main processor (510). The camera device (531) may include at least one of a camera sensor (e.g., CCD, CMOS, etc.), a photo sensor (or image sensor), and a laser sensor. The camera device (531) may be connected to an image sensor and process an image input to the image sensor.

[0061] The wireless communication unit (520) may include at least one of a broadcast reception module (521), a mobile communication module (522), a wireless internet module (523), a short-range communication module (524), and a location information module (525).

[0062] The broadcast receiving module (521) receives broadcast signals and / or broadcast-related information from an external broadcast management server through a broadcast channel. The broadcast channel may include a satellite channel and a terrestrial channel.

[0063] A mobile communication module (522) transmits and receives wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network built according to technical standards or communication methods for mobile communication (e.g., GSM (Global System for Mobile communication), CDMA (Code Division Multi Access), CDMA2000 (Code Division Multi Access 2000), EV-DO (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA (Wideband CDMA), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), etc.). The wireless signals may include various forms of data such as voice call signals, video call call signals, or text / multimedia message transmission and reception.

[0064] The wireless internet module (523) refers to a module for wireless internet access. The wireless internet module (523) may be configured to transmit and receive wireless signals in a communication network according to wireless internet technologies. Examples of wireless internet technologies include WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, DLNA (Digital Living Network Alliance), etc.

[0065] The short-range communication module (524) is for short-range communication and can support short-range communication by using at least one of Bluetooth, RFID (Radio Frequency Identification), Infrared Data Association (IrDA), UWB (Ultra Wideband), ZigBee, NFC (Near Field Communication), Wi-Fi (Wireless-Fidelity), Wi-Fi Direct, and Wireless USB (Wireless Universal Serial Bus) technologies. The short-range communication module (524) can support wireless communication between the electronic device (1) and a wireless communication system, between the electronic device (1) and another electronic device, or between the electronic device (1) and a network where another electronic device (or external server) is located, through a short-range wireless communication network. The short-range wireless communication network may be a short-range wireless personal area network. Other electronic devices may be wearable devices capable of exchanging data with (or interoperable with) the electronic device (1).

[0066] The location information module (525) is a module for obtaining the location (or current location) of the electronic device (1) and may include a GPS (Global Positioning System) module or a WiFi (Wireless Fidelity) module.

[0067] The input unit (530) may include a video input unit such as a camera device (531) for inputting a video signal, an audio input unit such as a microphone (532) for inputting an audio signal, and an input device (533) for receiving information from a user.

[0068] The camera device (531) processes image frames, such as still images or video, obtained by an image sensor in video call mode or shooting mode. The processed image frames may be displayed on a display panel (10) or stored in memory (570).

[0069] The microphone (532) processes an external acoustic signal into electrical voice data. The processed voice data can be utilized in various ways depending on the function (or application) being performed on the electronic device (1).

[0070] The main processor (510) can control the operation of the electronic device (1) to correspond to information input through the input device (533). The input device (533) may include mechanical input means or touch input means, such as a button, dome switch, jog wheel, jog switch, etc., located on the rear or side of the electronic device (1). The touch input means may be formed by a touchscreen layer of the display panel (10).

[0071] The sensor unit (540) may include one or more sensors that sense at least one of information within the electronic device (1), surrounding environment information surrounding the electronic device (1), and user information, and generate a corresponding sensing signal. Based on these sensing signals, the main processor (510) may control the operation or function of the electronic device (1), or perform data processing, functions, or operations related to an application installed on the electronic device (1). The sensor unit (540) may include at least one of a proximity sensor, an illumination sensor, an acceleration sensor, a magnetic sensor, a gravity sensor (G-sensor), a gyroscope sensor, a motion sensor, an RGB sensor, an infrared sensor (IR sensor: infrared sensor), a fingerprint sensor, an ultrasonic sensor, an optical sensor, a battery gauge, an environmental sensor (e.g., a barometer, a hygrometer, a thermometer, a radiation detection sensor, a heat detection sensor, a gas detection sensor, etc.), and a chemical sensor (e.g., an electronic nose, a healthcare sensor, a biometric sensor, etc.).

[0072] The output unit (550) is for generating output related to sight, hearing, or touch, and may include at least one of a display panel (10), an acoustic output unit (551), a haptic module (552), and a light output unit (553).

[0073] The display panel (10) displays (outputs) information processed by the electronic device (1). For example, the display panel (10) can display information on the execution screen of an application running on the electronic device (1), or UI (User Interface) and GUI (Graphic User Interface) information based on the execution screen information. The display panel (10) may include a display layer that displays an image and a touchscreen layer that detects touch input from a user. As a result, the display panel (10) can function as one of the input devices (533) that provide an input interface between the electronic device (1) and the user, and at the same time, as one of the output units (550) that provide an output interface between the electronic device (1) and the user.

[0074] The sound output unit (551) can output sound data received from the wireless communication unit (520) or stored in the memory (570) in signal reception, call mode or recording mode, voice recognition mode, broadcast reception mode, etc. The sound output unit (551) may also output sound signals related to functions performed by the electronic device (1) (e.g., call signal reception sound, message reception sound, etc.). The sound output unit (551) may include a receiver and a speaker. At least one of the receiver and the speaker may be a sound generating device attached to the lower part of the display panel (10) to vibrate the display panel (10) and output sound. The sound generating device may be a piezoelectric element or a piezoelectric actuator that contracts and expands according to an electrical signal, or an exciter that generates magnetic force using a voice coil to vibrate the display panel (10).

[0075] The haptic module (552) generates various tactile effects that the user can feel. The haptic module (552) can provide vibration to the user as a tactile effect. The haptic module (552) can not only transmit tactile effects through direct contact, but can also be implemented so that the user can feel tactile effects through the sense of touch of fingers or arms.

[0076] The light output unit (553) outputs a signal to indicate the occurrence of an event using light from a light source. Examples of events occurring in the electronic device (1) may include receiving a message, receiving a call signal, a missed call, an alarm, a schedule notification, receiving an email, receiving information through an application, etc. The signal output by the light output unit (553) is implemented as the electronic device (1) emits single-color or multiple-color light from the front or back. The signal output may be terminated when the electronic device (1) detects the user's confirmation of the event.

[0077] The interface section (560) serves as a passage for various types of external devices connected to the electronic device (1). The interface section (560) may include at least one of a wired / wireless headset port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting a device equipped with an identification module, an audio I / O (Input / Output) port, a video I / O (Input / Output) port, and an earphone port. The electronic device (1) can perform appropriate control related to the connected external device in response to the external device being connected to the interface section (560).

[0078] The memory (570) stores data that supports various functions of the electronic device (1). The memory (570) can store a number of application programs running on the electronic device (1), data for the operation of the electronic device (1), and commands. At least some of the number of applications can be downloaded from an external server via wireless communication. The memory (570) can store applications for the operation of the main processor (510) and can temporarily store input / output data, such as phonebooks, messages, still images, videos, etc. Additionally, the memory (570) can store haptic data for various patterns of vibration provided to the haptic module (552) and acoustic data regarding various sounds provided to the sound output unit (551). The memory (570) may include at least one type of storage medium among flash memory type, hard disk type, SSD type (Solid State Disk type), SSD type (Silicon Disk Drive type), multimedia card micro type, card type memory (e.g., SD or XD memory, etc.), RAM (random access memory; RAM), SRAM (static random access memory), ROM (read-only memory; ROM), EEPROM (electrically erasable programmable read-only memory), PROM (programmable read-only memory), magnetic memory, magnetic disk, and optical disk.

[0079] The power supply unit (580), under the control of the main processor (510), receives external power and internal power and supplies power to each component included in the electronic device (1). The power supply unit (580) may include a battery. Additionally, the power supply unit (580) is provided with a connection port, and the connection port may be configured as an example of an interface unit (560) to which an external charger that supplies power for charging the battery is electrically connected. Alternatively, the power supply unit (580) may be configured to charge the battery wirelessly without using the connection port.

[0080] FIG. 2 is a schematic perspective view of a display panel (10) according to an embodiment of the present invention. FIG. 3a and FIG. 3b are perspective views showing the display panel (10) of FIG. 2 extended in a first direction. FIG. 3c is a perspective view showing the display panel (10) of FIG. 1 extended in a second direction. FIG. 3d is a perspective view showing the display panel (10) of FIG. 1 extended in the first direction and the second direction. FIG. 3e is a perspective view showing the display panel (10) of FIG. 1 extended in a third direction.

[0081] Referring to FIG. 2, the display panel (10) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a plurality of pixels. The display panel (10) may provide a predetermined image using light emitted from a plurality of pixels. The non-display area (NDA) may be placed outside the display area (DA). The non-display area (NDA) may completely surround the display area (DA).

[0082] The display panel (10) can be extended or retracted in various directions. The display panel (10) can be extended in a first direction (e.g., x direction and / or -x direction) by an external force applied by an external object or a user. In one embodiment, as shown in FIGS. 3a and 3b, the display area (DA) and / or non-display area (NDA) of the display panel (10) can be extended in a first direction (e.g., x direction and / or -x direction). For example, as shown in FIG. 3a, it can be extended along the x direction and -x direction, or as shown in FIG. 3b, it can be extended along the x direction while one side of the display panel (10) remains fixed.

[0083] The display panel (10) can be extended in a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a user. In one embodiment, as shown in FIG. 3c, the display area (DA) and / or non-display area (NDA) of the display panel (10) can be extended in the y direction and the -y direction. In another embodiment, one side of the display panel (10) can be extended in the y direction or the -y direction while remaining fixed.

[0084] The display panel (10) can be extended in multiple directions, such as a first direction (e.g., x direction and / or -x direction) and a second direction (e.g., y direction and / or -y direction) by an external force applied by an external object or a part of a person's body. As shown in FIG. 3d, the display area (DA) and / or non-display area (NDA) of the display panel (10) can be extended in the ±x direction and ±y direction.

[0085] The display panel (10) can be extended in a third direction (e.g., the z direction or the -z direction) by an external force applied by an external object or a part of a person's body. In one embodiment, FIG. 3e illustrates a part of the display panel (10), such as a part of the display area (DA), protruding in the z direction. In another embodiment, a part of the display panel (10), such as a part of the display area (DA), may protrude along the z direction (or be sunken along the -z direction).

[0086] FIGS. 3a to 3e illustrate a display device (1) extended in a first direction, a second direction and / or a third direction, but the present invention is not limited thereto. In another embodiment, the display panel (10) may be varied into an irregular shape, such as having two or more axes, bent or twisted.

[0087] FIG. 4 is a schematic plan view showing a display panel (10) according to one embodiment of the present invention.

[0088] Referring to FIG. 4, the display panel (10) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). Pixels (P) are arranged in the display area (DA) of the substrate (100). Each pixel (P) can display an image using light emitted from a light-emitting element, such as a light-emitting diode. Each light-emitting diode can emit light, for example, red, green, or blue.

[0089] Each light-emitting diode may be electrically connected to a pixel circuit, and each pixel circuit may include transistors and a storage capacitor. Each pixel circuit may be electrically connected to peripheral circuits and peripheral wiring located in a non-display area (NDA). Peripheral circuits located in the non-display area (NDA) may include a gate driving circuit (GDC) and a terminal section (PAD). Peripheral wiring may include a driving voltage supply line (W11), a common voltage supply line (W13), and a fan-out line (FW).

[0090] The gate driving circuit (GDC) may include drivers for providing an electrical signal to the gate electrode of each of the transistors electrically connected to the light-emitting elements. Specifically, the gate driving circuit (GDC) may apply a scan signal to each of the pixel circuits corresponding to the pixels (P) through the gate line (GL).

[0091] The gate driving circuit (GDC) may include a first gate driving circuit (GDC1) and a second gate driving circuit (GDC2) positioned on both sides with the display area (DA) in between. The second gate driving circuit (GDC2) may be located on the opposite side of the first gate driving circuit (GDC1) with respect to the display area (DA) and may be approximately parallel to the first gate driving circuit (GDC1). Some of the pixel circuits may be electrically connected to the first gate driving circuit (GDC1), and the rest may be electrically connected to the second gate driving circuit (GDC2). In some embodiments, the second gate driving circuit (GDC2) may be omitted.

[0092] A terminal portion (PAD) may be disposed on one side of the substrate (100). The terminal portion (PAD) is exposed without being covered by an insulating layer (e.g., an electrical insulating layer) and is connected to a display circuit board (30). A display driving unit (32) may be disposed on the display circuit board (30). The display driving unit (32) may generate a control signal to be transmitted to a first gate driving circuit (GDC1) and a second gate driving circuit (GDC2). The display driving unit (32) generates a data signal, and the generated data signal may be transmitted to the pixel circuits of pixels (P) through a fan-out wiring (FW) and a data line (DL) connected to the fan-out wiring (FW).

[0093] The display driving unit (32) can supply a first power supply voltage (VDD, FIG. 7a) to the driving voltage supply wire (W11) and a second power supply voltage (VSS, FIG. 7a) to the common voltage supply wire (W13). The first power supply voltage (VDD, FIG. 7a) is applied to the pixel circuit of the pixel (P) through the driving voltage line (PL) connected to the driving voltage supply wire (W11), and the second power supply voltage (VSS, FIG. 7a) is connected to the common voltage supply wire (W13) and can be applied to the opposing electrode of the light-emitting element. The driving voltage supply wire (W11) may be provided extending along the x-direction from the lower side of the display area (DA). The common voltage supply wire (W13) may have a loop shape with one side open, so as to partially surround the display area (DA).

[0094] FIG. 5 is a plan view schematically showing the arrangement of pixels of a display panel (10) according to one embodiment of the present invention.

[0095] Referring to FIG. 5, the display area (DA) may include first areas (11) and a second area (12) surrounding each of the first areas (11). The first areas (11) may be arranged repeatedly along a first direction (e.g., x direction) and a second direction (e.g., y direction).

[0096] The display area (DA) may include first areas (11) and second areas (12) with different elongation rates. For example, the display panel (10) may include a first area (11) with a relatively small elongation rate and a second area (12) with a relatively large elongation rate. In this specification, elongation rate is a numerical value representing the change in length (ΔL / L) by which the display panel (10) can be stretched without physical damage to the display panel (10) when an external force is applied to the display panel (10). Here, ΔL is the amount of change in length of the display panel (10), and L represents the initial length of the display panel (10). Accordingly, the elongation rate of each of the first area (11) and the second area (12) may represent the change in length of each of the first area (11) and the second area (12) when the same external force is applied to the first area (11) and the second area (12).

[0097] The fact that the elongation rate of the first region (11) is smaller than the elongation rate of the second region (12) indicates that the deformation of the first region (11) due to external force occurs relatively less. Therefore, the first region (11) can be called a low-deformation region and the second region (12) can be called a high-deformation region.

[0098] The first regions (11) may be spaced apart from each other and arranged two-dimensionally in the display area (DA). The first region (11) may be an area where pixels are placed, and thus, the first region (11) may be referred to as a pixel area or a light-emitting area. One or more pixels may be placed in each first region (11). A pixel unit (PU) comprising a set of pixels may be provided in the first region (11), and each pixel unit (PU) may include a red pixel (PXr), a green pixel (PXg), and a blue pixel (PXb).

[0099] The second region (12) may be located between adjacent first regions (11). As illustrated in FIG. 5, the second region (12) may have a shape that surrounds each of the first regions (11). The second region (12) may be an area through which a connection line passes to electrically connect pixel circuits (PC, FIG. 4) placed in each of the two adjacent first regions (11).

[0100] FIG. 6 is a cross-sectional view schematically showing a part of a display panel according to one embodiment of the present invention.

[0101] Referring to FIG. 6, the display area (DA) may include first areas (11) and a second area (12), and the second area (12) may be an area connecting the first areas (11) that are arranged adjacent to each other. The first area (11) is an area with a relatively smaller elongation rate than the second area (12) and may include a light-emitting diode (LED) and a pixel circuit (PC). The second area (12) is an area with a relatively larger elongation rate than the first area (11) and may include a connection line (WL) included in a signal line that supplies a signal to each of the pixel circuits (PC).

[0102] A first region (11) and a second region (12) may be formed on a base layer (400). In other words, the base layer (400) may have a first region (11) and a second region (12) defined on it. A light-emitting diode (LED) and a pixel circuit (PC) may be placed on the first region (11) of the base layer (400), and a connection line (WL) may be placed on the second region (12) of the base layer (400).

[0103] The base layer (400) can absorb stress that may occur during the stretching of the display panel (10). The base layer (400) may include an elastomer. For example, the base layer (400) is thermoplastic polyurethane, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, fluoroelastomers, ethylene-vinyl acetate, PDMS (polydimethylsiloxane), and It may include at least one of the ecoflex.

[0104] A display layer (200) may be disposed on a first region (11) of a base layer (400). The display layer (200) may include an inorganic insulating layer (IIL) (e.g., an inorganic electrical insulating layer), a pixel circuit (PC), an organic insulating layer (OIL) (e.g., an organic electrical insulating layer), and a light-emitting diode (LED). A pixel circuit (PC) may be disposed on the base layer (400), and an inorganic insulating layer (IIL) may be disposed between electrodes included in the pixel circuit (PC). An organic insulating layer (OIL) may be disposed on the inorganic insulating layer (IIL) to cover the pixel circuit (PC). A light-emitting diode (LED) may be disposed on the organic insulating layer (OIL) and may be electrically connected to the corresponding pixel circuit (PC). The inorganic insulating layer (IIL) may include an inorganic insulating material such as silicon nitride and / or silicon oxide (e.g., an inorganic electrical insulating layer), and the organic insulating layer (OIL) may include an organic insulating material such as polyimide (e.g., an organic electrical insulating layer).

[0105] In one embodiment, a pixel unit (PU) may be disposed on one first region (11). As previously described, the pixel unit (PU) may include a red pixel (PXr, FIG. 5), a green pixel (PXg, FIG. 5), and a blue pixel (PXb, FIG. 5). The red pixel (PXr, FIG. 5a) may include a first light-emitting diode (LED1), the green pixel (PXg, FIG. 5a) may include a second light-emitting diode (LED2), and the blue pixel (PXb) may include a third light-emitting diode (LED3). For example, the first light-emitting diode (LED1) may emit red light, the second light-emitting diode (LED2) may emit green light, and the third light-emitting diode (LED3) may emit blue light. In some embodiments, the light-emitting diode (LED) may emit white light.

[0106] A connection line (WL) may be disposed on the second region (12) of the base layer (400). In one embodiment, as shown in FIG. 6, the connection line (WL) may be disposed on the base layer (400) but may be disposed relatively lower than the display layer (200). In other words, the base layer (400) may be disposed to cover the connection line (WL) disposed on the back surface of the display layer (200). Accordingly, the thickness of the base layer (400) corresponding to the second region (12) may be smaller than the thickness of the base layer (400) corresponding to the first region (11). However, it is not limited thereto, and in another embodiment, the connection line (WL) may be disposed on the base layer (400) but may be disposed on a layer substantially identical to some of the layers of the display layer (200).

[0107] The connecting lines (WL) may include a material having both excellent elasticity and electrical properties. In one embodiment, the connecting lines (WL) placed in the second region (12) may include liquid metal. In another embodiment, the connecting lines may include metal nanostructures and elastic polymers. In yet another embodiment, the connecting lines may include a conductive composite material (e.g., an electrically conductive composite material) containing an elastomer.

[0108] In one embodiment, a protective layer (300) may be disposed on the light-emitting diode (LED). The protective layer (300) may be disposed on both the first region (11) and the second region (12). That is, the protective layer (300) may be disposed to cover the entire display area (DA). The protective layer (300) may cover the light-emitting diode (LED) and the connection line (WL). The protective layer (300) may absorb stress that may occur when the display panel (10) is stretched. Specifically, the protective layer (300) may serve to prevent or reduce stress that may occur when the display panel (10) is stretched from being transmitted to the light-emitting diode (LED) and the pixel circuit (PC).

[0109] The protective layer (300) may include an elastic polymer. The protective layer (300) may include at least one of thermoplastic polyurethane, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, and fluoroelastomers, ethylene-vinyl acetate, and PDMS (polydimethylsiloxane). There is. In one embodiment, the protective layer (300) may include the same material as the base layer (400). However, it is not limited thereto, and the protective layer (300) may include a different material from the base layer (400).

[0110] FIGS. 7a to 7c are each equivalent circuit diagrams of pixels of a display panel (10) according to one embodiment of the present invention.

[0111] Referring to FIG. 7a, a light-emitting diode (LED) corresponding to a pixel is electrically connected to a pixel circuit (PC), and the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). The pixel circuit (PC) may be electrically connected to signal lines and voltage lines. The signal lines may include a gate line (GL, FIG. 4), such as a scan signal line (GWL), and a data line (DL), and the voltage lines may include a first voltage line (VDDL). In this case, the first voltage line (VDDL) may be connected to a driving voltage supply line (W11, FIG. 4), and the second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 4).

[0112] The second transistor (T2) can be electrically connected to the scan signal line (GWL) and the data line (DL). The scan signal line (GWL) can provide a scan signal (GW) to the gate electrode of the second transistor (T2). The second transistor (T2) can transmit a data signal (Dm) input from the data line (DL) to the first transistor (T1) according to the scan signal (GW) input from the scan signal line (GWL).

[0113] The storage capacitor (Cst) is electrically connected to the second transistor (T2) and the first voltage line (VDDL), and can store a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the first power supply voltage (VDD) supplied by the first voltage line (VDDL).

[0114] The first transistor (T1) is a driving transistor and can control the driving current flowing through the light-emitting diode (LED). The first transistor (T1) can be connected to the first voltage line (VDDL) and the storage capacitor (Cst). The first transistor (T1) can control the driving current flowing from the first voltage line (VDDL) to the light-emitting diode (LED) in correspondence with the voltage value stored in the storage capacitor (Cst). The light-emitting diode (LED) can emit light having a predetermined brightness by the driving current. The first electrode of the light-emitting diode (LED) is electrically connected to the first transistor (T1), and the second electrode can be electrically connected to the second voltage line (VSSL) that supplies the second power supply voltage (VSS).

[0115] FIG. 7a illustrates a pixel circuit (PC) comprising two transistors and one storage capacitor, but in other embodiments, the pixel circuit (PC) may comprise three or more transistors.

[0116] Referring to FIG. 7b, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a storage capacitor (Cst).

[0117] The pixel circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines (GL, FIG. 4), such as scan signal lines (GWL), bypass control lines (GBL), initialization control lines (GIL), and light emission control lines (EML), and data lines (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2) and a first voltage line (VDDL). In this case, the first voltage line (VDDL) may be connected to a driving voltage supply line (W11, FIG. 4), and the second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 4).

[0118] The first voltage line (VDDL) can transmit a first power supply voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) that initializes the first electrode of the light-emitting diode (LED) to the pixel circuit (PC).

[0119] The first transistor (T1) can be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The first transistor (T1) acts as a driving transistor and receives a data signal (Dm) according to the switching operation of the second transistor (T2) and supplies a driving current to the light-emitting diode (LED).

[0120] The second transistor (T2) is a data write transistor and is electrically connected to the scan signal line (GWL) and the data line (DL). The second transistor (T2) is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5). The second transistor (T2) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0121] The third transistor (T3) is electrically connected to the scan signal line (GWL) and is electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The third transistor (T3) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and can diode-connect the first transistor (T1).

[0122] The fourth transistor (T4) is the first initialization transistor and is electrically connected to the initialization control line (GIL) and the first initialization voltage line (VIL1). The fourth transistor (T4) is turned on according to the initialization control signal (GI) received through the initialization control line (GIL) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1), thereby initializing the voltage of the gate electrode of the first transistor (T1). The initialization control signal (GI) may correspond to a scan signal of another pixel circuit placed in the previous row of the corresponding pixel circuit (PC).

[0123] The fifth transistor (T5) may be an operation control transistor, and the sixth transistor (T6) may be a light emission control transistor. The fifth transistor (T5) and the sixth transistor (T6) are electrically connected to the light emission control line (EML) and are simultaneously turned on according to the light emission control signal (EM) received through the light emission control line (EML) to form a current path (e.g., an electrical current path) so that a driving current can flow from the first voltage line (VDDL) toward the light-emitting diode (LED).

[0124] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the bypass control line (GBL), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL), and can initialize the first electrode of the light-emitting diode (LED) by transmitting the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting diode (LED).

[0125] The storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the first voltage line (VDDL). The storage capacitor (Cst) can maintain the voltage applied to the gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to the difference between the voltages of the first voltage line (VDDL) and the gate electrode of the first transistor (T1).

[0126] Referring to FIG. 7c, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), a storage capacitor (Cst), and an auxiliary capacitor (Ca).

[0127] The pixel circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines (GL, FIG. 4), such as scan signal lines (GWL), bypass control lines (GBL), initialization control lines (GIL), and light emission control lines (EML), and data lines (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), holding voltage lines (VSL), and first voltage lines (VDDL). In this case, the first voltage line (VDDL) may be connected to a driving voltage supply line (W11, FIG. 4), and the second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 4).

[0128] The first voltage line (VDDL) can transmit a first power supply voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) that initializes the first electrode of the light-emitting diode (LED) to the pixel circuit (PC). The holding voltage line (VSL) can provide a holding voltage (VSUS) to the second electrode (CE2) of the second node (N2), for example, the storage capacitor (Cst), during the initialization period and the data writing period.

[0129] The first transistor (T1) can be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8), and can be electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The first transistor (T1) acts as a driving transistor and can receive a data signal (Dm) according to the switching operation of the second transistor (T2) and supply a driving current to the light-emitting diode (LED).

[0130] The second transistor (T2) is electrically connected to the scan signal line (GWL) and the data line (DL), and is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8). The second transistor (T2) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0131] The third transistor (T3) is electrically connected to the scan signal line (GWL) and is electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The third transistor (T3) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and connects the first transistor (T1) to the diode, thereby compensating for the threshold voltage of the first transistor (T1).

[0132] The fourth transistor (T4) is electrically connected to the initialization control line (GIL) and the first initialization voltage line (VIL1), and is turned on according to the initialization control signal (GI) received through the initialization control line (GIL) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The initialization control signal (GI) may correspond to a scan signal of another pixel circuit placed in the previous row of the corresponding pixel circuit (PC).

[0133] The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are electrically connected to the light emission control line (EML) and are simultaneously turned on according to the light emission control signal (EM) received through the light emission control line (EML) to form a current path (e.g., an electrical current path) so that a driving current can flow from the first voltage line (VDDL) toward the light-emitting diode (LED).

[0134] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the bypass control line (GBL), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL) and transmits the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting diode (LED) to initialize the first electrode of the light-emitting diode (LED).

[0135] The ninth transistor (T9) can be electrically connected to the bypass control line (GBL), the second electrode (CE2) of the storage capacitor (Cst), and the holding voltage line (VSL). The ninth transistor (T9) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL), and can transmit a holding voltage (VSUS) to the second node (N2), such as the second electrode (CE2) of the storage capacitor (Cst), during the initialization period and the data writing period.

[0136] The eighth transistor (T8) and the ninth transistor (T9) can each be electrically connected to the second node (N2), for example, the second electrode (CE2) of the storage capacitor (Cst). In some embodiments, the eighth transistor (T8) may be turned off and the ninth transistor (T9) may be turned on during the initialization period and the data writing period, and the eighth transistor (T8) may be turned on and the ninth transistor (T9) may be turned off during the light emission period. Since the second node (N2) receives the holding voltage (VSUS) during the initialization period and the data writing period, the uniformity of the brightness of the display device (e.g., LRU, Long Range Uniformity) due to the voltage drop of the first voltage line (VDDL) can be improved.

[0137] The storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the eighth transistor (T8) and the ninth transistor (T9).

[0138] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the holding voltage line (VSL), and the first electrode of the light-emitting diode (LED). By storing and maintaining a voltage corresponding to the voltage difference between the first electrode of the light-emitting diode (LED) and the holding voltage line (VSL) while the seventh transistor (T7) and the ninth transistor (T9) are turned on, the auxiliary capacitor (Ca) can prevent or reduce the problem of the black brightness rising when the sixth transistor (T6) is off.

[0139] FIGS. 8a to 8d are cross-sectional views schematically showing a light-emitting diode of a display panel (10) according to one embodiment of the present invention.

[0140] Referring to FIG. 8a, the light-emitting diode (LED) may include an inorganic light-emitting diode containing an inorganic material. The light-emitting diode (LED) may include a first semiconductor layer (231), a second semiconductor layer (232), an intermediate layer (233) between the first semiconductor layer (231) and the second semiconductor layer (232), a first electrode (235) electrically connected to the first semiconductor layer (231), and a second electrode (238) electrically connected to the second semiconductor layer (232). The first electrode (235) and the second electrode (238) of the light-emitting diode (LED) may each be electrically connected to a first electrode pad (241) and a second electrode pad (242) disposed on the same layer. The second electrode pad (242) may be a part of the second voltage line (VSSL, FIG. 7a) or a conductive layer (e.g., an electrical conductive layer) electrically connected to the second voltage line (VSSL, FIG. 7a).

[0141] In some embodiments, the first semiconductor layer (231) may include a p-type semiconductor layer. The p-type semiconductor layer may be selected from semiconductor materials having the compositional formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with p-type dopants such as Mg, Zn, Ca, Sr, Ba, etc.

[0142] The second semiconductor layer (232) may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be selected from semiconductor materials having the composition formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with n-type dopants such as Si, Ge, and Sn.

[0143] The intermediate layer (233) is a region where electrons and holes recombine, and as electrons and holes recombine, they transition to a lower energy level and can generate light having a corresponding wavelength. The intermediate layer (233) can be formed by including a semiconductor material having a composition formula of, for example, InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and can be formed as a single quantum well structure or a multi-quantum well (MQW) structure. Additionally, the intermediate layer (233) may include a quantum wire structure or a quantum dot structure.

[0144] FIG. 8a illustrates that the first semiconductor layer (231) includes a p-type semiconductor layer and the second semiconductor layer (232) includes an n-type semiconductor layer, but the present invention is not limited thereto. In another embodiment, the first semiconductor layer (231) may include an n-type semiconductor layer and the second semiconductor layer (232) may include a p-type semiconductor layer.

[0145] FIG. 8a illustrates that the first electrode pad (241) and the second electrode pad (242) are disposed on the same layer, but the present invention is not limited thereto. Referring to FIG. 8b, the first electrode pad (241) and the second electrode pad (242) may be disposed on different layers. For example, a bank layer (230) having an opening that overlaps with at least a portion of the first electrode pad (241) may be disposed on the first electrode pad (241), and the second electrode pad (242) may be disposed on the upper surface of the bank layer (230). The structure of the light-emitting diode (LED) illustrated in FIG. 8b is the same as previously described with reference to FIG. 8a.

[0146] In another embodiment, as shown in FIG. 8c, the second electrode pad (242) may be positioned on both sides centered on the first electrode pad (241) in a cross-sectional view. The bank layer (230) includes an opening that overlaps at least a portion of the first electrode pad (241), and the second electrode pad (242) may be positioned around the opening of the bank layer (230). In some embodiments, the second electrode pad (242) may have a closed-loop shape that completely surrounds the opening of the bank layer (230) and / or the first electrode pad (241) in a planar view. The structure of the light-emitting diode (LED) shown in FIG. 8c is the same as previously described with reference to FIG. 8a.

[0147] FIGS. 8a to 8c illustrate the first electrode (235) and the second electrode (238) of a light-emitting diode (LED) facing in the same direction (e.g., downward direction, -z direction), but the present invention is not limited thereto. As shown in FIG. 8d, the first electrode (235) and the second electrode (238) of the light-emitting diode (LED) may face in opposite directions.

[0148] The bank layer (230) includes an opening that exposes at least a portion of the first electrode pad (241), and the thickness of the bank layer (230) may be substantially the same as the thickness of the light-emitting diode (LED). The opening of the bank layer (230) may be filled with a filling material (FM), and the second electrode pad (242) may be disposed on the upper surface of the bank layer (230) so as to be electrically connected (e.g., in contact) with the second electrode (238) of the light-emitting diode (LED). The filling material (FM) may be an organic material having insulating properties (e.g., electrical insulating properties).

[0149] FIG. 9 is a schematic plan view showing a part of a display panel (10) according to an embodiment of the present invention. FIG. 10 is a schematic plan view showing a part of a display panel (10) according to an embodiment of the present invention. FIG. 9 and FIG. 10 are each schematic plan views showing area A of the display panel (10) of FIG. 4. FIG. 9 is a schematic plan view showing a part of the front surface of a display panel (10) according to an embodiment of the present invention, and FIG. 10 is a schematic plan view showing a part of the back surface of a display panel (10) according to an embodiment of the present invention.

[0150] First, referring to FIG. 9, the display area (DA) may include a plurality of first areas (11) and a second area (12) surrounding the plurality of first areas (11). The first area (11) may have a smaller elongation rate than the second area (12). Accordingly, when the display panel (10) is stretched, the first area (11) may undergo less deformation than the second area (12). The first area (11) may be referred to as a low-deformation area (or low-deformation part) as previously described. Additionally, the first area (11) may be referred to as a pixel area or a light-emitting area as an area where light-emitting diodes are arranged.

[0151] The second region (12) surrounds the first region (11) and may have a greater elongation rate than the first region (11). The second region (12) may be an area where the main deformation occurs according to the stretching of the display device. Since the second region (12) is positioned between a plurality of first regions (11), it may be referred to as a connecting part that connects the first regions (11). Additionally, the second region (12) may be referred to as a main deformation area (or peripheral deformation part) or a high deformation area (or high deformation part). The second region (12) may be referred to as a non-pixel area or a non-luminous area, as it is an area within the display area (DA) where a light-emitting diode is not positioned.

[0152] A pixel circuit (PC) for driving a light-emitting diode (LED) of each pixel may be placed in a first region (11). For example, a first pixel circuit (PC1) for a red pixel (PXr, FIG. 5), a second pixel circuit (PC2) for a green pixel (PXg, FIG. 5), and a third pixel circuit (PC3) for a blue pixel (PXb, FIG. 5) may be placed in the first region (11). The first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may each include a transistor and a capacitor, as described with reference to FIGS. 7a to 7c.

[0153] Lines electrically connected to the pixel circuit (PC) may be placed in the display area (DA). The aforementioned lines may include voltage lines or signal lines. In one embodiment, FIG. 7 illustrates that a gate line (GL) and a data line (DL) are each placed in the first area (11). The gate line (GL) and the data line (DL) may each be electrically connected to the pixel circuit (PC) through a contact hole.

[0154] The gate line (GL) of FIG. 9 is a line that provides a gate signal to the gate electrode of a transistor. In one embodiment, the gate line (GL) may include a first gate line (GL1), a second gate line (GL2), and a third gate line (GL3). The first to third gate lines (GL1, GL2, GL3) extending in a first direction (e.g., x-direction) may each be connected to pixel circuits (PCs) arranged in the same row to transmit different gate signals. For example, the gate line (GL) of FIG. 9 may be the scan signal line (GWL), bypass control line (GBL), initialization control line (GIL), and / or light emission control line (EML) of FIG. 7b or FIG. 7c.

[0155] The data line (DL) of FIG. 9 is a line that provides a data signal to each pixel circuit (PC). The data line (DL) extended in a second direction (e.g., the y-direction) may be electrically connected to pixel circuits (PCs) arranged in the same column. In one embodiment, the data line (DL) may include a first data line (DL1) electrically connected to a first pixel circuit (PC1), a second data line (DL2) electrically connected to a second pixel circuit (PC2), and a third data line (DL3) electrically connected to a third pixel circuit (PC3).

[0156] Two adjacent signal lines placed in each of two adjacent first regions (11) can be electrically connected by a connection line (WL). Specifically, two adjacent data lines (DL) placed in each of two adjacent first regions (11) can be electrically connected by a first connection line (WL1, or vertical connection line). The first connection line (WL1) is placed in the second region (12) and can extend in a second direction (e.g., the y-direction). Each of the data lines (DL) placed on opposite sides of the first connection line (WL1) can be connected to the first connection line (WL1).

[0157] Two adjacent gate lines (GL) placed in each of two adjacent first regions (11) may be electrically connected by a second connection line (WL2, or horizontal connection line). The second connection line (WL2) is placed in the second region (12) and may extend in a first direction (e.g., x-direction). Each of the gate lines (GL) placed on opposite sides of the second connection line (WL2) may be connected to the second connection line (WL2).

[0158] The gate line (GL) and the data line (DL) may intersect each other in the first region (11). In one embodiment, the data line (DL) may include a first part (DLa) and a second part (DLb) separated by the gate line (GL), and a bridge line (BL) positioned between the first part (DLa) and the second part (DLb). The first part (DLa) and the second part (DLb) may be electrically connected by the bridge line (BL).

[0159] A bridge line (BL) is placed in the area where a data line (DL) and a gate line (GL) intersect, and can connect a first part (DLa) and a second part (DLb) of the data line (DL). The bridge line (BL) can be placed on a different layer from the first part (DLa) and the second part (DLb). One end of the bridge line (BL) is connected to the first part (DLa) through a contact hole, and the other end of the bridge line (BL) can be connected to the second part (DLb) through another contact hole.

[0160] FIG. 9 illustrates a data line (DL) connected through a first part (DLa), a second part (DLb), and a bridge line (BL), but the present invention is not limited thereto. In another embodiment, a gate line (GL) may be separated into a first part and a second part and connected through a bridge line.

[0161] The first and second connection lines (WL1, WL2) placed in the second region (12) can be stretched better than the gate line (GL) and data line (DL) placed in the first region (11). The elongation rate of each of the first and second connection lines (WL1, WL2) can be greater than the elongation rate of each of the gate line (GL) and data line (DL).

[0162] The gate line (GL) and the data line (DL) may each comprise one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the gate line (GL) and the data line (DL) may each be a single layer or a plurality of layers containing the aforementioned metals. In one embodiment, the gate line (GL) and the data line (DL) may each comprise a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0163] The first and second connecting lines (WL1, WL2) may include liquid metal or a conductive composite material (e.g., an electrically conductive composite material) including a metal nanostructure, an elastic polymer, and / or an elastomer. Accordingly, when the display panel (10) is stretched, high deformation may occur in the first and second connecting lines (WL1, WL2) and the second region (12).

[0164] FIG. 9 illustrates that the gate line (GL) and the data line (DL) are electrically connected to the second connection line (WL2) and the first connection line (WL1), respectively, but the present invention is not limited thereto. As another embodiment, the first initialization voltage line (VIL1), the second initialization voltage line (VIL2), the holding voltage line (VSL), the first voltage line (VDDL), or the second voltage line (VSSL) described with reference to FIG. 7a to 7c may each be placed in the first region (11) and electrically connected to the connection line (WL) placed in the second region (12).

[0165] Next, FIG. 10 is a schematic plan view of a portion of the display area (DA) as seen from the rear direction of the display panel (10). Although not shown in FIG. 9 for convenience of explanation, in one embodiment, an auxiliary pattern (AP) may be arranged to cover both ends of the connection line (WL). That is, the ends of the connection line (WL) are fixed to the auxiliary pattern (AP), so that the display panel (10) may have a shape in which the ends of the connection line (WL) are embedded in the auxiliary pattern (AP). In other words, the auxiliary pattern (AP) may have a shape that caps the edges of the connection line (WL).

[0166] In one embodiment, a plurality of auxiliary patterns (AP) may be spaced apart from each other in a first area (11). As shown in FIG. 10, the ends of a plurality of connecting lines (WL) may be placed in a first area (11). For example, the ends of a plurality of first connecting lines (WL1) and the ends of a plurality of second connecting lines (WL2) may be placed in the first area (11). That is, the ends of the plurality of connecting lines (WL) and the auxiliary patterns (AP) may be placed in the first area (11), and the portions of the plurality of connecting lines (WL) excluding the ends may be placed in the second area (12). At this time, the plurality of auxiliary patterns (AP) may cover the ends of each connecting line (WL) and may be spaced apart from each other. In one embodiment, the auxiliary patterns (AP) may each have a rectangular shape in a planar shape. However, they are not limited thereto, and the auxiliary patterns (AP) may have a polygonal shape excluding a rectangle.

[0167] In one embodiment, the modulus of the auxiliary pattern (AP) may be greater than the modulus of the connecting line (WL). Specifically, the modulus of the auxiliary pattern (AP) may have a value in the range of 10 to 5000 times the modulus of the connecting line (WL). For example, the auxiliary pattern (AP) may be composed of a material including a nanocomposite. However, the material of the auxiliary pattern (AP) is not limited thereto, and the auxiliary pattern (AP) may include other materials having a modulus in the above range.

[0168] Typically, the larger the modulus of a material, the better the recovery rate, and the smaller the modulus of a material, the better the elongation rate. As in one embodiment of the present invention, when the auxiliary pattern (AP) has a relatively larger modulus than the connecting line (WL), the auxiliary pattern (AP) may have superior stiffness and recovery rate compared to the connecting line (WL), and the connecting line (WL) may have superior elasticity compared to the auxiliary pattern (AP).

[0169] As previously explained, when the display panel (10) is stretched, relatively higher deformation may occur in the second region (12) than in the first region (11). Accordingly, stress may be concentrated at the end of the connecting line (WL) placed on the boundary between the first region (11) and the second region (12). At this time, if an auxiliary pattern (AP) with a large modulus is placed to cover the end of the connecting line (WL), the auxiliary pattern (AP) can relieve the stress concentrated at the end of the connecting line (WL), and the deformation of the first region (11) that may occur during stretching can be minimized or reduced, thereby ensuring the stability of the device. That is, the display panel (10) according to one embodiment of the present invention can simultaneously achieve stretchability and mechanical stability of the display panel (10) by placing an auxiliary pattern (AP) with a large modulus at the end of the connecting line (WL).

[0170] FIG. 11 is a cross-sectional view schematically showing a part of a display panel (10) according to one embodiment of the present invention. FIG. 12 is a perspective view showing the first line, second line, connecting line, and auxiliary pattern of FIG. 11.

[0171] Referring to FIG. 11, the display panel (10) may include first regions (11) and a second region (12) between the first regions (11), as previously described with reference to FIG. 9 and FIG. 10. Since the components of the display panel (10) are placed on a base layer (400), the statement that the display panel (10) includes first regions (11) and a second region (12) may correspond to the base layer (400) including first regions (11) and a second region (12).

[0172] The display panel (10) may include a pixel circuit layer (PCL) and a light-emitting diode (LED) on the pixel circuit layer (PCL) disposed in each of two adjacent first regions (11). The light-emitting diode (LED) shown in FIG. 11 may correspond to any one of the first to third light-emitting diodes (LED1, LED2, LED3) shown in FIG. 6.

[0173] Each pixel circuit layer (PCL) may include an inorganic insulating stack (IIL) (e.g., an inorganic electrical insulating stack), a pixel circuit (PC), and an organic insulating layer (OIL) (e.g., an organic electrical insulating stack). For convenience of explanation, one of the pixel circuit layers (PCLs) disposed in each of two adjacent first regions (11) is referred to as the first pixel circuit layer (PCL1), and the other as the second pixel circuit layer (PCL2).

[0174] The first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) may each be disposed on the base layer (400). The first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) may each be disposed on the first surface (e.g., the top surface) of the base layer (400).

[0175] The base layer (400) can absorb stress generated during the stretching of the display panel (10). The base layer (400) may include an elastomer. The base layer (400) is thermoplastic polyurethane, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, fluoroelastomers, ethylene-vinyl acetate, PDMS (polydimethylsiloxane), and It may include at least one of the ecoflex.

[0176] Each of the first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) may include an inorganic insulating stack (IIL), a pixel circuit (PC), and an organic insulating layer (OIL). The inorganic insulating stack (IIL) may include a buffer layer (111), a gate insulating layer (113), a first interlayer insulating layer (115), and a second interlayer insulating layer (117). The organic insulating layer (OIL) may include a first organic insulating layer (121) and a second organic insulating layer (123).

[0177] The first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) may be spaced apart from each other. The statement that the first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) are spaced apart from each other means that the inorganic insulating stack (IIL), pixel circuit (PC), and organic insulating layer (OIL) of the first pixel circuit layer (PCL1) are spaced apart from the inorganic insulating stack (IIL), pixel circuit (PC), and organic insulating layer (OIL) of the second pixel circuit layer (PCL2), respectively.

[0178] The inorganic insulating stack (IIL) may be placed in the first region (11) and may not be placed in the second region (12). The inorganic insulating stack (IIL) may have an isolated shape placed in the first region (11). The inorganic insulating stacks (IIL) placed in each of the first regions (11) may be spaced apart from each other in a plane. For example, the buffer layer (111), gate insulating layer (113), first interlayer insulating layer (115), and second interlayer insulating layer (117) of the first pixel circuit layer (PCL1) may be separated from the buffer layer (111), gate insulating layer (113), first interlayer insulating layer (115), and second interlayer insulating layer (117) of the second pixel circuit layer (PCL2), respectively.

[0179] Likewise, the organic insulating layer (OIL) may be disposed in the first region (11) and not in the second region (12). The organic insulating layer (OIL) may have an isolated shape disposed in the first region (11). For example, the first organic insulating layer (121) and the second organic insulating layer (123) of the first pixel circuit layer (PCL1) may be separated from the first organic insulating layer (121) and the second organic insulating layer (123) of the second pixel circuit layer (PCL2), respectively.

[0180] As illustrated in FIG. 11, the buffer layer (111) is disposed on the base layer (400), and the pixel circuit (PC) can be disposed on the buffer layer (111). The buffer layer (111) may include an inorganic insulating material (e.g., an inorganic electrical insulating material) such as silicon oxide, silicon nitride, or silicon oxynitride.

[0181] The thin-film transistor (TFT) of the pixel circuit (PC) may include a semiconductor layer (Act), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE). FIG. 11 illustrates a top-gate type in which the gate electrode (GE) is placed on the semiconductor layer (Act) with the gate insulating layer (113) in between, but according to other embodiments, the thin-film transistor (TFT) may be a bottom-gate type.

[0182] The semiconductor layer (Act) may include polysilicon. Alternatively, the semiconductor layer (Act) may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. The gate electrode (GE) may include a metal thin film composed of a low-resistance (e.g., low electrical resistance) metal material. The gate electrode (GE) may include a conductive material (e.g., an electrically conductive material) including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. For example, the gate electrode (GE) may include a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0183] The gate insulating layer (113) between the semiconductor layer (Act) and the gate electrode (GE) may include an inorganic insulating material (e.g., an inorganic electrical insulating material) such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide. The gate insulating layer (113) may be a single layer or a multilayer containing the aforementioned material.

[0184] The source electrode (SE) and the drain electrode (DE) may be located on the same layer, for example, the second interlayer insulating layer (117), and may contain the same material. The source electrode (SE) and the drain electrode (DE) may contain a metal thin film composed of a low-resistance (e.g., low electrical resistance) metal material. The source electrode (SE) and the drain electrode (DE) may contain a conductive material (e.g., an electrically conductive material) including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer containing the above materials. For example, the source electrode (SE) and the drain electrode (DE) may be provided as a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure, similar to the gate electrode (GE). The second interlayer insulating layer (117) may include an inorganic insulating material (e.g., an inorganic electrical insulating material) such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or a multilayer containing the aforementioned material.

[0185] A storage capacitor (Cst) may include a first electrode (CE1) and a second electrode (CE2) that overlap with a first interlayer insulating layer (115) in between. The storage capacitor (Cst) may overlap with a thin-film transistor (TFT). In this regard, FIG. 7 illustrates that the gate electrode (GE) of the thin-film transistor (TFT) is the first electrode (CE1) of the storage capacitor (Cst). In another embodiment, the storage capacitor (Cst) may not overlap with the thin-film transistor (TFT). The storage capacitor (Cst) may be covered by a second interlayer insulating layer (117).

[0186] The first interlayer insulating layer (115) may be disposed between the gate insulating layer (113) and the second interlayer insulating layer (117). The first interlayer insulating layer (115) and the second interlayer insulating layer (117) may each include an inorganic insulating material (e.g., an inorganic electrical insulating material) such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or a multilayer containing the aforementioned material.

[0187] The second electrode (CE2) of the storage capacitor (Cst) may include a conductive material (e.g., an electrically conductive material) and may be formed as a multilayer or a single layer. The second electrode (CE2) may include a metal thin film composed of a low-resistance (e.g., low electrical resistance) metal material. The second electrode (CE2) may include a conductive material (e.g., an electrically conductive material) including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or a single layer including the above materials. For example, the second electrode (CE2) may be provided as a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0188] The first organic insulating layer (121) may be disposed on the second interlayer insulating layer (117). The second organic insulating layer (123) may be disposed on the first organic insulating layer (121). The connecting electrode (CM) and the second voltage line (VSSL) may be disposed on the first organic insulating layer (121). The connecting electrode (CM) may electrically connect the pixel circuit (PC) and the first electrode pad (241). The second voltage line (VSSL) may be electrically connected to the second electrode pad (242).

[0189] The connecting electrode (CM) and the second voltage line (VSSL) may include a metal thin film composed of a low-resistance (e.g., low electrical resistance) metal material. The connecting electrode (CM) and the second voltage line (VSSL) may include a conductive material (e.g., an electrically conductive material) including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. For example, the connecting electrode (CM) and the second voltage line (VSSL) may be provided with a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0190] The first electrode pad (241) and the second electrode pad (242) may be disposed on the second organic insulating layer (123). The first electrode pad (241) may be electrically connected to a thin-film transistor (TFT) through a connecting electrode (CM) between the first organic insulating layer (121) and the second organic insulating layer (123).

[0191] The light-emitting diode (LED) on the first electrode pad (241) and the second electrode pad (242) may be the same as the light-emitting diode (LED) described above with reference to FIG. 8a. In another embodiment, the light-emitting diode (LED) may have a structure such as FIG. 8b to FIG. 8d. One side of the light-emitting diode (LED) may be covered with a protective layer (240) comprising an organic insulating material (e.g., an organic electrical insulating material).

[0192] The first line (L1) may be a signal line or a voltage line electrically connected to the pixel circuit (PC) of the first pixel circuit layer (PCL1). The second line (L2) may be a signal line or a voltage line electrically connected to the pixel circuit (PC) of the second pixel circuit layer (PCL2). In one embodiment, the first line (L1) and the second line (L2) may include the gate line (GL, FIG. 9) or data line (DL, FIG. 9) described above with reference to FIG. 9. In another embodiment, the first line (L1) and the second line (L2) may be the first voltage line (VDDL) or the second voltage line (VSSL) described with reference to FIG. 7a, or the first initialization voltage line (VIL1), the second initialization voltage line (VIL2), the holding voltage line (VSL), the first voltage line (VDDL), or the second voltage line (VSSL) described with reference to FIG. 7b and FIG. 7c.

[0193] Each of the first line (L1) and the second line (L2) is positioned on the second interlayer insulation layer (117) and may extend onto the connecting line (WL). A portion of the first line (L1) may be located on the corresponding second interlayer insulation layer (117). Another portion of the first line (L1) may extend onto the connecting line (WL) through the inorganic insulation stack (IIL) and may come into direct contact with the connecting line (WL). Along the third direction (e.g., the z-direction), a portion of the first line (L1) may be positioned between the second interlayer insulation layer (117) and the first organic insulation layer (121), and another portion of the first line (L1) may be positioned between the third organic insulation layer (119) and the second organic insulation layer (123), which will be described later. Likewise, one part of the second line (L2) is located on the corresponding second interlayer insulating layer (117), and the other part of the second line (L2) extends onto the connecting line (WL) and can come into direct contact with the connecting line (WL). Along the third direction (e.g., z-direction), one part of the second line (L2) may be positioned between the second interlayer insulating layer (117) and the first organic insulating layer (121), and the other part of the second line (L2) may be positioned between the third organic insulating layer (119) and the second organic insulating layer (123), which will be described later.

[0194] An inorganic insulating stack (IIL) with an isolated shape on a plane may have a step with respect to the upper surface of the base layer (400) as shown in FIG. 11. In one embodiment, as shown in FIG. 11, the organic insulating layer (OIL) may further include a third organic insulating layer (119) arranged to cover the side of the inorganic insulating stack (IIL). The third organic insulating layer (119) may have a closed-loop shape on a plane to cover the side of the inorganic insulating stack (IIL). The first line (L1) and the second line (L2) may extend along the connecting line (WL) through the upper surface of the corresponding third organic insulating layer (119).

[0195] As previously explained, a connection line (WL) may be disposed in the second region (12). In one embodiment, the connection line (WL) may be disposed on the bottom surface of the pixel circuit layer (PCL). In other words, the base layer (400) may include a recess (400RC) that is concave from the top surface toward the bottom surface, and the connection line (WL) may be present within the recess (400RC).

[0196] The connection line (WL) includes a first surface (e.g., bottom surface) facing the base layer (400) and a second surface (e.g., top surface) opposite the first surface. The second surface (e.g., top surface) of the connection line (WL) may be located on the same surface as the top surface of the base layer (400). Accordingly, the thickness of a portion of the base layer (400) that overlaps with the connection line (WL) may be smaller than the thickness of another portion of the base layer (400) that does not overlap with the connection line (WL). That is, as the connection line (WL) has a structure embedded in the base layer (400), the base layer (400) can absorb the stress that may be concentrated on the connection line (WL) during the stretching of the display panel (10).

[0197] In one embodiment, auxiliary patterns (AP) may be placed at both ends of the connecting line (WL). The auxiliary patterns (AP) may have a shape that caps the edges of the connecting line (WL). As previously described, the modulus of the auxiliary patterns (AP) may have a value in the range of 10 to 5000 times the modulus of the connecting line (WL). Accordingly, the auxiliary patterns (AP) can reduce strain that may be concentrated at both ends of the connecting line (WL).

[0198] The auxiliary pattern (AP) may have a structure embedded in the base layer (400), similar to the connection line (WL). That is, the auxiliary pattern (AP) may be placed on the bottom surface of the pixel circuit layer (PCL). The base layer (400) may cover the bottom surface of the connection line (WL) and the bottom surface of the auxiliary pattern (AP). The volume of the recess (400RC) of the base layer (400) may be substantially the same as the sum of the volume of the connection line (WL) and the volume of the auxiliary pattern (AP).

[0199] Referring to FIG. 12, auxiliary patterns (AP) may be disposed at each of the two ends of the connecting line (WL), and the first line (L1) and the second line (L2) may each extend along the connecting line (WL) and come into direct contact with the upper surface of the connecting line (WL). The contact area (CNA) between the first line (L1) and the connecting line (WL) may be equal to the area of ​​the bottom surface of a part of the first line (L1) that meets the upper surface of the connecting line (WL). The contact area (CNA) between the second line (L2) and the connecting line (WL) may be equal to the area of ​​the bottom surface of a part of the second line (L2) that meets the upper surface of the connecting line (WL).

[0200] Based on a third direction (e.g., z-direction), the connecting line (WL) may have a first thickness (H1), and the auxiliary pattern (AP) may have a second thickness (H2). In one embodiment, the second thickness (H2) of the auxiliary pattern (AP) may be greater than the first thickness (H1) of the connecting line (WL). Specifically, the second thickness (H2) of the auxiliary pattern (AP) may have a length of at least 1.25 times the first thickness (H1) of the connecting line (WL).

[0201] Additionally, based on the second direction (e.g., the y-direction), the connecting line (WL) may have a first width (D1), and the auxiliary pattern (AP) may have a second width (D2). In one embodiment, the second width (D2) of the auxiliary pattern (AP) may be larger than the first width (D1) of the connecting line (WL). Specifically, the second width (D2) of the auxiliary pattern (AP) may have a length of at least 1.25 times the first width (D1) of the connecting line (WL).

[0202] That is, the width of the side of the auxiliary pattern (AP) facing the connection line (WL) may be larger than the width of the side of the connection line (WL) facing the auxiliary pattern (AP). As described above, when the side of the auxiliary pattern (AP) is formed to be wider than the side of the connection line (WL), the auxiliary pattern (AP) can have a shape that wraps around the end of the connection line (WL), so the auxiliary pattern (AP) can efficiently relieve the strain applied to the end of the connection line (WL).

[0203] Referring again to FIG. 11, a light-emitting diode (LED) may be placed on a corresponding pixel circuit layer (PCL). For example, a light-emitting diode (LED) electrically connected to a pixel circuit (PC) of a first pixel circuit layer (PCL1) may be placed on the corresponding first pixel circuit layer (PCL1), and a light-emitting diode (LED) electrically connected to a pixel circuit (PC) of a second pixel circuit layer (PCL2) may be placed on the corresponding second pixel circuit layer (PCL2). One side of each light-emitting diode (LED) may be covered by a protective layer (240). The protective layer (240) may include an organic insulating material such as polyimide (e.g., an organic electrical insulating material).

[0204] A protective layer (300) may be disposed on the light-emitting diode (LED) and the connection line (WL). The protective layer (300) may cover the light-emitting diode (LED) and the connection line (WL). The protective layer (300) may absorb stress that may be transmitted to the light-emitting diode (LED) and the connection line (WL) during the stretching of the display panel (10), and may flatten the upper surface of the display panel (10). The protective layer (300) may include an elastomer. For example, the protective layer (300) is thermoplastic polyurethane, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, fluoroelastomers, ethylene-vinyl acetate, PDMS (polydimethylsiloxane), and It may include at least one of the ecoflex.

[0205] The protective layer (300) can be in direct contact with the upper surface of the connection line (WL) and can be in direct contact with a part of the upper surface of the base layer (400). In one embodiment, if the material of the protective layer (300) and the material of the base layer (400) are the same, the bonding strength between the protective layer (300) and the base layer (400) can be increased, thereby maintaining the airtightness of the display panel (10) more effectively.

[0206] FIGS. 13a to 13f are schematic plan views showing parts of a display panel (10) according to embodiments of the present invention. Referring to FIGS. 13a to 13g, other features are as described in FIGS. 9 to 11, except for features regarding the auxiliary pattern (AP). Among the components of FIGS. 13a to 13g, identical reference numerals are replaced with those previously described with reference to FIGS. 9 to 11, and the differences are described below.

[0207] First, referring to FIG. 13a, auxiliary patterns (AP) may be arranged to cover the ends of the connecting lines (WL). In one embodiment, a plurality of auxiliary patterns (AP) may be spaced apart from each other in a first area (11). That is, the plurality of auxiliary patterns (AP) may each cover the ends of the plurality of connecting lines (WL) and may be spaced apart from each other. In one embodiment, the auxiliary patterns (AP) may each have a circular shape in a planar shape (e.g., substantially circular shape). However, they are not limited thereto, and the auxiliary patterns (AP) may each have an elliptical shape (e.g., substantially elliptical shape).

[0208] Next, referring to FIG. 13b, an auxiliary pattern (AP) may be arranged to cover the end of a connecting line (WL). However, in one first area (11), one auxiliary pattern (AP) may be arranged to cover the end of each of the multiple connecting lines (WL). For example, one auxiliary pattern (AP) may extend in a second direction (e.g., y-direction) to cover the end of a first connecting line (WL1, or vertical connecting line), and one auxiliary pattern (AP) may extend in a first direction (e.g., x-direction) to cover the end of a second connecting line (WL2, or horizontal connecting line). In other words, the auxiliary pattern (AP) may have a planar mesh pattern within the first area (11).

[0209] Next, referring to FIG. 13c, an auxiliary pattern (AP) may be arranged to cover the end of a connecting line (WL). In this case, one auxiliary pattern (AP) may be arranged to cover the end of two or more connecting lines (WL) among the plurality of connecting lines (WL). For example, one auxiliary pattern (AP) may be extended diagonally between a first direction (e.g., x-direction) and a second direction (e.g., y-direction). One end of the auxiliary pattern (AP) extended diagonally may cover the end of a first connecting line (WL1, or vertical connecting line), and the other end of the auxiliary pattern (AP) may cover the end of a second connecting line (WL2, or horizontal connecting line). A plurality of auxiliary patterns (AP) having such a shape may be arranged in the first area (11).

[0210] Next, referring to FIG. 13d, an auxiliary pattern (AP) may be positioned to cover the ends of the connecting lines (WL). In this case, one auxiliary pattern (AP) may be positioned to cover the ends of two or more connecting lines (WL) among the plurality of connecting lines (WL). For example, one auxiliary pattern (AP) may be extended in a first direction (e.g., x-direction) or a second direction (e.g., y-direction). One auxiliary pattern (AP) extended in the first direction (e.g., x-direction) may cover the ends of a plurality of first connecting lines (WL1, or vertical connecting lines) positioned on one side (e.g., upper or lower surface) of the first area (11). One auxiliary pattern (AP) extended in a second direction (e.g., y-direction) can cover the ends of a plurality of second connecting lines (WL2, or horizontal connecting lines) arranged on one side (e.g., left side or right side) of the first area (11). A plurality of auxiliary patterns (AP) having such a shape as described above can be arranged in the first area (11).

[0211] Next, referring to FIG. 13e, an auxiliary pattern (AP) may be placed to cover the ends of the connection lines (WL). However, in one first region (11), one auxiliary pattern (AP) may be placed to cover the ends of each of the multiple connection lines (WL). For example, one auxiliary pattern (AP) may have a single continuous shape to overlap with the planar pixel circuit layer (PCL, FIG. 11). As shown in FIG. 13e, the auxiliary pattern (AP) may have a rectangular shape having an area relatively smaller than the first region (11) and may be placed to overlap with the pixel circuit layer (PCL, FIG. 11). As the auxiliary pattern (AP) has such a shape, the auxiliary pattern (AP) can cover the ends of all the multiple connection lines (WL) placed on the four sides of the first region (11). That is, as one auxiliary pattern (AP) has an extended area to fill the first area (11), it can cover all ends of multiple first connection lines (WL1, or vertical connection lines) and multiple second connection lines (WL2, or horizontal connection lines).

[0212] Next, referring to FIG. 13f, auxiliary patterns (AP) may be arranged to cover the ends of a connecting line (WL). A plurality of auxiliary patterns (AP) may be arranged in the first area (11), some of the plurality of auxiliary patterns (AP) may cover only the ends of one connecting line (WL), and the remainder of the plurality of auxiliary patterns (AP) may cover the ends of a plurality of connecting lines (WL). For example, some of the plurality of auxiliary patterns (AP) may be arranged to cover the ends of the first connecting lines (WL1, or vertical connecting lines), but may be spaced apart from each other. The remainder of the plurality of auxiliary patterns (AP) may be extended in a first direction (e.g., x-direction), such that one end of the auxiliary pattern (AP) covers the end of the second connecting line (WL2, or horizontal connecting line) positioned on the left side of the first area (11), and the other end of the auxiliary pattern (AP) covers the end of the second connecting line (WL2, or horizontal connecting line) positioned on the right side of the first area (11). However, this is not limited thereto, and the arrangement and shape of the plurality of auxiliary patterns (AP) may be arranged differently depending on the plurality of connecting lines (WL).

[0213] As illustrated in FIGS. 13b to 13f, the auxiliary pattern (AP) may not only cover the end of a single connection line (WL) but may also cover each of the ends of multiple connection lines (WL). In one embodiment, when the auxiliary pattern (AP) has a structure that covers the ends of multiple connection lines (WL) as described above, the modulus of the auxiliary pattern (AP) may have a value in the range of 10 to 500 times the modulus of the connection line (WL). That is, the auxiliary pattern (AP) capable of covering the ends of multiple connection lines (WL) may have a relatively smaller modulus than the auxiliary pattern (AP) that covers only the end of a single connection line (WL) as shown in FIG. 10. However, even if the modulus of the auxiliary pattern (AP) has a relatively small value, when the auxiliary pattern (AP) covers the ends of multiple connection lines (WL), the volume of the auxiliary pattern (AP) increases, so the auxiliary pattern (AP) can efficiently relieve the strain applied to the ends of the connection lines (WL). Accordingly, the display panel according to other embodiments of the present invention can also simultaneously achieve excellent elongation and mechanical stability.

[0214] FIGS. 14a to 14g are schematic perspective views illustrating embodiments of an electronic device including a display panel according to one embodiment of the present invention.

[0215] Referring to FIG. 14a, a display panel according to one embodiment of the present invention can be utilized in a wearable electronic device (3100) that can be worn on a part of a user's body. The wearable electronic device (3100) may include a body part (3110) and a display part (3120) provided on the body part (3110). The display panel according to embodiments of the present invention can be used as the display part (3120) of the wearable electronic device (3100). As illustrated in FIG. 14a, the wearable electronic device (3100) may be modified. In one embodiment, it can be used as a smart watch or a smartphone depending on the user's choice.

[0216] FIG. 14b illustrates a medical electronic device (3200). In one embodiment, the medical electronic device (3200) may include a body part (3210) and a light-emitting part (3220). A display panel according to embodiments of the present invention may be used as the light-emitting part (3220) of the medical electronic device (3200). The light-emitting part (3220) may emit light of a specific wavelength band (e.g., infrared, visible light, etc.) to the patient's body. In one embodiment, the body part (3210) may have a stretchable fiber material and the light-emitting part (3220) may have a structure that can be worn on the user's body.

[0217] FIG. 14c illustrates an educational electronic device (3300). In one embodiment, the educational electronic device (3300) may include a display unit (3320) provided within a frame (3310). The display unit (3320) may utilize a display panel according to embodiments of the present invention. The display unit (3320) may provide images such as a sea with waves, a snow-covered mountain, or a volcano with flowing lava, wherein the display unit (3320) may extend in the height direction (e.g., z-direction) to reflect the height of the waves, mountain, or volcano. In some embodiments, a portion of the display unit (3320) may sequentially vary in height along the direction of the lava flow to show the movement of the lava in three dimensions. The educational electronic device (3300) may include a plurality of pins (or stroke units, 3330) arranged on the back of the display unit (3320) so that the display unit (3320) extends in the height direction. The pins (3330) can be implemented to move along a third direction (e.g., z direction or -z direction) so that the image displayed on the display unit (3320) has a three-dimensional height. FIG. 14c describes an educational electronic device (3300), but its use is not limited as long as it provides certain image information.

[0218] The electronic device illustrated in FIGS. 14a to 14c describes an electronic device whose shape may be variable, but the present invention is not limited thereto. As in the embodiments described below, the display panel according to the embodiments of the present invention may be used in an electronic device in which a portion capable of displaying an image (e.g., a screen) is fixed.

[0219] FIG. 14d illustrates a robot (3400) as another electronic device in one embodiment of the present invention. The robot (3400) can move or perceive objects using a camera unit (3440) and can display a predetermined image to a user through a display unit (3420, 3430). In some embodiments, since the display panels according to one embodiment of the present invention can be extended in various directions as described above, they can be assembled to a body frame having a hemispherical shape, and thus the robot (3400) may include a hemispherical display unit (3420, 3430).

[0220] FIG. 14e illustrates a vehicle display device (3500) as another electronic device in one embodiment of the present invention. The vehicle display device (3500) may include a cluster (3510), a Center Information Display (CID) (3520), and / or a passenger display. Since the display panel according to the embodiment of the present invention can be extended in various directions, it can be used for the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display without being constrained by the shape of the vehicle's internal frame.

[0221] FIG. 14e illustrates the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display being separated, but the invention is not limited thereto. In another embodiment, two or more selected from the cluster (3510), the Center Information Display (CID) (3520), and the co-driver display may be connected as a single unit.

[0222] In some embodiments, the vehicle display device (3500) may include a button (3540) capable of displaying a predetermined image. Referring to the enlarged view of FIG. 14e, the hemispherical button (3540) may include an object (3542) that provides a sense of use of the button while moving in the z-direction or -z-direction, and a display device placed on the object (3542). In some embodiments, if the object (3542) has a three-dimensionally rounded surface, the display device may also have a three-dimensionally rounded surface.

[0223] FIG. 14f illustrates that an electronic device according to one embodiment of the present invention is an electronic device for advertising or display (3600). In some embodiments, the electronic device for advertising or display (3600) may be installed on a fixed structure (3610), such as a wall or a column. If the structure (3610) includes an uneven surface as shown in FIG. 14f, the electronic device for advertising or display (3600) may also be placed along the uneven surface of the structure (3610). In some embodiments, the electronic device for advertising or display (3600) may be installed on the structure (3610) using a heat-shrink film or the like.

[0224] FIG. 14g illustrates that an electronic device according to one embodiment of the present invention is a controller (3700). The controller (3700) may include an image-type button. For example, the controller (3700) may include first to third button areas (3720, 3730, 3740) in which a portion of the display portion (3710) protrudes in the z-direction or protrudes in the -z-direction (or is recessed in the z-direction). In some embodiments, the first and third button areas (3720, 3740) may protrude in the z-direction, and the second button area (3730) may protrude in the -z-direction (or be recessed in the z-direction).

[0225] Although the present invention has been described with reference to an embodiment illustrated in the drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

A display panel comprising a plurality of first regions and a second region surrounding each of the plurality of first regions, A pixel circuit layer comprising a plurality of pixel circuits and insulating layers disposed in each of the plurality of first regions; A plurality of light-emitting diodes disposed on the pixel circuit layer and electrically connected to each of the plurality of pixel circuits; A connection line that electrically connects pixel circuits arranged adjacent to each other among the plurality of pixel circuits above; and A display panel comprising an auxiliary pattern positioned to cover both ends of the above-mentioned connection line. In Article 1, Both ends of the above connecting line and the above auxiliary pattern are placed in one of the plurality of first regions, and A display panel, wherein the portion of the above connecting line excluding both ends is positioned in the above second area. In Article 1, A display panel in which the modulus of the above auxiliary pattern is greater than the modulus of the above connection line. In Paragraph 3, A display panel in which the modulus of the above auxiliary pattern has a value in the range of 10 to 5000 times the modulus of the above connection line. In Article 1, A display panel further comprising: a base layer disposed below the pixel circuit layer and covering the lower surface of the connection line and the lower surface of the auxiliary pattern. In Article 1, Based on the thickness direction of the pixel circuit layer above, A display panel in which the thickness of the above auxiliary pattern is greater than the thickness of the above connecting line. In Article 6, Based on the thickness direction of the pixel circuit layer above, A display panel in which the thickness of the above auxiliary pattern is at least 1.25 times the thickness of the above connecting line. In Article 1, The above connecting line extends along the first direction, and The above connecting line has a first width following a second direction that intersects the above first direction, The above auxiliary pattern has a second width following the above second direction, and A display panel in which, on a flat plane, the second width of the auxiliary pattern is larger than the first width of the connecting line. In Article 8, A display panel in which the second width of the above auxiliary pattern is at least 1.25 times the first width of the above connecting line. In Article 1, The above connection lines are provided in multiple numbers, and Pixel circuits disposed in one of the plurality of first regions are connected to a plurality of connection lines, and A display panel comprising a plurality of connection lines, the plurality of connection lines including a plurality of horizontal connection lines extending along a first direction and a plurality of vertical connection lines extending along a second direction intersecting the first direction. In Article 10, The above auxiliary pattern is provided in plurality to cover the end of each of the plurality of connection lines, and A display panel in which multiple auxiliary patterns are spaced apart from each other. In Article 10, One of the above auxiliary patterns is a display panel that covers the ends of two or more of the plurality of connection lines. In Article 10, A display panel in which an auxiliary pattern covering all ends of the plurality of connection lines is disposed in one of the plurality of first regions. In Article 13, The above auxiliary pattern is a display panel having a planar mesh pattern in the first region. In Article 13, A display panel having a single continuous shape such that the above auxiliary pattern overlaps with the pixel circuit layer on a plane. In Article 10, The above auxiliary pattern is a display panel extending diagonally between the first direction and the second direction on the first area. In Article 16, A display panel in which one end of the auxiliary pattern covers one end of one of the plurality of horizontal connection lines, and the other end of the auxiliary pattern covers one end of one of the plurality of vertical connection lines. In Article 10, The above auxiliary pattern is extended in the above first direction or the above second direction, A display panel covering the ends of the plurality of connection lines disposed on one side of the first area. In Article 10, The above auxiliary patterns are provided in multiple numbers, and Some of the plurality of auxiliary patterns cover the end of one of the plurality of connection lines, and A display panel in which the remainder of the plurality of auxiliary patterns covers the ends of two or more of the plurality of connection lines. A display panel comprising a plurality of first regions and a second region surrounding each of the plurality of first regions; and It includes a lower cover that forms an exterior and has an opening that exposes a portion of the display panel on the front surface; and The above display panel is, A pixel circuit layer comprising a plurality of pixel circuits and insulating layers disposed in each of the plurality of first regions; A plurality of light-emitting diodes disposed on the pixel circuit layer and electrically connected to each of the plurality of pixel circuits; A connection line that electrically connects pixel circuits arranged adjacent to each other among the plurality of pixel circuits above; and An electronic device comprising an auxiliary pattern arranged to cover both ends of the above-mentioned connection line.

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