Display panel and display device

Abstract

A display panel, comprising: an active area (AA) and a peripheral area at least partially surrounding the active area. The peripheral area comprises: at least one first border region (L1) extending in a first direction (X), at least one second border region (L2) extending in a second direction (Y), and at least one border corner region connected between the adjacent first border region (L1) and second border region (L2). The display panel further comprises: a base substrate, and a plurality of sub-pixels (Pxij) and at least one first signal line (110) disposed on the base substrate. The at least one first signal line (110) comprises: a first border trace (120) located in the first border region, a second border trace (130) located in the second border region, and at least one set of signal connection lines (140) located in the active area (AA). The first border trace (120) is electrically connected to the second border trace (130) via the at least one set of signal connection lines (140).

Description

Display panel and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices, offering advantages such as self-illumination, low power consumption, thinness, flexibility, vibrant colors, high contrast, and fast response times. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. To better meet people's needs for multiple functions and a better screen experience (such as displays with ultra-high screen-to-body ratios), narrow-bezel displays have become the development direction; however, the four corner bezels of display devices have become a bottleneck in achieving narrower bezels. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display panel and display device to solve problems such as the inability to narrow the corner bezels.

[0005] On one hand, this disclosure provides a display panel, including a display area and a peripheral area at least partially surrounding the display area. The peripheral area includes: at least one first border area extending along a first direction, at least one second border area extending along a second direction, and at least one border corner area, the border corner area connecting adjacent first and second border areas; the first direction intersects the second direction. The display panel further includes: a substrate, a plurality of sub-pixels, and at least one first signal line. The plurality of sub-pixels are disposed on the substrate and located in the display area. The at least one first signal line is disposed on the substrate and configured to provide a first signal to the plurality of sub-pixels; the at least one first signal line includes: a first border trace located in the first border area, a second border trace located in the second border area, and at least one signal connection line and at least one set of signal connection lines located in the display area; the first border trace is electrically connected to the second border trace through the at least one signal connection line and at least one set of signal connection lines.

[0006] In some exemplary embodiments, the display area includes: at least one display corner area, the display corner area being connected to the frame corner area, a portion of the first frame area connected to the frame corner area, and a portion of the second frame area connected to the frame corner area; the outer contour of the display corner area, in its orthographic projection on the substrate, includes a first straight line segment, a corner segment, and a second straight line segment connected in sequence, the first straight line segment extending along a first direction, and the second straight line segment extending along a second direction; the at least one set of signal connection lines is located in at least one of the display corner areas.

[0007] In some exemplary embodiments, the at least one first border area includes a first border sub-area and a third border sub-area; the at least one second border area includes a second border sub-area and a fourth border sub-area. The display area includes a plurality of display corner areas, including: a first display corner area, a second display corner area, a third display corner area, and a fourth display corner area; the first display corner area is connected to the first border sub-area and the second border sub-area; the second display corner area is connected to the second border sub-area and the third border sub-area; the third display corner area is connected to the third border sub-area and the fourth border sub-area; and the fourth display corner area is connected to the first border sub-area and the fourth border sub-area. At least one signal connection line and at least one set of signal connection lines of the first signal line are located in the first display corner area and the fourth display corner area.

[0008] In some exemplary embodiments, the peripheral area includes multiple border corner areas, including a first border corner area, a second border corner area, a third border corner area, and a fourth border corner area. The first border corner area is connected to the first display corner area; the second border corner area is connected to the second display corner area; the third border corner area is connected to the third display corner area; and the fourth border corner area is connected to the fourth display corner area. The first signal line is discontinuous in the first border corner area and the fourth border corner area, or the first signal line is discontinuous in the first border corner area, the second border corner area, the third border corner area, and the fourth border corner area.

[0009] In some exemplary embodiments, the at least one set of signal connection lines includes: a plurality of signal connection lines located in the display area, the plurality of signal connection lines being distributed in a grid pattern in the display area.

[0010] In some exemplary embodiments, the at least one set of signal connection lines includes: multiple signal connection lines located in the display area, the multiple signal connection lines being distributed in an L-shaped plane in the display area.

[0011] In some exemplary embodiments, the display panel further includes: a plurality of auxiliary traces located in the display area, the plurality of auxiliary traces being distributed in a grid pattern in the display area; the orthographic projection of the plurality of auxiliary traces on the substrate overlaps or does not overlap with the orthographic projection portion of the at least one signal connection line or at least one group of signal connection lines on the substrate.

[0012] In some exemplary embodiments, the at least one set of signal connection lines includes: a plurality of signal connection lines located in the display area; the plurality of signal connection lines include: at least one first connection line extending along the first direction and at least one second connection line extending along the second direction; the at least one first connection line and the at least one second connection line are electrically connected in the display area; the at least one second connection line is connected to a first border trace located in the first border area, and the at least one first connection line is electrically connected to a second border trace located in the second border area.

[0013] In some exemplary embodiments, the first border trace, the second border trace, the at least one first connecting line, and the at least one second connecting line of the first signal line are arranged on the same layer; or, the first border trace, the second border trace, and the at least one first connecting line of the first signal line are arranged on the same layer; or, the first border trace, the second border trace, and the at least one second connecting line of the first signal line are arranged on the same layer.

[0014] In some exemplary embodiments, the display panel further includes: a plurality of data lines located in the display area, the plurality of data lines being electrically connected to the plurality of sub-pixels, the plurality of data lines being configured to provide data signals to the plurality of sub-pixels, and the plurality of data lines extending along the second direction. The plurality of data lines and the at least one first connecting line are located in different conductive layers, and at least one of the plurality of data lines overlaps with the at least one first connecting line in the orthographic projection portion of the substrate.

[0015] In some exemplary embodiments, the film layer containing the plurality of data lines is located on the side of the film layer containing the at least one first connecting line that is away from the substrate. The at least one second connecting line is disposed in the same layer as the plurality of data lines, or the film layer containing the at least one second connecting line is located on the side of the film layer containing the plurality of data lines that is closer to the substrate.

[0016] In some exemplary embodiments, the display panel further includes: a plurality of first power lines located in the display area and electrically connected to the plurality of sub-pixels, configured to transmit a first voltage signal to the plurality of sub-pixels, the plurality of first power lines extending along the second direction. At least one of the plurality of first power lines overlaps with the orthographic projection of at least one first connecting line onto the substrate. The plurality of first power lines are disposed on the same layer as the plurality of data lines.

[0017] In some exemplary embodiments, the plurality of sub-pixels are arranged in multiple columns along the first direction, and each column of sub-pixels includes a plurality of sub-pixels arranged sequentially along the second direction. At least one of the plurality of first power lines is configured to provide a first voltage signal to two adjacent columns of sub-pixels. The orthographic projection of the at least one first connection line on the substrate and the orthographic projection of the at least one first power line on the substrate do not overlap or only partially overlap.

[0018] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes: a first source / drain metal layer and a second source / drain metal layer disposed on the substrate, the second source / drain metal layer being located on the side of the first source / drain metal layer away from the substrate. The plurality of data lines and the plurality of first power lines are located on the second source / drain metal layer; the first border trace and the second border trace of the first signal lines are located on the first source / drain metal layer.

[0019] In some exemplary embodiments, the at least one first connection line and the at least one second connection line of the first signal line are located in the first source-drain metal layer; or, the at least one first connection line is located in the first source-drain metal layer, and the at least one second connection line is located in the second source-drain metal layer.

[0020] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel further includes: a gate metal layer disposed on the substrate, the gate metal layer being located on the side of the first source / drain metal layer near the substrate. The at least one second connection line of the first signal line is located in the first source / drain metal layer, and the at least one first connection line is located in the gate metal layer.

[0021] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel further includes: a bottom shielding metal layer and a gate metal layer disposed on the substrate, wherein the bottom shielding metal layer is located on the side of the gate metal layer near the substrate, and the gate metal layer is located on the side of the first source / drain metal layer near the substrate.

[0022] In some exemplary embodiments, the at least one first connection line of the first signal line is located in the first source / drain metal layer, and the at least one second connection line is located in the bottom shielding metal layer.

[0023] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel further includes an active layer disposed on the substrate, the active layer being located on the side of the bottom shielding metal layer away from the substrate and on the side of the gate metal layer close to the substrate. The orthographic projection of the bottom shielding metal layer onto the substrate covers the orthographic projection of the active layer onto the substrate.

[0024] In some exemplary embodiments, the at least one first connecting line and the at least one second connecting line are both located in the bottom shielding metal layer; the at least one first connecting line and the at least one second connecting line are distributed in an L-shaped plane in the display area.

[0025] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel further includes: a third source / drain metal layer disposed on the substrate, the third source / drain metal layer being located on the side of the second source / drain metal layer away from the substrate. The at least one first connection line of the first signal line is located in the third source / drain metal layer, and the at least one second connection line is located in the second source / drain metal layer.

[0026] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes: a first source / drain metal layer and a second source / drain metal layer disposed on the substrate, the second source / drain metal layer being located on the side of the first source / drain metal layer away from the substrate. The first and second border traces of the plurality of data lines, the plurality of first power lines, and the first signal lines are located in the first source / drain metal layer; the at least one first connection line and the at least one second connection line are located in the second source / drain metal layer.

[0027] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes: a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate, wherein the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate, and the third source / drain metal layer is located on the side of the second source / drain metal layer away from the substrate. The first border trace and the second border trace of the first signal line are located on the first source / drain metal layer, the plurality of data lines, the plurality of first power lines, and the at least one second connection line are located on the third source / drain metal layer, and the at least one first connection line is located on the second source / drain metal layer.

[0028] In some exemplary embodiments, the display panel further includes: at least one group of connecting holes and a plurality of auxiliary hole groups located in the display area; the group of connecting holes includes a plurality of connecting holes arranged in one direction, and one of the plurality of auxiliary hole groups includes a plurality of auxiliary holes arranged in one direction. The at least one first connecting line is connected to the at least one second connecting line through at least one connecting hole. The plurality of auxiliary hole groups include: a plurality of first auxiliary hole groups and a plurality of second auxiliary hole groups. The arrangement direction of the plurality of auxiliary holes in the first auxiliary hole group is different from the arrangement of the plurality of auxiliary holes in the second auxiliary hole group. The plurality of first auxiliary hole groups and the plurality of second auxiliary hole groups are arranged in an array along the first direction and the second direction in the display area.

[0029] In some exemplary embodiments, the display panel includes a plurality of connection hole groups, which include a first connection hole group, a second connection hole group, a third connection hole group, and a fourth connection hole group. The at least one first border area includes a first border sub-area and a third border sub-area; the at least one second border area includes a second border sub-area and a fourth border sub-area; the display area includes a plurality of display corner areas, which include a first display corner area, a second display corner area, a third display corner area, and a fourth display corner area; the first display corner area is connected to the first border sub-area and the second border sub-area; the second display corner area is connected to the second border sub-area and the third border area; the third display corner area is connected to the third border area and the fourth border area; the fourth display corner area is connected to the first border area and the fourth border area. The first connection hole group is located in the first display corner area, the second connection hole group is located in the second display corner area, the third connection hole group is located in the third display corner area, and the fourth connection hole group is located in the fourth display corner area. The plurality of connecting holes in the first connecting hole group and the third connecting hole group, as well as the plurality of auxiliary holes in the first auxiliary hole group, are arranged in the same direction, all along a third direction; the plurality of connecting holes in the second connecting hole group and the fourth connecting hole group, as well as the plurality of auxiliary holes in the second auxiliary hole group, are arranged in the same direction, all along a fourth direction; the third direction intersects with the fourth direction.

[0030] In some exemplary embodiments, the display area includes: a first center line extending along the first direction and a second center line extending along the second direction; the plurality of first auxiliary hole groups and the plurality of second auxiliary hole groups are symmetrically arranged about the first center line or about the second center line in the display area.

[0031] In some exemplary embodiments, the display panel further includes: a plurality of data lines and a plurality of data transmission lines, the plurality of data lines being located in the display area and connected to the plurality of sub-pixels, the plurality of data lines being configured to provide data signals to the plurality of sub-pixels, the plurality of data lines extending along the second direction; the plurality of data transmission lines being at least partially located in the display area; the plurality of data transmission lines corresponding one-to-one with the plurality of data lines and being configured to provide data signals to the plurality of data lines; the plurality of data transmission lines including a plurality of first sub-data transmission lines extending along the first direction and a plurality of second sub-data transmission lines extending along the second direction, the plurality of... A first sub-data transmission line is disposed on a different layer from the plurality of data lines; the orthographic projection of at least one of the plurality of first sub-data transmission lines on the substrate partially overlaps with the orthographic projection of at least one of the plurality of data lines on the substrate; and the plurality of first sub-data transmission lines are distributed on the side of the plurality of first connecting lines away from their nearest neighbor's peripheral area; the plurality of second sub-data transmission lines are distributed on the side of the plurality of second connecting lines away from their nearest neighbor's peripheral area; a second connecting line, a second sub-data transmission line, or an auxiliary trace is disposed between two adjacent data lines.

[0032] In some exemplary embodiments, the display panel further includes: at least one data connection hole group and a plurality of auxiliary hole groups located in the display area, the data connection hole group including a plurality of data connection holes; the plurality of first sub-data transmission lines correspond one-to-one with the plurality of data lines and are electrically connected through the data connection holes; the plurality of auxiliary holes in at least one of the plurality of auxiliary hole groups are arranged in a "Y" shape, the plurality of auxiliary hole groups are arranged in an array along the first direction and the second direction in the display area; and the display panel further includes: a second center line extending along the second direction, the plurality of auxiliary hole groups being symmetrically arranged about the second center line in the display area.

[0033] In some exemplary embodiments, the first signal line is a second power line configured to provide a second voltage signal to the plurality of sub-pixels; or, the display panel includes a plurality of first signal lines, the plurality of first signal lines including: at least one second power line and at least one initialization signal line, the at least one second power line being configured to provide a second voltage signal to the plurality of sub-pixels; the at least one initialization signal line being configured to provide an initialization signal to the plurality of sub-pixels.

[0034] On the other hand, embodiments of this disclosure provide a display device including the display panel described above.

[0035] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0036] Overview of the attached figures

[0037] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0038] Figure 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0039] Figure 2 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0040] Figure 3 is a partial structural schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0041] Figure 4 is a schematic diagram of another partial structure of the display panel according to at least one embodiment of the present disclosure;

[0042] Figure 5 is a schematic diagram of another partial structure of the display panel according to at least one embodiment of the present disclosure;

[0043] Figure 6 is a schematic diagram of a display panel after the formation of auxiliary wiring according to at least one embodiment of the present disclosure;

[0044] Figure 7-1 is a partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0045] Figure 7-2 is another partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0046] Figure 7-3 is another partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0047] Figure 7-4 is another partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0048] Figure 8-1 is a partial cross-sectional view of the connection line access method in the second frame sub-area of ​​Figure 3 along the 11' direction;

[0049] Figure 8-2 is another partial cross-sectional view of the connection line access method in the second frame sub-area of ​​Figure 3 along the 11' direction;

[0050] Figure 9 is a partial structural schematic diagram of the display panel after the data line is formed according to at least one embodiment;

[0051] Figure 10-1 shows a connection method for the signal connection line of the display panel in at least one embodiment;

[0052] Figure 10-2 is a partial cross-sectional view along the CC' direction in Figure 10-1;

[0053] Figure 11-1 shows another connection method for the signal connection line of the display panel in at least one embodiment;

[0054] Figure 11-2 is a partial cross-sectional view along the DD' direction in Figure 11-1;

[0055] Figure 11-3 is a partial cross-sectional view along the EE' direction in Figure 11-1;

[0056] Figure 12-1 shows another connection method for the signal connection line of the display panel in at least one embodiment;

[0057] Figure 12-2 is a partial cross-sectional view along the FF' direction in Figure 12-1;

[0058] Figure 12-3 is a partial cross-sectional view along the GG' direction in Figure 12-1;

[0059] Figure 13-1 shows another connection method for the signal connection line of the display panel in at least one embodiment;

[0060] Figure 13-2 is a partial cross-sectional view along the HH' direction in Figure 13-1;

[0061] Figure 13-3 is a partial cross-sectional view along the II' direction in Figure 13-1;

[0062] Figure 14-1 shows another connection method for the signal connection line of the display panel in at least one embodiment;

[0063] Figure 14-2 is a partial cross-sectional view along the JJ' direction in Figure 14-1;

[0064] Figure 14-3 is a partial cross-sectional view along the KK' direction in Figure 14-1;

[0065] Figure 15-1 shows another connection method for the signal connection line of the display panel in at least one embodiment;

[0066] Figure 15-2 is a partial cross-sectional view along the LL' direction in Figure 15-1;

[0067] Figure 15-3 is a partial cross-sectional view along the MM' direction in Figure 15-1;

[0068] Figure 15-4 is a schematic diagram of a partial cross-section along the NN' direction in Figure 15-1;

[0069] Figure 16-1 shows another connection method for the signal connection line of the display panel in at least one embodiment;

[0070] Figure 16-2 is a partial cross-sectional view along the OO' direction in Figure 16-1;

[0071] Figure 16-3 is a partial cross-sectional view along the PP' direction in Figure 16-1;

[0072] Figure 17-1 shows another connection method for the signal connection line of the display panel in at least one embodiment;

[0073] Figure 17-2 is a partial cross-sectional view along the QQ' direction in Figure 17-1;

[0074] Figure 17-3 is a partial cross-sectional view along the RR' direction in Figure 17-1;

[0075] Figure 17-4 is a partial cross-sectional view along the SS' direction in Figure 17-1;

[0076] Figure 18-1 shows another connection method for the signal connection line of the display panel in at least one embodiment;

[0077] Figure 18-2 is a partial cross-sectional view along the TT' direction in Figure 18-1;

[0078] Figure 18-3 is a partial cross-sectional view along the UU' direction in Figure 18-1;

[0079] Figure 18-4 is a partial cross-sectional view along the VV' direction in Figure 18-1;

[0080] Figure 19 shows a design of the auxiliary hole area of ​​a display panel according to at least one embodiment;

[0081] Figure 20 shows another design of the auxiliary hole area of ​​the display panel in at least one embodiment;

[0082] Figure 21 is another partial structural schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0083] Figure 22 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0084] Detailed Explanation

[0085] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0086] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0087] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0088] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0089] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0090] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0091] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0092] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0093] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0094] In this specification, "about" means a value that is not strictly limited and is within the allowable range of process and measurement errors.

[0095] In this specification, a cross-section along a certain direction refers to a cross-section that passes through that direction and is perpendicular to the plane where the substrate is located.

[0096] At least one embodiment of this disclosure provides a display panel, including a display area and a peripheral area at least partially surrounding the display area. The peripheral area includes: at least one first border area extending along a first direction, at least one second border area extending along a second direction, and at least one border corner area, the border corner area connecting adjacent first and second border areas; the first direction and the second direction intersect. The display panel further includes: a substrate, a plurality of sub-pixels, and at least one first signal line. The plurality of sub-pixels are disposed on the substrate and located in the display area; the at least one first signal line is disposed on the substrate and configured to provide a first signal to the plurality of sub-pixels; the at least one first signal line further includes: a first border trace located in the first border area, a second border trace located in the second border area, and at least one set of signal connection lines located in the display area; the first border trace is electrically connected to the second border trace via at least one set of signal connection lines.

[0097] The display panel provided in this embodiment realizes the electrical connection between the first frame trace and the second frame trace through at least one set of signal connection lines in the display area, which can reduce the wiring in the corner area of ​​the frame and is beneficial to the narrowing design of the corner area of ​​the frame.

[0098] In some exemplary embodiments, the display area includes: at least one display corner area, the display corner area being connected to a bezel corner area, a portion of a first bezel area connected to the bezel corner area, and a portion of a second bezel area connected to the bezel corner area. The orthographic projection of the outer contour of the display corner area onto the substrate includes a first straight line segment, a corner segment, and a second straight line segment connected in sequence, the first straight line segment extending along a first direction, and the second straight line segment extending along a second direction; at least one set of signal connection lines is located in at least one display corner area. For example, the orthographic projection of the corner segment onto the substrate can be an arc segment or a broken line segment. However, this embodiment is not limited to this.

[0099] In some exemplary embodiments, at least one first border area includes a first border sub-area and a second border sub-area; at least one second border area includes a third border sub-area and a fourth border sub-area. The display area includes multiple display corner areas, including: a first display corner area, a second display corner area, a third display corner area, and a fourth display corner area; wherein, the first display corner area is connected to the first border sub-area and the third border sub-area; the second display corner area is connected to the second sub-border area and the third border area; the third display corner area is connected to the second border sub-area and the fourth border area; and the fourth display corner area is connected to the first border area and the fourth border area; at least one set of signal connection lines is located in the first display corner area and the fourth display corner area. The display panel provided in this embodiment, by setting the signal lines of the lower border corner area in the first display corner area and the fourth display corner area in the prior art, can greatly reduce the width of the lower border corner area, thereby achieving a narrow bezel effect.

[0100] In some exemplary embodiments, the surrounding area includes multiple border corner areas, including a first border corner area, a second border corner area, a third border corner area, and a fourth border corner area; wherein, the first border corner area is connected to a first display corner area; the second border corner area is connected to a second display corner area; the third border corner area is connected to a third display corner area; the fourth border corner area is connected to a fourth display corner area; and the first signal line is discontinuous in the first border corner area and the fourth border corner area.

[0101] In some exemplary embodiments, at least one set of signal connection lines includes: multiple signal connection lines located in the display area, the multiple signal connection lines being distributed in a grid pattern in the display area. In other exemplary embodiments, at least one set of signal connection lines includes: multiple signal connection lines located in the display area, the multiple signal connection lines being distributed in an L-shaped planar pattern in the display area. The arrangement of the signal connection lines in this example helps to prevent the risk of high-current short circuits.

[0102] In some exemplary embodiments, the display panel further includes: a plurality of auxiliary traces located in the display area, the plurality of auxiliary traces being distributed in a grid pattern in the display area; the orthographic projections of the plurality of auxiliary traces onto the substrate overlap or do not overlap with the orthographic projections of at least one set of signal connection lines onto the substrate. This example eliminates the problem of increased local reflectivity caused by setting signal connection lines in the display area by providing multiple auxiliary traces.

[0103] In some exemplary embodiments, at least one set of signal connection lines includes: multiple signal connection lines located in the display area; the multiple signal connection lines include: at least one first connection line extending along a first direction and at least one second connection line extending along a second direction; at least one first connection line and at least one second connection line are electrically connected in the display area; at least one second connection line is connected to a first frame trace located in a first frame area, and at least one first connection line is connected to a second frame trace located in a second frame area.

[0104] In some exemplary embodiments, the first border trace, the second border trace, at least one first connecting line, and at least one second connecting line of the first signal line are arranged on the same layer; or, the first border trace, the second border trace, and at least one first connecting line of the first signal line are arranged on the same layer; or, the first border trace, the second border trace, and at least one second connecting line of the first signal line are arranged on the same layer. However, this embodiment is not limited to this.

[0105] In some exemplary embodiments, the display panel further includes multiple data lines located in the display area and electrically connected to multiple sub-pixels. The multiple data lines are configured to provide data signals to the multiple sub-pixels and extend along a second direction. The multiple data lines and at least one first connection line are located in different conductive layers, and at least one of the multiple data lines overlaps with at least one first connection line in the orthographic projection portion of the substrate.

[0106] In some exemplary embodiments, the film layer containing the multiple data lines is located on the side of the film layer containing at least one first connecting line that is away from the substrate; at least one second connecting line is disposed in the same layer as the multiple data lines, or the film layer containing at least one second connecting line is located on the side of the film layer containing the multiple data lines that is close to the substrate. However, this embodiment is not limited in this respect.

[0107] In some exemplary embodiments, the display panel further includes: a plurality of first power lines located in the display area and electrically connected to a plurality of sub-pixels, configured to transmit a first voltage signal to the plurality of sub-pixels, the plurality of first power lines extending along a second direction; at least one of the plurality of first power lines having its orthographic projection on the substrate overlapping with the orthographic projection of at least one first connecting line on the substrate; wherein the plurality of first power lines and the plurality of data lines are disposed on the same layer.

[0108] In some exemplary embodiments, multiple sub-pixels are arranged in multiple columns of sub-pixels along a first direction, and each column of sub-pixels includes multiple sub-pixels arranged sequentially along a second direction; at least one of the multiple first power lines is configured to provide a first voltage signal to two adjacent columns of sub-pixels; the orthographic projection of at least one first connection line on the substrate does not overlap or only partially overlaps with the orthographic projection of at least one first power line on the substrate. However, this embodiment is not limited in this respect.

[0109] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes: a first source / drain metal layer and a second source / drain metal layer disposed on a substrate, the second source / drain metal layer being located on the side of the first source / drain metal layer away from the substrate; a plurality of data lines and a plurality of first power lines being located on the second source / drain metal layer; and a first border trace and a second border trace of the first signal lines being located on the first source / drain metal layer.

[0110] In some exemplary embodiments, at least one first connection line and at least one second connection line of the first signal line are located in the first source-drain metal layer; or, at least one first connection line is located in the first source-drain metal layer and at least one second connection line is located in the second source-drain metal layer.

[0111] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel further includes: a gate metal layer disposed on a substrate, the gate metal layer being located on the side of the first source / drain metal layer close to the substrate; at least one second connection line of the first signal line being located in the first source / drain metal layer, the at least one first connection line being located in the gate metal layer.

[0112] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel further includes: a bottom shielding metal layer and a gate metal layer disposed on a substrate, wherein the bottom shielding metal layer is located on the side of the gate metal layer near the substrate, and the gate metal layer is located on the side of the first source / drain metal layer near the substrate.

[0113] In some exemplary embodiments, at least one first connection line of the first signal line is located in the first source / drain metal layer, and at least one second connection line is located in the bottom shielding metal layer. In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel further includes: an active layer disposed on a substrate, the active layer being located on the side of the bottom shielding metal layer away from the substrate and on the side of the gate metal layer close to the substrate; the orthographic projection of the bottom shielding metal layer on the substrate covers the orthographic projection of the active layer on the substrate.

[0114] In some exemplary embodiments, at least one first connecting line and at least one second connecting line are both located in the bottom shielding metal layer; at least one first connecting line and at least one second connecting line are distributed in an L-shaped plane in the display area.

[0115] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel further includes: a third source / drain metal layer disposed on a substrate, the third source / drain metal layer being located on the side of the second source / drain metal layer away from the substrate; at least one first connection line of the first signal line being located in the third source / drain metal layer, and at least one second connection line being located in the second source / drain metal layer.

[0116] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes: a first source / drain metal layer and a second source / drain metal layer disposed on a substrate, the second source / drain metal layer being located on the side of the first source / drain metal layer away from the substrate. First and second border traces for multiple data lines, multiple first power lines, and first signal lines are located on the first source / drain metal layer; at least one first connection line and at least one second connection line are located on the second source / drain metal layer.

[0117] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes: a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on a substrate. The second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate, and the third source / drain metal layer is located on the side of the second source / drain metal layer away from the substrate. First border traces and second border traces of the first signal lines are located on the first source / drain metal layer. Multiple data lines, multiple first power lines, and at least one second connection line are located on the third source / drain metal layer, and at least one first connection line is located on the second source / drain metal layer.

[0118] In some exemplary embodiments, the display panel further includes: at least one group of connecting holes and a plurality of auxiliary hole groups located in the display area; the connecting hole group includes a plurality of connecting holes arranged in one direction, and one of the auxiliary hole groups includes a plurality of auxiliary holes arranged in one direction; at least one first connecting line is connected to at least one second connecting line through at least one connecting hole; the plurality of auxiliary hole groups include: a plurality of first auxiliary hole groups and a plurality of second auxiliary hole groups; the arrangement direction of the plurality of auxiliary holes in the first auxiliary hole group is different from the arrangement of the plurality of auxiliary holes in the second auxiliary hole group; the plurality of first auxiliary hole groups and the plurality of second auxiliary hole groups are arranged in an array in the display area along a first direction and a second direction. This example, by setting multiple auxiliary hole groups, can reduce the reflectivity difference between the wiring area of ​​the signal connecting line and the remaining area.

[0119] In some exemplary embodiments, the display panel includes multiple connection hole groups, which include: a first connection hole group, a second connection hole group, a third connection hole group, and a fourth connection hole group; at least one first frame area includes a first frame sub-area and a second frame sub-area; at least one second frame area includes a third frame sub-area and a fourth frame sub-area; the display area includes multiple display corner areas, which include: a first display corner area, a second display corner area, a third display corner area, and a fourth display corner area; wherein, the first display corner area is connected to the first frame sub-area and the third frame sub-area; the second display corner area is connected to the second sub-frame area and the third frame sub-area; the third... The display corner area is connected to the second and fourth frame sub-areas; the fourth display corner area is connected to the first and fourth frame sub-areas; the first connecting hole group is located in the first display corner area, the second connecting hole group is located in the second display corner area, the third connecting hole group is located in the third display corner area, and the fourth connecting hole group is located in the fourth display corner area; the multiple connecting holes of the first and third connecting hole groups and the multiple auxiliary holes of the first auxiliary hole group are arranged in the same direction, all along the third direction; the multiple connecting holes of the second and fourth connecting hole groups and the multiple auxiliary holes of the second auxiliary hole group are arranged in the same direction, all along the fourth direction; the third direction intersects the fourth direction.

[0120] In some exemplary embodiments, the display area includes: a first center line extending along a first direction and a second center line extending along a second direction; a plurality of first auxiliary hole groups and a plurality of second auxiliary hole groups are symmetrically arranged about the first center line or about the second center line within the display area. The arrangement of the plurality of auxiliary hole groups in this example can help reduce the reflectivity difference between the wiring area of ​​the signal connection line and the remaining area.

[0121] In some exemplary embodiments, the display panel further includes: multiple data lines and multiple data transmission lines; the multiple data lines are located in the display area and connected to multiple sub-pixels, the multiple data lines are configured to provide data signals to the multiple sub-pixels, and the multiple data lines extend along a second direction; the multiple data transmission lines are at least partially located in the display area; the multiple data transmission lines correspond one-to-one with the multiple data lines and are configured to provide data signals to the multiple data lines; the multiple data transmission lines include multiple first sub-data transmission lines extending along a first direction and multiple second sub-data transmission lines extending along a second direction, the multiple first sub-data transmission lines are disposed on different layers from the multiple data lines; the orthographic projection of at least one of the multiple first sub-data transmission lines on the substrate partially overlaps with the orthographic projection of at least one of the multiple data lines on the substrate; and the multiple first sub-data transmission lines are distributed on the side of the multiple first connecting lines away from their nearest neighbor peripheral area; the multiple second sub-data transmission lines are distributed on the side of the multiple second connecting lines away from their nearest neighbor peripheral area; a second connecting line, a second sub-data transmission line, or an auxiliary trace is disposed between two adjacent data lines.

[0122] In some exemplary embodiments, the display panel further includes: at least one data connection hole group and a plurality of auxiliary hole groups located in the display area, wherein the data connection hole group includes a plurality of data connection holes; a plurality of first sub-data transmission lines correspond one-to-one with the plurality of data lines and are electrically connected through the data connection holes; the plurality of auxiliary holes in at least one of the plurality of auxiliary hole groups are arranged in a "Y" shape, and the plurality of auxiliary hole groups are arrayed in the display area along a first direction and a second direction; and the display panel further includes: a second center line extending along the second direction, and the plurality of auxiliary hole groups are symmetrically arranged about the second center line in the display area. The arrangement of the plurality of auxiliary hole groups in this example can help reduce the reflectivity difference between the wiring area of ​​the signal connection line and the remaining area.

[0123] In some exemplary embodiments, the first signal line is a second power line configured to provide a second voltage signal to a plurality of sub-pixels; or, the display panel includes a plurality of first signal lines, the plurality of first signal lines including: at least one second power line and at least one initialization signal line, the at least one second power line being configured to provide a second voltage signal to a plurality of sub-pixels; and the at least one initialization signal line being configured to provide an initialization signal to a plurality of sub-pixels.

[0124] The display panel of this embodiment will be illustrated with several examples below.

[0125] Figure 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in Figure 1, the display panel 100 includes a display area AA (Active Area, abbreviated as AA) and a peripheral area surrounding the display area AA. The peripheral area includes a first border area extending along a first direction X, a second border area extending along a second direction Y, and four border corner areas. The first border area may include a first border sub-area L1 and a third border sub-area L3 located on both sides of the display area AA along the second direction Y. The second border area may include a second border sub-area L2 and a fourth border sub-area L4 located on both sides of the display area AA along the first direction X. The four border corner areas may include a first border corner area R1, a second border corner area R2, a third border corner area R3, and a fourth border corner area R4. The first border corner area R1 connects the first border sub-area L1 and the second border sub-area L2, the second border corner area R2 connects the second border area L2 and the third border area L3, the third border corner area R3 connects the third border area L3 and the fourth border area L4, and the fourth border corner area R4 connects the fourth border sub-area L4 and the first border area L1. In some other examples, the surrounding area may also partially surround the display area AA; however, this embodiment is not limited to this.

[0126] In some exemplary embodiments, as shown in FIG1, the display area AA can be a rectangle, such as a rounded rectangle. However, this embodiment is not limited to this. For example, the display area AA can be a circle, an ellipse, or other shapes.

[0127] In some examples, the display area AA can be a flat area comprising multiple sub-pixels Pxij that make up the pixel array. These sub-pixels Pxij can be configured to display moving or still images, and the display area AA can be referred to as the effective area. In exemplary embodiments, the display panel can be made of a flexible substrate, thus allowing it to be deformable, such as rolled, bent, folded, or rolled up.

[0128] In some examples, at least one sub-pixel Pxij includes a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the light-emitting element. For example, the pixel circuit is configured to provide a driving current to drive the light-emitting element to emit light. For example, the light-emitting element can be an organic light-emitting diode (OLED), which emits red, green, blue, or white light under the drive of its corresponding pixel circuit. The color emitted by the light-emitting element can be determined as needed. In some exemplary embodiments, the light-emitting element may include: a first electrode (e.g., an anode), a second electrode (e.g., a cathode), and an organic light-emitting layer disposed between the first and second electrodes. The first electrode may be electrically connected to the pixel circuit. However, this embodiment is not limited to this. In other exemplary embodiments, the light-emitting element may be a quantum dot light-emitting diode (QLED), a micro-LED, or a mini-LED. In other examples, the second electrode of the light-emitting element may be electrically connected to the pixel circuit.

[0129] In some exemplary embodiments, the display area may include multiple pixel units. A pixel unit may include three sub-pixels (e.g., a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G), and the light-emitting elements of the three sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. Alternatively, a pixel unit may include four sub-pixels (a red sub-pixel R, a blue sub-pixel B, a green sub-pixel G, and a white sub-pixel), and the light-emitting elements of the four sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this disclosure does not limit the scope of the embodiments.

[0130] In some exemplary embodiments, the display panel further includes a bonding area BB located on one side of the display area AA. The bonding area BB may be disposed on the side of the first frame sub-area L1 away from the display area AA. The bonding area BB may include a bending area, a driver chip area, and a bonding pin area arranged sequentially along the direction away from the display area AA. The first frame sub-area L1 may be connected to the display area AA and includes at least data leads, power signal lines, initialization signal lines, etc. The bending area connected to the first frame sub-area L1 may include at least a composite insulating layer with grooves. The grooves are configured to bend the driver chip area and bonding pin area of ​​the bonding area BB to the back side of the display area AA. The driver chip area may include an integrated circuit (IC) configured to connect to multiple data leads. The bonding pin area may include bonding pads configured to bond to an external flexible printed circuit (FPC).

[0131] In some exemplary embodiments, a portion of the peripheral area, such as the second bezel area L2, may include a circuit area, a power line area, a crack dam area, and a cutting area arranged sequentially along a direction away from the display area AA. The circuit area, connected to the display area AA, may include at least a gate driving circuit connected to scan signal lines and light-emitting signal lines in the display area AA. The power line area, connected to the circuit area, may include at least bezel power leads extending parallel to the edge of the display area and connected to the cathode in the display area AA. The crack dam area, connected to the power line area, may include at least a plurality of cracks formed on the composite insulating layer. The cutting area, connected to the crack dam area, may include at least a cutting groove formed on the composite insulating layer, configured such that after all film layers of the display panel have been prepared, a cutting device cuts along the cutting grooves respectively.

[0132] In some implementations, the bezel traces originate from the first bezel sub-region L1 and are routed around the remaining sides of the display area AA. To achieve high brightness and heat dissipation, the bezel traces are typically designed with a large linewidth, especially in the bezel corners. However, bezel traces with large linewidths limit the narrowing of the display panel's bezels, making the four corners of the display panel a bottleneck for bezel reduction.

[0133] Figure 2 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. The display panel may include at least one panel corner area. The panel corner area may include a display corner area, a border corner area, and a portion of a first border area and a portion of a second border area connected to the border corner area. As shown in Figure 2, the display panel may include multiple panel corner areas, which may include a first panel corner area D1, a second panel corner area D2, a third panel corner area D3, and a fourth panel corner area D4. The panel corner areas in Figure 2 are indicated by dashed boxes. The first panel corner area D1 is connected to the first border sub-area L1 and the second border sub-area L2; the second panel corner area D2 is connected to the second sub-border area L2 and the third border sub-area L3; the third panel corner area D3 is connected to the third border sub-area L3 and the fourth border area L4; and the fourth panel corner area D4 is connected to the first border sub-area L1 and the fourth border area L4.

[0134] In some examples, as shown in Figure 2, the first signal line 110 may include: a first border trace 120 located in a first border area, a second border trace 130 located in a second border area, and at least one set of signal connection lines 140 located in the display area AA. In each display corner area, the first border trace 120 is electrically connected to the second border trace 130 through the at least one set of signal connection lines 140.

[0135] Figure 3 is an enlarged view of the first panel corner area D1 in Figure 2. As shown in Figures 2 and 3, the orthographic projection of the outer contour of the display corner area onto the substrate may include a first straight line segment extending along the first direction X, a corner segment, and a second straight line segment extending along the second direction Y, connected sequentially. As shown in Figure 2, the display area may include a first display corner area, a second display corner area, a third display corner area, and a fourth display corner area. The first display corner area is connected to the first frame sub-area L1 and the second frame sub-area L2, and the corner segment of the outer contour of the first display corner area corresponds to the first frame corner area R1. The second display corner area is connected to the second frame sub-area L2 and the third frame sub-area L3, and the corner segment of the outer contour of the second display corner area corresponds to the second frame corner area R2. The third display corner area is connected to the third frame sub-area L3 and the fourth frame sub-area L4, and the corner segment of the outer contour of the third display corner area corresponds to the third frame corner area R3. The fourth display corner area is connected to the first frame sub-area L1 and the fourth frame sub-area L4, and the corner segment of the outer contour of the fourth display corner area corresponds to the fourth frame corner area R4.

[0136] In some examples, taking the first panel corner area D1 as an example, within the first display corner area, the first signal line 110 may include a portion of the first frame trace 120 located in the first frame sub-area L1, a portion of the second frame trace 130 located in the second frame sub-area L2, and at least one set of signal connection lines 140 connecting the first frame trace 120 and the second frame trace 130. As shown in Figure 2, the first frame trace 120 and the second frame trace 130 are connected by a set of signal connection lines 140 located in the display area AA, meaning that the orthographic projection of the first signal line 110 on the display panel does not overlap with the first frame corner area R1. As shown in Figure 2, all four panel corner areas of the display panel adopt the above-described configuration. Through this connection method, the four frame areas of the display panel can be narrowed as much as possible, achieving an extremely narrow bezel. In other embodiments, the above configuration may only be used in the two panel corner areas of the lower frame of the display panel. Through this connection method, the width of the lower frame can be narrowed.

[0137] In some exemplary embodiments, as shown in FIG3, the first signal line may include multiple sets of signal connection lines 140. Taking the first panel corner area D1 as an example, one set of signal connection lines 140 may include multiple signal connection lines. For example, the orthographic projection of each signal connection line onto the substrate may be L-shaped. In other exemplary embodiments, as shown in FIG4, the first signal line may include a set of signal connection lines 140 located in the first display corner area, and this set of signal connection lines 140 may be a mesh structure. Within the display area AA, the signal connection lines are designed as a mesh structure to prevent the risk of high-current short circuits. In other examples, as shown in FIG5, a set of signal connection lines 140 may be an L-shaped planar structure, which can further prevent the risk of high-current short circuits and improve the heat dissipation performance of the first signal line 110. In the four corner areas of the entire display panel, any one of the connection methods shown in Figures 3, 4, and 5 can be used, or any combination of two or three methods can be used. For example, all four corner areas include a mesh-like signal connection line, or the lower corner area includes a mesh-like signal connection line, and the upper corner area includes a signal connection line with an L-shaped surface structure, etc. The embodiments disclosed herein are not limited.

[0138] In some exemplary embodiments, as shown in FIG6, the display panel may include multiple auxiliary traces 20. These auxiliary traces 20 may be dummy traces. The multiple auxiliary traces are distributed in a grid pattern within the display area AA. This grid-like trace design can eliminate the problem of increased local reflectivity caused by the signal connection line 140 crossing within the display area AA. The orthographic projections of the multiple auxiliary traces 20 onto the substrate may not overlap with the orthographic projections of the signal connection line 140 onto the substrate; for example, auxiliary traces 20 may not be provided in the display corner area. In other examples, the orthographic projections of the multiple auxiliary traces 20 onto the substrate may partially overlap with the orthographic projections of the signal connection line 140 onto the substrate. For example, at least one auxiliary trace extending along the second direction Y may extend to the display corner area.

[0139] In some examples, the auxiliary trace 20 can be selected to connect to a stable potential of the panel, such as a first voltage signal VDD, a second voltage signal VSS, or an initialization signal Vinit, to stabilize the voltage. This exemplary embodiment does not limit this.

[0140] Figure 7-1 is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure. Figure 7-1 illustrates the structure of a sub-pixel of the display area as an example. In this example, the pixel circuit includes a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor.

[0141] In some exemplary embodiments, as shown in FIG7-1, in a direction perpendicular to the display panel, the display area of ​​the display panel may include at least: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate 10. The circuit structure layer 12 may include at least: pixel circuits of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements of a plurality of sub-pixels. In other examples, the display panel may also include a touch structure layer located on the side of the encapsulation structure layer away from the substrate.

[0142] In some exemplary embodiments, Figure 7-1 illustrates an example where each sub-pixel includes a first-type transistor 21, a second-type transistor 22, and a capacitor 23. The first-type transistor 21 can be a low-temperature polycrystalline silicon thin-film transistor, and the second-type transistor 22 can be an oxide thin-film transistor.

[0143] In some exemplary embodiments, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer SD1, and a second source / drain metal layer SD2 disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer; a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be disposed between the third gate metal layer and the first source / drain metal layer SD1; a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planarization layer) may be disposed between the first source / drain metal layer SD1 and the second source / drain metal layer SD2, wherein the seventh insulating layer 107 may be located on the side of the sixth insulating layer 106 away from the substrate 10; an eighth insulating layer 108 (also referred to as a second planarization layer) may be disposed on the side of the second source / drain metal layer SD2 away from the substrate 10. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106 can be inorganic insulating layers, while the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, this embodiment is not limited to these. In some other examples, a buffer layer can also be provided on the side of the first semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating the interior of the display panel and can also increase the adhesion of the film layers in the display panel to the substrate. In some other examples, a bottom shielding metal layer (BSM) can also be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistors of the pixel circuit to avoid external light affecting the performance of the transistors. In some other examples, the sixth insulating layer can be omitted between the first source / drain metal layer SD1 and the second source / drain metal layer SD2, and only the seventh insulating layer can be provided between the first source / drain metal layer SD1 and the second source / drain metal layer SD2.

[0144] In some exemplary embodiments, as shown in FIG7-1, the first semiconductor layer of the display area may include at least: a first active layer 210 of a first type transistor 21. The first active layer 210 of the first type transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a first gate 213 of the first type transistor 21, and a first electrode 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first type transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 onto the substrate 10. The second gate metal layer may include at least: a second electrode 232 of the capacitor 23, and a third gate 224 of the second type transistor 22. The orthographic projections of the second electrode 232 and the first electrode 231 of the capacitor 23 onto the substrate 10 may at least partially overlap, for example, they may coincide. The second semiconductor layer may include at least: a second active layer 220 of the second type transistor 22. The third gate metal layer may include at least: a second gate 223 of the second type transistor 22. The orthographic projection of the second gate 223 of the second type transistor 22 onto the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 onto the substrate 10. The orthographic projection of the third gate 224 of the second type transistor 22 onto the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 onto the substrate 10. The third gate 224 may be the bottom gate of the second type transistor 22, and the second gate 223 may be the top gate of the second type transistor 22.

[0145] In some exemplary embodiments, as shown in FIG7-1, the first source-drain metal layer SD1 of the display area may include at least: a first source 211 and a first drain 212 of a first type transistor 21, and a second source 221 and a second drain 222 of a second type transistor 22. The fifth insulating layer 105 may have multiple pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105, the fourth insulating layer 104, and the third insulating layer 103 within the third and fourth pixel vias can be removed, exposing at least a portion of the surface at both ends of the second active layer 220. The first source 211 of the first type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer SD2 may include at least a first transition electrode 241. The first transition electrode 241 can be electrically connected to the first drain 212 of the first type transistor 21 in the pixel circuit through the fifth pixel via formed by the sixth insulating layer 106 and the seventh insulating layer 107. This example demonstrates the electrical connection between the pixel circuit and the light-emitting element via the first adapter electrode 241.

[0146] In some exemplary embodiments, the gate lines of the display area may be located, for example, in the first gate metal layer and the third gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer SD2; and the first power lines of the display area may be located, for example, in the second source-drain metal layer SD2. This embodiment is not limited in this respect.

[0147] In some exemplary embodiments, as shown in FIG7-1, the light-emitting structure layer 13 may include a pixel definition layer 134 and a plurality of light-emitting elements. For example, each light-emitting element may include a first electrode 131, an organic light-emitting layer 132, and a second electrode 133 stacked together. The first electrode 131 of the light-emitting element may be an anode, and the first electrode 131 may be disposed on an eighth insulating layer 108 and electrically connected to a first transition electrode 241 through a sixth pixel via formed in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108, and the pixel definition layer 134 may have a plurality of pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 may emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0148] In some exemplary embodiments, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be utilized to emit light at the required grayscale.

[0149] In some exemplary embodiments, the light-emitting layers of light-emitting elements of different colors can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, and the electron injection layer and electron transport layer on the other side of the light-emitting layer can also be common layers. In some exemplary embodiments, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some exemplary embodiments, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0150] In some exemplary embodiments, as shown in FIG7-1, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display panel and relieve stress on the first encapsulation layer 141 and the third encapsulation layer 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0151] In some exemplary embodiments, FIG7-1 is a partial cross-sectional view of a dual SD display panel. As shown in FIG7-1, the first transition electrode 241 is disposed on the second source / drain metal layer, and the signal connection line 140 can be disposed on the same layer and with the same patterning process as the first transition electrode 241. In addition, as shown in FIG7-3, the circuit structure layer of the display panel may include three source / drain metal layers. In a triple SD display panel, the signal connection line 140 can also be disposed on the same layer and with the same patterning process as the second transition electrode 251. The only difference between FIG7-3 and FIG7-1 is that FIG7-3 adds a ninth insulating layer 109 located on the side of the eighth insulating layer 108 away from the substrate 10, and a second transition electrode 251 located on the side of the eighth insulating layer 108 away from the substrate 10. The second transition electrode 251 is disposed on the third source / drain metal layer SD3.

[0152] Figure 7-2 is another partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some exemplary embodiments, the transistor types of the plurality of pixel transistors in the pixel circuit may be the same, for example, they may all be low-temperature polycrystalline silicon thin-film transistors. Figure 7-2 illustrates an example of each sub-pixel including a first-type transistor 21 and a capacitor 23.

[0153] In some exemplary embodiments, as shown in FIG7-2, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer SD1, and a second source / drain metal layer SD2 disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer; a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the first source / drain metal layer SD1; a sixth insulating layer 106 and a seventh insulating layer 107 may be disposed between the first source / drain metal layer SD1 and the second source / drain metal layer SD2; and an eighth insulating layer 108 may be disposed on the side of the second source / drain metal layer SD2 away from the substrate 10. The seventh insulating layer 107 and the eighth insulating layer 108 may be organic insulating layers, and the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers. The remaining structure of the display area of ​​the display panel in this example can be referred to the description of the embodiment shown in FIG7-1, and will not be repeated here.

[0154] Figure 7-4 is another partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure. As shown in Figure 7-4, the circuit structure layer 12 of the display panel may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a third source / drain metal layer SD3 disposed on a substrate 10. An eighth insulating layer 108 may be disposed between the second source / drain metal layer SD2 and the third source / drain metal layer SD3, and a ninth insulating layer 109 may be disposed on the side of the third source / drain metal layer SD3 away from the substrate 10. The eighth insulating layer 108 and the ninth insulating layer 109 may be organic insulating layers. Further descriptions of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0155] Figure 8-1 is a partial cross-sectional view along the 11' direction showing the connection method of the connecting line at the second frame sub-region L2 in Figure 3. In some exemplary embodiments, taking the film layer structure of the display panel shown in Figure 7-2 as an example, as shown in Figure 8-1, the circuit structure layer of the second frame sub-region L2 may include: a first source / drain metal layer SD1, a second source / drain metal layer SD2, an anode metal layer AND, and a cathode metal layer CAD disposed on the substrate 10. A seventh insulating layer 107 (also called a first planarization layer) may be disposed between the first source / drain metal layer SD1 and the second source / drain metal layer SD2, and an eighth insulating layer 108 (also called a second planarization layer) may be disposed between the second source / drain metal layer SD2 and the anode metal layer AND; a pixel definition layer 134 may be disposed between the anode metal layer AND and the cathode metal layer CAD. Figure 8-1 shows the connection of signal connection line 140 to the second frame sub-area L2 when it is located in the first source-drain metal layer SD1. Signal connection line 140 and the trace located in the second frame sub-area and in the second source-drain metal layer SD2 (e.g., the second frame trace) are electrically connected through a large via. Then, the trace located in the second source-drain metal layer SD2 (e.g., the second frame trace) is connected to the anode metal layer AND and the cathode metal layer CAD in the second frame sub-area L2 through vias in sequence. Then, it is electrically connected to the cathode of the display area through the cathode metal layer, thereby providing power signals and other display signals to the display area.

[0156] In some exemplary embodiments, the signal connection line 140 can also be disposed on the second source-drain metal layer SD2 and then connected to the second frame sub-region L2, as shown in FIG8-2. The signal connection line 140 located on the second source-drain metal layer SD2 is electrically connected to the anode metal layer AND located on the second frame sub-region L2 through a via. The anode metal layer AND is connected to the cathode metal layer CAD, and then electrically connected to the cathode of the display area through the cathode metal layer CAD, thereby providing display signals such as power signals to the display area. In addition, as shown in FIG8-2, the traces of the first source-drain metal layer SD1 and the traces of the second source-drain metal layer SD2 located on the second frame sub-region L2 are shorted through vias, which can effectively reduce the resistance of the signal line. For example, the signal connection line 140 and the second frame traces can be an integral structure, both located on the second source-drain metal layer, and the traces located on the first source-drain metal layer can be connected to the integral structure of the signal connection line and the second frame traces; or, for example, the signal connection line 140 is located on the second source-drain metal layer, and the second frame traces can be located on the first source-drain metal layer, and the signal connection line 140 can be electrically connected to the second frame traces through vias. In addition, the signal connection line can also be connected to the second frame sub-area L2 through the third source-drain metal layer SD3, which is not limited here.

[0157] In some exemplary embodiments, as shown in FIG9, the display panel further includes multiple data lines DL and multiple data transmission lines 150. The multiple data lines DL extend along a second direction Y within the display area AA and are electrically connected to multiple sub-pixels to provide data signals to the corresponding sub-pixels. The multiple data transmission lines 150 extend from a first border sub-area L1 and are at least partially located within the display area. Each of the multiple data transmission lines 150 corresponds one-to-one with the multiple data lines DL to provide data signals to the corresponding data lines DL. The multiple data transmission lines 150 include multiple first sub-data transmission lines 1501 extending along a first direction X and multiple second sub-data transmission lines 1502 extending along a second direction Y. The multiple first sub-data transmission lines 1501 are disposed on different layers from the multiple data lines DL. The orthographic projection of at least one of the first sub-data transmission lines 1501 on the substrate 10 partially overlaps with the orthographic projection of at least one of the multiple data lines DL on the substrate 10. Multiple data transmission lines 150 and at least one signal connection line 140 can be set on the same layer or on different layers; this is not limited here.

[0158] In some examples, multiple data transmission lines 150 can be positioned on the side of multiple signal connection lines 140 away from the surrounding area. For example, multiple first sub-data transmission lines 1501 are positioned on the side of multiple first connection lines 131 away from their nearest neighbor in the surrounding area; the multiple second sub-data transmission lines 1502 are distributed on the side of multiple second connection lines 132 away from their nearest neighbor in the surrounding area; this can minimize the length of the signal connection lines 140 and reduce resistance.

[0159] In some examples, the display panel may also include multiple auxiliary traces 20. These auxiliary traces 20 and data lines DL are spaced apart in the first direction X, forming a grid-like distribution. Specifically, a second connection line 132, a second sub-data transmission line 1502, or an auxiliary trace 20 can be positioned between adjacent data lines. The projections of the auxiliary traces 20 onto the substrate do not overlap with the projections of the data transmission lines 150 onto the substrate. By using multiple auxiliary traces, the problem of increased local reflectivity caused by the signal connection line 140 and the data transmission lines 150 crossing within the display area AA can be effectively eliminated. The multiple auxiliary data lines 20 can be selectively connected to a stable potential of the panel, such as VDD, VSS, or Vinit; this is not limited here.

[0160] Next, the specific implementation of the signal connection line will be described in detail with reference to the accompanying drawings. In the following example, the first border trace 120 and the second border trace 130 can both be located in the first source / drain metal layer.

[0161] Figure 10-1 illustrates a connection method for the signal connection lines of a display panel according to at least one embodiment. Figure 10-2 is a partial cross-sectional view along the CC' direction in Figure 10-1. As shown in Figures 10-1 and 10-2, the signal connection line 140 includes a first connection line 131 and a second connection line 132. The first power line VDDL and the data line DL of the display area can be disposed on the second source / drain metal layer SD2, and the first connection line 131 and the second connection line 132 can be disposed on the first source / drain metal layer SD1. The first connection line 131 and the second connection line 132 are formed in the same layer and with the same patterning process as the first bezel trace 120 and the second bezel trace 130, that is, the first connection line 131 and the second connection line 132 are integrally structured with the first bezel trace 120 and the second bezel trace 130. In this embodiment, the first power line VDDL, the data line DL, and the second connecting line 132 all extend along the second direction Y and are arranged sequentially away from the second border sub-region L2. The orthographic projections of the first power line VDDL, the data line DL, and the first connecting line 131 on the substrate do not overlap, but partially overlap with the orthographic projection of at least one sub-pixel Pxij on the substrate. The first connecting line 131 extends along the first direction X, and the projection of the first connecting line 131 on the substrate can be located in the gap between the orthographic projections of the pixel circuits of two adjacent sub-pixels Pxij on the substrate. For example, the first connecting line 131 is connected to the second border sub-region L2 through an integral structure with the second border trace 130, as shown in FIG8-1.

[0162] Figure 11-1 shows another connection method for the signal connection line of the display panel. Figure 11-2 is a partial cross-sectional view along the DD' direction in Figure 11-1, and Figure 11-3 is a partial cross-sectional view along the EE' direction in Figure 11-1. As shown in Figures 11-1, 11-2, and 11-3, the signal connection line 140 includes a first connection line 131 and a second connection line 132. The second connection line 132, the first power line VDDL, and the data line DL can be disposed on the second source-drain metal layer SD2, and the first connection line 131 can be disposed on the first source-drain metal layer SD1. The first connection line 131 and the second frame trace 130 can be on the same layer or as a single unit; the second connection line 132 and the first frame trace 120 are electrically connected through vias. In this embodiment, the first power line VDDL, the data line DL, and the second connecting line 132 all extend along the second direction Y and are arranged sequentially away from the second border sub-region L2. The projections of the first power line VDDL, the data line DL, and the second connecting line 132 on the substrate do not overlap, but partially overlap with the orthographic projection of at least one sub-pixel Pxij on the substrate. The first connecting line 131 extends along the first direction X, and the projection of the first connecting line 131 on the substrate is located in the gap between the orthographic projections of the pixel circuits of two adjacent sub-pixels Pxij on the substrate. For example, the first connecting line 131 can be integrated with the second border trace 130, as shown in FIG8-1, to access the second border sub-region L2.

[0163] Figure 12-1 shows another connection method for the signal connection lines of the display panel according to at least one embodiment; Figure 12-2 is a partial cross-sectional view along the FF' direction in Figure 12-1, and Figure 12-3 is a partial cross-sectional view along the GG' direction in Figure 12-1. As shown in Figures 12-1, 12-2, and 12-3, the signal connection line 140 includes a first connection line 131 and a second connection line 132. The first power line VDDL and the data line DL can be disposed on the second source / drain metal layer SD2, the second connection line 132 can be disposed on the first source / drain metal layer SD1, and the first connection line 131 can be disposed on the side of the second connection line 132 closer to the substrate, for example, it can be located in the first gate metal layer or the second gate metal layer. In this embodiment, the first power line VDDL, the data line DL, and the second connecting line 132 all extend along the second direction Y and are arranged sequentially away from the second border sub-region L2. The orthographic projections of the first power line VDDL, the data line DL, and the second connecting line 132 on the substrate do not overlap, but partially overlap with the orthographic projection of at least one sub-pixel Pxij on the substrate. The first connecting line 131 extends along the first direction X, and its projection on the substrate is located in the gap between the orthographic projections of the pixel circuits of two adjacent sub-pixels Pxij on the substrate. The first connecting line 131 and the second border trace 130 can be electrically connected through vias. The first border trace 120 and the second connecting line 132 can be an integral structure.

[0164] Figure 13-1 shows another connection method for the signal connection lines of the display panel according to at least one embodiment; Figure 13-2 is a partial cross-sectional view along the HH' direction in Figure 13-1, and Figure 13-3 is a partial cross-sectional view along the II' direction in Figure 13-1. As shown in Figures 13-1, 13-2, and 13-3, the signal connection line 140 includes a first connection line 131 extending along a first direction X and a second connection line 132 extending along a second direction Y. The first power line VDDL and the data line DL can be disposed on the second source / drain metal layer SD2, the first connection line 131 can be disposed on the first source / drain metal layer SD1, and the second connection line 132 can be located on the side of the first connection line 131 close to the substrate, for example, it can be disposed on the bottom light-shielding metal layer. In this embodiment, the first power line VDDL, the data line DL, and the second connecting line 132 all extend along the second direction Y and are arranged sequentially away from the second border sub-region L2. The orthographic projections of the first power line VDDL, the data line DL, and the second connecting line 132 on the substrate do not overlap, but partially overlap with the orthographic projection of at least one sub-pixel Pxij on the substrate. The first connecting line 131 extends along the first direction X, and its projection on the substrate can be located in the gap between the orthographic projections of the pixel circuits of two adjacent sub-pixels Pxij on the substrate. The second border trace 130 and the first border trace 120 can be located in the first source / drain metal layer. The second connecting line 132 and the first border trace 120 can be electrically connected through vias. The first connecting line 131 and the second border trace 130 can be an integral structure and can be connected to the second border sub-region L2 as shown in FIG8-1.

[0165] Furthermore, as shown in Figures 14-1, 14-2, and 14-3, unlike the exemplary embodiment shown in Figure 13-1, the second connecting line 132 located in the bottom light-shielding layer simultaneously blocks the active layer of the pixel circuit. For example, the orthographic projection of the second connecting line 132 onto the substrate can cover the orthographic projection of the active layer of multiple transistors of the pixel circuit onto the substrate. The projection of the second connecting line 132 onto the substrate partially overlaps with the projections of the first power line VDDL and the data line DL onto the substrate. All other aspects are the same as in the exemplary embodiment shown in Figure 13-1, and will not be repeated here.

[0166] Figure 15-1 shows another connection method for the signal connection line of the display panel in at least one embodiment. Figure 15-2 is a partial cross-sectional view of Figure 15-1 along the LL' direction. Figure 15-3 is a partial cross-sectional view of Figure 15-1 along the MM' direction. Figure 15-4 is a partial cross-sectional view of Figure 15-1 along the NN' direction. As shown in Figures 15-1, 15-2, 15-3, and 15-4, the signal connection line 140 includes a first connection line 131 extending along a first direction X and a second connection line 132 extending along a second direction Y. The first power line VDDL and the data line DL can be disposed on the first source-drain metal layer SD1, and the first connection line 131 and the second connection line 132 can be disposed on the second source-drain metal layer SD2. In this embodiment, the first power line VDDL, the data line DL, and the second connecting line 132 all extend along the second direction Y and are arranged sequentially away from the second border sub-region L2. The orthographic projections of the first power line VDDL, the data line DL, and the second connecting line 132 on the substrate do not overlap, but partially overlap with the orthographic projection of at least one sub-pixel Pxij on the substrate. The first connecting line 131 extends along the first direction X, and the projection of the first connecting line 131 on the substrate is located in the gap between the orthographic projections of the pixel circuits of two adjacent sub-pixels Pxij on the substrate. The first connecting line 131 is electrically connected to the second border trace 120 through a via; the second connecting line 132 is electrically connected to the first border trace 120 through a via. For example, the second connecting line 132 can be connected to the second border sub-region L2 in the manner shown in Figure 8-2.

[0167] Figure 16-1 shows another connection method for the signal connection lines of the display panel in at least one embodiment; Figure 16-2 is a partial cross-sectional view along the OO' direction in Figure 16-1, and Figure 16-3 is a partial cross-sectional view along the PP' direction in Figure 16-1. As shown in Figures 16-1, 16-2, and 16-3, the signal connection line 140 includes a first connection line 131 extending along a first direction X and a second connection line 132 extending along a second direction Y. The first power line VDDL and the data line DL can be disposed on the second source / drain metal layer SD2, and the first connection line 131 and the second connection line 132 can be disposed on the third source / drain metal layer SD3. The film layer structure of the display panel in this example can be as shown in Figure 7-4. In this embodiment, the first power line VDDL, the data line DL, and the second connecting line 132 all extend along the second direction Y and are arranged sequentially away from the second border sub-region L2. The orthographic projections of the first power line VDDL, the data line DL, and the second connecting line 132 on the substrate do not overlap, but partially overlap with the orthographic projection of at least one sub-pixel Pxij on the substrate. The first connecting line 131 extends along the first direction X, and the orthographic projection of the first connecting line 131 on the substrate can be located in the gap between the orthographic projections of the pixel circuits of two adjacent sub-pixels Pxij on the substrate. The first connecting line 131 and the second connecting line 132 are electrically connected through vias. The first connecting line 131 is electrically connected to the first border trace 120 through vias. The second connecting line 132 is connected to the second source / drain metal layer SD2 through vias, and then connected to the second border sub-region L2 in the manner shown in FIG8-2.

[0168] Figure 17-1 shows another connection method for the signal connection line of the display panel in at least one embodiment. Figure 17-2 is a partial cross-sectional view along the QQ' direction in Figure 17-1. Figure 17-3 is a partial cross-sectional view along the RR' direction in Figure 17-1. Figure 17-4 is a partial cross-sectional view along the SS' direction in Figure 17-1. As shown in Figures 17-1, 17-2, 17-3, and 17-4, the signal connection line 140 includes a first connection line 131 and a second connection line 132. The second connection line 132, the first power line VDDL, and the data line DL can be disposed on the third source-drain metal layer SD3, and the first connection line 131 can be disposed on the second source-drain metal layer SD2. In this embodiment, the first power line VDDL, the data line DL, and the second connecting line 132 all extend along the second direction Y and are arranged sequentially away from the second border sub-region L2. The orthographic projections of the first power line VDDL, the data line DL, and the second connecting line 132 on the substrate do not overlap, but partially overlap with the orthographic projections of at least one sub-pixel Pxij on the substrate. The first connecting line 131 extends along the first direction X, and the orthographic projection of the first connecting line 131 on the substrate can be located in the gap between the orthographic projections of the pixel circuits of two adjacent sub-pixels Pxij on the substrate. The first connecting line 131 and the second connecting line 132 are electrically connected through vias. The second connecting line 132 can first be connected to the connecting electrode located on the second source / drain metal layer SD2 through a via, and then the connecting electrode is electrically connected to the first border trace 120 located on the first source / drain metal layer through a via. The first connecting line 131 can be connected to the second border sub-region L2 in the manner shown in FIG8-2.

[0169] Furthermore, as shown in Figures 18-1, 18-2, 18-3, and 18-4, the pixels adopt a symmetrical design. That is, at least one of the multiple first power lines is configured to provide a first voltage signal to two adjacent columns of sub-pixels. The orthographic projection of at least one first connection line 131 on the substrate and the orthographic projection of at least one first power line VDDL on the substrate may not overlap or may partially overlap. Two columns of sub-pixels share a single first power line VDDL, which can save layout space.

[0170] Figure 19 illustrates a design of the auxiliary hole area of ​​a display panel according to at least one embodiment. As shown in Figure 19, in some exemplary embodiments, the display panel 100 includes multiple connection hole groups and multiple auxiliary hole groups. The multiple connection hole groups include: a first connection hole group K1, a second connection hole group K2, a third connection hole group K3, and a fourth connection hole group K4; the first connection hole group K1 is located in a first display corner area, the second connection hole group is located in a second display corner area, the third connection hole group K3 is located in a third display corner area, and the fourth connection hole group K4 is located in a fourth display corner area; the multiple auxiliary hole groups include multiple first auxiliary hole groups K11 and multiple second auxiliary hole groups K22. Each connection hole group may include multiple connection holes, and each auxiliary hole group may include multiple auxiliary vias. When multiple first connection lines and multiple second connection lines are located in different conductive layers, at least one first connection line can be electrically connected to at least one second connection line through at least one connection hole.

[0171] In some examples, the plurality of connecting holes in the first connecting hole group K1 and the third connecting hole group K3, as well as the plurality of auxiliary holes in the first auxiliary hole group K11, are arranged in the same direction, all along the third direction X'; the plurality of connecting holes in the second connecting hole group K2 and the fourth connecting hole group K4, as well as the plurality of auxiliary holes in the second auxiliary hole group K22, are arranged in the same direction, all along the fourth direction Y'; the third direction X' intersects the fourth direction Y'. The third direction X' intersects both the first direction X and the second direction Y, and the fourth direction Y' intersects both the first direction X and the second direction Y. For example, the third direction X' can be perpendicular to the fourth direction Y'.

[0172] In some examples, as shown in Figure 19, the display area AA may include a first centerline Z1 extending along a first direction X and a second centerline Z2 extending along a second direction Y. A plurality of first auxiliary hole groups K11 and a plurality of second auxiliary hole groups K22 may be arranged symmetrically about the first centerline Z1 or about the second centerline Z2.

[0173] This example, through the design of auxiliary aperture groups, can effectively reduce the difference in reflectivity between the partial aperture area and the normal display area when the signal connection line is transferred in the display area, thereby improving the display effect.

[0174] Figure 20 illustrates another design of the auxiliary aperture area of ​​a display panel according to at least one embodiment. As shown in Figures 9 and 20, the display panel includes multiple data transmission lines and may include multiple data connection aperture groups and multiple auxiliary aperture groups Y11. Each data connection aperture may include multiple data connection apertures. The first sub-data transmission line of the multiple data transmission lines can be electrically connected to the corresponding data line DL through the data connection aperture. A via group Y1 / Y2 / Y3 / Y4 in a "y" shape can be set in the four display corner areas. For example, each via group may include one data connection aperture group and one connection aperture group. In this example, the multiple auxiliary apertures within the auxiliary aperture group can be arranged in a "y" shape, and the multiple auxiliary aperture groups can be arranged in an array along the first direction X and the second direction Y. This example reduces the difference in reflectivity between the partial aperture area and the normal display area during display area transitions by setting multiple auxiliary aperture groups.

[0175] In some examples, as shown in Figure 20, multiple auxiliary hole groups Y11 can be arranged symmetrically about the second center line Z2 of the display area of ​​the display panel 100.

[0176] Figure 21 is a partial structural schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some embodiments, as shown in Figure 21, the first frame trace 120 may further include a first signal sub-line 1201 and a second signal sub-line 1202. The second frame trace 130 may further include a third signal sub-line 1301 and a fourth signal sub-line 1302. The first signal sub-line 1201 and the third signal sub-line 1301 are used to transmit the same signal, and the first signal sub-line 1201 and the third signal sub-line 1301 are connected by a fifth signal sub-line 1401 (e.g., including at least one set of signal connection lines). The second signal sub-line 1202 and the fourth signal sub-line 1302 are used to transmit the same signal, and the second signal sub-line 1202 and the fourth signal sub-line 1302 are connected by a sixth signal sub-line 1402 (e.g., including at least one set of signal connection lines). The first signal sub-line 1201, the third signal sub-line 1301, and the fifth signal sub-line 1401 can be used to transmit the second voltage signal VSS. The second signal sub-line 1202, the fourth signal sub-line 1302, and the sixth signal sub-line 1402 can be used to transmit other signals, such as one or more of the initialization signal Vinit, the high-level signal VGH, and the low-level signal VGL. There are no restrictions here. By setting the traces in the screen bezel area, especially the corner area of ​​the panel, in the display area, the bezel of the display panel can be further reduced, achieving an extremely narrow bezel effect.

[0177] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure, i.e., features within the embodiments, can be combined with each other to obtain new embodiments.

[0178] Figure 22 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 22, the display device 91 may include a display panel 910. The display panel 910 may be an OLED display panel. The display device 91 may be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited thereto.

[0179] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0180] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display panel, comprising: The display area and at least partially surrounding the display area, the peripheral area including: at least one first border area extending along a first direction, at least one second border area extending along a second direction, and at least one border corner area, the border corner area connecting adjacent first border areas and second border areas; the first direction intersects the second direction; The display panel also includes: Substrate; Multiple sub-pixels are disposed on the substrate and located in the display area; At least one first signal line is disposed on the substrate and configured to provide a first signal to the plurality of sub-pixels; the at least one first signal line includes: a first border trace located in the first border area, a second border trace located in the second border area, and at least one set of signal connection lines located in the display area; the first border trace is electrically connected to the second border trace through the at least one set of signal connection lines.

2. The display panel according to claim 1, wherein, The display area includes: at least one display corner area, which is connected to the border corner area, a portion of the first border area connected to the border corner area, and a portion of the second border area connected to the border corner area; The outer contour of the display corner area, projected onto the substrate, includes a first straight line segment, a corner segment, and a second straight line segment connected in sequence. The first straight line segment extends along the first direction, and the second straight line segment extends along the second direction. The at least one set of signal connection lines is located in at least one of the display corner areas.

3. The display panel according to claim 2, wherein, The at least one first border area includes a first border sub-area and a third border sub-area; the at least one second border area includes a second border sub-area and a fourth border area; The display area includes multiple display corner areas, namely: a first display corner area, a second display corner area, a third display corner area, and a fourth display corner area; the first display corner area is connected to the first border sub-area and the second border sub-area; the second display corner area is connected to the second border sub-area and the third border sub-area; the third display corner area is connected to the third border sub-area and the fourth border sub-area; and the fourth display corner area is connected to the first border sub-area and the fourth border sub-area. The at least one set of signal connection lines is located in the first display corner area and the fourth display corner area.

4. The display panel according to claim 3, wherein, The surrounding area includes multiple border corner areas, which include a first border corner area, a second border corner area, a third border corner area, and a fourth border corner area. The first border corner area is connected to the first display corner area; the second border corner area is connected to the second display corner area; the third border corner area is connected to the third display corner area; and the fourth border corner area is connected to the fourth display corner area. The first signal line is discontinuous in the first frame corner area and the fourth frame corner area.

5. The display panel according to claim 1, wherein, The at least one set of signal connection lines includes: multiple signal connection lines located in the display area, the multiple signal connection lines being distributed in a grid pattern in the display area.

6. The display panel according to claim 1, wherein, The at least one set of signal connection lines includes: multiple signal connection lines located in the display area, the multiple signal connection lines being distributed in an L-shaped plane in the display area.

7. The display panel according to claim 1, further comprising: Multiple auxiliary traces are located in the display area, and the multiple auxiliary traces are distributed in a grid pattern in the display area; The projections of the multiple auxiliary traces onto the substrate overlap or do not overlap with the projections of the at least one set of signal connection lines onto the substrate.

8. The display panel according to any one of claims 1 to 7, wherein, The at least one set of signal connection lines includes: multiple signal connection lines located in the display area; the multiple signal connection lines include: at least one first connection line extending along the first direction and at least one second connection line extending along the second direction; the at least one first connection line and the at least one second connection line are electrically connected in the display area; The at least one second connecting line is electrically connected to the first frame trace located in the first frame area, and the at least one first connecting line is electrically connected to the second frame trace located in the second frame area.

9. The display panel according to claim 8, wherein, The first border trace, the second border trace, the at least one first connecting line, and the at least one second connecting line of the first signal line are arranged on the same layer; Alternatively, the first border trace, the second border trace, and the at least one first connecting line of the first signal line are arranged on the same layer; Alternatively, the first border trace, the second border trace, and the at least one second connecting line of the first signal line are arranged on the same layer.

10. The display panel according to claim 8 or 9, further comprising: Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels. The multiple data lines are configured to provide data signals to the multiple sub-pixels and extend along the second direction. The plurality of data lines and the at least one first connection line are located in different conductive layers, and at least one of the plurality of data lines overlaps with the at least one first connection line in the orthogonal projection portion of the substrate.

11. The display panel according to claim 10, wherein, The film layer containing the multiple data lines is located on the side of the film layer containing the at least one first connection line that is away from the substrate. The at least one second connection line is disposed in the same layer as the plurality of data lines, or the film layer containing the at least one second connection line is located on the side of the film layer containing the plurality of data lines closer to the substrate.

12. The display panel according to claim 10 or 11, further comprising: Multiple first power lines are located in the display area and electrically connected to the multiple sub-pixels, configured to transmit a first voltage signal to the multiple sub-pixels, and the multiple first power lines extend along the second direction; At least one of the plurality of first power lines overlaps with the orthographic projection of the first power line on the substrate with the orthographic projection of the at least one first connecting line on the substrate. The multiple first power lines and the multiple data lines are arranged on the same layer.

13. The display panel according to claim 12, wherein, The plurality of sub-pixels are arranged in multiple columns of sub-pixels along the first direction, and each column of sub-pixels includes a plurality of sub-pixels arranged sequentially along the second direction; At least one of the plurality of first power lines is configured to provide a first voltage signal to two adjacent columns of sub-pixels; The orthographic projection of the at least one first connecting line on the substrate does not overlap with or only partially overlaps with the orthographic projection of the at least one first power line on the substrate.

14. The display panel according to claim 12 or 13, wherein, In a direction perpendicular to the display panel, the display panel includes: a first source / drain metal layer and a second source / drain metal layer disposed on the substrate, wherein the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate. The multiple data lines and the multiple first power lines are located in the second source-drain metal layer; the first border trace and the second border trace of the first signal line are located in the first source-drain metal layer.

15. The display panel according to claim 14, wherein, The at least one first connection line and the at least one second connection line of the first signal line are located in the first source-drain metal layer; or, the at least one first connection line is located in the first source-drain metal layer and the at least one second connection line is located in the second source-drain metal layer.

16. The display panel according to claim 14, wherein, In a direction perpendicular to the display panel, the display panel further includes: a gate metal layer disposed on the substrate, the gate metal layer being located on the side of the first source / drain metal layer close to the substrate; The at least one second connection line of the first signal line is located in the first source / drain metal layer, and the at least one first connection line is located in the gate metal layer.

17. The display panel according to claim 14, wherein, In a direction perpendicular to the display panel, the display panel further includes: a bottom shielding metal layer and a gate metal layer disposed on the substrate, wherein the bottom shielding metal layer is located on the side of the gate metal layer near the substrate, and the gate metal layer is located on the side of the first source / drain metal layer near the substrate.

18. The display panel according to claim 17, characterized in that, The first signal line has at least one first connection line located in the first source / drain metal layer, and the first at least one second connection line located in the bottom shielding metal layer.

19. The display panel according to claim 18, wherein, In a direction perpendicular to the display panel, the display panel further includes: an active layer disposed on the substrate, the active layer being located on the side of the bottom shielding metal layer away from the substrate and on the side of the gate metal layer close to the substrate; The projection of the bottom shielding metal layer onto the substrate covers the projection of the active layer onto the substrate.

20. The display panel according to claim 17, wherein, The at least one first connecting line and the at least one second connecting line are both located in the bottom shielding metal layer; the at least one first connecting line and the at least one second connecting line are distributed in an L-shaped plane in the display area.

21. The display panel according to claim 14, wherein, In a direction perpendicular to the display panel, the display panel further includes: a third source / drain metal layer disposed on the substrate, the third source / drain metal layer being located on the side of the second source / drain metal layer away from the substrate; The first signal line has at least one first connection line located in the third source / drain metal layer, and the first second connection line is located in the second source / drain metal layer.

22. The display panel according to claim 12 or 13, wherein, In a direction perpendicular to the display panel, the display panel includes: a first source / drain metal layer and a second source / drain metal layer disposed on the substrate, wherein the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate. The plurality of data lines, the plurality of first power lines, the first border traces and the second border traces of the first signal lines are located in the first source-drain metal layer; the at least one first connection line and the at least one second connection line are located in the second source-drain metal layer.

23. The display panel according to claim 12 or 13, wherein, In a direction perpendicular to the display panel, the display panel includes: a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate, wherein the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate, and the third source / drain metal layer is located on the side of the second source / drain metal layer away from the substrate. The first border trace and the second border trace of the first signal line are located in the first source-drain metal layer, the multiple data lines, the multiple first power lines and the at least one second connection line are located in the third source-drain metal layer, and the at least one first connection line is located in the second source-drain metal layer.

24. The display panel according to any one of claims 8 to 23, further comprising: At least one group of connecting holes and multiple groups of auxiliary holes are located in the display area; The connecting hole group includes a plurality of connecting holes arranged in one direction, and one of the plurality of auxiliary hole groups includes a plurality of auxiliary holes arranged in one direction. The at least one first connecting line is connected to the at least one second connecting line through at least one connecting hole; The plurality of auxiliary hole groups includes: a plurality of first auxiliary hole groups and a plurality of second auxiliary hole groups; The arrangement direction of the multiple auxiliary holes in the first auxiliary hole group is different from the arrangement of the multiple auxiliary holes in the second auxiliary hole group; The plurality of first auxiliary hole groups and the plurality of second auxiliary hole groups are arranged in an array along the first direction and the second direction within the display area.

25. The display panel according to claim 24, wherein, The display panel includes multiple connection hole groups, which include: a first connection hole group, a second connection hole group, a third connection hole group, and a fourth connection hole group; The at least one first border area includes a first border sub-area and a third border sub-area; the at least one second border area includes a second border sub-area and a fourth border sub-area; the display area includes a plurality of display corner areas, the plurality of display corner areas including: a first display corner area, a second display corner area, a third display corner area, and a fourth display corner area; the first display corner area is connected to the first border sub-area and the second border sub-area; the second display corner area is connected to the second border sub-area and the third border area; the third display corner area is connected to the third border sub-area and the fourth border area; the fourth display corner area is connected to the first border sub-area and the fourth border area; The first connection hole group is located in the first display corner area, the second connection hole group is located in the second display corner area, the third connection hole group is located in the third display corner area, and the fourth connection hole group is located in the fourth display corner area; The plurality of connecting holes in the first connecting hole group and the third connecting hole group, as well as the plurality of auxiliary holes in the first auxiliary hole group, are arranged in the same direction, all along a third direction; the plurality of connecting holes in the second connecting hole group and the fourth connecting hole group, as well as the plurality of auxiliary holes in the second auxiliary hole group, are arranged in the same direction, all along a fourth direction; the third direction intersects with the fourth direction.

26. The display panel according to claim 24 or 25, wherein, The display area includes: a first center line extending along the first direction and a second center line extending along the second direction; the plurality of first auxiliary hole groups and the plurality of second auxiliary hole groups are symmetrically arranged about the first center line or about the second center line in the display area.

27. The display panel according to claim 8, further comprising: Multiple data lines are located in the display area and connected to the multiple sub-pixels. The multiple data lines are configured to provide data signals to the multiple sub-pixels and extend along the second direction. Multiple data transmission lines, at least partially located in the display area; each of the multiple data transmission lines corresponds one-to-one with a multiple data line and is configured to provide data signals to the multiple data lines; The plurality of data transmission lines include a plurality of first sub-data transmission lines extending along the first direction and a plurality of second sub-data transmission lines extending along the second direction. The plurality of first sub-data transmission lines are disposed on different layers from the plurality of data lines. The orthographic projection of at least one of the plurality of first sub-data transmission lines on the substrate partially overlaps with the orthographic projection of at least one of the plurality of data lines on the substrate. The plurality of first sub-data transmission lines are distributed on the side of the plurality of first connecting lines away from their nearest neighbor in the surrounding area; the plurality of second sub-data transmission lines are distributed on the side of the plurality of second connecting lines away from their nearest neighbor in the surrounding area; A second connecting line, a second sub-data transmission line, or an auxiliary line is set between two adjacent data lines.

28. The display panel according to claim 27, further comprising: At least one data connection hole group and multiple auxiliary hole groups are located in the display area, wherein the data connection hole group includes multiple data connection holes; The plurality of first sub-data transmission lines correspond one-to-one with the plurality of data lines and are electrically connected through the data connection holes; The auxiliary holes in at least one of the plurality of auxiliary hole groups are arranged in a "Y" shape, and the plurality of auxiliary hole groups are arranged in an array along the first direction and the second direction in the display area; and, The display panel further includes a second center line extending along the second direction, and the plurality of auxiliary hole groups are symmetrically arranged about the second center line within the display area.

29. The display panel according to claim 1, wherein, The first signal line is a second power line, and the second power line is configured to provide a second voltage signal to the plurality of sub-pixels; Alternatively, the display panel includes multiple first signal lines, the multiple first signal lines including: at least one second power line and at least one initialization signal line, the at least one second power line being configured to provide a second voltage signal to the multiple sub-pixels; The at least one initialization signal line is configured to provide an initialization signal to the plurality of sub-pixels.

30. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 29.

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