Array substrate, display panel and display device

Abstract

The present application provides an array substrate, a display panel and a display device. The array substrate comprises a first transistor. The first transistor comprises a first conductor portion, a second conductor portion, a first semiconductor portion, a first gate electrode, a first source electrode and a first drain electrode, wherein the first conductor portion and the second conductor portion are spaced apart from each other, and the first semiconductor portion is at least connected between the first conductor portion and the second conductor portion.

Description

Array substrate, display panel and display device

[0001] This application claims priority to Chinese patent application No. 202411999663.9, filed on December 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0003] With the continuous development of display technology, the requirements for the resolution and screen-to-body ratio of display panels are becoming increasingly stringent. In order to improve the resolution and screen-to-body ratio of display panels, it is necessary to reduce the size of thin-film transistors in the array substrate. Invention Overview

[0004] Currently, the channel length of conventional thin-film transistors (TFTs) is limited by exposure and etching precision, making it difficult to further reduce the size and footprint of TFTs. Further reducing the channel length of TFTs would lead to a negatively biased threshold voltage, and could even cause the TFT to conduct, thus reducing its stability.

[0005] Therefore, it is necessary to provide an array substrate, a display panel, and a display device to improve this defect.

[0006] In a first aspect, embodiments of this application provide an array substrate including a first transistor, the first transistor including a first conductor portion, a second conductor portion, a first semiconductor portion, a first gate, a first source, and a first drain, the array substrate further including:

[0007] Substrate;

[0008] A conductor layer is disposed on the substrate, and a first conductor portion and a second conductor portion are disposed on the conductor layer, with the first conductor portion and the second conductor portion being disposed at a distance from each other;

[0009] A semiconductor layer is disposed on the substrate, the semiconductor layer including a first semiconductor portion, the first semiconductor portion being at least connected between the first conductor portion and the second conductor portion;

[0010] A gate layer, disposed on the side of the semiconductor layer away from the substrate, the gate layer including the first gate; and

[0011] A source-drain layer is disposed on the side of the semiconductor layer away from the substrate, and the source-drain layer includes a first source and a first drain;

[0012] Wherein, one end of the first semiconductor portion is recessed within the end of the first conductor portion away from the second conductor portion, the other end of the first semiconductor portion is recessed within the end of the second conductor portion away from the first conductor portion, the first source is connected to the first conductor portion, and the first drain is connected to the second conductor portion.

[0013] Secondly, embodiments of this application also provide a display panel, including the array substrate as described above.

[0014] Thirdly, embodiments of this application also provide a display device, including the display panel as described above. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments disclosed. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 is a top view of the array substrate provided in an embodiment of this application;

[0017] Figure 2 is a schematic diagram of the film structure of the array substrate provided in an embodiment of this application;

[0018] Figures 3a to 3h are schematic diagrams of the method for fabricating an array substrate provided in the embodiments of this application;

[0019] Figure 4 is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0020] Figure 5 is a schematic diagram of the structure of the display device provided in an embodiment of this application.

[0021] Explanation of reference numerals in the attached figures:

[0022] 1. Substrate;

[0023] 2. Conductor layer; 21. First conductor section; 22. Second conductor section;

[0024] 3. Semiconductor layer; 31. First semiconductor section; 311. First sub-semiconductor section; 312. Second sub-semiconductor section; 313. Third sub-semiconductor section; 32. Second semiconductor section; 321. Source contact section; 322. Drain contact section; 323. Channel section;

[0025] 4. Gate layer; 41. First gate portion; 42. Second gate portion;

[0026] 5. Source-drain layer; 51. First source; 52. First drain; 53. Second source; 54. Second drain;

[0027] 6. Light-shielding layer; 61. First light-shielding part; 62. Second light-shielding part;

[0028] 7. Buffer layer;

[0029] 8. Gate insulating layer;

[0030] 9. Interlayer dielectric layer;

[0031] 10. Passivation layer;

[0032] 11. Pixel electrode layer;

[0033] 101. Gate driving circuit; 102. Demultiplexer circuit; 103. Pixel driving circuit;

[0034] 100, Array substrate; 200, Opposing substrate; 300, Liquid crystal layer;

[0035] 1000, display panel; 2000, housing; 10000, display device. Embodiments of the present invention

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0037] In the description of this application, it should be understood that the terms "upper," "lower," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0038] Reference numerals and / or reference letters may be repeated in different embodiments of this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0039] The embodiments of this application provide an array substrate, a display panel, and a display device, which can reduce the size of thin-film transistors and improve the stability of thin-film transistors.

[0040] To achieve the above objectives, according to a first aspect of this application, an array substrate is provided, including a first transistor, the first transistor including a first conductor portion, a second conductor portion, a first semiconductor portion, a first gate, a first source, and a first drain, the array substrate further including:

[0041] Substrate;

[0042] A conductor layer is disposed on the substrate, and a first conductor portion and a second conductor portion are disposed on the conductor layer, with the first conductor portion and the second conductor portion being disposed at a distance from each other;

[0043] A semiconductor layer is disposed on the substrate, the semiconductor layer including a first semiconductor portion, the first semiconductor portion being at least connected between the first conductor portion and the second conductor portion;

[0044] A gate layer, disposed on the side of the semiconductor layer away from the substrate, the gate layer including the first gate; and

[0045] A source-drain layer is disposed on the side of the semiconductor layer away from the substrate, and the source-drain layer includes a first source and a first drain;

[0046] Wherein, one end of the first semiconductor portion is recessed within the end of the first conductor portion away from the second conductor portion, the other end of the first semiconductor portion is recessed within the end of the second conductor portion away from the first conductor portion, the first source is connected to the first conductor portion, and the first drain is connected to the second conductor portion.

[0047] Optionally, along the direction from the first conductor portion to the second conductor portion, the distance between the first conductor portion and the second conductor portion is greater than or equal to 0.5 micrometers and less than or equal to 1.5 micrometers.

[0048] Optionally, the first semiconductor portion includes:

[0049] A first sub-semiconductor portion is disposed on the surface of the first conductor portion away from the substrate;

[0050] A second sub-semiconductor portion is disposed on the surface of the second conductor portion away from the substrate; and

[0051] A third sub-semiconductor portion is connected between the first sub-semiconductor portion and the second sub-semiconductor portion, and the third sub-semiconductor portion is disposed between the first conductor portion and the second conductor portion;

[0052] Wherein, the orthographic projection of the first sub-semiconductor portion onto the first conductor portion is located within the first conductor portion, and the orthographic projection of the second sub-semiconductor portion onto the second conductor portion is located within the second conductor portion.

[0053] Optionally, along the direction from the first conductor portion to the second conductor portion, the width of the first sub-semiconductor portion is smaller than the width of the first conductor portion, and the width of the second sub-semiconductor portion is smaller than the width of the second conductor portion.

[0054] Optionally, along the direction from the first conductor portion to the second conductor portion, the difference in width between the first conductor portion and the first sub-semiconductor portion is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers;

[0055] The difference in width between the second conductor portion and the second sub-semiconductor portion is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers.

[0056] Optionally, the orthogonal projection of the first gate onto the substrate overlaps the orthogonal projection of the first semiconductor portion onto the substrate.

[0057] Optionally, along the direction from the first conductor portion to the second conductor portion, the width of the first semiconductor portion is smaller than the width of the first gate.

[0058] Optionally, the array substrate further includes:

[0059] A gate insulating layer is disposed between the semiconductor layer and the gate layer, and the gate insulating layer covers the semiconductor layer and the conductor layer;

[0060] An interlayer dielectric layer is disposed between the gate layer and the source / drain layer;

[0061] The array substrate includes a first via and a second via. The first via penetrates the interlayer dielectric layer and the gate insulating layer, and the first source electrode is connected to the first conductor portion through the first via. The second via penetrates the interlayer dielectric layer and the gate insulating layer, and the first drain electrode is connected to the second conductor portion through the second via.

[0062] Optionally, the array substrate further includes a second transistor, the second transistor including a second semiconductor portion;

[0063] The semiconductor layer includes a second semiconductor section, and the maximum collector current of the first transistor is greater than the maximum collector current of the second transistor.

[0064] Optionally, the second transistor further includes a second gate, a second source, and a second drain;

[0065] Wherein, the gate layer includes the second gate; and / or, the source-drain layer includes the second source and the second drain.

[0066] Optionally, the array substrate includes a display area and a non-display area surrounding the display area, wherein the first transistor is disposed at least in the non-display area and the second transistor is disposed at least in the display area.

[0067] According to a second aspect of this application, a display panel is provided, including an array substrate as described above.

[0068] According to a third aspect of this application, a display device is provided, including a display panel as described above.

[0069] In the array substrate of this application embodiment, by spacing the first conductor portion and the second conductor portion of the first transistor, and connecting the first semiconductor portion of the first transistor at least between the first conductor portion and the second conductor portion, one end of the first semiconductor portion is recessed at the end of the first conductor portion away from the second conductor portion, and the other end of the first semiconductor portion is recessed at the end of the second conductor portion away from the first conductor portion. The first source is connected to the first conductor portion, and the first drain is connected to the second conductor portion. The portion of the first semiconductor portion located between the first conductor portion and the second conductor portion is the channel. This can reduce the channel length of the first transistor, thereby not only reducing the size of the first transistor, but also improving the current carrying capacity of the first transistor, preventing the threshold voltage of the first transistor from drifting negatively, and thus improving the stability of the first transistor.

[0070] Embodiments of this application provide an array substrate including a first transistor. The first transistor includes a first conductor portion, a second conductor portion, a first semiconductor portion, a first gate, a first source, and a first drain. The array substrate further includes a substrate, a conductor layer, a semiconductor layer, a gate layer, and a source-drain layer. The conductor layer is disposed on the substrate and includes a first conductor portion and a second conductor portion, which are spaced apart. The semiconductor layer is disposed on the substrate and includes a first semiconductor portion, which is at least connected between the first conductor portion and the second conductor portion. The gate layer is disposed on the side of the semiconductor layer away from the substrate and includes a first gate. The source-drain layer is disposed on the side of the semiconductor layer away from the substrate and includes a first source and a first drain. One end of the first semiconductor portion is recessed within the end of the first conductor portion away from the second conductor portion, and the other end of the first semiconductor portion is recessed within the end of the second conductor portion away from the first conductor portion. The first source is directly connected to the first conductor portion, and the first drain is directly connected to the second conductor portion.

[0071] In the embodiments of this application, by spacing the first conductor portion and the second conductor portion of the first transistor, and connecting the first semiconductor portion of the first transistor at least between the first conductor portion and the second conductor portion, one end of the first semiconductor portion is recessed at the end of the first conductor portion away from the second conductor portion, and the other end of the first semiconductor portion is recessed at the end of the second conductor portion away from the first conductor portion. The first source is directly connected to the first conductor portion, and the first drain is directly connected to the second conductor portion. The portion of the first semiconductor portion located between the first conductor portion and the second conductor portion is the channel. This can reduce the channel length of the first transistor, thereby not only reducing the size of the first transistor, but also improving the current carrying capacity of the first transistor, preventing the threshold voltage of the first transistor from drifting negatively, and thus improving the stability of the first transistor.

[0072] Please refer to Figures 1 and 2. Figure 1 is a top view of the array substrate provided in the embodiment of this application, and Figure 2 is a schematic diagram of the film layer structure of the array substrate provided in the embodiment of this application. The array substrate 100 includes a first transistor T1. The first transistor T1 includes a first conductor portion 21, a second conductor portion 22, a first semiconductor portion 31, a first gate 41, a first source 51, and a first drain 52.

[0073] Referring to Figure 2, the array substrate 100 includes a substrate 1, a conductor layer 2, a semiconductor layer 3, a gate layer 4, and a source / drain layer 5. The conductor layer 2 is disposed on the substrate 1, and a first conductor portion 21 and a second conductor portion 22 are disposed on the conductor layer 2, spaced apart from each other. The semiconductor layer 3 is disposed on the substrate 1 and includes a first semiconductor portion 31. The gate layer 4 is disposed on the side of the semiconductor layer 3 away from the substrate 1, and includes a first gate 41. In the thickness direction of the gate layer 4, the first gate 41 is aligned with the first semiconductor portion 31, and the thickness direction of the gate layer 4 is the third direction Z shown in Figure 2.

[0074] Referring to Figure 2, the source-drain layer 5 is disposed on the side of the semiconductor layer 3 away from the substrate 1. The source-drain layer 5 includes a first source 51 and a first drain 52. One end of the first semiconductor portion 31 is recessed at the end of the first conductor portion 21 away from the second conductor portion 22, and the other end of the first semiconductor portion 31 is recessed at the end of the second conductor portion 22 away from the first conductor portion 21. The first source 51 overlaps with the first conductor portion 21, and the first drain 52 overlaps with the second conductor portion 22.

[0075] Referring to Figure 2, one end of the first semiconductor portion 31 is recessed within the end of the first conductor portion 21 away from the second conductor portion 22, and the other end of the first semiconductor portion 31 is recessed within the end of the second conductor portion 22 away from the first conductor portion 21. The first source 51 is directly connected to the first conductor portion 21, and the first drain 52 is directly connected to the second conductor portion 22. By spaced apart the first conductor portion and the second conductor portion of the first transistor, and by connecting the first semiconductor portion of the first transistor at least between the first conductor portion and the second conductor portion, with one end of the first semiconductor portion recessed within the end of the first conductor portion away from the second conductor portion, and the other end of the first semiconductor portion recessed within the end of the second conductor portion away from the first conductor portion, the first source directly connected to the first conductor portion, and the first drain directly connected to the second conductor portion, the portion of the first semiconductor portion located between the first conductor portion and the second conductor portion forms the channel. This reduces the channel length of the first transistor, thereby not only reducing the size of the first transistor but also improving its current carrying capacity and preventing negative threshold voltage drift, thus improving the stability of the first transistor.

[0076] It should be noted that "conductor layer 2 is disposed on substrate 1" means that conductor layer 2 is located above substrate 1, and conductor layer 2 and substrate 1 are separated by light-shielding layer 6 and buffer layer 7; "conductor layer 2 is disposed on substrate 1" means that conductor layer 2 is located above substrate 1, and conductor layer 2 is in direct contact with the upper surface of substrate 1.

[0077] In some embodiments, substrate 1 is a rigid substrate, and the material of substrate 1 can be glass. In other embodiments, substrate 1 can also be a flexible substrate, which can be a single-layer flexible substrate formed of organic materials, or a multilayer flexible substrate formed by stacking organic and inorganic materials, wherein the organic material can be polyimide, and the inorganic material can be any one of silicon nitride, silicon oxide, or silicon oxynitride.

[0078] In some embodiments, referring to FIG2, the array substrate 100 further includes a light-shielding layer 6 and a buffer layer 7. The light-shielding layer 6 is disposed on the substrate 1, the buffer layer 7 is disposed on the surface of the light-shielding layer 6 away from the substrate 1, and the conductor layer 2 is disposed on the surface of the buffer layer 7 away from the light-shielding layer 6.

[0079] In some embodiments, the material of the light-shielding layer 6 is selected from at least one of molybdenum, aluminum, titanium, copper, indium tin oxide, and indium zinc oxide. For example, the light-shielding layer 6 can be a single-layer metal structure formed of metal materials such as molybdenum, copper, aluminum, and titanium. The light-shielding layer 6 can also be a stacked structure formed of at least two of molybdenum, aluminum, titanium, copper, indium tin oxide, and indium zinc oxide. For example, the light-shielding layer 6 can be any one of the following stacked structures: copper / aluminum, molybdenum / copper, molybdenum / titanium, molybdenum-titanium alloy / copper / molybdenum-titanium alloy, titanium / aluminum / titanium, titanium / copper / titanium, molybdenum / copper / indium zinc oxide, indium zinc oxide / copper / indium zinc oxide, and molybdenum / copper / indium tin oxide.

[0080] In some embodiments, the material of the buffer layer 7 is selected from at least one of silicon nitride, silicon oxide, and silicon oxynitride. For example, the buffer layer 7 can be a single-layer structure of silicon nitride or silicon oxide, or it can be a stacked structure of silicon nitride and silicon oxide.

[0081] In the embodiments of this application, the first conductor portion 21 and the second conductor portion 22 are part of the conductor layer 2. The first conductor portion 21 and the second conductor portion 22 are made of the same material as the conductor layer 2. The first conductor portion 21 and the second conductor portion 22 can be fabricated by the process of the conductor layer 2.

[0082] In some embodiments, the material of conductor layer 2 is selected from at least one of indium tin oxide, indium zinc oxide, tin zinc oxide, molybdenum, titanium, tantalum, and niobium. For example, the material of conductor layer 2 is a metal or alloy. Conductor layer 2 can be a single-layer metal structure formed by at least one of molybdenum, titanium, tantalum, and niobium, or a multilayer structure formed by at least two of molybdenum, titanium, tantalum, and niobium. The material of conductor layer 2 can also be an oxide conductive material, specifically any one of indium tin oxide, indium zinc oxide, and tin zinc oxide. Conductor layer 2 can also be a multilayer structure formed by a metal material and an oxide conductive material.

[0083] In some embodiments, along the channel length direction of the first semiconductor portion 31, the distance d1 between the first conductor portion 21 and the second conductor portion 22 is greater than or equal to 0.5 micrometers and less than or equal to 1.5 micrometers. For example, the distance d1 between the first conductor portion 21 and the second conductor portion 22 can be 0.5 micrometers, 0.7 micrometers, 1 micrometer, 1.2 micrometers, or 1.5 micrometers, etc.

[0084] Referring to Figure 2, the first semiconductor portion 31 is connected between the first conductor portion 21 and the second conductor portion 22, and fills the gap between the first conductor portion 21 and the second conductor portion 22. The portion of the first semiconductor portion 31 located between the first conductor portion 21 and the second conductor portion 22 can be considered as the channel of the first semiconductor portion 31. Along the channel length direction of the first semiconductor portion 31, the distance d1 between the first conductor portion 21 and the second conductor portion 22 is the channel length of the first semiconductor portion 31. In this way, the first transistor T1 can have a submicron-level ultra-short channel, thereby not only reducing the size of the first transistor T1, but also improving the current carrying capacity of the first transistor, preventing the threshold voltage of the first transistor from drifting negatively, and thus improving the stability of the first transistor.

[0085] It should be noted that the channel length direction of the first semiconductor section 31 is the direction from the first conductor section 21 to the second conductor section 22, and can also be regarded as the first direction X shown in FIG2.

[0086] As shown in Figures 1 and 2, the bearing surface of the array substrate 100 is a plane defined by the first direction X and the second direction Y. The first direction X is perpendicular to the second direction Y, and the third direction Z is perpendicular to the plane defined by the first direction X and the second direction Y. The third direction Z is the film thickness direction of the array substrate.

[0087] In the embodiments of this application, the first semiconductor part 31 is part of the semiconductor layer 3. The first semiconductor part 31 is made of the same material as the semiconductor layer 3. The first semiconductor part 31 can be fabricated by the process of the semiconductor layer 3.

[0088] In some embodiments, the material of semiconductor layer 3 is selected from silicon semiconductor materials and oxide semiconductor materials. For example, the material of semiconductor layer 3 is a silicon semiconductor material, which can be polycrystalline silicon, obtained by amorphous silicon laser annealing crystallization or other crystallization methods. The material of semiconductor layer 3 can also be any one of indium gallium zinc oxide, indium gallium titanium oxide, indium gallium oxide, indium zinc oxide, aluminum indium zinc oxide, and aluminum tin co-doped zinc oxide.

[0089] In some embodiments, referring to FIG2, the first semiconductor portion 31 includes a first sub-semiconductor portion 311, a second sub-semiconductor portion 312, and a third sub-semiconductor portion 313. The first sub-semiconductor portion 311 is disposed on the surface of the first conductor portion 21 away from the substrate 1, the second sub-semiconductor portion 312 is disposed on the surface of the second conductor portion 22 away from the substrate 1, and the third sub-semiconductor portion 313 is connected between the first sub-semiconductor portion 311 and the second sub-semiconductor portion 312. The third sub-semiconductor portion 313 is disposed between the first conductor portion 21 and the second conductor portion 22. The third sub-semiconductor portion 313 can be regarded as the channel of the first semiconductor portion 31. The orthogonal projection of the first gate 41 on the substrate 1 covers the orthogonal projection of the third sub-semiconductor portion 313 on the substrate 1.

[0090] It should be noted that the patterning processes of the first gate 41 and the first semiconductor portion 31 both have certain deviations. If the first semiconductor portion 31 is only connected between the first conductor portion 21 and the second conductor portion 22, when the position of the first semiconductor portion 31 shifts, the first semiconductor portion 31 may not be able to connect between the first conductor portion 21 and the second conductor portion 22, making it impossible for the first semiconductor portion 31 to function as a channel. This could lead to display defects in the array substrate 100, ultimately reducing the production yield of the array substrate. In this embodiment, by forming the first sub-semiconductor portion 311 and the second sub-semiconductor portion 312 of the first semiconductor portion 31 on the first conductor portion 21 and the second conductor portion 22, even if the position of the first semiconductor portion 31 shifts, it can be ensured that the first semiconductor portion 31 can fill the gap between the first conductor portion 21 and the second conductor portion 22, ensuring that the first semiconductor portion 31 can function as a channel, thereby improving the production yield of the array substrate.

[0091] In some embodiments, referring to FIG2, the orthographic projection of the first sub-semiconductor portion 311 onto the first conductor portion 21 is located within the first conductor portion 21, and the orthographic projection of the second sub-semiconductor portion 312 onto the second conductor portion 22 is located within the second conductor portion 22. This prevents the first sub-semiconductor portion 311 from blocking the first conductor portion 21 and the second sub-semiconductor portion 312 from blocking the second conductor portion 22, ensuring that the first source 51 is directly connected to the first conductor portion 21 and that the first drain 52 is directly connected to the second conductor portion 22. By making the first source 51 directly connected to the first conductor portion 21 and the first drain 52 directly connected to the second conductor portion 22, not only can the impedance between the first source 51 and the first conductor portion 21 and the impedance between the first drain 52 and the second conductor portion 22 be reduced, increasing the maximum collector current of the first transistor T1, but also the diffusion of excessively high carrier concentration at the third sub-semiconductor portion 313 to both sides of the channel can be reduced, and the problem of plasma contamination caused by the opening at the first semiconductor portion 31 can be avoided.

[0092] In some embodiments, referring to FIG2, in the direction from the first conductor portion 21 to the second conductor portion 22, the width of the first sub-semiconductor portion 311 is smaller than the width of the first conductor portion 21. The end of the first sub-semiconductor portion 311 away from the second sub-semiconductor portion 312 is recessed within the end of the first conductor portion 21 away from the second conductor portion 22, and the first source electrode 51 is directly connected to the end of the first conductor portion 21 away from the second conductor portion 22. The width of the second sub-semiconductor portion 312 is smaller than the width of the second conductor portion 22. The end of the second sub-semiconductor portion 312 away from the first sub-semiconductor portion 311 is recessed within the end of the second conductor portion 22 away from the first conductor portion 21, and the first drain electrode 52 is directly connected to the end of the second conductor portion 22 away from the first conductor portion 21. This prevents the first sub-semiconductor portion 311 from blocking the first conductor portion 21 and prevents the second sub-semiconductor portion 312 from blocking the second conductor portion 22, ensuring that the first source electrode 51 is directly connected to the first conductor portion 21 and that the first drain electrode 52 is directly connected to the second conductor portion 22. By directly connecting the first source 51 to the first conductor 21 and the first drain 52 to the second conductor 22, not only can the impedance between the first source 51 and the first conductor 21 and the impedance between the first drain 52 and the second conductor 22 be reduced, thus increasing the maximum collector current of the first transistor T1, but also the diffusion of excessively high carrier concentration at the third sub-semiconductor 313 to both sides of the channel can be reduced, and the problem of plasma contamination caused by the opening at the first semiconductor 31 can be avoided.

[0093] In some embodiments, along the direction from the first conductor portion 21 to the second conductor portion 22, the width difference between the first conductor portion 21 and the first sub-semiconductor portion is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers. The width difference between the second conductor portion 22 and the second sub-semiconductor portion 312 is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers.

[0094] It should be noted that, taking the first source 51 and the first conductor portion 21 as an example, the first source 51 is connected to the first conductor portion 21 through the first via V1. If the width of the portion of the first conductor portion 21 extending beyond the first sub-semiconductor portion 311 is too small, interference may occur between the first via V1 and the first gate 41 or the first sub-semiconductor portion 311. During the formation of the first via V1, etching may occur on the first gate 41 or the first sub-semiconductor portion 311, and the subsequently formed first source 51 may directly overlap with the first gate 41 or the first sub-semiconductor portion 311, affecting the electrical performance of the first transistor T1. By ensuring that the width difference between the first conductor portion 21 and the first sub-semiconductor portion is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers, interference between the first via V1 and the first gate 41 or the first sub-semiconductor portion 311 can be avoided. This ensures that while reducing the size of the first transistor T1, the current carrying capacity of the first transistor T1 is improved, preventing negative threshold voltage drift of the first transistor, and thus improving the stability of the first transistor.

[0095] In some embodiments, referring to FIG2, the orthogonal projection of the first gate 41 on the substrate 1 covers the orthogonal projection of the first semiconductor portion 31 on the substrate 1. This ensures that when the position of the first gate 41 or the first semiconductor portion 31 is offset, the first semiconductor portion 31 can also be within the control range of the first gate 41.

[0096] In some embodiments, referring to FIG2, the width of the first sub-semiconductor portion 311 is smaller than the width of the first gate 41 in the direction from the first conductor portion 21 to the second conductor portion 22. This ensures that when the position of the first gate 41 or the first semiconductor portion 31 is offset, the first semiconductor portion 31 can also be within the control range of the first gate 41.

[0097] In some embodiments, referring to FIG2, the array substrate 100 further includes a gate insulating layer 8 and an interlayer dielectric layer 9. The gate insulating layer 8 is disposed between the semiconductor layer 3 and the gate layer 4, and covers the semiconductor layer 3 and the conductor layer 2. The interlayer dielectric layer 9 is disposed between the gate layer 4 and the source / drain layers 5. The array substrate 100 includes a first via V1 and a second via V2. The first via V1 penetrates the interlayer dielectric layer 9 and the gate insulating layer 8. The first source 51 is connected to the first conductor portion 21 through the first via V1. The second via V2 penetrates the interlayer dielectric layer 9 and the gate insulating layer 8. The first drain 52 is connected to the second conductor portion 22 through the second via V2.

[0098] In some embodiments, the material of the gate insulating layer 8 is selected from at least one of silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. For example, the gate insulating layer 8 can be a single-layer structure formed of silicon oxide, or it can be a stacked structure formed by sequentially stacking aluminum oxide, silicon nitride, and silicon oxide, or it can be a stacked structure formed by sequentially stacking silicon oxide, silicon nitride, and silicon oxide.

[0099] In some embodiments, referring to FIG2, the array substrate 100 further includes a second transistor T2, the second transistor T2 including a second semiconductor portion 32 disposed on the semiconductor layer 3.

[0100] It should be noted that the second semiconductor part 32 being disposed on the semiconductor layer 3 means that the second semiconductor part 32 is part of the semiconductor layer 3. The second semiconductor part 32 and the semiconductor layer 3 are made of the same material and are manufactured by the same process. That is, the semiconductor layer 3 includes the second semiconductor part 32.

[0101] In this embodiment, the first semiconductor section 31 and the second semiconductor section 32 are disposed on the same layer, and the first semiconductor section 31 and the second semiconductor section 32 are made of the same material. The first semiconductor section 31 and the second semiconductor section 32 are fabricated simultaneously through the process of semiconductor layer 3. In this way, while reducing the size of the first transistor T1 and improving the current conduction capability and stability of the first transistor T1, the number of process steps and photomasks is reduced, thereby reducing production costs.

[0102] In some embodiments, the maximum collector current of the first transistor T1 is greater than the maximum collector current of the second transistor T2.

[0103] Referring to Figure 2, the second semiconductor section 32 includes a source contact 321, a drain contact 322, and a channel section 323, with the channel section 323 connecting the source contact 321 and the drain contact 322. Along the direction from the first conductor section 21 to the second conductor section 22, the width of the channel section 323 is greater than the width of the third sub-semiconductor section 313. The second transistor T2 is a conventional transistor, not a submicron-level ultra-short channel transistor. The maximum collector current is the maximum current that a transistor can carry, used to measure the high current carrying capacity of a transistor. The high current carrying capacity of the first transistor T1 is better than that of the second transistor T2.

[0104] In some embodiments, the second transistor T2 further includes a second gate 42, a second source 53, and a second drain 54, wherein the second gate 42 is disposed on the gate layer 4; and / or, the second source 53 and the second drain 54 are disposed on the source-drain layer 5.

[0105] In some embodiments, referring to FIG2, the first gate 41 and the second gate 42 are disposed on the gate layer 4. The first gate 41 and the second gate 42 are disposed on the same layer. The first gate 41 and the second gate 42 are made of the same material. The first gate 41 and the second gate 42 can be fabricated simultaneously by the process of the gate layer 4. In this way, the size of the first transistor T1 can be reduced, and the current conduction capability and stability of the first transistor T1 can be improved. At the same time, the film structure of the array substrate can be simplified, the process and the number of photomasks can be reduced, thereby reducing the production cost.

[0106] In some embodiments, the material of the gate layer 4 is selected from at least one of molybdenum, aluminum, titanium, copper, indium tin oxide, and indium zinc oxide. For example, the gate layer 4 can be a single-layer metal structure formed of metal materials such as molybdenum, copper, aluminum, and titanium. The gate layer 4 can also be a stacked structure formed of at least two of molybdenum, aluminum, titanium, copper, indium tin oxide, and indium zinc oxide. For example, the gate layer 4 can be any one of the following stacked structures: copper / aluminum, molybdenum / copper, molybdenum / titanium, molybdenum-titanium alloy / copper / molybdenum-titanium alloy, titanium / aluminum / titanium, titanium / copper / titanium, molybdenum / copper / indium zinc oxide, indium zinc oxide / copper / indium zinc oxide, and molybdenum / copper / indium tin oxide.

[0107] In some other embodiments, the first gate 41 and the second gate 42 may also be disposed in different layers. For example, the gate layer 4 includes the first gate, and the array substrate 100 also includes the second gate layer. The second gate layer may be disposed on the side of the gate layer 4 close to or far from the substrate 1. The second gate layer includes the second gate 42. In this way, the technical effect of improving the current conduction capability and stability of the first transistor T1 can also be achieved.

[0108] In some embodiments, referring to FIG2, a first source 51, a first drain 52, a second source 53, and a second drain 54 are disposed on a source-drain layer 5. The first source 51, the first drain 52, the second source 53, and the second drain 54 are disposed on the same layer. The first source 51, the first drain 52, the second source 53, and the second drain 54 are made of the same material. The first source 51, the first drain 52, the second source 53, and the second drain 54 can be fabricated simultaneously through the process of the source-drain layer 5. In this way, the size of the first transistor T1 can be reduced, and the current conduction capability and stability of the first transistor T1 can be improved, while simplifying the film structure of the array substrate, reducing the process and the number of photomasks, thereby reducing production costs.

[0109] In some embodiments, the material of the source / drain layer 5 is selected from at least one of molybdenum, aluminum, titanium, copper, indium tin oxide, and indium zinc oxide. For example, the source / drain layer 5 can be a single-layer metal structure formed of metal materials such as molybdenum, copper, aluminum, and titanium. The source / drain layer 5 can also be a stacked structure formed of at least two of molybdenum, aluminum, titanium, copper, indium tin oxide, and indium zinc oxide. For example, the source / drain layer 5 can be any one of the following stacked structures: copper / aluminum, molybdenum / copper, molybdenum / titanium, molybdenum-titanium alloy / copper / molybdenum-titanium alloy, titanium / aluminum / titanium, titanium / copper / titanium, molybdenum / copper / zinc oxide, indium zinc oxide / copper / zinc oxide, and molybdenum / copper / indium tin oxide.

[0110] In some other embodiments, the first source 51 and the first drain 52 are disposed on the source-drain layer 5, and the array substrate 100 further includes a second source-drain layer, which includes a second source 53 and a second drain 54. The second source-drain layer can be disposed on the side of the source-drain layer 5 that is close to or far from the substrate 1, which can also achieve the technical effect of improving the current conduction capability and stability of the first transistor T1.

[0111] In some embodiments, referring to FIG2, the light-shielding layer 6 includes a first light-shielding portion 61 and a second light-shielding portion 62, which are spaced apart. A first source electrode 51 is connected to the first light-shielding portion 61, and a second source electrode 53 is connected to the second light-shielding portion 62.

[0112] In some embodiments, referring to FIG1, the array substrate 100 includes a display area AA and a non-display area NA disposed around the display area AA. A first transistor T1 is disposed at least in the non-display area NA, and a second transistor T2 is disposed at least in the display area AA.

[0113] In this embodiment, the non-display area NA is equipped with a driving circuit that requires high current carrying capacity. In addition to the driving circuit, the non-display area may also integrate system functional components. These circuits and components place high demands on transistor size and high current carrying capacity. By placing the first transistor T1 in the non-display area NA, this embodiment not only improves the performance of the driving circuit and system functional components in the non-display area NA but also reduces their occupied area. This reduces the width of the non-display area NA, thereby increasing the screen-to-body ratio of the display panel suitable for the array substrate. In this embodiment, by placing the second transistor T2 in the display area AA, which is equipped with a pixel driving circuit including the second transistor T2, the high stability of the second transistor T2 ensures the stability of the display effect in the display area AA.

[0114] In some embodiments, please refer to FIG1 and FIG2, the array substrate 100 includes a gate driving circuit 101, the gate driving circuit 101 is disposed in the non-display area NA, and the gate driving circuit 101 includes a first transistor T1.

[0115] In some embodiments, the gate driving circuit 101 may include a plurality of transistors, at least one of which is a first transistor T1, or all of the transistors may be first transistors T1. This reduces the area occupied by the gate driving circuit 101, thereby improving the performance of the gate driving circuit while increasing the screen-to-body ratio of the display panel to which the array substrate is applied. The circuit structure of the gate driving circuit 101 can be replaced with the circuit structure of a known gate driving circuit in an array substrate to achieve the same or similar function.

[0116] In some embodiments, referring to Figures 1 and 2, the array substrate 100 includes a demultiplexer circuit 102 disposed in the non-display area NA, and the demultiplexer circuit 102 includes a first transistor T1.

[0117] In some embodiments, the demultiplexer circuit 102 may include a plurality of transistors, at least one of which is a first transistor T1, or all of the transistors may be first transistors T1. This reduces the area occupied by the demultiplexer circuit 102, thereby improving the performance of the demultiplexer circuit 102 while increasing the screen-to-body ratio of the display panel to which the array substrate is applied. The circuit structure of the demultiplexer circuit 102 can be replaced with the circuit structure of a known demultiplexer circuit 102 in an array substrate to achieve the same or similar function.

[0118] In some embodiments, please refer to FIG1 and FIG2, the array substrate 100 includes a plurality of pixel driving circuits 103, the pixel driving circuits 103 are disposed in the display area AA, and the pixel driving circuit includes a second transistor T2. The second transistor T2 has high stability and can ensure the stability of the display effect of the display area AA.

[0119] In some embodiments, both the display area AA and the non-display area NA are provided with a first transistor T1. By replacing at least some of the transistors in the display area AA with the first transistor T1, the area occupied by the circuit in the display area AA can be reduced, so as to free up more space to place sub-pixels. This can increase the pixel density per unit area in the display area AA, thereby improving the resolution of the display panel to which the array substrate is applicable.

[0120] In some embodiments, referring to Figures 1 and 2, the array substrate 100 includes a plurality of pixel driving circuits 103. The pixel driving circuits 103 are disposed in the display area AA. The pixel driving circuit includes a first transistor T1 and a second transistor T2. By replacing some of the transistors in the pixel driving circuit with the first transistor T1, the area occupied by the circuit in the display area AA can be reduced, so as to free up more space to place sub-pixels. This can increase the pixel density per unit area in the display area AA, thereby improving the resolution of the display panel to which the array substrate is applicable.

[0121] In some embodiments, the driving transistor in the pixel driving circuit can be a first transistor T1, and the other transistors in the pixel driving circuit can be a second transistor T2. This can improve the driving capability of the pixel driving circuit while ensuring its stability, thereby improving the display effect of the array substrate.

[0122] In some embodiments, referring to FIG2, the array substrate 100 further includes a passivation layer 10 and a pixel electrode layer 11. The passivation layer 10 is disposed on the source / drain layer 5 and the interlayer dielectric layer 9, and the pixel electrode layer 11 is disposed on the passivation layer 10.

[0123] In some embodiments, the material of the passivation layer 10 is selected from at least one of silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. For example, the passivation layer 10 can be a single-layer structure formed of silicon oxide, or it can be a stacked structure formed by sequentially stacking aluminum oxide, silicon nitride, and silicon oxide, or it can be a stacked structure formed by sequentially stacking silicon oxide, silicon nitride, and silicon oxide.

[0124] In some embodiments, the material of the pixel electrode layer 11 is selected from at least one of a metal and a transparent metal oxide. The metal material can be at least one of copper, molybdenum, silver, and titanium, and the transparent metal oxide can be at least one of indium tin oxide and indium zinc oxide. For example, the pixel electrode layer 11 can be a single-layer transparent conductive structure of indium tin oxide or indium zinc oxide. The pixel electrode layer 11 can also be any of the following stacked structures: indium tin oxide / silver / indium tin oxide, indium zinc oxide / silver / indium zinc oxide, molybdenum / copper, molybdenum-titanium alloy / copper / molybdenum-titanium alloy, etc.

[0125] Based on the array substrate provided in the above embodiments of this application, embodiments of this application also provide a method for manufacturing an array substrate, used to manufacture an array substrate as provided in any of the above embodiments. Referring to Figures 3a to 3h, which are schematic diagrams of the method for manufacturing an array substrate provided in the embodiments of this application, the method for manufacturing an array substrate includes:

[0126] Step S1: Form a light-shielding material on substrate 1, and pattern the light-shielding material to form light-shielding layer 6.

[0127] As shown in Figure 3a, the light-shielding layer 6 includes a first light-shielding part 61 and a second light-shielding part 62, which are spaced apart.

[0128] Step S2: A buffer layer 7 is formed on the substrate 1, and the buffer layer 7 covers the light-shielding layer 6; a conductor material is formed on the light-shielding layer 6, and the conductor material is patterned to form a conductor layer 2.

[0129] As shown in Figure 3b, the conductor layer 2 includes a first conductor portion 21 and a second conductor portion 22, which are spaced apart.

[0130] Step S3: A semiconductor material is formed on the buffer layer 7 and the conductor layer 2, and the semiconductor material is patterned to form the semiconductor layer 3.

[0131] As shown in Figure 3c, the semiconductor layer 3 includes a first semiconductor portion 31 and a second semiconductor portion 32, which are spaced apart. The first semiconductor portion 31 is disposed on the first conductor portion 21 and the second conductor portion 22, and fills the gap between the first conductor portion 21 and the second conductor portion 22. The second semiconductor portion 32 is disposed on the buffer layer 7.

[0132] Step S4: A gate insulating layer 8 is formed on the semiconductor layer 3, a gate material is formed on the gate insulating layer 8, and the gate material is patterned to form the gate layer 4.

[0133] As shown in Figure 3d, the gate layer 4 includes a first gate 41 and a second gate 42. In the film thickness direction of the gate layer 4, the first gate 41 is aligned with the first semiconductor portion 31, and the second gate 42 is aligned with the second semiconductor portion 32.

[0134] Step S5: Form an interlayer dielectric layer 9 on the gate layer 4, and pattern the interlayer dielectric layer 9 to form multiple vias.

[0135] As shown in Figure 3e, the multiple vias include a first via V1 and a second via V2. The first via V1 exposes a first conductor portion 21, and the second via V2 exposes a second conductor portion 22.

[0136] Step S6: Deposit source and drain materials on the interlayer dielectric layer 9, and pattern the source and drain materials to form source and drain layer 5.

[0137] As shown in Figure 3f, the source-drain layer 5 includes a first source 51, a first drain 52, a second source 53, and a second drain 54. The first source 51 is directly connected to the first conductor portion 21 through a first via V1, the first drain 52 is directly connected to the second conductor portion 22 through a second via V2, the second source 53 is directly connected to the source contact portion 321, and the second drain 54 is directly connected to the drain contact portion 322.

[0138] Step S7: As shown in Figure 3g, a passivation material is formed on the source-drain layer 5, and the passivation material is patterned to form a passivation layer 10.

[0139] Step S8: As shown in Figure 3h, a pixel electrode material is formed on the passivation layer 10, and the pixel electrode material is patterned to form a pixel electrode layer 11.

[0140] In some embodiments, please refer to FIG4, which is a schematic diagram of the structure of a display panel provided in the embodiments of this application. The display panel provided in the embodiments of this application is a liquid crystal display panel. The display panel 1000 includes an array substrate 100, a counter substrate 200 and a liquid crystal layer 300. The array substrate 100 and the counter substrate 200 are disposed opposite to each other. The liquid crystal layer 300 is disposed between the array substrate 100 and the counter substrate 200. The counter substrate 200 can be a color filter substrate. The array substrate 100 can be the array substrate provided in any of the above embodiments.

[0141] In other embodiments, the type of display panel 1000 is not limited to the liquid crystal display panel in the above embodiments. The display panel 1000 may also be any one of organic light-emitting diode display panel, mini light-emitting diode display panel and micro light-emitting diode display panel.

[0142] The display panel 1000 provided in the embodiments of this application can achieve the same technical effect as the array substrate provided in any of the above embodiments, and will not be described in detail here.

[0143] Based on the array substrate provided in the above embodiments of this application, embodiments of this application also provide a display device. Please refer to FIG5, which is a schematic structural diagram of the display device provided in an embodiment of this application. The display device 10000 includes a display panel 1000 and a housing 2000, with the display panel 1000 disposed on the housing 2000. The display panel 1000 can be any of the display panels provided in the above embodiments. The display device provided in the embodiments of this application can achieve the same technical effects as the display panels provided in any of the above embodiments, and will not be elaborated upon here.

[0144] The beneficial effects of the embodiments of this application are as follows: This application provides an array substrate, a display panel, and a display device. The array substrate includes a first transistor. The first transistor includes a first conductor portion, a second conductor portion, a first semiconductor portion, a first gate, a first source, and a first drain. By spaced apart the first conductor portion and the second conductor portion, and connecting the first semiconductor portion at least between the first conductor portion and the second conductor portion, one end of the first semiconductor portion is recessed at the end of the first conductor portion away from the second conductor portion, and the other end of the first semiconductor portion is recessed at the end of the second conductor portion away from the first conductor portion. The first source is directly connected to the first conductor portion, and the first drain is directly connected to the second conductor portion. The portion of the first semiconductor portion located between the first conductor portion and the second conductor portion is the channel. This not only reduces the size of the first transistor but also improves its stability.

[0145] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0146] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0147] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0148] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate comprising a first transistor, the first transistor comprising a first conductor portion, a second conductor portion, a first semiconductor portion, a first gate, a first source, and a first drain, the array substrate further comprising: Substrate; A conductor layer is disposed on the substrate, the conductor layer including a first conductor portion and a second conductor portion, the first conductor portion and the second conductor portion being disposed at a distance from each other; A semiconductor layer is disposed on the substrate, the semiconductor layer including a first semiconductor portion, the first semiconductor portion being at least connected between the first conductor portion and the second conductor portion; A gate layer is disposed on the side of the semiconductor layer away from the substrate, and the gate layer includes the first gate; as well as A source-drain layer is disposed on the side of the semiconductor layer away from the substrate, and the source-drain layer includes a first source and a first drain; Wherein, one end of the first semiconductor portion is recessed within the end of the first conductor portion away from the second conductor portion, the other end of the first semiconductor portion is recessed within the end of the second conductor portion away from the first conductor portion, the first source is connected to the first conductor portion, and the first drain is connected to the second conductor portion.

2. The array substrate as claimed in claim 1, wherein, Along the direction from the first conductor portion to the second conductor portion, the distance between the first conductor portion and the second conductor portion is greater than or equal to 0.5 micrometers and less than or equal to 1.5 micrometers.

3. The array substrate as claimed in claim 1, wherein, The first semiconductor unit includes: A first sub-semiconductor portion is disposed on the surface of the first conductor portion away from the substrate; A second sub-semiconductor portion is disposed on the surface of the second conductor portion away from the substrate; and A third sub-semiconductor portion is connected between the first sub-semiconductor portion and the second sub-semiconductor portion, and the third sub-semiconductor portion is disposed between the first conductor portion and the second conductor portion; Wherein, the orthographic projection of the first sub-semiconductor portion onto the first conductor portion is located within the first conductor portion, and the orthographic projection of the second sub-semiconductor portion onto the second conductor portion is located within the second conductor portion.

4. The array substrate as claimed in claim 3, wherein, Along the direction from the first conductor portion to the second conductor portion, the width of the first sub-semiconductor portion is smaller than the width of the first conductor portion, and the width of the second sub-semiconductor portion is smaller than the width of the second conductor portion.

5. The array substrate as claimed in claim 4, wherein, Along the direction from the first conductor portion to the second conductor portion, the difference in width between the first conductor portion and the first sub-semiconductor portion is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers; The difference in width between the second conductor portion and the second sub-semiconductor portion is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers.

6. The array substrate as claimed in claim 1, wherein, The orthogonal projection of the first gate onto the substrate overlaps the orthogonal projection of the first semiconductor onto the substrate.

7. The array substrate as claimed in claim 1, wherein, Along the direction from the first conductor portion to the second conductor portion, the width of the first semiconductor portion is smaller than the width of the first gate.

8. The array substrate as claimed in claim 1, wherein, The array substrate further includes: A gate insulating layer is disposed between the semiconductor layer and the gate layer, and the gate insulating layer covers the semiconductor layer and the conductor layer; An interlayer dielectric layer is disposed between the gate layer and the source / drain layer; The array substrate includes a first via and a second via. The first via penetrates the interlayer dielectric layer and the gate insulating layer, and the first source electrode is connected to the first conductor portion through the first via. The second via penetrates the interlayer dielectric layer and the gate insulating layer, and the first drain electrode is connected to the second conductor portion through the second via.

9. The array substrate according to any one of claims 1 to 8, wherein, The array substrate further includes a second transistor, the second transistor including a second semiconductor portion; The semiconductor layer includes a second semiconductor section, and the maximum collector current of the first transistor is greater than the maximum collector current of the second transistor.

10. The array substrate as claimed in claim 9, wherein, The second transistor further includes a second gate, a second source, and a second drain; Wherein, the gate layer includes the second gate; and / or, the source-drain layer includes the second source and the second drain.

11. The array substrate as claimed in claim 9, wherein, The array substrate includes a display area and a non-display area surrounding the display area, wherein the first transistor is disposed at least in the non-display area and the second transistor is disposed at least in the display area.

12. The array substrate as claimed in claim 1, wherein, The material of the semiconductor layer is selected from silicon semiconductor materials and oxide semiconductor materials.

13. A display panel, comprising an array substrate, the array substrate including a first transistor, the first transistor including a first conductor portion, a second conductor portion, a first semiconductor portion, a first gate, a first source, and a first drain, the array substrate further comprising: Substrate; A conductor layer is disposed on the substrate, the conductor layer including a first conductor portion and a second conductor portion, the first conductor portion and the second conductor portion being disposed at a distance from each other; A semiconductor layer is disposed on the substrate, the semiconductor layer including a first semiconductor portion, the first semiconductor portion being at least connected between the first conductor portion and the second conductor portion; A gate layer is disposed on the side of the semiconductor layer away from the substrate, and the gate layer includes the first gate; as well as A source-drain layer is disposed on the side of the semiconductor layer away from the substrate, and the source-drain layer includes a first source and a first drain; Wherein, one end of the first semiconductor portion is recessed within the end of the first conductor portion away from the second conductor portion, the other end of the first semiconductor portion is recessed within the end of the second conductor portion away from the first conductor portion, the first source is connected to the first conductor portion, and the first drain is connected to the second conductor portion.

14. The display panel as claimed in claim 13, wherein, Along the direction from the first conductor portion to the second conductor portion, the distance between the first conductor portion and the second conductor portion is greater than or equal to 0.5 micrometers and less than or equal to 1.5 micrometers.

15. The display panel as claimed in claim 13, wherein, The first semiconductor unit includes: A first sub-semiconductor portion is disposed on the surface of the first conductor portion away from the substrate; A second sub-semiconductor portion is disposed on the surface of the second conductor portion away from the substrate; and A third sub-semiconductor portion is connected between the first sub-semiconductor portion and the second sub-semiconductor portion, and the third sub-semiconductor portion is disposed between the first conductor portion and the second conductor portion; Wherein, the orthographic projection of the first sub-semiconductor portion onto the first conductor portion is located within the first conductor portion, and the orthographic projection of the second sub-semiconductor portion onto the second conductor portion is located within the second conductor portion.

16. The display panel as claimed in claim 15, wherein, Along the direction from the first conductor portion to the second conductor portion, the width of the first sub-semiconductor portion is smaller than the width of the first conductor portion, and the width of the second sub-semiconductor portion is smaller than the width of the second conductor portion.

17. The display panel as claimed in claim 16, wherein, Along the direction from the first conductor portion to the second conductor portion, the difference in width between the first conductor portion and the first sub-semiconductor portion is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers; The difference in width between the second conductor portion and the second sub-semiconductor portion is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers.

18. The display panel as claimed in claim 13, wherein, The orthogonal projection of the first gate onto the substrate overlaps the orthogonal projection of the first semiconductor onto the substrate.

19. The display panel as claimed in claim 13, wherein, Along the direction from the first conductor portion to the second conductor portion, the width of the first semiconductor portion is smaller than the width of the first gate.

20. A display device comprising a display panel as described in any one of claims 13 to 19.

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