Display panel and manufacturing method therefor, and display device

Abstract

The present disclosure relates to the technical field of display, and relates to a display panel and a manufacturing method therefor, and a display device. The display panel comprises a substrate, a first pixel defining layer, a second pixel defining layer, a light-emitting layer, and a cathode layer. First openings of the first pixel defining layer expose part of an anode. The orthographic projection of each second opening comprised in the second pixel defining layer on the substrate at least partially overlaps the orthographic projection of the corresponding first opening on the substrate. The display panel comprises at least one partition opening between two adjacent sub-pixels; the partition opening comprises a first sub-partition running through the second pixel defining layer and a second sub-partition running through at least part of the first pixel defining layer; and at the junction of the first sub-partition and the second sub-partition, the second sub-partition protrudes toward the sub-pixels relative to the first sub-partition. The manufacturing method is used for manufacturing the display panel. The display device comprises the display panel. The present disclosure can avoid color crosstalk between adjacent sub-pixels, mitigate electrical light leakage, and improve the display effect.

Description

Display panel and its manufacturing method, display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411997382.X, filed on December 31, 2024, entitled “Display Panel and Method of Manufacturing Thereof, Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0004] OLED (Organic Light-Emitting Diode) displays are widely used in various fields due to their lightweight, wide viewing angle, fast response, low-temperature resistance, high luminous efficiency, and the ability to fabricate flexible displays. OLED displays use a vapor deposition process to form organic light-emitting materials, and pixel definition layers define the light-emitting areas. When current flows through them, these organic light-emitting materials emit light in the light-emitting areas, thus achieving the display.

[0005] In existing technologies, when a sub-pixel (target sub-pixel) is lit, due to the lateral leakage current problem in the display panel, adjacent sub-pixels are easily affected by this sub-pixel and may also be illuminated, resulting in light leakage and color crosstalk. This electrical light leakage phenomenon is particularly noticeable in full-color OLED display panels, especially in low grayscale displays, where color shift is particularly severe, thereby reducing the display quality of the OLED display panel.

[0006] Therefore, providing a display panel and its manufacturing method and display device that can avoid color crosstalk between adjacent sub-pixels, improve electrical light leakage, and at the same time not affect the normal light emission of pixels and ensure low grayscale display effect is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] To address the aforementioned technical problems, this disclosure provides a display panel and its manufacturing method, as well as a display device, to solve the problem that display devices in the prior art are prone to color distortion due to lateral leakage current, which affects display quality.

[0008] This disclosure provides a display panel including a plurality of sub-pixels, wherein each sub-pixel includes an anode;

[0009] The display panel also includes:

[0010] The substrate has the anode located on one side.

[0011] The first pixel defining layer is located on the side of the anode away from the substrate. The first pixel defining layer includes a plurality of first openings, and the first openings expose a portion of the anode.

[0012] The second pixel definition layer is located on the side of the first pixel definition layer away from the substrate. The second pixel definition layer includes a plurality of second openings. The orthographic projection of the second openings onto the substrate at least partially overlaps with the orthographic projection of the first openings onto the substrate.

[0013] A light-emitting layer, at least a portion of which is located within the first opening;

[0014] The cathode layer is located on the side of the light-emitting layer away from the substrate.

[0015] Between two adjacent sub-pixels, the display panel includes at least one partition opening. Along a direction perpendicular to the plane of the substrate, the partition opening includes a first sub-partition that penetrates the second pixel definition layer and a second sub-partition that penetrates at least a portion of the first pixel definition layer. The first sub-partition and the second sub-partition are connected.

[0016] At the junction of the first and second sub-blocks, the second sub-block protrudes towards the sub-pixel relative to the first sub-block, along the direction from one sub-pixel to the next adjacent sub-pixel.

[0017] Based on the same inventive concept, this disclosure also provides a method for manufacturing a display panel, the method comprising:

[0018] Provide substrate;

[0019] Create multiple anodes, with each anode corresponding to a sub-pixel;

[0020] Create a first pixel definition layer, pattern the first pixel definition layer, form multiple first openings, and expose a portion of the anode through the first openings;

[0021] A second pixel definition layer is fabricated, the second pixel definition layer is patterned, and multiple second openings are formed. The orthographic projection of the second opening onto the substrate at least partially overlaps with the orthographic projection of the first opening onto the substrate.

[0022] A partition is made, which is located between two adjacent sub-pixels and in a direction perpendicular to the plane of the substrate. The partition includes a first sub-partition that penetrates the second pixel definition layer and a second sub-partition that penetrates at least a portion of the first pixel definition layer. The first sub-partition and the second sub-partition are connected to form the partition.

[0023] At the junction of the first sub-division and the second sub-division, along the direction from one sub-pixel to another adjacent sub-pixel, the second sub-division protrudes towards the sub-pixel relative to the first sub-division.

[0024] A light-emitting layer is fabricated, at least a portion of which is located within a first opening on the side of the second pixel definition layer away from the substrate; the light-emitting layer includes a common layer, which is interrupted at a partition opening;

[0025] A cathode layer is fabricated, and the cathode layer is isolated at the partition opening.

[0026] Based on the same inventive concept, this disclosure also provides a display device, which includes the above-described display panel. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0028] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 is a schematic diagram of a planar structure of a display panel provided in an embodiment of this disclosure;

[0030] Figure 2 is a schematic diagram of a cross-sectional structure along A-A' in Figure 1;

[0031] Figure 3 is a schematic diagram of a structure in Figure 2 in which the light-emitting layer is located between the anode and cathode layers;

[0032] Figure 4 is a schematic diagram of another cross-sectional structure along the A-A' direction in Figure 1;

[0033] Figure 5 is a schematic diagram of another structure in Figure 2 where the light-emitting layer is located between the anode and cathode layers;

[0034] Figure 6 is a schematic diagram of another cross-sectional structure along the A-A' direction in Figure 1;

[0035] Figure 7 is a schematic diagram of a partition structure in related technologies;

[0036] Figure 8 is an enlarged structural schematic diagram of the partition location in Figure 2;

[0037] Figure 9 is a schematic diagram of the combination of sub-pixel arrangement and partition arrangement provided in an embodiment of this disclosure;

[0038] Figure 10 is a schematic diagram of another combination of sub-pixel arrangement and partition arrangement provided in an embodiment of this disclosure;

[0039] Figure 11 is a schematic diagram of another cross-sectional structure along the A-A' direction in Figure 1;

[0040] Figure 12 is a schematic diagram of another cross-sectional structure along the A-A' direction in Figure 1;

[0041] Figure 13 is a schematic diagram of another cross-sectional structure along the A-A' direction in Figure 1;

[0042] Figure 14 is a schematic diagram of another cross-sectional structure along the A-A' direction in Figure 1;

[0043] Figure 15 is a schematic diagram of another cross-sectional structure along the A-A' direction in Figure 1;

[0044] Figure 16 is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure;

[0045] Figure 17 is a schematic diagram of a cross-sectional structure along the B-B' direction in Figure 16;

[0046] Figure 18 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure;

[0047] Figure 19 is a schematic diagram of the structure after anode fabrication in the method shown in Figure 18;

[0048] Figure 20 is a schematic diagram of the structure after the first pixel definition layer of patterning is completed in the production method of Figure 18;

[0049] Figure 21 is a schematic diagram of the structure after the second opening of the second pixel definition layer is completed in the manufacturing method of Figure 18;

[0050] Figure 22 is a schematic diagram of the structure after the partition is completed in the manufacturing method of Figure 18;

[0051] Figure 23 is a schematic diagram of the structure after the light-emitting layer is completed in the fabrication method of Figure 18;

[0052] Figure 24 is a schematic diagram of the structure after the cathode layer is completed in the fabrication method of Figure 18;

[0053] Figure 25 is another flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure;

[0054] Figure 26 is a schematic diagram of the structure after the first pixel definition layer of patterning is completed in the production method of Figure 25;

[0055] Figure 27 is a schematic diagram of the structure after the second opening of the second pixel definition layer is completed in the manufacturing method of Figure 25;

[0056] Figure 28 is a schematic diagram of the position of a mask plate when making the partition in the manufacturing method of Figure 25;

[0057] Figure 29 is a schematic diagram of the position of another mask plate when making the partition in the manufacturing method of Figure 25;

[0058] Figure 30 is a schematic diagram of the structure after the light-emitting layer is completed in the fabrication method of Figure 25;

[0059] Figure 31 is a schematic diagram of the structure after the cathode layer is completed in the fabrication method of Figure 25;

[0060] Figure 32 is a schematic diagram of a planar structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0061] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0062] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0063] Please refer to Figures 1 and 2. Figure 1 is a planar structural schematic diagram of a display panel provided in an embodiment of the present disclosure, and Figure 2 is a cross-sectional structural schematic diagram along A-A' in Figure 1. The display panel 000 provided in this embodiment includes a plurality of sub-pixels 00, and each sub-pixel 00 includes an anode 20.

[0064] The display panel 000 also includes:

[0065] Substrate 10, anode 20 is located on one side of substrate 10;

[0066] The first pixel definition layer 30 is located on the side of the anode 20 away from the substrate 10. The first pixel definition layer 30 includes a plurality of first openings 30K1, and the first openings 30K1 expose a portion of the anode 20.

[0067] The second pixel definition layer 40 is located on the side of the first pixel definition layer 30 away from the substrate 10. The second pixel definition layer 40 includes a plurality of second openings 40K1. The orthographic projection of the second openings 40K1 onto the substrate 10 at least partially overlaps with the orthographic projection of the first openings 30K1 onto the substrate 10.

[0068] The light-emitting layer 50, at least a portion of which is located within the first opening 30K1; it is understood that the light-emitting layer 50 may include a common light-emitting layer, such as a hole transport layer, an electron transport layer, a charge generation layer, etc.

[0069] Cathode layer 60, which is located on the side of light-emitting layer 50 away from substrate 10;

[0070] Between two adjacent sub-pixels 00, the display panel 000 includes at least one partition JK. Along the direction Z perpendicular to the plane of the substrate 10, the partition JK includes a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating at least a portion of the first pixel definition layer 30. The first sub-partition JK1 and the second sub-partition JK2 are connected.

[0071] At the junction of the first sub-block JK1 and the second sub-block JK2, along the direction from one sub-pixel 00 to another adjacent sub-pixel 00, the second sub-block JK2 protrudes towards the sub-pixel 00 relative to the first sub-block JK1.

[0072] Specifically, the display panel 000 provided in this embodiment can be an organic light-emitting diode (OLED) display panel. The display panel 000 includes a substrate 10 (not filled in Figure 2), which serves as a carrier substrate for setting other film layer structures of the display panel 000. Optionally, in this embodiment, the substrate 10 of the display panel 000 can be a rigid material such as glass or ceramic, or a flexible material such as polymers like polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). The substrate 10 can be any of a transparent substrate, a semi-transparent substrate, or an opaque substrate; this embodiment is not limited to any one of these. The sub-pixels 00 of the display panel 000 include an anode 20, which can be located on one side of the substrate 10. Optionally, a driving array layer 70 may be included between the substrate 10 and the anode 20 along the direction Z perpendicular to the plane of the substrate 10. The driving array layer 70 may contain thin-film transistors 70T arranged in multiple conductive film layers. The multiple thin-film transistors 70T are used to form a driving circuit that provides driving signals to the display panel 000, such as a pixel circuit. The driving array layer 70 may also be used to set driving traces. The layout structure of the driving array layer 70 is not described in detail in this embodiment; for details, please refer to the film layer structure of OLED display panels in related technologies for understanding. The anode 20 corresponding to the sub-pixel 00 may be electrically connected to the thin-film transistor 70T to transmit the driving signals of the pixel circuit to the anode 20. Optionally, the anode 20 may be formed of various conductive materials, such as a transparent anode or a reflective anode, depending on its intended use. When the anode 20 is formed as a transparent anode, the material of the anode 20 may include indium tin oxide (ITO), indium zinc oxide (IZO), etc.; when the anode 20 is formed as a reflective anode, the material of the anode 20 may include silver, magnesium, aluminum, or other metal mixtures, and this embodiment does not specifically limit this.

[0073] In this embodiment, the side of the anode 20 away from the substrate 10 includes a first pixel definition layer 30 and a second pixel definition layer 40. The first pixel definition layer 30 and the second pixel definition layer 40 can be stacked, meaning that the surface of the first pixel definition layer 30 away from the substrate 10 can contact the surface of the second pixel definition layer 40 facing the substrate 10. The first pixel definition layer 30 includes a plurality of first openings 30K1, which expose a portion of the anode 20. The second pixel definition layer 40 includes a plurality of second openings 40K1, whose orthogonal projections onto the substrate 10 at least partially overlap with the orthogonal projections of the first openings 30K1 onto the substrate 10. That is, the at least partially overlapping first openings 30K1 and second openings 40K1 together form an opening for exposing a portion of the anode 20, which is subsequently used for depositing organic light-emitting materials. The side of the second pixel definition layer 40 away from the substrate 10 includes a light-emitting layer 50, at least a portion of which is located within the first opening 30K1. Optionally, at least a portion of the light-emitting layer 50 is located within the second opening 40K1. The light-emitting layer 50 can be formed by vapor deposition of organic light-emitting materials. The first opening 30K1 of the first pixel definition layer 30 and the second opening 40K1 of the second pixel definition layer 40 are used to prevent color mixing or cross-coloring between the light-emitting layers 50 of two adjacent sub-pixels 00. That is, the first opening 30K1 of the first pixel definition layer 30 and the second opening 40K1 of the second pixel definition layer 40 are used to define the light-emitting layers 50 of the organic light-emitting materials of adjacent sub-pixels 00, so as to separate the light-emitting layers 50 of different colors into relatively independent structures.

[0074] Optionally, the display panel 000 includes multiple sub-pixels 00. Each sub-pixel 00 can be correspondingly configured with a light-emitting layer 50 provided with a first opening 30K1. The multiple sub-pixels 00 can include various different colors (represented by different filling patterns in Figure 1), such as at least red sub-pixels, green sub-pixels, and blue sub-pixels, and may also include white sub-pixels, etc. The multiple sub-pixels 00 can be arranged in an array on the display panel 000, or the multiple sub-pixels 00 can be arranged in other ways. For details, please refer to the pixel arrangement structure of OLED display panels in related technologies. Figure 1 of this embodiment is only an example and does not represent the actual arrangement of the sub-pixels 00. Figure 1 of this embodiment is only used as an example of an array arrangement of multiple sub-pixels 00. It can be understood that Figure 1 of this embodiment uses the example of a strip shape as the orthogonal projection shape of a sub-pixel 00 onto the light-emitting surface of the display panel 000. In specific implementation, the shape of the sub-pixel 00 includes but is not limited to this shape and can be designed according to actual needs.

[0075] In this embodiment, the side of the light-emitting layer 50 away from the substrate 10 also includes a cathode layer 60. The cathode layer 60 on the light-emitting layer 50 can make the anode 20, the light-emitting layer 50 and the cathode layer 60 stacked. By applying a voltage between the anode 20 and the cathode layer 60, the light-emitting layers 50 of different sub-pixels 00 emit visible light, thereby realizing an image that can be recognized by the user.

[0076] It is understood that the display panel 000 of this embodiment includes, but is not limited to, the above-described film layer structure. It may also include other film layer structures, such as a thin-film encapsulation layer 80 disposed on the side of the cathode layer 60 away from the substrate 10. The thin-film encapsulation layer 80 can be used to isolate water and oxygen, preventing water vapor and oxygen in the air from entering the light-emitting layer 50 and the driving array layer 70, thereby damaging the components therein. Other film layer structures may also be included, such as a planarization layer, etc. These will not be elaborated upon in this embodiment; for details, please refer to the structure of organic light-emitting display panels in related technologies for understanding. Optionally, the thin-film encapsulation layer 80 in this embodiment may include a first inorganic layer, an organic layer, and a second inorganic layer. The first inorganic layer is used to block the organic layer, preventing water vapor and oxygen or other impurities in the organic layer from penetrating into the light-emitting layer 50 of the organic light-emitting material and reacting to damage the organic light-emitting material, leading to display panel failure. The organic layer is used to relieve stress, preventing the inorganic layer from cracking under stress and allowing water vapor and oxygen to intrude. The second inorganic layer is used to prevent water vapor and oxygen from the external environment from intruding into the display panel 000. The first and second inorganic layers of the thin-film encapsulation layer 80 form a dual protection, which can further reduce the probability of intrusion.

[0077] Optionally, as shown in Figures 1, 2, and 3, Figure 3 is a schematic diagram of a structure in Figure 2 where the light-emitting layer is located between the anode and cathode layers. In this embodiment, the light-emitting layer 50 may include a hole injection layer 501, a hole transport layer 502, an organic light-emitting layer 503, a hole blocking layer 504, an electron transport layer 505, and an electron injection layer 506 stacked along the Z-direction perpendicular to the plane of the substrate 10. The hole injection layer 501 and the hole transport layer 502 are located between the organic light-emitting layer 503 and the anode 20, while the hole blocking layer 504, the electron transport layer 505, and the electron injection layer 506 are located between the organic light-emitting layer 503 and the cathode layer 60, and are sequentially close to the cathode layer 60. The light-emitting layer 50 includes a common layer; the common layer includes one or more of the hole injection layer 501, the hole transport layer 502, the hole blocking layer 504, the electron transport layer 505, and the electron injection layer 506.

[0078] In existing technologies, OLED evaporation masks are mainly used for deposition using open masks. This means that the light-emitting layer of the organic light-emitting material is deposited across the entire surface, forming a hole injection layer, hole transport layer, organic light-emitting layer, hole blocking layer, electron transport layer, and electron injection layer. The hole injection layer and hole transport layer form a common layer, which can be understood as the film layer corresponding to at least three sub-pixels of different colors, deposited together by the open mask. This film layer covers all sub-pixel areas and the spaces between sub-pixels. When the OLED device is operating, because the common layers of each sub-pixel are connected, charge carriers will conduct laterally within these common layers, causing lateral leakage current. When a sub-pixel (target sub-pixel) is lit, due to the leakage current in the display panel, adjacent sub-pixels are easily affected and may also be illuminated, resulting in light leakage and color crosstalk. This electrical light leakage phenomenon is particularly noticeable in full-color OLED display panels, especially in low grayscale displays, where color shift is particularly severe, thereby reducing the display quality of OLED display panels.

[0079] To solve the above problems, this embodiment sets a partition JK between two adjacent sub-pixels 00. The display panel 000 includes at least one partition JK, as shown in Figures 2 and 4. Figure 4 is a schematic diagram of another cross-sectional structure along A-A' in Figure 1 (the film layer above the second pixel definition layer is not shown in Figure 4 to clearly illustrate the structure of the partition JK in this embodiment). Along the direction Z perpendicular to the plane where the substrate 10 is located, the partition JK includes a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating at least part of the first pixel definition layer 30. The first sub-partition JK1 and the second sub-partition JK2 are connected. That is, by opening the second sub-partition JK2 and the first sub-partition JK1 in the first pixel definition layer 30 and the second pixel definition layer 40 respectively, and the first sub-partition JK1 and the second sub-partition JK2 are connected in the direction Z perpendicular to the plane where the substrate 10 is located to form a partition JK. The partition JK is located between two adjacent sub-pixels 00, and the partition JK is also located between two adjacent second openings 40K1. In this embodiment, the partition JK is configured such that at the junction of the first sub-partition JK1 and the second sub-partition JK2 (as shown in the dashed circle J1 position in Figure 4), along the direction from one sub-pixel 00 to the adjacent sub-pixel 00, the second sub-partition JK2 protrudes towards the sub-pixel 00 relative to the first sub-partition JK1. Thus, the double-layered structure of the first pixel definition layer 30 and the second pixel definition layer 40 can form at least one side of the second sub-partition JK2 as a single-sided undercut structure at the dashed circle J1 position. Therefore, when the above-mentioned film layers of the light-emitting layer 50 are deposited, the organic light-emitting material can form a light-emitting layer 50 corresponding to the anode 20 of the sub-pixel 00 in the first opening 30K1 and the second opening 40K1. Moreover, due to the single-sided undercut structure of the second sub-segment JK2 formed at the J1 position, the common layer of the light-emitting layer 50 can be effectively isolated at the J1 position, which is equivalent to the leakage current path being isolated. This can effectively improve the color crosstalk between adjacent sub-pixels. Especially when the display panel 000 performs low grayscale display, it can avoid color crosstalk between adjacent sub-pixels, improve electrical light leakage, and at the same time, it does not affect the normal light emission of the pixel, ensuring the low grayscale display effect.

[0080] In this embodiment, the first pixel definition layer 30 and the second pixel definition layer 40 are different film layers. The materials used to manufacture the first pixel definition layer 30 and the second pixel definition layer 40 can be different. Since they are stacked and made of different materials, it is more convenient and faster to form a single-sided undercut structure of the second sub-partition JK2 at the junction of the first sub-partition JK1 and the second sub-partition JK2. This makes it possible to form the partition opening JK shown in Figures 2 and 4. Thus, in this embodiment, at least the common layer in the light-emitting layer 50 can be effectively isolated at the partition opening JK. That is, the partition opening JK shown in Figures 2 and 4 can ensure the isolation of lateral leakage current, which is beneficial to simplify the manufacturing process, improve the manufacturing efficiency, and also improve the color deviation problem and improve the display quality.

[0081] It should be noted that Figures 2 and 4 in this embodiment are merely illustrative depictions of the unilateral undercut structure of the second sub-partition JK2 formed at the junction of the first sub-partition JK1 and the second sub-partition JK2 of the partition JK. In specific implementations, the unilateral undercut structure of the second sub-partition JK2 formed at the junction of the first sub-partition JK1 and the second sub-partition JK2 may include, but is not limited to, this, and may also include other forms. It is only necessary to satisfy that at the junction of the first sub-partition JK1 and the second sub-partition JK2, along the direction from one sub-pixel 00 to another adjacent sub-pixel 00, the second sub-partition JK2 protrudes towards the sub-pixel 00 relative to the first sub-partition JK1, so that at least the common layer or other film layer in the light-emitting layer 50 with the possibility of lateral leakage current transmission is isolated at this unilateral undercut structure. In this embodiment, the unilateral undercut structure of the second sub-partition JK2 formed at the junction of the first sub-partition JK1 and the second sub-partition JK2 will not be described in detail.

[0082] Optionally, as shown in Figures 1, 2 and 4, sub-pixel 00 includes an adjacent first sub-pixel 00A and a second sub-pixel 00B. The colors of the first sub-pixel 00A and the second sub-pixel 00B can be different. Along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-segment JK2 includes a first end JK2A and a second end JK2B, with the first end JK2A located between the second end JK2B and the first sub-pixel 00A.

[0083] At the junction of the first sub-block JK1 and the second sub-block JK2 (at position J1 in Figure 4), the first end JK2A of the second sub-block JK2 protrudes towards the first sub-pixel 00A relative to the first sub-block JK1, thus forming the shape of a single-sided undercut structure of the second sub-block JK2.

[0084] Alternatively, it can be understood that, as shown in Figures 1, 2 and 4, the second pixel definition layer 40 includes a first surface 40A that contacts the first pixel definition layer 30;

[0085] Along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, at the first end JK2A, the second sub-partition JK2 exposes a portion of the first surface 40A;

[0086] At the second end JK2B, the first surface 40A of the second pixel definition layer 40 is not exposed in the partition JK, thus forming a single-sided undercut structure on the side of the second sub-partition JK2 near the first sub-pixel 00A, while the side of the second sub-partition JK2 near the second sub-pixel 00B remains smooth or continuous. This ensures that the common layer or cathode layer 60 included in the light-emitting layer 50 will not remain at the partition JK. For a detailed explanation of this structure, please refer to the subsequent embodiments. This embodiment will not be elaborated here.

[0087] Optionally, other film layers may also be included between the cathode layer 60 and the thin film encapsulation layer 80 in this embodiment, such as a cathode capping layer (CPL) on the cathode layer 60 and a lithium fluoride (LiF) layer on the planarization layer. The cathode capping layer can improve the light extraction efficiency and increase the luminous refractive index, thereby improving the efficiency and lifespan of the luminescent layer 50. It can also suppress light absorption, reduce energy loss, and further enhance the performance of the display panel. The lithium fluoride layer can isolate ions to improve the light extraction efficiency. This embodiment does not elaborate on the film layer structure of the display panel 000. In specific implementation, the film layer structure of the display panel includes, but is not limited to, this, and may also include other film layer structures that can realize display functions and improve display quality. For details, please refer to the film layer structure of OLED display panels in related technologies for understanding.

[0088] Optionally, as shown in Figures 1-2 and 5, Figure 5 is another structural schematic diagram of the light-emitting layer located between the anode and cathode layers in Figure 2. In this embodiment, the light-emitting layer 50 may include a hole injection layer 5011, a hole transport layer 5012, a first organic light-emitting layer 5013, a charge generation layer 5014, a second organic light-emitting layer 5015, a hole blocking layer 5016, an electron transport layer 5017, and an electron injection layer 5018 stacked along the Z direction perpendicular to the plane of the substrate 10.

[0089] The light-emitting layer 50 includes a common layer;

[0090] The common layer includes one or more of the following: hole injection layer 5011, hole transport layer 5012, charge generation layer 5014, hole blocking layer 5016, electron transport layer 5017, and electron injection layer 5018.

[0091] This embodiment explains that the light-emitting layer 50 of the display panel 000 may include at least two organic light-emitting layers. Specifically, the light-emitting layer 50 may include a hole injection layer 5011, a hole transport layer 5012, a first organic light-emitting layer 5013, a charge generation layer 5014, a second organic light-emitting layer 5015, a hole blocking layer 5016, an electron transport layer 5017, and an electron injection layer 5018 stacked along the Z direction perpendicular to the plane of the substrate 10. The hole injection layer 5011 and the hole transport layer 5012 are located between the anode 20 and the first organic light-emitting layer 5013, and the hole blocking layer 5016, the electron transport layer 5017, and the electron injection layer 5018 are located between the second organic light-emitting layer 5015 and the cathode layer 60, and are sequentially close to the cathode layer 60.

[0092] In the display panel 000 of this embodiment, the light-emitting layer 50 adopts a structure of at least two organic light-emitting layers, which can be understood as more organic light-emitting layers connected in series. The light emission efficiency can be effectively improved, and the brightness is also higher under the same current density. Therefore, the display panel 000 with this structure has better light emission efficiency and higher brightness, which is beneficial to improving the display effect.

[0093] In this embodiment, a charge generation layer 5014 is also included between the first organic light-emitting layer 5013 and the second organic light-emitting layer 5015. The charge generation layer can also be called an electron-hole pair secondary generation layer. The charge generation layer 5014 may include an electron secondary generation layer 5014A and a hole secondary generation layer 5014B. Although the charge generation layer 5014 does not need to be connected to an electrical signal and relies on electric field induction to generate electrons and holes, its conductivity is better due to doping. Once the common layer of the light-emitting layer 50 includes the charge generation layer 5014, the impact of lateral leakage current is greater. Therefore, as shown in Figures 2 and 4, in this embodiment, the single-sided undercut structure of the second sub-partition JK2 formed at the junction of the first sub-partition JK1 and the second sub-partition JK2 (at position J1) allows the common layer of the light-emitting layer 50, including the charge generation layer 5014, to be more effectively isolated at position J1. The leakage current path is completely isolated, which can effectively improve the color crosstalk between adjacent sub-pixels, especially when the display panel 000 performs low grayscale display, ensuring the low grayscale display effect.

[0094] Optionally, as shown in Figures 1 and 6, Figure 6 is another cross-sectional view of the structure along A-A' in Figure 1. The display panel 000 provided in this embodiment also includes a touch layer 90, which is located on the side of the cathode layer 60 away from the substrate 10. Further optionally, the touch layer 90 is located on the side of the thin film encapsulation layer 80 away from the substrate 10.

[0095] The touch layer 90 includes a touch electrode 901, which is a mesh structure surrounding the light-emitting layer 50. The orthogonal projection of the touch electrode 901 onto the substrate 10 is located between two adjacent sub-pixels 00.

[0096] This embodiment explains that the display panel 000 can achieve touch function by setting a touch layer 90. The touch layer 90 is located on the side of the cathode layer 60 away from the substrate 10. The touch electrodes 901 set in the touch layer 90 are generally metal mesh structures. The touch electrodes 901 with metal mesh structures are routed around the sub-pixels 00. The area enclosed by the touch electrodes 901 with mesh structures corresponds to the location of the light-emitting layer 50. That is, the touch electrodes 901 with mesh routes are located between adjacent sub-pixels 00.

[0097] It is understood that the structure of the touch electrode 901 of the touch layer 90 will not be described in detail in this embodiment. The touch layer 90 may include a double layer or a single layer of conductive layer to form a grid-like touch electrode 901. The touch electrode 901 may include a touch driving electrode and a touch sensing electrode to realize the touch detection function. In specific implementation, the structure of the display touch panel in related technologies can be referred to for understanding. This embodiment will not be described in detail here.

[0098] As shown in Figure 7, which is a schematic diagram of a partition opening in the related technology, since the thin film encapsulation layer 80' is generally thin and the distance between the touch layer 90' and the cathode layer 60' is relatively close, when the touch electrode 901' of the touch layer 90' is located between adjacent sub-pixels 00' and a partition opening JK' is provided between adjacent sub-pixels 00', if the forming shape of the partition opening JK' is as shown in Figure 7, then although the cathode layer 60' can be isolated at the partition opening JK' position, it is very likely that due to the presence of the partition opening JK' in Figure 7, cathode material residue will form in the partition opening JK'. That is, the cathode layer material 601' remaining in the partition opening JK' as shown in Figure 7 is in a floating state. The floating cathode layer material 601' is relatively close to the touch layer 90', so it will interfere with touch detection and affect touch accuracy.

[0099] Therefore, in this embodiment, the second sub-partition JK2 is positioned at the junction of the first sub-partition JK1 and the second sub-partition JK2 (as shown in the dotted circle J1 position in Figure 4). The direction is from one sub-pixel 00 to the adjacent sub-pixel 00, such as the direction X from the first sub-pixel 00A to the second sub-pixel 00B. The second sub-partition JK2 protrudes towards the sub-pixel 00 relative to the first sub-partition JK1. Thus, the structure of the double-layered first pixel definition layer 30 and the second pixel definition layer 40 can form a single-sided undercut structure for the second sub-partition JK2 at the dotted circle J1 position. This not only ensures that when the aforementioned layers of the light-emitting layer 50 are deposited, the organic light-emitting material forms a light-emitting layer 50 corresponding to the anode 20 of the sub-pixel 00 within the first opening 30K1 and the second opening 40K1, but also, due to the single-sided undercut structure of the second sub-separation JK2 formed at position J1, the common layer of the light-emitting layer 50 can be effectively isolated at position J1, which is equivalent to the leakage current path being isolated. This effectively improves color crosstalk between adjacent sub-pixels, especially ensuring a low grayscale display effect when the display panel 000 is displaying at low grayscale. Furthermore, the cathode layer 60 can also be isolated within the isolation opening JK, where only one side of the second sub-separation JK2 has a single-sided undercut structure, ensuring that no cathode layer material remains within the isolation opening JK.

[0100] Specifically, in the display panel 000 film layer structure of this embodiment, as shown in FIG4, the second pixel definition layer 40 includes a first surface 40A that contacts the first pixel definition layer 30; in the partition opening JK provided between two adjacent sub-pixels 00, along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, at the first end JK2A of the second sub-partition JK2, the first surface 40A of the second sub-partition JK2 is exposed; at the second end JK2B of the second sub-partition JK2, the first surface 40A of the second pixel definition layer 40 is not exposed in the partition opening JK, and so on. The second sub-partition JK2 is formed with a single-sided undercut structure only on the side near the first sub-pixel 00A, while the side of the second sub-partition JK2 near the second sub-pixel 00B remains rounded. The cathode layer 60 can still form a continuous structure at the second end JK2B of the rounded second sub-partition JK2. This not only ensures that the common layer included in the light-emitting layer 50 is separated at the partition opening JK, but also ensures that the cathode layer 60 will not remain at the partition opening JK. This is beneficial to improving the touch performance of the display panel 000 and ensuring touch accuracy.

[0101] In some alternative embodiments, please refer to Figures 1, 2, 4 and 8. Figure 8 is an enlarged structural schematic diagram of the partition location in Figure 2. In this embodiment, along the direction from one sub-pixel 00 to another adjacent sub-pixel 00, and along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, the cathode layer 60 includes only one slit 60K within the partition JK.

[0102] This embodiment explains that in the partition JK set between two adjacent sub-pixels 00, along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, at the first end JK2A of the second sub-partition JK2, a portion of the first surface 40A of the second sub-partition JK2 is exposed; at the second end JK2B of the second sub-partition JK2, the first surface 40A of the second pixel definition layer 40 is not exposed within the partition JK, thus forming a shape where the second sub-partition JK2 has a single-sided undercut structure only on the side closest to the first sub-pixel 00A, while the first... The second sub-partition JK2 remains rounded on the side closest to the second sub-pixel 00B. The cathode layer 60 can still form a continuous structure at the second end JK2B of the rounded second sub-partition JK2. This can also be understood as the cathode layer 60 within the partition opening JK, where the cathode layer 60 includes only one slit 60K. That is, one partition opening JK corresponds to only one slit 60K of the cathode layer 60. This more effectively ensures that the cathode layer 60 material will not remain at the partition opening JK, thus improving touch sensitivity.

[0103] Optionally, in the cathode layer 60 structure set in this embodiment, the cathode layer 60 is a continuous structure except for the slit 60K. That is, the cathode 60 in the display panel 000 can still be understood as a whole surface. It is only separated at the partition JK position to form a finite-sized slit 60K. The slit 60K is still continuous. Therefore, the cathode layer 60 corresponding to different sub-pixels 00 does not need to be controlled separately, which helps to simplify the driving.

[0104] Optionally, as shown in Figures 1, 2, 4, 8, 9, and 10, Figure 9 is a schematic diagram of a combination of sub-pixel arrangement and partition arrangement provided in an embodiment of this disclosure, and Figure 10 is a schematic diagram of another combination of sub-pixel arrangement and partition arrangement provided in an embodiment of this disclosure. In this embodiment, as shown in Figure 9, the arrangement of multiple sub-pixels 00 of the display panel 000 is illustrated using a diamond pentile arrangement as an example, and a partition JK can be set between two adjacent sub-pixels 00; as shown in Figure 10, the arrangement of multiple sub-pixels 00 of the display panel 000 is illustrated using a diamond pentile arrangement as an example, and two partition JKs can be set between two adjacent sub-pixels 00. Setting two partition JKs between two adjacent sub-pixels 00 can more thoroughly isolate the leakage current path, and the leakage current improvement effect will be better. However, the space between two adjacent sub-pixels 00 is limited, and the more partition JKs between two adjacent sub-pixels 00, the more difficult it is for the current to flow in the cathode layer 60, the greater the voltage drop will be, and the higher the power consumption will be. Therefore, in this embodiment, the number of gaps JK between two adjacent sub-pixels 00 can be set to 1-2. This can improve the color crosstalk problem, improve the impact of cathode material residue on touch performance, and improve the problem of high power consumption of the cathode layer. In other words, this embodiment can improve the color deviation problem, improve the display quality, improve the touch sensitivity, and ensure the current flow of the cathode layer 60, thereby reducing power consumption.

[0105] In some alternative embodiments, please continue to refer to Figures 1, 2 and 4. In this embodiment, the width W1 of the partition JK ranges from 2 to 8 μm along the direction from one sub-pixel 00 to another adjacent sub-pixel 00, such as the direction X from the first sub-pixel 00A to the second sub-pixel 00B.

[0106] This embodiment explains that along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, the width W1 of the partition JK ranges from 2 to 8 μm. The width W1 of the partition JK cannot be too small, as this would make it difficult to separate the common layer of the light-emitting layer 50 and the cathode layer 60 at the partition JK. Conversely, the width W1 of the partition JK cannot be too large, as this would affect the current flow and transmission in the cathode layer 60, leading to an increased current voltage drop and thus increased power consumption. This embodiment sets the width W1 of the partition JK in the direction X from the first sub-pixel 00A to the second sub-pixel 00B within the range of 2-8 μm. This not only improves color crosstalk and color cast issues, enhancing display quality, but also increases touch sensitivity and reduces power consumption.

[0107] In some alternative embodiments, please refer to Figures 1 and 11. Figure 11 is a schematic diagram of another cross-sectional structure along A-A' in Figure 1. In this embodiment, the display panel 000 further includes a color filter layer 100, which is located on the side of the cathode layer 60 away from the substrate 10.

[0108] The color filter layer 100 includes a black matrix 1001 and a color filter 1002 disposed between the black matrix 1001;

[0109] In the direction Z perpendicular to the plane of substrate 10, color resist 1002 corresponds to light-emitting layer 50.

[0110] This embodiment explains that the display panel 000 is an OLED display panel. The display panel 000 may also include a color filter layer 100, which can be disposed on the side of the cathode layer 60 away from the substrate 10. Specifically, the color filter layer 100 can be disposed on the side of the thin film encapsulation layer 80 away from the substrate 10, or the color filter layer 100 can be disposed between the thin film encapsulation layer 80 and the touch layer 90. In related technologies, in order to prevent the light-emitting layer 50 from reflecting ambient light and affecting the display quality, an anti-reflective polarizer is generally attached to the display panel. The polarizer is prone to causing some loss of emitted light, which may reduce the brightness of the display panel. Furthermore, the polarizer is relatively thick, which is not conducive to the design of flexible display panels. In this embodiment, a color filter layer 100 is used instead of a polarizer. The color filter layer 100 includes a black matrix 1001 and color resists 1002 disposed between the black matrix 1001. In the direction Z perpendicular to the plane of the substrate 10, the color resists 1002 correspond to the light-emitting layer 50. The black matrix 1001 has a low transmittance, and the multiple openings in the black matrix 1001 are the light-transmitting areas of the black matrix 1001. The color resists 1002 are disposed in the multiple openings in the black matrix 1001, that is, each color resist 1002 is placed in the corresponding opening of the black matrix 1001. The color resists 1002 are used to absorb light of a different color than themselves, allowing light of the same color to pass through, thereby achieving light filtering of the display panel 000. In this embodiment, by setting the color filter layer 100, the color gamut of the display panel can be compensated while reducing ambient light reflection, thus improving the display quality.

[0111] Optionally, referring to Figures 1 and 11, in this embodiment, the transmittance of the first pixel definition layer 30 is less than the transmittance of the second pixel definition layer 40.

[0112] Further optionally, the first pixel definition layer 30 includes a black material.

[0113] This embodiment explains that when the display panel 000 includes a color filter layer 100, the light transmittance of the material used to manufacture the first pixel definition layer 30 can be less than the light transmittance of the second pixel definition layer 40. That is, the material of the first pixel definition layer 30 can be a light-shielding material such as a black material, which can enable the first pixel definition layer 30 to block external light, thereby reducing the reflectivity of light irradiating the surface of the first pixel definition layer 30 and preventing external light from irradiating the thin film transistors 70T of the driving array layer 70. This is beneficial to improving the stability of the thin film transistors 70T. In addition, the black material of the first pixel definition layer 30 can block crosstalk between adjacent sub-pixels 00, thereby improving the contrast of the display panel 000.

[0114] In some alternative embodiments, please continue to refer to FIG1 and FIG2. In this embodiment, the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 onto the substrate 10 is located within the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 onto the substrate 10.

[0115] This embodiment explains that the size of the first opening 30K1 can be slightly smaller than the size of the second opening 40K1. That is, the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 onto the substrate 10 is located within the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 onto the substrate 10, so that the first opening 30K1 and the second opening 40K1 overlap to form at least a portion of the accommodating space of the light-emitting layer 50, and the first opening 30K1 and the second opening 40K1 overlap to form the light-emitting area of ​​the sub-pixel 00.

[0116] In some alternative embodiments, please refer to Figures 1 and 12. Figure 12 is a schematic diagram of another cross-sectional structure along A-A' in Figure 1. In this embodiment, the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 onto the substrate 10 is located within the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 onto the substrate 10.

[0117] At the first opening 30K1, the second pixel definition layer 40 covers the first pixel definition layer 30.

[0118] This embodiment explains that the size of the first opening 30K1 can be slightly larger than the size of the second opening 40K1. That is, the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 onto the substrate 10 lies within the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 onto the substrate 10. Thus, after the first pixel definition layer 30 is patterned, when fabricating the second pixel definition layer 40, the second pixel definition layer 40 can cover the first pixel definition layer 30 at the first opening 30K1. This prevents foreign matter residue at the first opening 30K1 from affecting the evaporation of the light-emitting layer 50, which could lead to abnormal light emission and thus ensures light emission quality. In this embodiment, the second pixel definition layer 40 can cover the first pixel definition layer 30 at the first opening 30K1. Since the second pixel definition layer 40 can be produced using a coating process, it has a stronger ability to fill gaps and is less prone to breakage. Therefore, it can effectively cover any foreign matter residue that may appear at the first opening 30K1, which is beneficial for improving display and light emission quality.

[0119] In some alternative embodiments, please continue to refer to Figures 1, 2, 4 and 6. In this embodiment, in the direction Z perpendicular to the plane where the substrate 10 is located, the second sub-segment JK2 penetrates a portion of the thickness of the first pixel definition layer 30, and the first sub-segment JK1 penetrates the thickness of the second pixel definition layer 40.

[0120] This embodiment explains that along the direction Z perpendicular to the plane where the substrate 10 is located, the partition opening JK includes a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating a portion of the first pixel definition layer 30. The first sub-partition JK1 and the second sub-partition JK2 are connected, that is, by opening the second sub-partition JK2 and the first sub-partition JK1 in the first pixel definition layer 30 and the second pixel definition layer 40 respectively, and the first sub-partition JK1 and the second sub-partition JK2 are connected in the direction Z perpendicular to the plane where the substrate 10 is located to form a partition opening JK. The partition opening JK is located between two adjacent sub-pixels 00, and the partition opening JK is also located between two adjacent second openings 40K1. Therefore, along the direction X pointing from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-block JK2 protrudes towards the first sub-pixel 00A relative to the first sub-block JK1, forming a single-sided undercut structure on one side of the second sub-block JK2. Not only can the common layer of the light-emitting layer 50 be effectively blocked at the position marked by the dotted circle J1, but the cathode layer 60 is also effectively blocked at the position marked by the dotted circle J1, and there will be no cathode layer material residue. This can effectively improve the color crosstalk between adjacent sub-pixels and also improve the touch performance.

[0121] In some alternative embodiments, please refer to Figures 1, 13, and 14. Figure 13 is a schematic diagram of another cross-sectional structure along the A-A' direction in Figure 1, and Figure 14 is a schematic diagram of another cross-sectional structure along the A-A' direction in Figure 1 (the film layer above the second pixel definition layer is not shown in Figure 14 to clearly illustrate the structure of the partition in this embodiment). In this embodiment, in the direction Z perpendicular to the plane where the substrate 10 is located, the second sub-partition JK2 penetrates the thickness of the first pixel definition layer 30, and the first sub-partition JK1 penetrates the thickness of the second pixel definition layer 40.

[0122] This embodiment explains that along the direction Z perpendicular to the plane where the substrate 10 is located, the partition opening JK includes a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating the first pixel definition layer 30. The first sub-partition JK1 and the second sub-partition JK2 are connected, that is, by opening the second sub-partition JK2 and the first sub-partition JK1 in the first pixel definition layer 30 and the second pixel definition layer 40 respectively, and the first sub-partition JK1 and the second sub-partition JK2 are connected in the direction Z perpendicular to the plane where the substrate 10 is located to form a partition opening JK. The partition opening JK is located between two adjacent sub-pixels 00, and the partition opening JK is also located between two adjacent second openings 40K1. Therefore, along the direction X pointing from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-block JK2 protrudes towards the first sub-pixel 00A relative to the first sub-block JK1, forming a single-sided undercut structure on one side of the second sub-block JK2. Not only can the common layer of the light-emitting layer 50 be effectively blocked at the J2 position circled in Figure 14, but the cathode layer 50 is also effectively blocked at the J2 position circled in the dotted circle, and there will be no cathode layer material residue. This can effectively improve the color crosstalk between adjacent sub-pixels and also improve the touch performance.

[0123] In this embodiment, the partition JK is composed of a first sub-partition JK1 that penetrates the entire thickness of the second pixel definition layer 40 and a second sub-partition JK2 that penetrates the entire thickness of the first pixel definition layer 30. The side marking of the second sub-partition JK2, which has a single-sided undercut structure on one side, can be larger, resulting in a better partition effect.

[0124] In some alternative embodiments, please continue to refer to Figures 1, 2, 4, 6, 13 and 14. In this embodiment, the first pixel definition layer 30 further includes a plurality of third openings 30K2. The third openings 30K2 are located between two adjacent first openings 30K1 and penetrate the first pixel definition layer 30.

[0125] In the direction Z perpendicular to the plane of the substrate 10, the partition JK and the third opening 30K2 at least partially overlap, and at least part of the second pixel definition layer 40 is filled in the third opening 30K2.

[0126] This embodiment explains that in order to make the double-layered first pixel definition layer 30 and second pixel definition layer 40, a second sub-partition JK2 can be formed at the position J1 circled in Figure 4 and the position J2 circled in Figure 14, with only one side being a single-sided undercut structure. When fabricating and patterning the first pixel definition layer 30, the first pixel definition layer 30 can be set to include multiple first openings 30K1 corresponding to the anode 20, as well as multiple third openings 30K2. The third openings 30K2 are located between two adjacent first openings 30K1, that is, between two adjacent sub-pixels 00. The third openings 30K2 penetrate the entire thickness of the first pixel definition layer 30. In this embodiment, by setting the third opening 30K2 in the first pixel definition layer 30, the second pixel definition layer 40 can fill the third opening 30K2 after the second pixel definition layer 40 is coated, covering one side of the first pixel definition layer 30 (as shown in the dashed circle J3 position in Figures 4 and 14, the second pixel definition layer 40 can fill the third opening 30K2 and cover one side of the first pixel definition layer 30). After the first pixel definition layer 30 and the second pixel definition layer 40 are both fabricated, when fabricating the partition JK, it is equivalent to the first pixel definition layer 30 on one side of the third opening 30K2 being protected. This allows the second sub-partition JK2 to be formed only on the side near the first sub-pixel 00A. This makes the shape of the partition JK required in this embodiment possible during the manufacturing process, ensuring that the common layer of the light-emitting layer 50 can be effectively isolated, the cathode layer 50 can also be effectively isolated, and there will be no cathode layer material residue. This effectively improves the color crosstalk between adjacent sub-pixels and enhances touch performance.

[0127] It is understood that the figures in this embodiment are only illustrative examples of the third opening 30K2 penetrating the entire thickness of the first pixel definition layer 30. In specific implementation, as shown in Figures 1 and 15, Figure 15 is a schematic diagram of another cross-sectional structure along A-A' in Figure 1. The third opening 30K2 may also penetrate only part of the thickness of the first pixel definition layer 30. Since the single-sided undercut structure of the second sub-partition JK2 is relatively shallow, the area of ​​the first pixel definition layer 30 that needs to be covered and protected by the second pixel definition layer 40 at the third opening 30K2 may also be relatively shallow. Therefore, the first pixel definition layer 30 at the third opening 30K2 may not be completely removed. It is only necessary to ensure that one side of the first pixel definition layer 30 at the third opening 30K2 can be covered by the second pixel definition layer 40 without being side-cut. In specific implementation, the shape of the third opening 30K2 can be set according to actual needs.

[0128] In some alternative embodiments, please refer to Figures 16 and 17. Figure 16 is a schematic diagram of another planar structure of the display panel provided in the present disclosure embodiment, and Figure 17 is a schematic diagram of a cross-sectional structure along B-B' in Figure 16. In this embodiment, in the direction Z perpendicular to the plane where the substrate 10 is located, the third opening 30K2 penetrates the thickness of the first pixel definition layer 30.

[0129] The display panel 000 also includes a photosensitive element 00X, which at least partially overlaps with the third opening 30K2 in the direction Z perpendicular to the plane of the substrate 10.

[0130] This embodiment explains that with the development of display technology, various display devices with fingerprint recognition functions have emerged on the market, such as mobile phones, tablets, and smart wearable devices. Common fingerprint recognition methods mainly include under-display optical fingerprint recognition and under-display ultrasonic fingerprint recognition, among which under-display optical fingerprint recognition has become the mainstream in the market due to its price advantage. When under-display optical fingerprint recognition is applied to an OLED display panel, the under-display fingerprint recognition element or a photosensitive element 00X such as a distance sensor can be placed at the opening of the pixel definition layer with poor light transmittance. In this embodiment, two adjacent sub-pixels 00 are provided with a third opening 30K2 that penetrates the first pixel definition layer 30. When the display panel 000 includes a photosensitive element 00X, the third opening 30K2 can be reused as the light-transmitting port of the photosensitive element 00X. The photosensitive element 00X is set in the direction Z perpendicular to the plane of the substrate 10, at least partially overlapping the third opening 30K2, to ensure that the photosensitive element 00X can be used normally and realize the fingerprint recognition, palm print recognition, distance detection, and other light-sensing detection functions of the display panel 000.

[0131] It is understood that in the display panel 000 of this embodiment, photosensitive elements 00X can be provided between two adjacent sub-pixels 00. The photosensitive elements 00X can be fingerprint recognition elements. By integrating the photosensitive elements 00X into the entire surface of the display panel 000, large-area fingerprint recognition or full-screen fingerprint recognition can be realized.

[0132] Optionally, in this embodiment, the film layer of the photosensitive element 00X can be disposed co-layered with a portion of the film layer of the driving array layer 70, so that the photosensitive element 00X and the thin-film transistors 70T or signal traces in the driving array layer 70 are formed under the same process conditions, which helps to simplify the process flow. Further optionally, the photosensitive element 00X may include a lower electrode 00X1, an upper electrode 00X2, and an intrinsic semiconductor layer 00X3 disposed between the lower electrode 00X1 and the upper electrode 00X2. It is understood that the structure of the photosensitive element 00X in this embodiment is merely illustrative; in specific implementations, the structure of the photosensitive element 00X can be other than that described above. This embodiment is only for explaining that the film layer of the photosensitive element 00X can be disposed co-layered with a portion of the film layer of the driving array layer 70.

[0133] It is understood that Figure 16 in this embodiment is only an example illustrating the arrangement of sub-pixels 00 and the placement of photosensitive elements 00X. In specific implementations, the arrangement of sub-pixels 00 can also be other pixel arrangement structures, which can be selected and set according to actual needs. In this embodiment, the number of third openings 30K2 and the number of photosensitive elements 00X can be different. That is, the photosensitive elements 00X can be placed directly below a portion of the third openings 30K2, i.e., a portion of the third openings 30K2 can be reused as the light-transmitting openings of the photosensitive elements 00X.

[0134] Optionally, in this embodiment, the materials used to fabricate the first pixel definition layer 30 and the second pixel definition layer 40 may be different. Under the same etching conditions, the etching rate of the first pixel definition layer 30 is greater than that of the second pixel definition layer 40. The etching rate of the first pixel definition layer 30 with low light transmittance can be about three times that of the second pixel definition layer 40 with high light transmittance. If the first pixel definition layer 30 is a negative material and the second pixel definition layer 40 is a positive material, when the same mask is used to fabricate the partition opening JK, the exposure position of the mask opening of the second pixel definition layer 40 with positive material will be removed, and the mask blocking position will remain; the exposure position of the mask opening of the first pixel definition layer 30 with negative material will remain, and the mask blocking position will be removed. This allows the partition opening JK to form a single-sided undercut structure on only one side of the second sub-partition JK2 at the junction of the first sub-partition JK1 and the second sub-partition JK2, ensuring that the common layer of the light-emitting layer 50 can be effectively isolated, and the cathode layer 50 can also be effectively isolated, without any cathode layer material residue. This effectively improves color crosstalk between adjacent sub-pixels and enhances touch performance.

[0135] In some optional embodiments, please refer to Figures 1-5 and 18, which are flowcharts of a method for manufacturing a display panel according to an embodiment of this disclosure. This embodiment provides a method for manufacturing a display panel, which is used to manufacture the display panel 000 in any of the above embodiments. The manufacturing method of this embodiment includes:

[0136] S10: Provides substrate 10;

[0137] S11: Fabricate multiple anodes 20, each anode 20 corresponding to a sub-pixel 00; optionally, fabricating anodes 20 can also complete the fabrication of the driving array layer 70; as shown in Figure 19, Figure 19 is a schematic diagram of the structure after the anodes are completed in the fabrication method of Figure 18.

[0138] S12: Fabricate the first pixel definition layer 30, pattern the first pixel definition layer 30, and form multiple first openings 30K1, with the first openings 30K1 exposing a portion of the anode 20; as shown in Figure 20, Figure 20 is a schematic diagram of the structure after the patterned first pixel definition layer is completed in the fabrication method of Figure 18.

[0139] S13: Fabricate a second pixel definition layer 40, pattern the second pixel definition layer 40, and form a plurality of second openings 40K1. The orthographic projection of the second opening 40K1 on the substrate 10 at least partially overlaps with the orthographic projection of the first opening 30K1 on the substrate 10. As shown in Figure 21, Figure 21 is a schematic diagram of the structure after the second opening of the second pixel definition layer is completed in the fabrication method of Figure 18.

[0140] S14: Fabricate a partition JK. The partition JK is located between two adjacent sub-pixels 00 and in the direction Z perpendicular to the plane of the substrate 10. The partition JK includes a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating at least part of the first pixel definition layer 30. The first sub-partition JK1 and the second sub-partition JK2 are connected to form the partition JK. In the partition JK formed in this step, at the junction of the first sub-partition JK1 and the second sub-partition JK2, in the direction from one sub-pixel 00 to the adjacent other sub-pixel 00, such as in the direction X from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-partition JK2 protrudes towards the first sub-pixel 00A relative to the first sub-partition JK1. As shown in Figure 22, Figure 22 is a schematic diagram of the structure after the partition is completed in the fabrication method of Figure 18.

[0141] S15: Fabricate a light-emitting layer 50, at least a portion of which is located within a first opening 30K1 on the side of the second pixel definition layer 40 away from the substrate 10; the light-emitting layer 50 includes a common layer, which is interrupted at the partition opening JK; as shown in Figure 3, the common layer may be one or more of the following: hole injection layer 501, hole transport layer 502, hole blocking layer 504, electron transport layer 505, and electron injection layer 506; as shown in Figure 5, the common layer may be one or more of the following: hole injection layer 5011, hole transport layer 5012, charge generation layer 5014, hole blocking layer 5016, electron transport layer 5017, and electron injection layer 5018; as shown in Figure 23, Figure 23 is a schematic diagram of the structure after the light-emitting layer is completed in the fabrication method of Figure 18.

[0142] S16: Fabricate cathode layer 60, which is isolated at partition JK; as shown in Figure 24, which is a schematic diagram of the structure after the cathode layer is completed in the fabrication method of Figure 18.

[0143] The display panel manufacturing method provided in this embodiment can create a structure of a first pixel definition layer 30 and a second pixel definition layer 40 with two stacked layers of different materials. At least one partition JK is formed between two adjacent sub-pixels 00. Along the direction Z perpendicular to the plane of the substrate 10, the partition JK includes a first sub-partition JK1 penetrating the second pixel definition layer 40 and a second sub-partition JK2 penetrating at least a portion of the first pixel definition layer 30. The second sub-partition JK2 is formed when the first pixel definition layer 30 is patterned. The partition JK1 is formed during the patterning of the second pixel definition layer 40. Ultimately, the first sub-partition JK1 and the second sub-partition JK2 are connected. This is achieved by creating the second sub-partition JK2 and the first sub-partition JK1 in the first pixel definition layer 30 and the second pixel definition layer 40 respectively. The first sub-partition JK1 and the second sub-partition JK2 are connected in the direction Z perpendicular to the plane of the substrate 10, forming a partition opening JK. The partition opening JK is located between two adjacent sub-pixels 00, which is also between two adjacent second openings 40K1. The formed partition opening JK is shaped as follows: at the junction of the first sub-partition JK1 and the second sub-partition JK2 (at the position marked by the dashed circle in Figure 4), it points from one sub-pixel 00 to the adjacent sub-pixel 00. The second sub-partition JK2 protrudes towards the sub-pixel 00 relative to the first sub-partition JK1. Therefore, at the position marked by the dashed circle J1, one side of the second sub-partition JK2 can be formed as a single-sided undercut structure. When the various layers of the light-emitting layer 50 are subsequently deposited, the organic light-emitting material can be positioned in the first opening 30K1 and the second opening 40K1 to form the light-emitting layer 50 corresponding to the anode 20 of the sub-pixel 00. Moreover, due to the single-sided undercut structure of the second sub-segment JK2 formed at position J1, the common layer of the light-emitting layer 50 can be effectively isolated at position J1 (as shown in Figure 23), which is equivalent to the leakage current path being isolated. This can effectively improve the color crosstalk between adjacent sub-pixels. The cathode layer 60 can also be isolated at the isolation opening JK in this form (as shown in Figure 24). Especially when the display panel 000 performs low grayscale display, it can avoid color crosstalk between adjacent sub-pixels, improve electrical light leakage, and at the same time, it does not affect the normal light emission of the pixel, ensuring the low grayscale display effect and also improving the touch performance.

[0144] It is understood that the manufacturing method of this embodiment may also include manufacturing other film layer structures of the display panel 000, such as thin film encapsulation layer 80, touch layer 90, color filter layer 100, etc. This embodiment will not elaborate on these details, but you can refer to the manufacturing process of OLED display panels in related technologies for a better understanding.

[0145] Optionally, in this embodiment, when fabricating the cathode layer 60, due to the presence of the partition JK, along the direction from one sub-pixel 00 to another adjacent sub-pixel 00, that is, along the direction X from the first sub-pixel 00A to the second sub-pixel 00B, the cathode layer 60 includes only one slit 60K within the partition JK. This can more effectively ensure that the cathode layer 60 material does not remain at the partition JK, thereby improving touch sensitivity.

[0146] Optionally, in this embodiment, the first pixel definition layer 30 and the second pixel definition layer 40 are different film layers. The materials used to fabricate the first pixel definition layer 30 and the second pixel definition layer 40 can be different. The first pixel definition layer 30 includes a negative material, and the second pixel definition layer 40 includes a positive material. The transmittance of the first pixel definition layer 30 is less than that of the second pixel definition layer 40. Under the same etching conditions, the etching rate of the first pixel definition layer 30 is greater than that of the second pixel definition layer 40. Because the two are stacked and made of different materials, it is easier and faster to form a single-sided undercut structure of the second sub-partition JK2 at the junction of the first sub-partition JK1 and the second sub-partition JK2 during the manufacturing process. This makes it possible to form the partition opening JK shown in Figures 2 and 4. Thus, in this embodiment, at least the common layer in the light-emitting layer 50 can be effectively isolated at the partition opening JK, that is, the partition opening JK setting shown in Figures 2 and 4 can ensure the isolation of lateral leakage current, which is beneficial to simplify the manufacturing process, improve the manufacturing efficiency, and also improve the color deviation problem and improve the display quality.

[0147] In some optional embodiments, please refer to Figures 1-5 and 25, which are another flowchart of a method for manufacturing a display panel according to an embodiment of this disclosure. This embodiment provides a method for manufacturing a display panel, which is used to manufacture the display panel 000 in any of the above embodiments. The manufacturing method of this embodiment includes:

[0148] S20: Provides substrate 10;

[0149] S21: Fabricate multiple anodes 20, each anode 20 corresponding to a sub-pixel 00; optionally, fabricating anodes 20 can also complete the fabrication of the driving array layer 70, as shown in Figure 19;

[0150] S22: Fabricate a first pixel definition layer 30, pattern the first pixel definition layer 30 to form multiple first openings 30K1 and multiple third openings 30K2. The third openings 30K2 are located between two adjacent first openings 30K1 and penetrate the thickness of the first pixel definition layer 30. The first openings 30K1 expose a portion of the anode 20, as shown in Figure 20; or the third openings 30K2 penetrate a portion of the thickness of the first pixel definition layer 30, as shown in Figure 26. Figure 26 is a schematic diagram of the structure after the patterned first pixel definition layer is completed in the fabrication method of Figure 25. Optionally, the third openings 30K2 and the first openings 30K1 can be completed in one patterning process, or they can be completed by two patterning processes respectively. This embodiment does not limit this.

[0151] S23: Fabricate a second pixel definition layer 40, pattern the second pixel definition layer 40 to form a plurality of second openings 40K1, the orthographic projection of the second opening 40K1 on the substrate 10 at least partially overlaps with the orthographic projection of the first opening 30K1 on the substrate 10; at least a portion of the second pixel definition layer 40 fills the third opening 30K2, as shown in Figures 21 and 27. Figure 27 is a schematic diagram of the structure after the second opening of the second pixel definition layer is completed in the fabrication method of Figure 25. In this process, the size of the first opening 30K1 can be slightly smaller than the size of the second opening 40K1, that is, the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 on the substrate 10 is located within the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 on the substrate 10, so that the first opening 30K1 and the second opening 40K1 overlap to form at least a portion of the accommodating space of the light-emitting layer 50, and the first opening 30K1 and the second opening 40K1 overlap to form the light-emitting area of ​​the sub-pixel 00. The size of the first opening 30K1 can also be slightly larger than the size of the second opening 40K1. That is, the orthographic projection of the second opening 40K1 of the second pixel definition layer 40 onto the substrate 10 is located within the orthographic projection of the first opening 30K1 of the first pixel definition layer 30 onto the substrate 10. In this way, after the first pixel definition layer 30 is patterned, when the second pixel definition layer 40 is fabricated, the second pixel definition layer 40 can cover the first pixel definition layer 30 at the first opening 30K1, avoiding the possibility of foreign matter residue at the first opening 30K1 affecting the evaporation of the light-emitting layer 50.

[0152] S24: Create a partition JK. The partition JK is located between two adjacent sub-pixels 00 and in the direction Z perpendicular to the plane of the substrate 10. The partition JK includes a first sub-partition JK1 that penetrates the second pixel definition layer 40 and a second sub-partition JK2 that penetrates at least part of the first pixel definition layer 30. The first sub-partition JK1 and the second sub-partition JK2 are connected to form the partition JK. In the partition JK formed in this step, at the junction of the first sub-partition JK1 and the second sub-partition JK2, in the direction from one sub-pixel 00 to another sub-pixel 00 adjacent to it, such as in the direction X from the first sub-pixel 00A to the second sub-pixel 00B, the second sub-partition JK2 protrudes towards the first sub-pixel 00A relative to the first sub-partition JK1.

[0153] S241: Fabricating the partition JK includes providing a mask L1 (not filled in the figure), the opening L1K of the mask L1 is located between two adjacent sub-pixels 00; etching the second pixel definition layer 40 and the first pixel definition layer 30 at the same etching rate; wherein, in the direction Z perpendicular to the plane where the substrate 10 is located, one side of the opening L1K of the mask L1 is located inside the third opening 30K2, and the other side of the opening L1K of the mask L1 is located outside the third opening 30K2;

[0154] A first sub-segment JK1 is formed between two adjacent sub-pixels 00 of the second pixel definition layer 40, and a second sub-segment JK2 is formed between two adjacent sub-pixels 00 of the first pixel definition layer 30. The first sub-segment JK1 and the second sub-segment JK2 are connected in the direction Z perpendicular to the plane of the substrate 10.

[0155] The second sub-partition JK2 exposes the first surface 40A of the second pixel definition layer 40, where the first surface 40A refers to the surface of the second pixel definition layer 40 facing the first pixel definition layer 30; as shown in Figures 28 and 29, Figure 28 is a schematic diagram of the position of a mask when making the partition opening in the manufacturing method of Figure 25, and Figure 29 is a schematic diagram of the position of another mask when making the partition opening in the manufacturing method of Figure 25.

[0156] S25: Fabricate a light-emitting layer 50, at least a portion of which is located within a first opening 30K1 on the side of the second pixel definition layer 40 away from the substrate 10; the light-emitting layer 50 includes a common layer, which is isolated at the partition opening JK; as shown in Figure 3, the common layer may be one or more of the hole injection layer 501, hole transport layer 502, hole blocking layer 504, electron transport layer 505, and electron injection layer 506; as shown in Figure 5, the common layer may be one or more of the hole injection layer 5011, hole transport layer 5012, charge generation layer 5014, hole blocking layer 5016, electron transport layer 5017, and electron injection layer 5018; as shown in Figures 23 and 30, Figure 30 is a schematic diagram of the structure after the light-emitting layer is completed in the fabrication method of Figure 25;

[0157] S26: Fabricate cathode layer 60. Cathode layer 60 is separated at partition JK, as shown in Figures 24 and 31. Figure 31 is a schematic diagram of the structure after the cathode layer is completed in the fabrication method of Figure 25.

[0158] This embodiment explains that when patterning the first pixel definition layer 30, a third opening 30K2 can be formed between two adjacent first openings 30K1. The third opening 30K2 can penetrate the thickness of the first pixel definition layer 30 (as shown in Figure 20), or it can only penetrate a portion of the thickness of the first pixel definition layer 30 (as shown in Figure 26). The setting of the third opening 30K2 in the first pixel definition layer 30 allows the second pixel definition layer 40 to fill the third opening 30K2 and cover one side of the first pixel definition layer 30 after the second pixel definition layer 40 is coated (as shown in Figures 21 and 27, the second pixel definition layer 40 can fill the third opening 30K2 and cover one side of the first pixel definition layer 30). Therefore, after both the first pixel definition layer 30 and the second pixel definition layer 40 are fabricated, when fabricating the partition JK, it is equivalent to the third... The first pixel definition layer 30 on one side of the opening 30K2 is protected so that the second sub-block JK2 undercut structure can be formed only on the side close to the first sub-pixel 00A (as shown in Figures 28 and 29). When making the block opening JK, a mask L1 is used. The opening L1K of the mask L1 is located between two adjacent sub-pixels 00. The second pixel definition layer 40 and the first pixel definition layer 30 are etched at the same etching rate. In the direction Z perpendicular to the plane where the substrate 10 is located, one side of the opening L1K of the mask L1 is located inside the third opening 30K2, and the other side of the opening L1K of the mask L1 is located outside the third opening 30K2. Since the materials used to make the first pixel definition layer 30 and the second pixel definition layer 40 can be different, under the same etching conditions, the etching rate of the first pixel definition layer 30 is greater than the etching rate of the second pixel definition layer 40. The etching rate of the first pixel definition layer 30 with low light transmittance can be about three times that of the second pixel definition layer 40 with high light transmittance. If the first pixel definition layer 30 is a negative material and the second pixel definition layer 40 is a positive material, when the same mask L1 is used to fabricate the partition opening JK, the exposure position of the mask L1 opening L1K of the second pixel definition layer 40 with positive material will be removed, and the mask L1 blocking position will remain; the exposure position of the mask L1 opening L1K of the first pixel definition layer 30 with negative material will remain, and the mask L1 blocking position will be removed. This allows the partition opening JK to form a single-sided undercut structure on only one side of the second sub-partition JK2 at the junction of the first sub-partition JK1 and the second sub-partition JK2. The manufacturing process of the first pixel definition layer 30 and the partition JK in this embodiment makes it possible to achieve the shape of the partition JK required in this embodiment during the manufacturing process, ensuring that the common layer of the light-emitting layer 50 can be effectively isolated, the cathode layer 50 can also be effectively isolated, and there will be no cathode layer material residue, which effectively improves the color crosstalk between adjacent sub-pixels and improves touch performance.

[0159] It is understandable that, since the materials of the first pixel definition layer 30 and the second pixel definition layer 40 are different in this embodiment, the first pixel definition layer 30 can be a negative material, while the second pixel definition layer can be a positive material. Therefore, after the first pixel definition layer 30 is coated, a patterning process is performed to form the first opening 30K1 and the third opening 30K2 of the first pixel definition layer 30. Then, the second pixel definition layer 40 is coated, and the second opening 40K1 is formed. Finally, a mask L1 is used to form a partition JK, including the first sub-partition JK1 and the second sub-partition JK2, between adjacent sub-pixels 00.

[0160] In some optional embodiments, please refer to FIG32, which is a schematic planar structure diagram of a display device provided in an embodiment of the present disclosure. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiments of the present application. FIG32 only uses a mobile phone as an example to illustrate the display device 111. It can be understood that the display device 111 provided in the embodiments of the present disclosure can be other display devices 111 with display functions, such as computers, televisions, and vehicle display devices. This application does not make specific limitations in this regard. The display device 111 provided in the embodiments of the present disclosure has the beneficial effects of the display panel 000 provided in the embodiments of the present disclosure. For details, please refer to the specific description of the display panel 000 in the above embodiments. This embodiment will not repeat it here.

[0161] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0162] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, the display panel comprising a plurality of sub-pixels, the sub-pixels comprising an anode; The display panel also includes: A substrate, wherein the anode is located on one side of the substrate; A first pixel definition layer is located on the side of the anode away from the substrate. The first pixel definition layer includes a plurality of first openings, the first openings exposing a portion of the anode. A second pixel definition layer is located on the side of the first pixel definition layer away from the substrate. The second pixel definition layer includes a plurality of second openings, and the orthographic projection of the second openings on the substrate at least partially overlaps with the orthographic projection of the first openings on the substrate. A light-emitting layer, at least a portion of which is located within the first opening; A cathode layer, the cathode layer being located on the side of the light-emitting layer away from the substrate; Between two adjacent sub-pixels, the display panel includes at least one partition opening along a direction perpendicular to the plane of the substrate. The partition opening includes a first sub-partition penetrating the second pixel definition layer and a second sub-partition penetrating at least a portion of the first pixel definition layer. The first sub-partition and the second sub-partition are connected. At the junction of the first sub-division and the second sub-division, along the direction from one of the sub-pixels to the adjacent sub-pixel, the second sub-division protrudes towards the sub-pixel relative to the first sub-division.

2. The display panel according to claim 1, wherein, The sub-pixel includes an adjacent first sub-pixel and a second sub-pixel, and the second sub-division includes a first end and a second end opposite to each other, with the first end located between the second end and the first sub-pixel; At the junction of the first sub-partition and the second sub-partition, the first end of the second sub-partition protrudes toward the first sub-pixel relative to the first sub-partition.

3. The display panel according to claim 2, wherein, The second pixel definition layer includes a first surface that contacts the first pixel definition layer; Along the direction from the first sub-pixel to the second sub-pixel, at the first end, the second sub-partition exposes a portion of the first surface; At the second end, the first surface of the second pixel definition layer is not exposed within the partition.

4. The display panel according to claim 1, wherein, Within the partition, the cathode layer comprises only one slit along the direction from one of the sub-pixels to its adjacent sub-pixel.

5. The display panel according to claim 4, wherein, The cathode layer, except for the slit, has a continuous structure.

6. The display panel according to claim 1, wherein, The display panel further includes a color filter layer, which is located on the side of the cathode layer away from the substrate; The color filter layer includes a black matrix and color resist disposed between the black matrix; In a direction perpendicular to the plane of the substrate, the color resist corresponds to the light-emitting layer.

7. The display panel according to claim 6, wherein, The transmittance of the first pixel definition layer is less than that of the second pixel definition layer.

8. The display panel according to claim 7, wherein, The first pixel definition layer includes black material.

9. The display panel according to claim 1, wherein, The display panel further includes a touch layer located on the side of the cathode layer away from the substrate; The touch layer includes touch electrodes, which are mesh structures surrounding the light-emitting layer. The orthographic projection of the touch electrodes onto the substrate is located between two adjacent sub-pixels.

10. The display panel according to claim 1, wherein, The orthographic projection of the first opening onto the substrate lies within the orthographic projection of the second opening onto the substrate.

11. The display panel according to claim 1, wherein, The second opening is projected onto the substrate in the same direction as the first opening in the same direction as the substrate. At the first opening, the second pixel definition layer covers the first pixel definition layer.

12. The display panel according to claim 1, wherein, In a direction perpendicular to the plane of the substrate, the second sub-partition penetrates a portion of the thickness of the first pixel definition layer, and the first sub-partition penetrates the thickness of the second pixel definition layer.

13. The display panel according to claim 1, wherein, In a direction perpendicular to the plane of the substrate, the second sub-partition penetrates the thickness of the first pixel definition layer, and the first sub-partition penetrates the thickness of the second pixel definition layer.

14. The display panel according to claim 1, wherein, The first pixel definition layer also includes a plurality of third openings, the third openings being located between two adjacent first openings and penetrating the first pixel definition layer; In a direction perpendicular to the plane of the substrate, the partition opening at least partially overlaps with the third opening, and at least a portion of the second pixel definition layer fills the third opening.

15. The display panel according to claim 14, wherein, In a direction perpendicular to the plane of the substrate, the third opening penetrates the thickness of the first pixel definition layer; The display panel further includes a photosensitive element, which at least partially overlaps with the third opening in a direction perpendicular to the plane of the substrate.

16. The display panel according to claim 1, wherein, The light-emitting layer includes a hole injection layer, a hole transport layer, an organic light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer stacked along a direction perpendicular to the plane of the substrate. The light-emitting layer includes a common layer; the common layer includes one or more of the hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, and the electron injection layer.

17. The display panel according to claim 1, wherein, The light-emitting layer includes a hole injection layer, a hole transport layer, a first organic light-emitting layer, a charge generation layer, a second organic light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer, which are stacked along a direction perpendicular to the plane of the substrate. The light-emitting layer includes a common layer; The common layer includes one or more of the hole injection layer, the hole transport layer, the charge generation layer, the hole blocking layer, the electron transport layer, and the electron injection layer.

18. The display panel according to claim 1, wherein, Under the same etching conditions, the etching rate of the first pixel definition layer is greater than that of the second pixel definition layer.

19. The display panel according to claim 18, wherein, The first pixel definition layer is made of negative material, and the second pixel definition layer is made of positive material.

20. The display panel according to claim 1, wherein, The width of the gap ranges from 2 to 8 μm along the direction from one of the sub-pixels to another adjacent sub-pixel.

21. A method for manufacturing a display panel, comprising: Provide substrate; Multiple anodes are fabricated, each anode corresponding to a sub-pixel; A first pixel definition layer is created, the first pixel definition layer is patterned, and a plurality of first openings are formed, the first openings exposing a portion of the anode; A second pixel definition layer is fabricated, the second pixel definition layer is patterned, and a plurality of second openings are formed, wherein the orthographic projection of the second opening on the substrate at least partially overlaps with the orthographic projection of the first opening on the substrate; A partition is fabricated, the partition being located between two adjacent sub-pixels, and in a direction perpendicular to the plane of the substrate, the partition includes a first sub-partition penetrating the second pixel definition layer and a second sub-partition penetrating at least a portion of the first pixel definition layer, the first sub-partition and the second sub-partition communicating to form the partition. At the junction of the first sub-partition and the second sub-partition, along the direction from one of the sub-pixels to the other adjacent sub-pixel, the second sub-partition protrudes towards the sub-pixel relative to the first sub-partition; A light-emitting layer is fabricated, at least a portion of which is located within a first opening on the side of the second pixel definition layer away from the substrate; the light-emitting layer includes a common layer that is interrupted at the partition opening; A cathode layer is fabricated, wherein the cathode layer is isolated at the partition opening.

22. The method for manufacturing a display panel according to claim 21, wherein, Within the partition, the cathode layer comprises only one slit along the direction from one of the sub-pixels to its adjacent sub-pixel.

23. The method for manufacturing a display panel according to claim 21, wherein, The first pixel definition layer includes a negative material, the second pixel definition layer includes a positive material, and the transmittance of the first pixel definition layer is less than that of the second pixel definition layer. Under the same etching conditions, the etching rate of the first pixel definition layer is greater than that of the second pixel definition layer.

24. The method for manufacturing a display panel according to claim 23, wherein, Creating the first pixel definition layer, patterning the first pixel definition layer, also includes: A third opening is formed, which is located between two adjacent first openings, and the third opening at least partially penetrates the thickness of the first pixel definition layer.

25. The method for manufacturing a display panel according to claim 24, wherein, Creating a second pixel definition layer and patterning the second pixel definition layer further includes: at least a portion of the second pixel definition layer filling the third opening; The construction of the partition includes: A mask is provided, the opening of the mask being located between two adjacent sub-pixels; the second pixel definition layer and the first pixel definition layer are etched at the same etching rate; wherein, in a direction perpendicular to the plane of the substrate, one side of the opening of the mask is located inside the third opening, and the other side of the opening of the mask is located outside the third opening; A first sub-separation is formed between two adjacent sub-pixels of the second pixel definition layer, and a second sub-separation is formed between two adjacent sub-pixels of the first pixel definition layer. The first sub-separation and the second sub-separation are connected in a direction perpendicular to the plane of the substrate. The second sub-partition exposes a portion of the first surface of the second pixel definition layer, wherein the first surface refers to the surface of the second pixel definition layer facing the first pixel definition layer.

26. A display device comprising the display panel according to any one of claims 1-20.

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