Overcurrent protection circuit for power transistor

Abstract

Disclosed in the present invention is an overcurrent protection circuit for a power transistor. The overcurrent protection circuit comprises: a reference voltage terminal, a first comparator, a single-edge delay circuit, a deglitch delay circuit and a logic circuit, wherein the deglitch delay circuit comprises an external capacitor disposed between the reference voltage terminal and a reference ground; and the deglitch delay circuit is used for charging the external capacitor on the basis of a delay control signal, and generating a valid second indication signal when the capacitor voltage of the external capacitor rises to a reference voltage threshold value, so as to control a deglitch delay time of the circuit. In the overcurrent protection circuit of the present embodiment, a user may set different deglitch delay times in the circuit by means of the capacitance value of an external capacitor disposed outside a chip, such that the circuit can be adjusted for application scenarios of different power devices, thereby facilitating an improvement in the stability and reliability of the circuit.

Description

Overcurrent protection circuit for power transistors Cross-reference to related applications

[0001] This application claims priority to Chinese Patent Application No. 202411996976.9, filed on December 31, 2024, entitled "Overcurrent Protection Circuit for Power Transistor", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of power supply technology, and more specifically, to an overcurrent protection circuit for a power transistor. Background Technology

[0003] A major application of power transistors such as IGBTs (Insulated Gate Bipolar Transistors) and SiCs (Silicon Carbide) is as switching devices for turning loads on and off. However, because power transistors are relatively fragile, they are prone to burning out in many applications due to excessive current and rapid heating caused by internal short circuits or other abnormal conditions within the load. For example, when a power transistor is short-circuited to ground or the power supply, the current can increase to 30A within 100ns. Therefore, protecting power transistors is of paramount importance.

[0004] Figure 1 shows a prior art overcurrent protection circuit for a power transistor. Prior art overcurrent protection circuits require a long deglitch time to avoid false triggering during load transients. This circuit includes a comparator 110 and a delay circuit 120. The comparator 110 compares a sampled voltage Vsen, representing the drain-source voltage difference of the power transistor, with a reference voltage Vref to generate an indication signal SC for the delay circuit 120. When an overcurrent event occurs in the power transistor, the sampled voltage Vsen rises. When the sampled voltage Vsen is greater than the reference voltage Vref, the comparator 110 outputs a high-level indication signal SC. Since the sampled voltage Vsen may also be greater than the reference voltage Vref during load transients, to avoid false triggering, the delay circuit 120 only triggers the overcurrent protection signal Fault to shut down the power transistor after the sampled voltage Vsen has been continuously greater than the reference voltage Vref for a certain period.

[0005] Currently, there are many types of power devices on the market, and different power devices have different requirements for the anti-spiking pulse delay time. However, the anti-spiking pulse delay time of the existing overcurrent protection circuit is fixed and cannot be adjusted according to the specific application scenario. This may lead to the protection response being too sensitive or too sluggish in some cases, affecting the stability and reliability of the system. Summary of the Invention

[0006] In view of the above problems, the purpose of this invention is to provide an overcurrent protection circuit for power transistors, which can set different anti-spiking pulse delay times in the circuit by using an external capacitor, thereby improving the stability and reliability of the circuit.

[0007] According to one aspect of the present invention, an overcurrent protection circuit for a power transistor is provided, comprising: a reference voltage terminal for receiving a reference threshold voltage; a first comparator for comparing a sampled voltage representing the drain-source voltage difference of the power transistor with the reference threshold voltage, and generating a valid first indication signal when the sampled voltage is greater than the reference threshold voltage; a single-edge delay circuit for delaying the valid edge of the first indication signal by a set time to generate a delay control signal; an anti-spike delay circuit including an external capacitor disposed between the reference voltage terminal and a reference ground, the anti-spike delay circuit being used to charge the external capacitor according to the delay control signal, and generating a valid second indication signal when the capacitor voltage of the external capacitor rises to the reference voltage threshold; and a logic circuit for generating an overcurrent protection signal when both the delay control signal and the second indication signal are valid.

[0008] Optionally, the positive input terminal of the first comparator is used to receive the sampled voltage, the negative input terminal is used to connect to the reference voltage terminal, and the output terminal is used to provide the first indication signal. The overcurrent protection circuit further includes: a first switch, which is used to disconnect the signal path between the negative input terminal of the first comparator and the reference voltage terminal when the delay control signal is valid; and a holding capacitor, which is connected between the negative input terminal of the first comparator and the reference ground.

[0009] Optionally, the anti-spiking pulse delay circuit further includes: a single-pulse module for generating a single-pulse signal with a set pulse width according to the delay control signal; a discharge transistor, the first terminal of which is connected to the first terminal of the external capacitor and the reference voltage terminal, the second terminal of which is connected to a reference ground, and the control terminal of which is used to receive the single-pulse signal; and a current source, the first terminal of which is connected to the on-chip power supply voltage, and the second terminal of which is connected to the reference voltage terminal, wherein the discharge transistor is used to discharge the charge of the external capacitor to the reference ground during the effective level time of the single-pulse signal, and the current source is used to charge the external capacitor after the effective level time of the single-pulse signal ends.

[0010] Optionally, the anti-spiking pulse delay circuit further includes: a second switch connected between the second terminal of the current source and the reference voltage terminal; and a switch control module, the switch control module being used to turn on the second switch when the invalid edge of the single pulse signal arrives.

[0011] Optionally, the anti-spiking pulse delay circuit further includes: a second comparator, the positive input terminal of the second comparator being used to receive the capacitor voltage of the external capacitor, the negative input terminal of the second comparator being connected to the holding capacitor to receive the reference threshold voltage, and the output terminal of the second comparator being used to provide the second indication signal.

[0012] Optionally, the logic circuit is implemented using an AND gate.

[0013] Optionally, the anti-spiking delay time of the overcurrent protection circuit can be set by adjusting the voltage value of the reference threshold voltage, the capacitance value of the external capacitor, and / or the output current of the current source.

[0014] Optionally, the overcurrent protection circuit further includes: a reference threshold circuit connected to the reference voltage terminal for providing the reference threshold voltage, wherein the reference threshold circuit includes: a first resistor and a second resistor connected in series between the external power supply voltage and the reference ground; and a third resistor, wherein a first end of the third resistor is connected to the intermediate node between the first resistor and the second resistor, and a second end of the third resistor is connected to the reference voltage terminal.

[0015] Optionally, the overcurrent protection circuit is a monolithic integrated circuit, and the reference threshold circuit and the external capacitor are external devices.

[0016] In summary, the overcurrent protection circuit for a power transistor according to this embodiment of the invention includes: a reference voltage terminal, a first comparator, a single-sided delay circuit, an anti-spiking delay circuit, and a logic circuit. The first comparator compares the sampled voltage of the power transistor with a reference threshold voltage to generate a first indication signal. The single-sided delay circuit generates a delay control signal based on the first indication signal. The anti-spiking delay circuit includes an external capacitor disposed between the reference voltage terminal and a reference ground. The anti-spiking delay circuit charges the external capacitor according to the delay control signal and generates a valid second indication signal when the capacitor voltage rises to the reference voltage threshold. The logic circuit then determines whether an overcurrent event has occurred in the power transistor based on the delay control signal and the second indication signal. In this overcurrent protection circuit, the user can set different anti-spiking delay times in the circuit by setting the external capacitor value outside the chip, thereby adjusting the circuit for different power device application scenarios, which helps improve the stability and reliability of the circuit. Attached Figure Description

[0017] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0018] Figure 1 shows an existing overcurrent protection circuit for a power transistor.

[0019] Figure 2 shows an overcurrent protection circuit for a power transistor according to an embodiment of the present invention.

[0020] Figure 3 is a waveform diagram of the overcurrent protection circuit in an embodiment of the present invention. Detailed Implementation

[0021] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0022] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "coupled" to another element or "coupled" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.

[0023] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0025] Figure 2 illustrates an overcurrent protection circuit 200 for a power transistor according to an embodiment of the present invention. The overcurrent protection circuit 200 is, for example, a monolithic integrated circuit. The portion to the left of the dashed line represents the exterior of the monolithic integrated circuit, and the portion to the right of the dashed line represents the interior of the monolithic integrated circuit. As shown in Figure 2, the overcurrent protection circuit 200 of this embodiment includes a reference threshold circuit 210 located outside the chip, a comparator 220, a switch S1, a single-sided delay circuit 230, an anti-spiking delay circuit 240, and a logic circuit 250 located inside the chip.

[0026] The reference threshold circuit 210 generates a reference threshold voltage Vref representing an overcurrent detection threshold. Further, the reference threshold circuit 210 includes resistors R1 to R3, where resistors R1 and R2 are connected in series between the external power supply voltage VDDIO and a reference ground. The first end of resistor R3 is connected to the midpoint between resistors R1 and R2, and the second end of resistor R3 is connected to the reference voltage terminal 201 of the overcurrent protection chip to supply the reference threshold voltage Vref to the reference voltage terminal 201. Furthermore, in practical applications, those skilled in the art can adjust the voltage division ratio of resistors R1 to R3 as needed to adjust the voltage value of the reference threshold voltage Vref. For example, the external power supply voltage VDDIO is provided, for instance, as an input / output power supply voltage, which refers to the voltage level used when the chip interacts with external devices, and it directly affects the chip's performance and stability.

[0027] Comparator 220 compares a sampled voltage Vsen, representing the drain-source voltage difference of the power transistor, with a reference threshold voltage Vref, and generates a valid (e.g., high-level) first indication signal SC if the sampled voltage Vsen is greater than the reference threshold voltage Vref. For example, comparator 220 has a positive input, a negative input, and an output. Its positive input is connected to the sampled voltage Vsen, its negative input is connected to the reference voltage terminal 201 via switch S1, and its output provides the first indication signal SC.

[0028] A single-sided delay circuit 230 is used to delay the rising edge of the first indication signal SC by a set time. If the effective level (e.g., high level) of the first indication signal SC still exists after the set time, the single-sided delay circuit 230 generates an effective (e.g., high level) delay control signal CTL. In one embodiment, the single-sided delay circuit 230 is used to change the delay control signal CTL to a high level when the effective level time of the first indication signal SC reaches 1µs. For example, the delay control signal CTL is used to control the on and off of the switch S1, which is configured to turn off when the delay control signal CTL becomes high, thereby disconnecting the signal path between the negative input terminal of the comparator 220 and the reference voltage terminal 201. Furthermore, the overcurrent protection circuit 200 of this embodiment also includes a holding capacitor C1 connected between the negative input terminal of the comparator 220 and the reference ground, for maintaining the voltage at the negative input terminal of the comparator 220 at the reference threshold voltage Vref after the switch S1 is turned off.

[0029] The anti-spiking delay circuit 240 includes an external capacitor Cdeg disposed between the reference voltage terminal 201 and the reference ground. The anti-spiking delay circuit 240 is used to charge the external capacitor Cdeg according to the delay control signal CTL, and generate a valid (e.g., high level) second indication signal SCP when the capacitor voltage Vcap on the external capacitor Cdeg rises to the reference threshold voltage Vref.

[0030] Specifically, the anti-spiking pulse delay circuit 240 of this embodiment further includes: a single-pulse module 241, a switch control module 242, a discharge transistor M1, a current source Iset, a switch S2, and a comparator 243. The single-pulse module 241 generates a single-pulse signal Pulse with a set pulse width according to the delay control signal CTL. For example, the pulse width of the single-pulse signal Pulse can be equal to 100ns. The discharge transistor M1 can be implemented using an NMOS transistor, with its drain connected to the first terminal of the external capacitor Cdeg and the reference voltage terminal 201, its source connected to reference ground, and its gate used to receive the single-pulse signal Pulse. The first terminal of the current source Iset is connected to the on-chip power supply voltage VDD, and the second terminal of the current source Iset is connected to the reference voltage terminal 201 via the switch S2. The discharge transistor M1 is used to turn on during the effective level (e.g., high level) of the single pulse signal Pulse to discharge the charge on the external capacitor Cdeg to the reference ground, and the switch S2 is used to turn on after the effective level of the single pulse signal Pulse ends to control the current source Iset to charge the external capacitor Cdeg.

[0031] In one embodiment, the switch control module 242 is configured to receive the single-pulse signal Pulse and turn on the switch S2 when an invalid edge (e.g., a falling edge) of the single-pulse signal Pulse arrives.

[0032] In this embodiment, the positive input terminal of the comparator 243 is connected to the reference voltage terminal 201 to receive the capacitor voltage Vcap, and the negative input terminal of the comparator 243 is connected to the holding capacitor C1 to receive the reference threshold voltage Vref stored therein. The comparator 243 is used to compare the capacitor voltage Vcap with the reference threshold voltage Vref to provide the second indication signal SCP at the output terminal.

[0033] Logic circuit 250 is used to receive the delay control signal CTL and the second indication signal SCP. It is used to generate a valid (e.g., high-level) overcurrent protection signal Fault when both the delay control signal CTL and the second indication signal SCP are valid. For example, the logic circuit 250 can be implemented using an AND gate circuit, which detects the delay control signal CTL when the second indication signal SCP changes from low to high. If the delay control signal CTL remains high, the overcurrent protection signal Fault is set to high; otherwise, the overcurrent protection signal Fault is set to low.

[0034] Figure 3 shows the operating waveforms of the overcurrent protection circuit according to an embodiment of the present invention. Figure 3 illustrates the waveforms of the voltage Vcap on the external capacitor Cdeg, the sampling voltage Vsen, the delay control signal CTL, the single-pulse signal Pulse, the second indicator signal SCP, and the overcurrent protection signal Fault. As shown in Figure 3, in the initial state, the voltage Vcap on the external capacitor Cdeg is equal to the reference threshold voltage Vref. At time t1, the sampling voltage Vsen is greater than the reference threshold voltage Vref, and comparator 220 outputs a high-level first indicator signal SC. At time t2, after the duration of the sampling voltage Vsen being greater than the reference threshold voltage Vref reaches T1, the delay control signal CTL becomes high, switch S1 is turned off, and the voltage at the negative input terminal of comparator 220 is maintained at the reference threshold voltage Vref by holding capacitor C1. Simultaneously, the single-pulse module 241 generates a single-pulse signal Pulse with a pulse width of T2 based on the rising edge of the delay control signal CTL. The single-pulse signal Pulse turns on the discharge transistor M1, pulling the voltage on the external capacitor Cdeg down to 0V. At time t3, when the falling edge of the single-pulse signal Pulse arrives, the switch control module 242 turns on switch S2, charging the external capacitor Cdeg through the current source Iset, and the voltage Vcap on the external capacitor Cdeg gradually rises. At time t4, when the voltage Vcap on the external capacitor Cdeg rises to the reference threshold voltage Vref, the second indicator signal SCP output by comparator 243 goes high. If the sampled voltage Vsen is still greater than the reference threshold voltage Vref at this time (i.e., the delay control signal CTL remains high), then the AND gate circuit 250 turns the overcurrent fault signal Fault high, thereby turning off the external power transistor through the internal control module of the chip to achieve overcurrent protection. If the sampled voltage Vsen is less than the reference threshold voltage Vref before the second indicator signal SCP output by comparator 243 goes high, the delay control signal CTL will immediately change from high to low because the single-sided delay circuit 230 only delays the rising edge of the first indicator signal SC. Therefore, when the second indicator signal SCP goes high, the overcurrent fault signal Fault is still low, which can filter out this part of the spike pulse on the power transistor and prevent the circuit from triggering overcurrent protection.

[0035] As can be seen from Figure 3, the overcurrent protection circuit 200 of this embodiment has a spike pulse delay time. Wherein, time T1 is the delay time set in the single-sided delay circuit 230 (e.g., 1µs), and time T2 is the pulse width of the single-pulse signal Pulse (e.g., 100ns). Where Cdeg is the capacitance of the external capacitor, Vref is the reference threshold voltage, and Iset is the output current of the current source. Therefore, those skilled in the art can adjust the anti-spiking delay time of the overcurrent protection circuit by adjusting the reference threshold voltage, the capacitance of the external capacitor, and / or the output current of the current source in practical applications. In some embodiments, the output current of the current source Iset and the reference threshold voltage are generally fixed after chip fabrication. Those skilled in the art can adjust the anti-spiking delay time of the circuit by adjusting the capacitance of the external capacitor, thereby improving the stability and reliability of the system in different power device application scenarios.

[0036] In summary, the overcurrent protection circuit for a power transistor according to this embodiment of the invention includes: a reference voltage terminal, a first comparator, a single-sided delay circuit, an anti-spiking delay circuit, and a logic circuit. The first comparator compares the sampled voltage of the power transistor with a reference threshold voltage to generate a first indication signal. The single-sided delay circuit generates a delay control signal based on the first indication signal. The anti-spiking delay circuit includes an external capacitor disposed between the reference voltage terminal and a reference ground. The anti-spiking delay circuit charges the external capacitor according to the delay control signal and generates a valid second indication signal when the capacitor voltage rises to the reference voltage threshold. The logic circuit then determines whether an overcurrent event has occurred in the power transistor based on the delay control signal and the second indication signal. In this overcurrent protection circuit, the user can set different anti-spiking delay times in the circuit by setting the external capacitor value outside the chip, thereby adjusting the circuit for different power device application scenarios, which helps improve the stability and reliability of the circuit.

[0037] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0038] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. An overcurrent protection circuit for a power transistor, comprising: Reference voltage terminal, used to receive reference threshold voltage; A first comparator is configured to compare a sampled voltage representing the drain-source voltage difference of the power transistor with a reference threshold voltage, and generate a valid first indication signal if the sampled voltage is greater than the reference threshold voltage. A single-sided delay circuit is used to delay the effective edge of the first indication signal by a set time to generate a delay control signal; An anti-spiking delay circuit includes an external capacitor disposed between the reference voltage terminal and the reference ground. The anti-spiking delay circuit is used to charge the external capacitor according to the delay control signal and generate a valid second indication signal when the capacitor voltage of the external capacitor rises to the reference voltage threshold. as well as A logic circuit is used to generate an overcurrent protection signal when both the delay control signal and the second indication signal are valid.

2. The overcurrent protection circuit according to claim 1, wherein, The positive input terminal of the first comparator is used to receive the sampled voltage, the negative input terminal is used to connect to the reference voltage terminal, and the output terminal is used to provide the first indication signal. The overcurrent protection circuit further includes: A first switch, configured to disconnect the signal path between the negative input terminal of the first comparator and the reference voltage terminal when the delay control signal is valid; and A holding capacitor is connected between the negative input of the first comparator and a reference ground.

3. The overcurrent protection circuit according to claim 2, wherein, The anti-spiking pulse delay circuit further includes: A single-pulse module is used to generate a single-pulse signal with a set pulse width based on the delay control signal; A discharge transistor, wherein a first terminal of the discharge transistor is connected to a first terminal of the external capacitor and a reference voltage terminal, a second terminal of the discharge transistor is connected to a reference ground, and a control terminal of the discharge transistor is used to receive the single-pulse signal; and A current source, wherein a first terminal of the current source is connected to the on-chip power supply voltage, and a second terminal of the current source is connected to the reference voltage terminal. The discharge transistor is used to discharge the charge of the external capacitor to the reference ground during the effective level time of the single pulse signal, and the current source is used to charge the external capacitor after the effective level time of the single pulse signal ends.

4. The overcurrent protection circuit according to claim 3, wherein, The anti-spiking pulse delay circuit further includes: A second switch is connected between the second terminal of the current source and the reference voltage terminal; and A switch control module is provided for turning on the second switch when the invalid edge of the single pulse signal arrives.

5. The overcurrent protection circuit according to claim 3, wherein, The anti-spiking pulse delay circuit further includes: The second comparator has a positive input terminal for receiving the capacitance voltage of the external capacitor, a negative input terminal connected to the holding capacitor to receive the reference threshold voltage, and an output terminal for providing the second indication signal.

6. The overcurrent protection circuit according to claim 1, wherein, The logic circuit is implemented using AND gates.

7. The overcurrent protection circuit according to claim 3, wherein, The anti-spiking delay time of the overcurrent protection circuit is set by adjusting the voltage value of the reference threshold voltage, the capacitance value of the external capacitor, and / or the output current of the current source.

8. The overcurrent protection circuit according to claim 1, wherein, Also includes: A reference threshold circuit, connected to the reference voltage terminal, is used to provide the reference threshold voltage. The reference threshold circuit includes: A first resistor and a second resistor connected in series between the external power supply voltage and the reference ground; and The third resistor has its first end connected to the midpoint between the first resistor and the second resistor, and its second end connected to the reference voltage terminal.

9. The overcurrent protection circuit according to claim 8, wherein, The overcurrent protection circuit is a monolithic integrated circuit, and the reference threshold circuit and the external capacitor are external devices.

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