Semiconductor structure and method for forming same

Abstract

Disclosed in embodiments of the present disclosure are a semiconductor structure and a method for forming same. The semiconductor structure comprises: a semiconductor substrate, a stacked structure, and bit line structures. The stacked structure and the bit line structures are located on the semiconductor substrate. The stacked structure comprises: separation layers and composite layers alternately stacked in a vertical direction. The bit line structures extend in the vertical direction and pass through the stacked structure. The semiconductor substrate comprises: an array region and a peripheral region. The stacked structure located in the peripheral region comprises: a capacitor region. A row of bit line structures is formed outside each of two opposite sides of the capacitor region in a first direction. The composite layers in the capacitor region comprise: first electrode plates. The first electrode plates are distributed at intervals on two opposite sides of the composite layers in the capacitor region in the first direction, and protrude outward. Each first plate is connected to a corresponding bit line structure.

Description

A semiconductor structure and its formation method

[0001] This application claims priority to Chinese Patent Application No. 202411979486.8, filed on December 30, 2024, entitled "A Semiconductor Structure and a Method for Forming the Same", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0003] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in electronic devices such as computers. DRAM chips are divided into an array area and a peripheral area. The array area includes an array of memory cells for storing data, while the peripheral area includes peripheral circuitry located around the array of memory cells.

[0004] The capacitors in the peripheral region are commonly referred to as NICAPs. NICAPs require a large capacitance to function as power sources or for signal processing in the peripheral region. However, in existing technologies, NICAPs have relatively complex structures and high manufacturing costs, requiring further optimization. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can save costs and improve performance.

[0006] The technical solution of this disclosure embodiment is implemented as follows:

[0007] This disclosure provides a semiconductor structure comprising: a semiconductor substrate, a stacked structure, and a bit line structure; the stacked structure and the bit line structure are located on the semiconductor substrate; the semiconductor substrate comprises: an array region and a peripheral region; the stacked structure comprises: a separator layer and a composite layer alternately stacked along a vertical direction; the bit line structure extends along the vertical direction and penetrates the stacked structure; the stacked structure located in the peripheral region comprises: a capacitor region; a row of bit line structures is formed on both sides of the capacitor region opposite to each other along a first direction; wherein, the composite layer of the capacitor region comprises: a first electrode plate; the first electrode plates are spaced apart on both sides of the composite layer of the capacitor region opposite to each other along the first direction and protrude outward; each first electrode plate is connected to a corresponding bit line structure.

[0008] In some embodiments of this disclosure, the composite layer of the capacitor region further includes: a dielectric layer and a second electrode plate; the second electrode plate is located inside the composite layer of the capacitor region; the dielectric layer is located between the first electrode plate and the second electrode plate; and the inner side of the second electrode plate is filled with a semiconductor material.

[0009] In some embodiments of this disclosure, the composite layer of the capacitor region further includes: a contact plug; the contact plug is located between the first electrode plate and the bit line structure; each first electrode plate is connected to the corresponding bit line structure through the contact plug.

[0010] In some embodiments of this disclosure, the stacked structure located in the array region includes: a storage cell region; an array of storage cells arranged in the storage cell region; a bit line structure formed between two storage cells opposite each other along the first direction; two storage cells connected to a corresponding bit line structure; and both the capacitor region and the storage cell region are formed based on a first photomask.

[0011] In some embodiments of this disclosure, the semiconductor structure further includes: a back-end connection structure; the back-end connection structure extends along the vertical direction; the back-end connection structure is located above the capacitor region and above the bit line structure.

[0012] This disclosure also provides a method for forming a semiconductor structure, the method comprising: providing a semiconductor substrate; the semiconductor substrate comprising: an array region and a peripheral region; forming a stacked structure on the semiconductor substrate; the stacked structure comprising: a separator layer and a composite layer alternately stacked along a vertical direction; forming a bit line structure in the stacked structure based on a first photomask, and forming a capacitor region in the peripheral region; wherein the bit line structure extends along the vertical direction and penetrates the stacked structure; a row of bit line structures is formed on each of the two opposite sides of the capacitor region along a first direction; the composite layer of the capacitor region comprises: a first electrode plate; the first electrode plates are spaced apart on the two opposite sides of the composite layer of the capacitor region along the first direction and protrude outward; each first electrode plate is connected to a corresponding bit line structure.

[0013] In some embodiments of this disclosure, the method of forming the bit line structure and the capacitor region includes: forming a first cavity and bit line holes in the stacked structure based on the first photomask; both the first cavity and the bit line holes penetrate the stacked structure along the vertical direction; a row of bit line holes is formed on each of the two opposite sides of the first cavity along the first direction; spaced protrusions are formed at the intersection of the two opposite sides of the first cavity along the first direction with the composite layer; filling the first cavity and the bit line holes with sacrificial material; removing the sacrificial material from the bit line holes to form the bit line structure in the bit line holes; removing the sacrificial material from the first cavity to form the capacitor region in the first cavity; wherein the first electrode plate is formed in the protrusions.

[0014] In some embodiments of this disclosure, forming the capacitor region in the first cavity includes: depositing a first conductive layer on the inner wall of the first cavity; etching within the first cavity to partially remove the first conductive layer, retaining and exposing the first conductive layer in the protrusion groove to form a first electrode; depositing a dielectric layer on the inner wall of the first cavity; depositing a second conductive layer covering the dielectric layer on the inner wall of the first cavity to form a second electrode; and filling the first cavity with semiconductor material.

[0015] In some embodiments of this disclosure, etching within the first cavity to partially remove the first conductive layer while retaining and exposing the first conductive layer in the protrusion groove includes: filling the protrusion groove with a sacrificial material; etching within the first cavity to partially remove the first conductive layer while retaining the first conductive layer in the protrusion groove; enlarging the size of the first cavity along the first direction to expose the first conductive layer in the protrusion groove, and removing the sacrificial material in the protrusion groove.

[0016] In some embodiments of this disclosure, after forming the bit line structure and the capacitor region, the method further includes: forming a rear-end connection structure extending in the vertical direction above the capacitor region and above the bit line structure.

[0017] Understandably, the first electrode protrudes outwards to facilitate connection with the bit line structure located on the outer side, thereby benefiting the fabrication of the semiconductor structure. Simultaneously, the outward protrusion of the first electrode forms a curved electrode shape, which increases the area between the electrodes, thus increasing the capacitance of the NICAP capacitor. Attached Figure Description

[0018] Figure 1 is a schematic diagram of the semiconductor structure provided in an embodiment of this disclosure;

[0019] Figure 2 is a schematic diagram of the semiconductor structure provided in an embodiment of this disclosure.

[0020] Figure 3A is a schematic diagram of a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0021] Figure 3B is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0022] Figure 3C is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0023] Figure 4A is a schematic diagram of the semiconductor structure formation method provided in the embodiment of this disclosure.

[0024] Figure 4B is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0025] Figure 4C is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0026] Figure 5A is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0027] Figure 5B is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0028] Figure 5C is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0029] Figure 6A is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0030] Figure 6B is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0031] Figure 6C is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0032] Figure 7A is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0033] Figure 7B is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0034] Figure 7C is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0035] Figure 8A is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0036] Figure 8B is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0037] Figure 8C is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0038] Figure 9A is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0039] Figure 9B is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0040] Figure 9C is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0041] Figure 10A is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0042] Figure 10B is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of this disclosure.

[0043] Figure 10C is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0044] Figure 11A is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0045] Figure 11B is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0046] Figure 11C is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0047] Figure 12A is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0048] Figure 12B is a schematic diagram of the method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0049] Figure 12C is a schematic diagram of the method for forming a semiconductor structure provided in an embodiment of this disclosure. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0051] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0052] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0053] In this document, when a layer / component is referred to as being "above" another layer / component, the layer / component may be directly above the other layer / component, or there may be an intermediate layer / component between them. Furthermore, in one orientation, a layer / component is "above" another layer / component; when the orientation is reversed, the layer / component may be "below" the other layer / component.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0055] It should be noted that Figures 1 and 2 are schematic diagrams of the semiconductor structure provided in the embodiments of this disclosure, wherein both Figures 1 and 2 are schematic diagrams of the structure from a three-dimensional perspective.

[0056] Figures 3A, 3B, and 3C up to Figures 12A, 12B, and 12C are schematic diagrams of the various steps in the semiconductor structure formation method provided in the embodiments of this disclosure. Specifically, the schematic diagram numbered A is a three-dimensional view, the schematic diagram numbered B is a cross-sectional view along the cutting line A-A1 in the schematic diagram numbered A, and the schematic diagram numbered C is a cross-sectional view along the cutting line B-B1 in the schematic diagram numbered A. Furthermore, for ease of explanation, the internal structure is cut open in the schematic diagram numbered A; however, in reality, the cut-open area is filled with a corresponding structure.

[0057] This disclosure provides a semiconductor structure, as shown in FIG1, including: a semiconductor substrate 10, a stacked structure 20, and a bit line structure 30.

[0058] In this embodiment of the disclosure, referring to FIG1, the stacked structure 20 and the bit line structure 30 are located on the semiconductor substrate 10. The stacked structure 20 includes: a separator layer and a composite layer alternately stacked along the vertical direction Z; wherein devices and circuit structures are formed in the composite layer, and the separator layer is used to separate the various composite layers. The bit line structure 30 extends along the vertical direction Z and penetrates the stacked structure 20. In this way, a 3D semiconductor structure is formed, thereby improving integration, enhancing performance, and reducing cost.

[0059] In this embodiment of the disclosure, the semiconductor substrate 10 includes an array region and a peripheral region; wherein, the array region includes a memory cell array for storing data, and the peripheral region includes peripheral circuitry located around the memory cell array. The stacked structure 20 located in the peripheral region includes a capacitor region 40, which forms the capacitor NICAP in the peripheral region. The area shown at the center of Figure 1 is the capacitor region 40.

[0060] It should be noted that in memory chips (such as DRAM chips), the NICAP capacitor in the peripheral area serves as a decoupling capacitor. Its main function is to provide a stable power supply, reduce power supply noise, and protect the chip from high-frequency electromagnetic interference. On the one hand, the decoupling capacitor can be placed at the power supply terminal as a local source of transient current, maintaining the stability of the power supply voltage; on the other hand, the decoupling capacitor can also bypass high-frequency noise, reducing high-frequency electromagnetic interference.

[0061] In this embodiment of the present disclosure, referring to FIG1, a row line structure 30 is formed on each of the two opposite sides of the capacitor region 40 along the first direction X. The first direction X is located in a horizontal plane perpendicular to the vertical direction Z, that is, the first direction X is perpendicular to the vertical direction Z.

[0062] Referring again to Figure 1, the composite layer of capacitor region 40 includes a first electrode plate 41. The first electrode plates 41 are spaced apart on opposite sides of the composite layer of capacitor region 40 along the first direction X, wherein adjacent first electrode plates 41 are not directly connected.

[0063] Referring again to Figure 1, each first electrode plate 41 protrudes outward from the capacitor region 40, that is, each first electrode plate 41 protrudes into the corresponding bit line structure 30 and is connected to the corresponding bit line structure 30.

[0064] Understandably, the first electrode 41 protrudes outwards, which facilitates its connection with the bit line structure 30 located on the outer side, thereby benefiting the processing and manufacturing of the semiconductor structure. Simultaneously, the outward protrusion of the first electrode 41 forms a curved electrode shape, which increases the area between the electrodes, thereby increasing the capacitance of the capacitor NICAP.

[0065] In some embodiments of this disclosure, referring to FIG1, the composite layer of capacitor region 40 further includes: a dielectric layer 43 and a second electrode 42. The second electrode 42 is located inside the composite layer of capacitor region 40. The dielectric layer 43 is located between the first electrode and the second electrode.

[0066] The inner side of the second electrode plate 42 is filled with a semiconductor material, which can serve as a support and isolation element. The semiconductor material may include polycrystalline silicon.

[0067] In this embodiment of the present disclosure, in the composite layer of each capacitor region 40, the second electrode 42 is a single integral electrode, meaning that the same second electrode 42 and multiple first electrodes 41 form a capacitor. This is equivalent to connecting multiple capacitors in parallel, thereby enabling the realization of a capacitor with a larger capacity.

[0068] Meanwhile, in the composite layer of each capacitor region 40, the second electrode plate 42 is located on the inner side, forming a closed structure. This effectively reduces the size occupied by the capacitor, thereby improving the integration density.

[0069] In this embodiment of the present disclosure, referring to FIG1, the surface of the bit line structure 30 along the vertical direction Z is wavy, wherein the bit line structure 30 protrudes outward at the position where it connects with the contact structure. In this way, on the one hand, the contact area with the contact structure can be increased, thereby reducing the contact resistance; on the other hand, the cross-sectional area of ​​the bit line structure 30 is enlarged, thereby reducing the resistance of the bit line structure 30.

[0070] In this embodiment of the disclosure, referring to FIG1, the bit line structure 30 may be composed of one or more layers of conductive material, wherein the conductive material may include one or more of titanium (Ti), titanium nitride (TiN), and tungsten (W). The etching selectivity ratio between the conductive material and the dielectric material of the bit line structure 30 has a large difference, thus ensuring selective etching of the conductive material to form the bit line structure 30; wherein the dielectric material may be silicon nitride (SiN) or silicon oxide (SiO).

[0071] In this embodiment of the disclosure, referring to FIG1, the materials of the first electrode 41 and the second electrode 42 may include titanium (Ti) and / or titanium nitride (TiN). The material of the dielectric layer 43 may include a high-k material, and using a high-k material can increase the capacitance of the capacitor.

[0072] In some embodiments of this disclosure, referring to FIG1, the composite layer of capacitor region 40 further includes a contact plug 44. The contact plug 44 is located between the first electrode plate 41 and the bit line structure 30. Each first electrode plate 41 is connected to the corresponding bit line structure 30 via the contact plug 44.

[0073] Understandably, the contact plug 44 can establish a good electrical connection between the first electrode plate 41 and the bit line structure 30, avoiding open circuits due to poor contact. Specifically, at the connection point between the contact plug 44 and the bit line structure 30, the bit line structure 30 protrudes outwards, thereby increasing the contact area and reducing the contact resistance.

[0074] In some embodiments of this disclosure, as shown in FIG2, the stacked structure located in the array region includes a storage cell region 50. The storage cell region 50 contains an array of storage cells 51.

[0075] In this embodiment of the present disclosure, referring to FIG2, a bit line structure 30 is formed between two memory cells 51 that are opposite each other along the first direction X, and the two memory cells 51 are connected to a corresponding bit line structure 30 (i.e., the bit line structure 30 between the two memory cells 51).

[0076] In this embodiment of the present disclosure, referring to FIG2, an isolation structure 60 may be formed on the side of the memory cell 51 away from the bit line structure 30. The isolation structure 60 penetrates the stacked structure and extends along the second direction Y. In FIG2, the dielectric material filling the isolation structure 60 is not shown; it is shown as a cavity. The second direction Y lies in a horizontal plane perpendicular to the vertical direction Z, that is, the second direction Y is perpendicular to the vertical direction Z. Meanwhile, the first direction X intersects the second direction Y, and the included angle is not limited.

[0077] In some embodiments of this disclosure, in conjunction with Figures 1 and 2, both the capacitor region 40 and the storage cell region 50 are formed based on a first photomask.

[0078] In Figure 2, the projection of the storage cell 51 and the isolation structure 60 between the two rows of line structures 30 onto the horizontal plane is consistent with the projection of the capacitor region 40 onto the horizontal plane in Figure 1. Furthermore, the storage cell 51 shown in Figure 2 can be a capacitor within the storage cell, and the capacitors in the storage cell and the capacitors in the peripheral area (i.e., capacitor region 40) are formed on the same layer. Therefore, the same photomask can be used to form both the capacitor region 40 and the storage cell region 50, thus reducing the number of photomasks required and saving costs.

[0079] In some embodiments of this disclosure, referring to FIG2, the semiconductor structure further includes a word line structure 70. The word line structure 70 extends along the second direction Y and is located between the memory cell 51 and the bit line structure 30.

[0080] In some embodiments of this disclosure, referring to Figures 12A, 12B, and 12C, the semiconductor structure further includes a back-end interconnect 80. The back-end interconnect 80 extends in a vertical direction Z. The back-end interconnect 80 is located above the capacitor region 40 and above the bit line structure 30. The material of the back-end interconnect 80 includes a metallic material, such as tungsten (W).

[0081] This disclosure also provides a method for forming a semiconductor structure, including steps S101 to S103.

[0082] S101, Provides a semiconductor substrate 10.

[0083] In this embodiment of the present disclosure, referring to FIG1, the semiconductor substrate 10 is divided into an array region and a peripheral region. The array region can be used to form a memory cell array to store data; the peripheral region can be used to form peripheral circuits located around the memory cell array.

[0084] S102. A stacked structure 20 is formed on the semiconductor substrate 10.

[0085] In this embodiment of the present disclosure, referring to FIG1, the stacked structure 20 includes: a separator layer and a composite layer alternately stacked in a vertical direction. Devices and circuit structures are formed in the composite layer, while the separator layer separates the individual composite layers. The stacked structure 20 allows for the formation of a 3D semiconductor structure, thereby improving integration, enhancing performance, and reducing costs.

[0086] In this embodiment of the disclosure, referring to FIG1, the stacked structure 20 can be generated layer by layer by an epitaxial growth process; or the stacked structure 20 can be generated by alternating stacking of ONO (silicon oxide-silicon nitride-silicon oxide).

[0087] S103. Based on the first photomask, a bit line structure 30 is formed in the stacked structure 20, and a capacitor region 40 is formed in the peripheral region.

[0088] Referring to Figure 1, the bit line structure 30 extends along the vertical direction Z and penetrates the stacked structure 20. A row of bit line structures 30 is formed on each of the two opposite sides of the capacitor region 40 along the first direction X.

[0089] Referring again to Figure 1, the composite layer of capacitor region 40 includes a first electrode plate 41. The first electrode plates 41 are spaced apart on opposite sides of the composite layer of capacitor region 40 along the first direction X, wherein adjacent first electrode plates 41 are not directly connected.

[0090] Referring again to Figure 1, each first electrode plate 41 protrudes outward from the capacitor region 40, that is, each first electrode plate 41 protrudes into the corresponding bit line structure 30 and is connected to the corresponding bit line structure 30.

[0091] Understandably, the first electrode 41 protrudes outwards, which facilitates its connection with the bit line structure 30 located on the outer side, thereby benefiting the processing and manufacturing of the semiconductor structure. Simultaneously, the outward protrusion of the first electrode 41 forms a curved electrode shape, which increases the area between the electrodes, thereby increasing the capacitance of the capacitor NICAP.

[0092] In some embodiments of this disclosure, in conjunction with Figures 1 and 2, a storage cell area 50 of the array region can also be formed based on the first photomask.

[0093] In Figure 2, the projection of the storage cell 51 and the isolation structure 60 between the two rows of line structures 30 onto the horizontal plane is consistent with the projection of the capacitor region 40 onto the horizontal plane in Figure 1. Furthermore, the storage cell 51 shown in Figure 2 can be a capacitor within the storage cell, and the capacitors in the storage cell and the capacitors in the peripheral area (i.e., capacitor region 40) are formed on the same layer. Therefore, the same photomask can be used to form both the capacitor region 40 and the storage cell region 50, thus reducing the number of photomasks required and saving costs.

[0094] In some embodiments of this disclosure, the method of forming bit line structure 30 and capacitor region 40 includes steps S201 to S204.

[0095] S201. Based on the first photomask, a first cavity 401 and a bit line hole 301 are formed in the stacked structure.

[0096] S202. Sacrificial material is filled into the first cavity 401 and the bit hole 301.

[0097] In Figures 3A, 3B, and 3C, the first cavity 401 and the bit line holes 301 are filled with sacrificial material. Both the first cavity 401 and the bit line holes 301 penetrate the stacked structure 20 along the vertical direction Z. A row of bit line holes 301 is formed on each of the two opposite sides of the first cavity 401 along the first direction X. At the intersections of the two opposite sides of the first cavity 401 along the first direction X with the composite layer, spaced-apart protrusions 402 are formed.

[0098] S203. Remove the sacrificial material in the bit line hole 301 and form a bit line structure 30 in the bit line hole 301.

[0099] Referring to Figures 4A and 5A, after the sacrificial material in the bit line via 301 is removed, one or more layers of conductive material can be sequentially deposited in the bit line via 301 to form the bit line structure 30. The conductive material may include one or more of titanium (Ti), titanium nitride (TiN), and tungsten (W). The etching selectivity ratio between the conductive material and the dielectric material in the bit line structure 30 has a large difference, thus ensuring selective etching of the conductive material to form the bit line structure 30; the dielectric material may be silicon nitride (SiN) or silicon oxide (SiO).

[0100] S204. Remove the sacrificial material from the first cavity 401 and form a capacitor region 40 in the first cavity 401; wherein, the first electrode plate 41 is formed in the protrusion groove 402.

[0101] It should be noted that during the process of forming the bit line structure 30 in the bit line hole 301, a protective layer can be formed above the first cavity 401 to avoid the first cavity 401 from being affected; correspondingly, during the process of forming the capacitor region 40 in the first cavity 401, a protective layer can be formed above the bit line structure 30 to avoid the bit line structure 30 from being affected.

[0102] In some embodiments of this disclosure, step S204 can be achieved through steps S301 to S305.

[0103] S301. A first conductive layer is deposited on the inner wall of the first cavity 401.

[0104] Referring to Figures 6A and 7A, after the sacrificial material in the first cavity 401 is removed, a conductive layer (i.e., the first conductive layer) can be deposited on the inner wall of the first cavity 401. The first conductive layer covers the inner wall of the protrusion groove 402, as well as the inner walls of other areas in the first cavity 401. The material of the first conductive layer may include titanium (Ti) and / or titanium nitride (TiN).

[0105] S302. Etching is performed in the first cavity 401 to partially remove the first conductive layer, while retaining and exposing the first conductive layer in the protrusion groove 402 to form the first electrode plate 41.

[0106] Referring to Figures 8A and 9A, etching can be performed within the first cavity 401, retaining only the first conductive layer covering the inner sidewall of the protrusion groove 402, removing the rest of the first conductive layer, and exposing the first conductive layer within the protrusion groove 402. This forms the spaced-apart first electrode plates 41. Because the protrusion grooves 402 are spaced-apart, adjacent first electrode plates 41 are not directly connected.

[0107] S303. A dielectric layer 43 is deposited on the inner wall of the first cavity 401.

[0108] Referring to Figures 10A, 10B, and 10C, the dielectric layer 43 covers the inner wall of the first cavity 401 and also covers the exposed surface of the first electrode plate 41. The material of the dielectric layer 43 may include a high-k material, which can increase the capacitance of the capacitor.

[0109] S304. On the inner wall of the first cavity 401, a second conductive layer covering the dielectric layer 43 is deposited to form a second electrode plate 42.

[0110] Referring to Figures 11A, 11B, and 11C, a second electrode 42 covers the surface of the dielectric layer 43 on the inner wall of the first cavity 401, thereby forming a capacitor NICAP. The material of the second electrode 42 may include titanium (Ti) and / or titanium nitride (TiN).

[0111] In this embodiment of the present disclosure, in the composite layer of each capacitor region 40, the second electrode 42 is a single integral electrode, meaning that the same second electrode 42 and multiple first electrodes 41 form a capacitor. This is equivalent to connecting multiple capacitors in parallel, thereby enabling the realization of a capacitor with a larger capacity.

[0112] Meanwhile, in the composite layer of each capacitor region 40, the second electrode plate 42 is located on the inner side, forming a closed structure. In this way, compared with sleeve capacitors or parallel plate capacitors, the size occupied by the capacitor can be effectively reduced, thereby improving the integration density.

[0113] S305. A semiconductor material is filled into the first cavity 401. The semiconductor material filling the first cavity 401 can serve as support and isolation. The semiconductor material may include polycrystalline silicon.

[0114] In some embodiments of this disclosure, step S302 can be achieved through steps S401 to S403.

[0115] S401. Fill the protruding groove 402 with sacrificial material.

[0116] In this embodiment, sacrificial material can be filled into the first cavity 401 (including the protrusion groove 402 and other areas); then, etching is performed to retain only the sacrificial material in the protrusion groove 402 and remove the sacrificial material in other areas, thus obtaining the structure shown in Figures 8A, 8B, and 8C. Since the protrusion groove 402 protrudes outward from the first cavity 401, the sacrificial material in the protrusion groove 402 can be retained during the etching process.

[0117] S402. Etching is performed in the first cavity 401 to partially remove the first conductive layer while retaining the first conductive layer in the protrusion groove 402.

[0118] In this embodiment of the disclosure, since the protrusion groove 402 is filled with sacrificial material, the first conductive layer in the protrusion groove 402 is protected by the sacrificial material and thus preserved during the etching of the first conductive layer.

[0119] S403, enlarge the dimension of the first cavity 401 along the first direction X, expose the first conductive layer in the protrusion groove 402, and remove the sacrificial material in the protrusion groove 402.

[0120] In this embodiment, the exposed sidewalls of the first cavity 401 can be etched to increase the size of the first cavity 401 along the first direction X. For example, an etching solution with a certain etching selectivity can be injected into the first cavity 401 to selectively etch the sidewalls of the first cavity 401. Alternatively, a plasma beam can be used to bombard the sidewalls of the first cavity 401 to etch the sidewalls of the first cavity 401.

[0121] In some embodiments of this disclosure, after step S103 described above, the method for forming a semiconductor structure further includes step S104.

[0122] S104. Above the capacitor region 40 and above the bit line structure 30, a rear-end connection structure 80 extending in the vertical direction Z is formed.

[0123] Referring to Figures 12A, 12B and 12C, the material of the rear connection structure 80 includes a metallic material, such as tungsten (W).

[0124] It should be noted that the semiconductor structure and its formation method provided in this disclosure can be applied to dynamic random access memory (DRAM), providing a new solution for three-dimensional memory products. The capacitor NICAP (i.e., capacitor region 40) in the peripheral region is located in the same composite layer as the memory cell; the capacitor NICAP in the peripheral region is used as a power source or for signal processing in the peripheral region, enabling frequency modulation and noise reduction, increasing capacitance, and realizing a separate IC test structure.

[0125] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0126] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0127] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: a semiconductor substrate (10), a stacked structure (20), and a bit line structure (30); The stacked structure (20) and the bit line structure (30) are located on the semiconductor substrate (10); The semiconductor substrate (10) includes an array region and a peripheral region; The stacked structure (20) includes: a separator layer and a composite layer that are alternately stacked in the vertical direction; the bit line structure (30) extends in the vertical direction and penetrates the stacked structure (20); The stacked structure (20) located in the peripheral area includes: a capacitor region (40); a row of bit line structures (30) is formed on both sides opposite to each other along the first direction of the capacitor region (40); The composite layer of the capacitor region (40) includes: a first electrode plate (41); the first electrode plates (41) are spaced apart on opposite sides of the composite layer of the capacitor region (40) along the first direction and protrude outward; each first electrode plate (41) is connected to the corresponding bit line structure (30).

2. The semiconductor structure according to claim 1, wherein, The composite layer of the capacitor region (40) further includes: a dielectric layer (43) and a second electrode plate (42); The second electrode plate (42) is located inside the composite layer of the capacitor region (40); the dielectric layer (43) is located between the first electrode plate (41) and the second electrode plate (42); The inner side of the second electrode plate (42) is filled with semiconductor material.

3. The semiconductor structure according to claim 1, wherein, The composite layer of the capacitor region (40) further includes: a contact plug (44); The contact plug (44) is located between the first electrode plate (41) and the bit line structure (30); each first electrode plate (41) is connected to the corresponding bit line structure (30) through the contact plug (44).

4. The semiconductor structure according to any one of claims 1-3, wherein, The stacked structure (20) located in the array region includes: a storage cell region (50); The storage unit area (50) is provided with an array of storage units (51); A bit line structure (30) is formed between two memory cells (51) that are opposite each other along the first direction; the two memory cells (51) are connected to a corresponding bit line structure (30); Both the capacitor region (40) and the storage cell region (51) are formed based on the first photomask.

5. The semiconductor structure according to any one of claims 1-4, wherein, The semiconductor structure further includes: a back-end connection structure (80); The rear connection structure (80) extends along the vertical direction; The rear connection structure (80) is located above the capacitor region (40) and above the bit line structure (30).

6. A method for forming a semiconductor structure, characterized in that, The method includes: A semiconductor substrate (10) is provided; the semiconductor substrate (10) includes an array region and a peripheral region; A stacked structure (20) is formed on the semiconductor substrate (10); the stacked structure (20) includes: a separator layer and a composite layer that are alternately stacked in the vertical direction; Based on the first photomask, bit line structures (30) and capacitor regions (40) are formed in the stacked structure (20) in the peripheral region; wherein, the bit line structures (30) extend along the vertical direction and penetrate the stacked structure (20); a row of bit line structures (30) is formed on both sides opposite to each other along the first direction of the capacitor region (40); the composite layer of the capacitor region (40) includes: a first electrode plate (41); the first electrode plates (41) are spaced apart on both sides opposite to each other along the first direction of the composite layer of the capacitor region (40) and protrude outward; each first electrode plate (41) is connected to the corresponding bit line structure (30).

7. The method for forming a semiconductor structure according to claim 6, wherein, The method of forming the bit line structure (30) and the capacitor region (40) includes: Based on the first photomask, a first cavity (401) and bit line holes (301) are formed in the stacked structure (20); the first cavity (401) and the bit line holes (301) both penetrate the stacked structure (20) along the vertical direction; a row of bit line holes (301) is formed on the two opposite sides of the first cavity (401) along the first direction; at the intersection of the two opposite sides of the first cavity (401) along the first direction and the composite layer, there are spaced protrusions (402); Sacrificial material is filled into the first cavity (401) and the bit line hole (301); Remove the sacrificial material from the bit line hole (301) and form the bit line structure (30) in the bit line hole (301); The sacrificial material in the first cavity (401) is removed, and the capacitor region (40) is formed in the first cavity (401); wherein the first electrode plate (41) is formed in the protrusion (402).

8. The method for forming a semiconductor structure according to claim 7, wherein, Forming the capacitor region (40) in the first cavity (401) includes: A first conductive layer is deposited on the inner wall of the first cavity (401); Etching is performed in the first cavity (401) to partially remove the first conductive layer, while retaining and exposing the first conductive layer in the protrusion groove (402) to form the first electrode plate (41). A dielectric layer (43) is deposited on the inner wall of the first cavity (401); On the inner wall of the first cavity (401), a second conductive layer is deposited covering the dielectric layer (43) to form a second electrode plate (42); Semiconductor material is filled into the first cavity (401).

9. The method for forming a semiconductor structure according to claim 8, wherein, Etching is performed within the first cavity (401) to partially remove the first conductive layer, leaving and exposing the first conductive layer in the protrusion groove (402), including: The protruding groove (402) is filled with sacrificial material; Etching is performed in the first cavity (401) to partially remove the first conductive layer while retaining the first conductive layer in the protrusion groove (402); The dimensions of the first cavity (401) along the first direction are increased to expose the first conductive layer in the protrusion groove (402) and the sacrificial material in the protrusion groove (402) is removed.

10. The method for forming a semiconductor structure according to claim 6, wherein, After forming the bit line structure (30) and the capacitor region (40), the method further includes: Above the capacitor region (40) and above the bit line structure (30), a rear end connection structure (80) extending in the vertical direction is formed.

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