Semiconductor processing apparatus

Abstract

The present invention provides a semiconductor processing apparatus, comprising at least two processing chambers sharing a vacuumizing device. Each processing chamber comprises: a base, used for carrying a wafer; a gas blocking ring, surrounding the periphery of the base and dividing the space inside the processing chamber into a wafer processing area and a gas supplementing and pressure regulation area which are in gas communication with each other; and a bottom liner ring, dividing the gas supplementing and pressure regulation area into a gas supplementing area and a pressure regulation area, wherein the gas supplementing area is in gas communication with an external supplementary gas source, the pressure regulation area is in gas communication with the gas supplementing area, the corresponding wafer processing area, and the vacuumizing device, and the bottom liner ring is provided with a plurality of first vent holes in communication with the gas supplementing areas and the pressure regulation areas. By adjusting the distribution of first vent holes, the flow rate of the supplementary gas injected into pressure regulation areas is regulated in different areas, so that the uniform distribution of the gas flow field in wafer processing areas is realized. The advantages of the present invention are: realizing the uniform distribution of the process gases in wafer processing areas of processing chambers, improving the quality and efficiency of wafer processing, and reducing the volume of corrosive process gases diffused in the processing chambers.

Description

A semiconductor processing device Technical Field

[0001] This invention relates to the field of semiconductor equipment technology, and in particular to a semiconductor processing device. Background Technology

[0002] In semiconductor manufacturing, physical methods (such as sputtering) or chemical methods (such as chemical vapor deposition and atomic layer deposition) are typically used to deposit material layers onto silicon wafers. During manufacturing, wafers need to be transferred between different manufacturing systems, and oxide layers (such as silicon oxide layers) may form on the wafer surface due to exposure to oxygen during wafer transfer. Oxide layers may also form on the wafer surface when residual oxygen is present in some manufacturing systems. During the formation of some material layers, oxide layers formed on the wafer surface may hinder the deposition of material layers on the wafer and cause defects within the material layers. Therefore, it is necessary to remove the oxide layers on the wafer surface before depositing the required material layers onto the wafer.

[0003] The oxide layer on the wafer surface is removed by introducing a corrosive cleaning gas into the processing chamber. To reduce gas consumption and environmental impact, and to protect other material layers on the wafer, a smaller flow rate of cleaning gas is typically used.

[0004] To achieve uniform cleaning, the uniformity of the cleaning gas distribution within the processing chamber is crucial, typically requiring a single-chamber setup for wafer processing. The advantages of this setup are: 1) It reduces the volume of the processing chamber, thereby minimizing the time and space required for the cleaning gas to flow through it; 2) It allows for symmetric pumping to create a vacuum within the chamber, improving the symmetry of the gas flow field. However, the efficiency of a single processing chamber is relatively low.

[0005] Improving wafer processing efficiency while ensuring processing quality is a pressing issue that needs to be addressed. Technical solutions

[0006] The purpose of this invention is to provide a semiconductor processing apparatus that effectively solves the problem of uneven distribution of process gases on the wafer surface caused by multiple processing cavities sharing a single vacuum pump. This invention significantly improves the consistency of processing rates across different areas of the wafer and increases wafer processing efficiency. Furthermore, this invention reduces the diffusion volume of process gases within the processing cavity, which not only saves on the amount of process gases used but also helps reduce the erosion of components within the processing cavity by the process gases.

[0007] To achieve the above objectives, the present invention provides a semiconductor processing apparatus, comprising: at least two processing chambers, wherein the two processing chambers share a set of vacuum pumping devices;

[0008] The processing chamber includes:

[0009] The base is used to support the wafer;

[0010] A gas-blocking ring surrounds the outer periphery of the base, dividing the space within the processing cavity into a wafer processing area with gas-connected pathways and a gas replenishment and pressure regulation area.

[0011] The bottom inner ring divides the gas replenishment and pressure regulation area into a gas replenishment zone and a pressure regulation zone. The gas supply path of the gas replenishment zone is connected to an external gas supply source, and the gas supply path of the pressure regulation zone is connected to the gas replenishment zone, the wafer processing zone, and the vacuum pump. The bottom inner ring has multiple first vent holes that connect the gas replenishment zone and the pressure regulation zone. By adjusting the distribution of the first vent holes, the flow rate of the replenishment gas injected into the pressure regulation zone can be adjusted in different areas to achieve a uniform distribution of the airflow field in the wafer processing zone.

[0012] Optionally, the processing chamber is provided with an air extraction port at one end near the vacuum device, and the distribution density of the first air vent gradually increases along the direction near the air extraction port.

[0013] Optionally, the processing chamber is provided with an air extraction port at one end near the vacuum device, and the diameter of the first vent gradually increases along the direction near the air extraction port.

[0014] Optionally, the air-blocking ring is disposed around the base and the inner wall of the processing chamber, and there is no gap between the air-blocking ring and the base and the inner wall of the processing chamber.

[0015] Optionally, the gas barrier ring has multiple second vent holes that connect the wafer processing area and the gas replenishment and pressure regulation area, and the second vent holes are evenly distributed.

[0016] Optionally, the bottom liner ring surrounds the outer periphery of the base; the top of the bottom liner ring is connected to the inner end of the air-blocking ring, and the bottom of the bottom liner ring is fixedly connected to the inner bottom wall of the processing chamber.

[0017] Optionally, the bottom wall of the processing chamber has a supplementary gas injection hole at its center, and the processing chamber also includes a spacer cylinder; the top of the spacer cylinder is sealed to the bottom of the base, and the bottom of the spacer cylinder is located inside the supplementary gas injection hole; the spacer cylinder divides the gas replenishment zone into a non-communicating flow zone and a spacer zone, with the flow zone surrounding the outer periphery of the spacer zone; the supplementary gas flows into the supplementary gas injection hole from the outside of the bottom of the spacer cylinder, and sequentially flows into the pressure regulating zone from the supplementary gas injection hole and the flow zone.

[0018] Optionally, the supplementary gas injection hole, the occupier, and the base are arranged concentrically.

[0019] Optionally, the supplementary gas is an inert gas.

[0020] Optionally, the vacuuming device is a gas trapping vacuum pump.

[0021] Optionally, the processing chamber further includes a gas spray head, which is disposed above and opposite the base, for injecting process gas into the wafer processing area.

[0022] Optionally, the process gas includes a gas that is corrosive to the inner wall of the processing chamber.

[0023] Optionally, the base may contain a heating element.

[0024] Optionally, the base is provided with a cooling fluid channel.

[0025] Optionally, the processing chambers are separated by partition walls; a main pressure gauge is provided on the partition wall, and the detection port of the main pressure gauge is connected to each of the processing chambers through an air passage in the partition wall.

[0026] Optionally, the end of the pressure regulating zone closest to the air extraction port is the first end of the pressure regulating zone, and the end of the pressure regulating zone furthest from the air extraction port is the second end of the pressure regulating zone.

[0027] The processing chamber also includes a first pressure gauge and a second pressure gauge, which are used to measure the air pressure values ​​at the first end and the second end of the pressure regulating zone, respectively. Beneficial effects

[0028] Compared with the prior art, the present invention has at least the following beneficial effects:

[0029] 1) The semiconductor processing apparatus of this invention uses a gas-blocking ring to divide the space within the processing cavity into a wafer processing area with interconnected gas paths and a gas replenishment and pressure regulation area. A bottom inner liner ring further divides the gas replenishment and pressure regulation area into a gas replenishment area (connected to the replenishment gas source) and a pressure regulation area. By adjusting the distribution of the first vent holes on the bottom inner liner ring, the flow rate of the replenishment gas flowing from the replenishment area into the pressure regulation area is adjusted in different regions. This ensures that the mixture of replenishment gas and process gas forms a uniform gas pressure distribution within the pressure regulation area. Consequently, the process gas within the wafer processing area can flow through all positions of the gas-blocking ring at the same speed, effectively solving the problem of uneven distribution of process gas on the wafer surface caused by multiple processing cavities sharing a single vacuum device. Compared to semiconductor processing apparatuses with a single processing cavity, this invention not only improves the consistency of processing rates across different areas of the wafer but also increases wafer processing efficiency.

[0030] 2) In this invention, under the suppression of the supplementary gas in the supplementary gas zone, the process gas in the pressure regulating zone is less likely to enter the supplementary gas zone, thus reducing the diffusion volume of the process gas in the processing chamber. This not only reduces the corrosion of the components in the processing chamber by the process gas but also reduces the amount of process gas used. The reduction in process gas usage has positive implications for environmental protection, especially since the process gas includes highly corrosive gases. This invention significantly reduces the amount of process gas used, promoting green production and sustainable development for enterprises. By optimizing production processes and reducing energy consumption and pollution emissions, enterprises can better respond to the global call for environmental protection and sustainable development, establish a green, environmentally friendly, and low-carbon corporate image, and make a positive contribution to the sustainable development of society.

[0031] 3) By injecting supplementary gas into the pressure regulation zone, the present invention increases the overall gas pressure in the pressure regulation zone, thereby extending the residence time of the process gas in the wafer processing zone, thus improving the utilization rate of the process gas and greatly saving the economic cost of wafer processing.

[0032] 4) The present invention has a spacer cylinder in the gas replenishment zone, which reduces the diffusion volume of the replenishment gas in the gas replenishment zone. Under the premise of uniform pressurization of the pressure regulating zone, the amount of replenishment gas used is reduced, which further saves the economic cost of wafer processing.

[0033] 5) In this invention, the gas pressure value in the wafer processing area can be monitored in real time by the main pressure gauge. The gas pressure values ​​at the first end and the second end of the pressure regulating area can also be measured by the first and second auxiliary pressure gauges, respectively, to ensure that the desired airflow field distribution is obtained within the wafer processing area. Attached Figure Description

[0034] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are one embodiment of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 is a schematic diagram of a semiconductor processing device.

[0036] Figure 2 is a schematic diagram of a semiconductor processing device in an embodiment of the present invention.

[0037] Figure 3 is a schematic diagram of the asymmetrical bottom inner lining ring in an embodiment of the present invention.

[0038] Figure 4 is a schematic diagram of a symmetrical bottom inner lining ring.

[0039] Figure 5 is a schematic diagram of the air passage connection between the symmetrical bottom inner liner ring and the asymmetrical bottom inner liner ring.

[0040] Figure 6 shows the gas mass flux at various locations on the wafer edge in two processing cavities, one with a symmetrical bottom liner ring and the other with an asymmetrical bottom liner ring.

[0041] Figure 7 shows the gas mass flux above the wafer surface in two processing cavities, one with a symmetrical bottom liner ring and the other with an asymmetrical bottom liner ring. Embodiments of the present invention

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0044] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0045] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0046] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrases "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0047] Furthermore, in the description of this application, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0048] During semiconductor manufacturing, wafers need to be transferred between different manufacturing systems. During this transfer, wafers are inevitably exposed to oxygen, leading to the formation of oxides (such as silicon oxide) on their surfaces. Additionally, residual oxygen present in some manufacturing systems can also form oxides on the wafer surface during the manufacturing process.

[0049] When depositing the required material layer on a wafer surface using physical or chemical methods, silicon oxide on the wafer surface may hinder the deposition of the material layer and cause defects within the material layer. Therefore, it is necessary to pre-treat the wafer before the deposition process to remove silicon oxide from the wafer surface.

[0050] Figure 1 illustrates a semiconductor processing apparatus 1 having a processing cavity 10 in which a wafer W is processed monolithically. The processing cavity 10 includes a cavity cover 101 and a cavity body, the cavity body including cavity sidewalls 102 and a cavity bottom wall 103. The cavity cover 101 covers the cavity body, and the cavity cover 101 and the cavity body together form an airtight internal processing space.

[0051] As shown in Figure 1, the processing chamber 10 is equipped with a gas spray head 110 and a base 120 for supporting the wafer W. The gas spray head 110 is attached to the chamber cover 101 and is used to deliver process gases for pre-treating the wafer W into the processing chamber 10. The process gases are typically corrosive gases, such as a mixture of HF (hydrofluoric acid) and NH3 (ammonia). A vacuum port 130 is located at the center of the bottom wall 103 of the chamber. The vacuum port 130 is connected to an external vacuum device (not shown in the figure) to discharge unreacted process gases and reaction byproducts from the processing chamber 10 and maintain a vacuum environment within the processing chamber 10.

[0052] As shown in Figure 1, the base 120 is positioned below and opposite the gas spray head 110. The base 120 typically contains a heating element 121 and a cooling fluid channel 122 for regulating the temperature of the base 120, thereby regulating the temperature of the wafer W.

[0053] The pretreatment process, also known as chemical etching, requires extremely high uniformity in the gas flow distribution within the processing chamber 10 and consistent temperature on the wafer W surface. A mixture of HF (hydrofluoric acid) and NH3 (ammonia) reacts with the silicon oxide on the wafer W surface to form ammonium fluorosilicate (NH4)2SiF6, a readily sublimable substance that can be removed from the wafer W surface at relatively low temperatures (not lower than 100°C). The chemical etching selectivity ratio of silicon oxide to silicon nitride is typically between 5:1 and 20:1, which helps reduce damage to the wafer W surface during pretreatment.

[0054] Typically, a small flow rate of HF and NH3 gas is injected into the processing chamber 10. This avoids excessively vigorous chemical reactions on the wafer W surface due to excessive gas flow, preventing damage to the wafer W surface. Simultaneously, a small flow rate of HF and NH3 gas allows for more uniform distribution on the wafer W surface, achieving a more uniform chemical etching effect. By controlling the flow rates of HF and NH3, reaction conditions can be optimized, improving selective etching of silicon oxide while protecting other material layers on the wafer W. Furthermore, HF and NH3 are hazardous chemicals; a small flow rate reduces gas consumption and potential safety risks, while also helping to minimize environmental impact.

[0055] When the process gas flow rate is low, even minor changes in the layout within the processing chamber 10 can significantly impact the airflow distribution. Uneven airflow distribution not only leads to incomplete cleaning of the silicon oxide on the wafer W surface, but may also result in excessively harsh chemical etching in certain areas of the wafer W surface, damaging the wafer W.

[0056] Using the semiconductor processing apparatus 1 with a single processing cavity 10 shown in Figure 1 to preprocess wafer W can reduce the volume of the processing cavity 10, thereby reducing the time and space for process gas to flow through the processing cavity 10. Furthermore, when the processing cavity 10 is evacuated through the evacuation port 130 located at the center of the bottom wall 103 of the cavity, the symmetry and uniformity of the gas flow field within the processing cavity 10 can be ensured. However, the semiconductor processing apparatus 1 can only process one wafer W at a time, resulting in low operating efficiency.

[0057] The purpose of this invention is to provide a semiconductor processing apparatus having multiple processing chambers, capable of processing multiple wafers W simultaneously. This improves wafer W processing efficiency while effectively solving the problems of asymmetrical gas flow fields and uneven distribution of process gases on the wafer W surface caused by multiple processing chambers sharing a single vacuum pump. This invention significantly improves the consistency of processing rates across different areas of the wafer W surface and reduces the diffusion volume of process gases within the processing chambers. This not only saves on process gas consumption but also helps reduce the erosion of components within the processing chambers by the process gases.

[0058] Figure 2 is a schematic diagram of the semiconductor processing device 2 in an embodiment of the present invention. The semiconductor processing device 2 can not only be used to preprocess the wafer W, but also to perform other semiconductor processes, such as plasma etching, chemical vapor deposition, etc., which are not limited in the present invention.

[0059] The semiconductor processing apparatus 2 includes at least two processing cavities 20. Each processing cavity 20 includes a chamber cover 201, a chamber sidewall 202, and a chamber bottom wall 203, which together form an airtight internal processing space. In a preferred embodiment, the chamber sidewall 202 is cylindrical.

[0060] As shown in Figure 2, adjacent processing chambers 20 are separated by a partition wall 2021, which is formed by the chamber sidewalls 202 between adjacent processing chambers 20. In this embodiment, all processing chambers 20 share a single vacuum pumping device 206 (e.g., a gas trapping vacuum pump) to save costs. Figure 2 shows two processing chambers 20, which is only an example; the number of processing chambers 20 is not limited in this invention.

[0061] As shown in Figure 2, the processing cavity 20 includes: a base 220 for supporting the wafer W, a gas spray head 210, a gas barrier ring 260, and a bottom inner liner ring 280.

[0062] In semiconductor manufacturing processes, wafer temperature (W) is a key parameter affecting process performance. Taking chemical vapor deposition (CVD) as an example, wafer temperature is one of the important factors influencing the deposition rate and uniformity of materials on the wafer surface. In this embodiment, as shown in Figure 2, a heating element 221 and a cooling fluid channel 222 are provided inside the substrate 220 to regulate the temperature of the substrate 220. This, in turn, regulates the wafer temperature through heat transfer between the substrate 220 and the wafer W.

[0063] As shown in Figure 2, the gas spray head 210 is attached to the chamber cover and is opposite to the base 220. It is used to deliver process gas for processing wafer W into the processing chamber 20. In this embodiment, the process gas includes a gas that is corrosive to the inner wall of the processing chamber 20 and the components inside the processing chamber 20.

[0064] The end of the processing chamber 20 closest to the vacuum pumping device 206 is the first end of the processing chamber, and the end of the processing chamber furthest from the vacuum pumping device 206 is the second end of the processing chamber. As shown in Figure 2, an air extraction port 230 is provided below the first end of the processing chamber. Multiple air extraction ports 230 are arranged close to each other, which facilitates the sharing of a set of vacuum pumping device 206 among multiple air extraction ports 230.

[0065] Compared with the setting of the air extraction port 130 in Figure 1, the setting of the air extraction port 230 in Figure 2 is more likely to cause the gas flow rate in the first end of the processing chamber to be greater than the gas flow rate in the second end of the processing chamber. The gas flow rate and pressure distribution above the surface of wafer W are uneven, which ultimately leads to inconsistent processing effects on different areas of wafer W and affects the yield of wafer W processing.

[0066] As shown in Figure 2, the air-blocking ring 260 is disposed around the inner wall of the base 220 and the processing chamber 20, and is located above the air extraction port 230. There is no gap between the air-blocking ring 260 and the base 220 and the inner wall of the processing chamber 20. In this embodiment, the inner wall of the processing chamber 20 has a radially inwardly protruding annular platform 204, through which the air-blocking ring 260 is supported.

[0067] The gas-blocking ring 260 divides the space within the processing cavity 20 into a wafer processing area 21 and a gas replenishment and pressure regulation area. The gas-blocking ring 260 has multiple second vent holes 261 that connect the wafer processing area 21 and the gas replenishment and pressure regulation area; in this embodiment, the second vent holes 261 are evenly distributed. The gas-blocking ring 260 extends the residence time of the process gas within the wafer processing area 21, helping to improve the uniformity of process gas distribution and the utilization rate of the process gas within the wafer processing area 21.

[0068] However, compared to the second vent 261b further away from the exhaust port 230, the gas velocity through the second vent 261a near the exhaust port 230 is still greater than that through the second vent 261b (when the bottom inner liner ring 280 is not provided in the processing cavity 20), and the gas flow field in the wafer processing area 21 remains asymmetrical. Although the uniformity of the process gas distribution above the wafer W surface is improved compared to not having the gas barrier ring 260, it still does not meet the process requirements.

[0069] Furthermore, in this invention, a bottom inner liner ring 280 is provided in the air replenishment and pressure regulation zone. As shown in Figure 2, the bottom inner liner ring 280 surrounds the outer periphery of the base 220, the top of the bottom inner liner ring 280 is connected to the inner end of the air blocking ring 260, and the bottom of the bottom inner liner ring 280 is fixedly connected to the inner bottom wall of the processing chamber 20.

[0070] As shown in Figure 2, the bottom inner liner ring 280 divides the air supply and pressure regulation area into an air supply zone (the space surrounded by the bottom inner liner ring 280) and a pressure regulation zone 22. The pressure regulation zone 22 is located below the air baffle ring 260 and surrounds the outer periphery of the air supply zone.

[0071] As shown in Figure 2, the bottom inner liner ring 280 has multiple first vent holes 281, through which the gas supply zone and the pressure regulating zone 22 are connected by gas paths. A supplementary gas injection hole 250 is located at the center of the chamber bottom wall 203, and the gas supply zone is also connected to an external supplementary gas source (not shown in the figure) through the supplementary gas injection hole 250. The pressure regulating zone 22 is also connected by gas paths to the wafer processing zone 21 and the vacuum pumping device 206.

[0072] A supplementary gas source injects supplementary gas (e.g., inert gas) into the supplementary gas replenishment zone to increase the gas pressure within the zone. Under the pressure of the supplementary gas in the replenishment zone, the process gas in the pressure regulating zone 22 is less likely to enter the replenishment zone, thus reducing the diffusion volume of the process gas within the processing chamber 20. This not only saves on the amount of process gas used but also helps reduce the erosion of the components (e.g., base 220) and the bottom wall of the processing chamber by the process gas.

[0073] By injecting supplementary gas into the pressure regulating zone 22, the overall gas pressure in the pressure regulating zone 22 is increased, thereby further extending the residence time of the process gas in the wafer processing zone 21, thus improving the utilization rate of the process gas and greatly saving the economic cost of wafer W processing.

[0074] The end of the pressure regulating zone 22 closest to the exhaust port 230 is the first end of the pressure regulating zone, and the end of the pressure regulating zone 22 furthest from the exhaust port 230 is the second end of the pressure regulating zone. When the gas supply source stops working, the process gas flow rate in the first end of the pressure regulating zone is faster than that in the second end of the pressure regulating zone. Therefore, the gas pressure in the first end of the pressure regulating zone is lower than that in the second end of the pressure regulating zone. This makes it easier for gas in the wafer processing area 21 to flow into the first end of the pressure regulating zone, and the gas flow rate and pressure distribution in the wafer processing area 21 remains uneven.

[0075] In this invention, by adjusting the distribution of the first vent 281, the flow rate of the supplementary gas injected into the pressure regulating zone 22 is adjusted in different regions, so that the mixture of supplementary gas and process gas forms a uniform pressure distribution in the pressure regulating zone 22.

[0076] In this embodiment, as shown in FIG3, the distribution density of the first vent holes 281 gradually increases along the direction near the exhaust port 230. In another embodiment, the aperture of the first vent holes 281 gradually increases along the direction near the exhaust port 230. This allows more supplementary gas to be injected into the region of the pressure regulating zone 22 near the exhaust port 230 to compensate for the lack of process gas. For ease of subsequent description, the bottom liner ring 280 with non-uniformly distributed first vent holes 281 is referred to as the asymmetric bottom liner ring 280a.

[0077] By adjusting the distribution of the first vent 281, the gas pressure distribution within the pressure regulating zone 22 becomes uniform. Consequently, the process gas within the wafer processing zone 21 can flow through various positions of the gas-blocking ring 260 at approximately the same speed. This achieves a dynamic balance between the input and output speeds of the process gas within the wafer processing zone 21, and results in a uniform gas flow field distribution above the wafer W surface. This invention effectively solves the problem of poor uniformity of the process gas on the wafer W surface and inconsistent processing effects across different areas of the wafer W surface when multiple processing chambers 20 of the semiconductor processing equipment 2 share a single vacuum pump 206. Compared to the semiconductor processing equipment 1 with a single processing chamber 10, this invention not only improves the consistency of processing effects across different areas of the wafer W but also increases the processing efficiency of the wafer W.

[0078] Figure 4 shows a symmetrical bottom liner ring 280b, on which multiple first vent holes 281 are evenly distributed. The symmetrical bottom liner ring 280b in Figure 4 is only used for effect comparison; in actual semiconductor processes, the asymmetrical bottom liner ring 280a is still used.

[0079] To verify the effect of the asymmetric bottom liner ring 280a on regulating the airflow field above the wafer W surface, an experiment was conducted in which a symmetric bottom liner ring 280b and an asymmetric bottom liner ring 280a were respectively installed in the two processing cavities 20 of the semiconductor processing device 2. Figure 5 is a schematic diagram of the air passages of the symmetric bottom liner ring 280b and the asymmetric bottom liner ring 280a connected to the vacuum pumping device 2061 in this experiment. In Figure 5, the asymmetric bottom liner ring 280a has only one first vent hole 281 at a position near the venting port 230.

[0080] Figure 6 shows the gas mass flux at various locations along the edge of wafer W within two processing cavities 20, one with a symmetrical bottom liner ring 280b and the other with an asymmetrical bottom liner ring 280a. Gas mass flux is a physical quantity that measures the rate at which gas passes through a surface or interface, measured in kilograms per square meter per second (kg / m²·s). In Figure 6, the horizontal axis represents the position of each point along the edge of wafer W on the X-axis, which is the horizontal axis. The vertical axis represents the gas mass flux. Figure 6 can be understood as the gas mass flux along the circumferential direction of wafer W. The smaller the difference in gas mass flux along the circumferential direction of wafer W, the better the uniformity of gas distribution above the surface of wafer W.

[0081] In Figure 6, arcs abc and efg represent the gas mass flux at the positions closest to and furthest from the vent 230 on the edge of wafer W within the processing cavity 20 employing the asymmetric bottom liner ring 280a, respectively. Arcs ABC and EFG represent the gas mass flux at the positions closest to and furthest from the vent 230 on the edge of wafer W within the processing cavity 20 employing the symmetrical bottom liner ring 280b, respectively. It can be seen that the asymmetric bottom liner ring 280a effectively reduces the difference in gas mass flux along the circumferential direction of wafer W, achieving better airflow uniformity in the circumferential direction of wafer W.

[0082] Figure 7 shows a schematic diagram of the gas mass flux above the surface of wafer W in two processing cavities 20, one with a symmetrical bottom liner ring 280b and the other with an asymmetrical bottom liner ring 280a. Figure 7 further illustrates that the asymmetrical bottom liner ring 280a effectively reduces the difference in gas mass flux above the surface of wafer W, resulting in better gas flow uniformity above the surface of wafer W.

[0083] In this embodiment, as shown in FIG2, the processing chamber 20 also includes a placeholder cylinder 290. The top of the placeholder cylinder 290 is sealed to the bottom of the base 220, and the bottom of the placeholder cylinder 290 is located inside the supplementary gas injection hole 250. In this embodiment, the supplementary gas injection hole 250, the placeholder cylinder 290, and the base 220 are concentrically arranged. As shown in FIG2, the placeholder cylinder 290 divides the gas supply area into a non-communicating flow area 23 and a placeholder area 24 (for example, the bottom of the placeholder cylinder 290 can be set as a closed end). The placeholder area 24 is the area surrounded by the placeholder cylinder 290, and the flow area 23 surrounds the outer periphery of the placeholder area 24. The supplementary gas flows into the supplementary gas injection hole 250 from the outside of the bottom of the placeholder cylinder 290, and sequentially flows into the pressure regulating area 22 from the supplementary gas injection hole 250 and the flow area 23.

[0084] Since the supplementary gas does not enter the occupancy area 24, the diffusion volume of the supplementary gas in the gas replenishment area is reduced by the occupancy cylinder 290. Under the premise of uniformly increasing the pressure in the pressure regulating area 22, the present invention reduces the amount of supplementary gas used, and further saves the economic cost of wafer W processing.

[0085] Furthermore, as shown in Figure 2, a 270 is provided at the top of the partition wall, and the detection port of the main pressure gauge 270 is connected to multiple wafer processing areas 21 through air channels within the partition wall. The main pressure gauge 270 is used to monitor the average air pressure value within the multiple wafer processing areas 21 in real time. By having multiple processing chambers 20 share a single main pressure gauge 270, the economic cost of wafer W processing can be further reduced.

[0086] Furthermore, the processing chamber 20 also includes a first auxiliary pressure gauge 271 and a second auxiliary pressure gauge 272, which are used to measure the air pressure values ​​at the first end of the pressure regulating region and the second end of the pressure regulating region, respectively. Based on the difference between the air pressure values ​​measured by the first auxiliary pressure gauge 271 and the second auxiliary pressure gauge 272, it can be determined whether the desired airflow field distribution has been obtained in the wafer processing region 21.

[0087] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0088] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor processing apparatus, characterized in that, It includes: at least two processing chambers, the two processing chambers sharing a single vacuum pumping device; The processing chamber includes: The base is used to support the wafer; A gas-blocking ring surrounds the outer periphery of the base, dividing the space within the processing cavity into a wafer processing area with gas-connected pathways and a gas replenishment and pressure regulation area. The bottom inner ring divides the gas replenishment and pressure regulation area into a gas replenishment zone and a pressure regulation zone. The gas supply path of the gas replenishment zone is connected to an external gas supply source, and the gas supply path of the pressure regulation zone is connected to the gas replenishment zone, the wafer processing zone, and the vacuum pump. The bottom inner ring has multiple first vent holes that connect the gas replenishment zone and the pressure regulation zone. By adjusting the distribution of the first vent holes, the flow rate of the replenishment gas injected into the pressure regulation zone can be adjusted in different areas to achieve a uniform distribution of the airflow field in the wafer processing zone.

2. The semiconductor processing apparatus as described in claim 1, characterized in that, The processing chamber has an air extraction port at one end near the vacuum device, and the distribution density of the first air vent gradually increases along the direction near the air extraction port.

3. The semiconductor processing apparatus as described in claim 1, characterized in that, The processing chamber has an air extraction port at one end near the vacuum device, and the diameter of the first vent gradually increases along the direction near the air extraction port.

4. The semiconductor processing apparatus as described in claim 1, characterized in that, The air-blocking ring is disposed around the inner wall of the base and the processing chamber, and there is no gap between the air-blocking ring and the inner wall of the base and the processing chamber.

5. The semiconductor processing apparatus as described in claim 4, characterized in that, The gas barrier ring has multiple second vent holes that connect the wafer processing area and the gas replenishment and pressure regulation area, and the second vent holes are evenly distributed.

6. The semiconductor processing apparatus as described in claim 4, characterized in that, The bottom inner liner ring surrounds the outer periphery of the base; the top of the bottom inner liner ring is connected to the inner end of the air-blocking ring, and the bottom of the bottom inner liner ring is fixedly connected to the inner bottom wall of the processing chamber.

7. The semiconductor processing apparatus as claimed in claim 1, characterized in that, The processing chamber has a supplementary gas injection hole at the center of its bottom wall, and the processing chamber also includes a spacer cylinder; the top of the spacer cylinder is sealed to the bottom of the base, and the bottom of the spacer cylinder is located inside the supplementary gas injection hole; the spacer cylinder divides the gas replenishment zone into a non-communicating flow zone and a spacer zone, with the flow zone surrounding the outer periphery of the spacer zone; the supplementary gas flows into the supplementary gas injection hole from the outside of the bottom of the spacer cylinder, and then sequentially flows into the pressure regulating zone from the supplementary gas injection hole and the flow zone.

8. The semiconductor processing apparatus as described in claim 7, characterized in that, The supplementary gas injection hole, the spacer cylinder, and the base are arranged concentrically.

9. The semiconductor processing apparatus as claimed in claim 1, characterized in that, The supplementary gas is an inert gas.

10. The semiconductor processing apparatus as claimed in claim 1, characterized in that, The vacuum pumping device is a gas trapping vacuum pump.

11. The semiconductor processing apparatus as claimed in claim 1, characterized in that, The processing chamber also includes a gas spray head, which is disposed above and opposite the base, for injecting process gas into the wafer processing area.

12. The semiconductor processing apparatus as claimed in claim 11, characterized in that, The process gas includes gases that are corrosive to the inner wall of the processing chamber.

13. The semiconductor processing apparatus as claimed in claim 1, characterized in that, The base is equipped with a heating element.

14. The semiconductor processing apparatus as claimed in claim 1, characterized in that, The base is equipped with cooling fluid channels.

15. The semiconductor processing apparatus as claimed in claim 1, characterized in that, The processing chambers are separated by partition walls; a main pressure gauge is provided on the partition wall, and the detection port of the main pressure gauge is connected to each of the processing chambers through an air passage in the partition wall.

16. The semiconductor processing apparatus as claimed in claim 2, characterized in that, The end of the pressure regulating zone closest to the air extraction port is the first end of the pressure regulating zone, and the end of the pressure regulating zone furthest from the air extraction port is the second end of the pressure regulating zone. The processing chamber also includes a first pressure gauge and a second pressure gauge, which are used to measure the air pressure values ​​at the first end and the second end of the pressure regulating zone, respectively.

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