Display panel and display device

Abstract

The present disclosure relates to the technical field of display, and provides a display panel and a display device. The display panel of the present disclosure has a display area, a peripheral area surrounding the display area, a bonding area located on the side of the peripheral area away from the display area, and a bending area connected between the peripheral area and the bonding area in a bendable manner; and the peripheral area comprises a first transition area close to the bending area. The display panel comprises a base substrate, and signal wires and stress dispersion structures which are arranged on the base substrate, wherein two ends of each signal wire respectively extend from the bending area to the first transition area and the bonding area, and the stress dispersion structures are each at least partially located in the bending area and are configured to disperse bending stress of the signal wires during bending.

Description

Display panel and display device Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display panel and a display device. Background Technology

[0002] With the rapid development of organic light-emitting diodes (OLEDs), the market demands for OLED displays are constantly increasing. Among them, narrow-bezel display products have a higher screen-to-body ratio and can provide users with a better visual experience.

[0003] OLED display panels can bend part of their peripheral structure to the back, thereby reducing bezel size; at the same time, the smaller the bending radius (Bending R), the narrower the bezel. However, a smaller bending radius (Bending R) design can significantly affect process variations such as the application of adhesive (used to protect signal traces in the bending area), resulting in uneven stress distribution in the bending area. This makes the signal traces highly susceptible to cracking, ultimately leading to adverse effects such as bright lines. Summary of the Invention

[0004] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a display panel and a display device.

[0005] In a first aspect, the technical solution adopted to solve the technical problem of this disclosure is a display panel having a display area, a peripheral area surrounding the display area, a binding area located on the side of the peripheral area away from the display area, and a bent area connecting the peripheral area and the binding area; the peripheral area includes a first transition area near the bent area.

[0006] The display panel includes a substrate, signal traces disposed on the substrate, and a stress dispersion structure; wherein, both ends of the signal traces extend from the bending area to the first transition area and the bonding area, respectively;

[0007] The stress-dispersing structure is located at least partially in the bending region and is used to disperse the bending stress when the signal trace is bent.

[0008] In some embodiments, the display panel includes a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer disposed sequentially along a direction away from the substrate.

[0009] The source and drain of the transistor in the pixel driving circuit are both disposed in at least one of the first conductive layer, the second conductive layer and the third conductive layer; the signal trace is located in the second conductive layer.

[0010] In some embodiments, the orthographic projection of the stress dispersion structure on the substrate lies between the orthographic projections of adjacent signal traces on the substrate.

[0011] In some embodiments, the stress dispersion structure is disposed on the same layer as the signal trace.

[0012] In some embodiments, the stress-dispersing structure is located in the first conductive layer or the third conductive layer.

[0013] In some embodiments, the stress dispersion structure is a first substructure located in the first conductive layer;

[0014] The orthographic projection of the first substructure onto the substrate at least partially overlaps with the orthographic projection of the signal trace onto the substrate.

[0015] In some embodiments, the stress dispersion structure is a second substructure located in the third conductive layer;

[0016] The orthographic projection of the second substructure onto the substrate at least partially overlaps with the orthographic projection of the signal trace onto the substrate.

[0017] In some embodiments, the stress dispersion structure includes a first substructure located in the first conductive layer and a second substructure located in the third conductive layer;

[0018] The first substructure, the second substructure, and the signal trace have at least partial overlap in their orthogonal projections onto the substrate.

[0019] In some embodiments, the two ends of the first substructure are electrically connected to the two ends of the signal trace through two first connection vias penetrating the first insulating layer; the two ends of the second substructure are electrically connected to the two ends of the signal trace through two second connection vias penetrating the second insulating layer.

[0020] In some embodiments, the stress dispersion structure includes a third substructure located in the first conductive layer; the signal trace includes a first trace located in the bending region, a second trace located in the first transition region, and a third trace located in the bonding region; the orthographic projection of the third substructure on the substrate overlaps with the orthographic projection of the first trace on the substrate.

[0021] The first insulating layer includes a first slot located in the bending region; the first slot penetrates the first insulating layer along its thickness direction.

[0022] The first trace and the third substructure are in contact through the first slot.

[0023] In some embodiments, the stress dispersion structure includes a fourth substructure located in the third conductive layer; the signal trace includes a first trace located in the bending region, a second trace located in the first transition region, and a third trace located in the bonding region; the orthographic projection of the fourth substructure on the substrate overlaps with the orthographic projection of the first trace on the substrate.

[0024] The second insulating layer includes a second slot located in the bending region; the second slot penetrates the second insulating layer along its thickness direction.

[0025] The first trace and the fourth substructure are in contact through the second slot.

[0026] In some embodiments, the first insulating layer includes a plurality of first grooves extending along a first direction; the first grooves penetrate at least a portion of the first insulating layer along the thickness direction of the second insulating layer; the first direction is intersecting the extension direction of the signal trace.

[0027] A plurality of first grooves are arranged side by side along the signal trace extension direction, and at least a portion of the plurality of first grooves are distributed in the bending area;

[0028] The signal trace falls into the first groove in its extension direction, and the signal trace falling into the first groove is multiplexed as the fifth substructure of the stress dispersion structure.

[0029] In some embodiments, the first groove includes a first sidewall and a first bottom wall, and the dihedral angle between the extended surface of the first sidewall and the plane containing the first bottom wall is an acute angle.

[0030] In some embodiments, the second insulating layer includes a plurality of second grooves extending along a first direction; the second grooves penetrate at least a portion of the second insulating layer along its thickness direction; the first direction intersects the extension direction of the signal trace.

[0031] A plurality of second grooves are arranged side by side along the signal trace extension direction, and at least a portion of the plurality of second grooves are distributed in the bending area;

[0032] The stress dispersion structure includes a sixth substructure located in the third conductive layer, and the orthographic projection of the sixth substructure on the substrate overlaps with the orthographic projection of the signal trace on the substrate.

[0033] In the extension direction of the signal trace, the portion of the sixth substructure that falls into the second groove contacts the signal trace.

[0034] In some embodiments, a plurality of second grooves and a plurality of first grooves are alternately arranged in orthographic projection on the substrate.

[0035] In some embodiments, the second conductive layer includes a first titanium material layer, an aluminum material layer, and a second titanium material layer disposed sequentially along a direction away from the substrate.

[0036] In some embodiments, the signal trace includes a first trace located in the bending region, a second trace located in the first transition region, and a third trace located in the bonding region; the first trace is located in the aluminum material layer.

[0037] In some embodiments, the signal trace includes a first trace located in the bend region, a second trace located in the first transition region, and a third trace located in the bonding region;

[0038] The first trace includes a first sub-trace located in the aluminum material layer and a second sub-trace located in the second titanium material layer.

[0039] In some embodiments, the first titanium material layer includes a first opening located in the bending region, a portion of the aluminum material layer and a portion of the second titanium material layer located in the bending region fall into the first opening, and the portion of the aluminum material layer and the portion of the second titanium material layer falling into the first opening are reused as the stress dispersion structure.

[0040] In some embodiments, the first titanium material layer includes a first opening located in the bending region, and the second titanium material layer includes a second opening located in the bending region, the second opening exposing a portion of the aluminum material layer located in the bending region;

[0041] A portion of the aluminum material layer located in the bending area falls into the first opening, and the portion of the aluminum material layer falling into the first opening is reused as the stress dispersion structure.

[0042] Secondly, embodiments of this disclosure also provide a display device, including a display panel as described in any one of the first aspects. Attached Figure Description

[0043] Figures 1a and 1b are schematic diagrams of two different types of signal traces;

[0044] Figure 2 is a schematic diagram of cracks caused by bending of signal traces in related technologies;

[0045] Figure 3 is a plan view of the display panel provided in an embodiment of this disclosure;

[0046] Figure 4 is a schematic diagram of the stacking of various film layers located in the display area according to an embodiment of this disclosure;

[0047] Figures 5a and 5b are schematic diagrams of the stress dispersion structure under different types of signal traces and Example 1, respectively.

[0048] Figures 6a and 6b are schematic diagrams of the stress dispersion structure under different types of signal traces and Example 2, respectively.

[0049] Figure 7a is a cross-sectional schematic diagram of an example of signal traces and stress dispersion structure;

[0050] Figure 7b is a cross-sectional schematic diagram of another example of signal traces and stress dispersion structure;

[0051] Figures 8a and 8b are schematic diagrams of the stress dispersion structure under different types of signal traces and Example 3, respectively.

[0052] Figure 8c is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 3;

[0053] Figures 9a and 9b are schematic diagrams of the stress dispersion structure under different types of signal traces and Example 4, respectively.

[0054] Figure 9c is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 4;

[0055] Figures 10a and 10b are schematic diagrams of the stress dispersion structure under different types of signal traces and Example 5, respectively.

[0056] Figure 10c is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 5;

[0057] Figure 11 is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 6;

[0058] Figure 12 is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 7;

[0059] Figure 13 is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 8;

[0060] Figures 14a and 14b are schematic diagrams of the stress dispersion structure under different types of signal traces and Example 9, respectively.

[0061] Figure 14c is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 9;

[0062] Figures 15a and 15b are schematic diagrams of the stress dispersion structure under different types of signal traces and Example 10, respectively.

[0063] Figure 15c is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 10;

[0064] Figure 16 is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 11;

[0065] Figure 17 is a cross-sectional schematic diagram of the second conductive layer located in the display area;

[0066] Figure 18 is a cross-sectional schematic diagram of a second conductive layer located in the bending region;

[0067] Figure 19 is a cross-sectional schematic diagram of another type of second conductive layer located in the bending region;

[0068] Figure 20 is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 12;

[0069] Figure 21 is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 13. Detailed Implementation

[0070] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0071] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0072] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0073] In related technologies, the bezels of OLED display panels are becoming increasingly narrow, and the bending radius (Bending R) is also constantly decreasing, which can easily lead to uneven stress distribution within the bending area (CC). As shown in Figures 1a and 1b, these represent two types of signal trace designs: a chain-like structure trace and a straight trace, respectively. However, in the area with the smallest bending radius—which depends on the actual product and could be the bending center or the bending start area—both can produce bending cracks in the signal trace, as shown in Figure 2.

[0074] In view of this, the present disclosure provides a display panel. FIG3 is a plan view of the display panel provided in the present disclosure. As shown in FIG3, the display panel has a display area AA, a peripheral area BB surrounding the display area AA, a bonding area DD located on the side of the peripheral area BB away from the display area AA, and a bending area CC that bends and connects the peripheral area BB and the bonding area DD. The peripheral area BB includes a first transition area BB1 near the bending area CC. The display panel includes a substrate 1, signal traces 4 (not shown in FIG3, see the figures in Examples 1 to 13 below) disposed on the substrate 1, and a stress dispersion structure 5 (not shown in FIG3, see the figures in Examples 1 to 13 below). The two ends of the signal traces 4 extend from the bending area CC to the first transition area BB1 and the bonding area DD, respectively. For example, one end of the signal traces 4 extends to the first transition area BB1 and is electrically connected to a signal line extending from the display area AA to the first transition area BB1. This signal line is, for example, a touch electrode or a data line. The other end of the signal traces 4 extends to the bonding area DD and is electrically connected to a driver chip located in the bonding area DD. The display panel is bent in the bending zone CC, causing structures on the bonding zone DD (such as driver chips) to bend towards the backlight side of the display panel, thus achieving a narrow bezel. The stress-dispersing structure 5 is at least partially located in the bending zone CC to disperse the bending stress of the signal trace 4 when it is bent.

[0075] The present invention essentially eliminates bending crack defects caused by defects in related technologies by adding a stress dispersion structure 5 to the bending region CC to disperse the bending stress of the signal trace 4 located in the bending region CC during bending.

[0076] Before describing the stress dispersion structure 5 in detail, it is necessary to determine the location of the signal trace 4 of this disclosure. In some embodiments, FIG4 is a stacked schematic diagram of the various film layers located in the display area provided by an embodiment of this disclosure. As shown in FIG4, the display panel includes a first conductive layer SD1, a first insulating layer PLN1, a second conductive layer SD2, a second insulating layer PLN2, and a third conductive layer SD3 sequentially disposed along the direction away from the substrate 1; the display panel includes a light-emitting device 2 and a pixel driving circuit 3 for driving the light-emitting device 2; the source and drain of the transistor in the pixel driving circuit 3 are both disposed in at least one of the first conductive layer SD1, the second conductive layer SD2, and the third conductive layer SD3. For example, the source and drain of the transistor in the pixel driving circuit 3 are disposed in the same layer and are arranged in a three-layer trace layout, respectively disposed in the first conductive layer SD1, the second conductive layer SD2, and the third conductive layer SD3. Meanwhile, the signal trace 4 is located in the second conductive layer SD2 and can be electrically connected to the source or drain of the transistor in the pixel driving circuit 3.

[0077] For example, the light-emitting device 2 is an OLED device. The pixel driving circuit 3 is a relatively complex circuit structure, such as a 7T1C (7 transistors and 1 capacitor, as shown in Figure 4, the driving transistor TFT and the storage capacitor Cst) driving circuit. The source and drain of multiple transistors, as well as the electrical connection structure of the source or drain of multiple transistors, can be implemented through the first conductive layer SD1, the second conductive layer SD2, and the third conductive layer SD3, for example, by implementing cross-layer electrode connections through vias penetrating the first insulating layer PLN1 and / or the second insulating layer PLN2.

[0078] To address the cracking issue in the CC signal trace 4 in the bending region, the stress dispersion structure 5 will be explained in detail below with a specific example.

[0079] In some embodiments, the orthographic projection of the stress dispersion structure 5 on the substrate 1 is located between the orthographic projections of adjacent signal traces 4 on the substrate 1, so as to disperse the bending stress of the signal traces 4 located in the bending region CC by means of the stress dispersion structure 5.

[0080] Optionally, Figures 5a and 5b are schematic diagrams of the stress dispersion structure under different types of signal traces and Example 1, respectively. As shown in Figures 5a and 5b, the orthographic projection of the stress dispersion structure 5 on the substrate 1 is spaced apart from the orthographic projection of the adjacent signal trace 4 on the substrate 1. In this example, the stress dispersion structure 5 is disposed between adjacent signal traces 4 and spaced apart. By using the narrower stress dispersion structure 5, the bending stress of the signal trace 4 located in the bending region CC is dispersed without increasing the bending stress of the stress dispersion structure 5 itself.

[0081] Optionally, Figures 6a and 6b are schematic planar views of different types of signal traces and stress dispersion structures under Example 2, respectively. As shown in Figures 6a and 6b, the orthographic projection of the stress dispersion structure 5 on the substrate 1 is in contact with the orthographic projection of the adjacent signal trace 4 on the substrate 1.

[0082] Optionally, as shown in Figures 6a and 6b, the stress dispersion structure 5 includes a plurality of through holes V0 extending along its thickness direction, which further disperse the bending stress of the stress dispersion structure 5.

[0083] Optionally, for Examples 1 and 2, Figure 7a is a cross-sectional schematic diagram of an example of signal trace and stress dispersion structure. As shown in Figure 7a, the stress dispersion structure 5 and the signal trace 4 are arranged in layers. For example, the stress dispersion structure 5 is located in the third conductive layer SD3.

[0084] Alternatively, for Example 1 and / or Example 2, Figure 7b is a cross-sectional schematic diagram of another example of signal traces and stress dispersion structure, as shown in Figure 7b, where stress dispersion structure 5 is located in the first conductive layer SD1.

[0085] Optionally, for Example 1 and / or Example 2, the stress dispersion structure 5 is disposed on the same layer as the signal trace 4, that is, both are located on the second conductive layer SD2.

[0086] In some embodiments, the stress dispersion structure 5 includes a first substructure 51 located on the first conductive layer SD1; the orthographic projection of the first substructure 51 on the substrate 1 at least partially overlaps with the orthographic projection of the signal trace 4 on the substrate 1. In this embodiment, the stress dispersion structure 5 is disposed on the signal trace 4 and forms a double-layer composite film (SD1+SD2 double-layer composite film) with the signal trace 4, thereby improving the bending stress of the overall bending structure of the bending region CC.

[0087] Figures 8a and 8b are schematic diagrams of different types of signal traces and stress dispersion structures under Example 3, respectively. It should be noted that, for ease of understanding, the film layer of the stress dispersion structure 5 in this schematic diagram is made transparent to show the signal trace 4 underneath, but this does not mean that the actual structure of the film layer is a transparent film layer. In addition, to more clearly show the film layer structure, the film layers are misaligned. The actual film layer stacking structure is subject to the actual description in the instruction manual. As shown in Figures 8a and 8b, the two ends of the first substructure 51 extend from the bending region CC to the first transition region BB1 and the bonding region DD, respectively. The orthographic projection of the first substructure 51 on the substrate 1 completely overlaps with the orthographic projection of the signal trace 4 on the substrate 1.

[0088] The display panel includes multiple signal traces 4, which are arranged side-by-side along a first direction X. The stress dispersion structure 5 includes multiple first substructures 51 arranged side-by-side along the first direction X. The extension direction of the first substructures 51 is the same as the extension direction of the signal traces 4, which is a second direction Y. The first direction X intersects the second direction Y. For example, the first direction X is perpendicular to the second direction Y.

[0089] Optionally, Figure 8c is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 3. As shown in Figure 8c, the two ends of the first substructure 51 and the two ends of the signal trace 4 are electrically connected through two first connection vias V1 penetrating the first insulating layer PLN1. In this example, the first substructure 51 and the signal trace 4 are connected end-to-end, achieving parallel routing, which can improve the problem of signal trace 4 breaking and opening due to abnormal particles. Because, if the signal trace 4 is open, the signal path can be maintained by means of the first substructure 51 connected end-to-end with it.

[0090] Optionally, the first substructure 51 and the signal trace 4 are spaced apart, that is, a first insulating layer PLN1 is provided between them.

[0091] In some embodiments, the stress dispersion structure 5 is a second substructure 52 located in the third conductive layer SD3; the orthographic projection of the second substructure 52 on the substrate 1 at least partially overlaps with the orthographic projection of the signal trace 4 on the substrate 1. In this embodiment, the stress dispersion structure 5 is disposed below the signal trace 4 and forms a double-layer composite film (SD2+SD3 double-layer composite film) with the signal trace 4, thereby improving the bending stress of the overall bending structure of the bending region CC.

[0092] Figures 9a and 9b are schematic planar representations of different types of signal traces and the stress dispersion structure in Example 4, respectively. It should be noted that, for ease of understanding, the film layer of the stress dispersion structure 5 in these schematics is made transparent to allow the signal trace 4 underneath to be seen; however, this does not mean that the actual structure of the film layer is transparent. As shown in Figures 9a and 9b, the two ends of the second substructure 52 extend from the bending region CC to the first transition region BB1 and the bonding region DD, respectively. The orthographic projection of the second substructure 52 on the substrate 1 completely overlaps with the orthographic projection of the signal trace 4 on the substrate 1. The extension direction of the second substructure 52 is the same as the extension direction of the signal trace 4, both being the second direction Y.

[0093] Optionally, Figure 9c is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 4. As shown in Figure 9c, the two ends of the second substructure 52 and the two ends of the signal trace 4 are electrically connected through two second connection vias V2 penetrating the second insulating layer PLN2. In this example, the second substructure 52 and the signal trace 4 are connected end-to-end, achieving parallel routing, which can improve the problem of signal trace 4 breaking and opening due to abnormal particles. Because, if the signal trace 4 is open, the signal path can be maintained by means of the second substructure 52 connected to it end-to-end.

[0094] Optionally, the second substructure 52 is spaced apart from the signal trace 4, that is, a second insulating layer PLN2 is provided between the two.

[0095] In some embodiments, the stress dispersion structure 5 includes a first substructure 51 located in the first conductive layer SD1 and a second substructure 52 located in the third conductive layer SD3; the orthogonal projections of the first substructure 51, the second substructure 52 and the signal trace 4 on the substrate 1 at least partially overlap.

[0096] Figures 10a and 10b are schematic planar representations of different types of signal traces and the stress dispersion structure in Example 5, respectively. It should be noted that, for ease of understanding, the film layer of the stress dispersion structure 5 in these schematics is made transparent to allow the signal trace 4 underneath to be seen; however, this does not mean that the actual structure of the film layer is transparent. The difference between Example 6 and Example 4 is the addition of a second substructure 52. The difference between Example 6 and Example 5 is the addition of a first substructure 51. As shown in Figures 10a and 10b, the orthographic projections of the first substructure 51 and the second substructure 52 on the substrate 1 completely overlap, and this completely overlapping orthographic projection covers the orthographic projection of the signal trace 4 on the substrate 1.

[0097] Optionally, Figure 10c is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 5. As shown in Figure 10c, the two ends of the first substructure 51 are electrically connected to the two ends of the signal trace 4 through two first connecting vias V1 penetrating the first insulating layer PLN1, respectively; the two ends of the second substructure 52 are electrically connected to the two ends of the signal trace 4 through two second connecting vias V2 penetrating the second insulating layer PLN2, respectively. In this example, the first substructure 51 is connected end-to-end to the signal trace 4, and the second substructure 52 is also connected end-to-end to the signal trace 4. The three are connected in parallel in pairs, which can improve the problem of signal trace 4 breaking and opening due to abnormal particles. Because, if the signal trace 4 is open, the signal path can be maintained by means of the first substructure 51 and / or the second substructure 52 connected to it end-to-end.

[0098] Optionally, the first substructure 51 is spaced apart from the signal trace 4, that is, a first insulating layer PLN1 is provided between the two; the second substructure 52 is spaced apart from the signal trace 4, that is, a second insulating layer PLN2 is provided between the two.

[0099] In some embodiments, FIG11 is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 6. As shown in FIG11, the stress dispersion structure 5 includes a third substructure 53 located in the first conductive layer SD1; the signal trace 4 includes a first trace 41 located in the bending region CC, a second trace 42 located in the first transition region BB1, and a third trace 43 located in the bonding region DD; the orthographic projection of the third substructure 53 on the substrate 1 overlaps with the orthographic projection of the first trace 41 on the substrate 1; the first insulating layer PLN1 includes a first slot 61 located in the bending region CC; the first slot 61 penetrates the first insulating layer PLN1 along the thickness direction; wherein, the first trace 41 and the third substructure 53 are in contact through the first slot 61. Specifically, the surface of the third substructure 53 facing away from the substrate 1 is in direct contact with the surface of the first trace 41 near the substrate 1.

[0100] For example, the first slot 61 penetrates the first insulating layer PLN1 along its thickness direction, exposing the third substructure 53, so that the first trace 41 formed thereon falls directly into the first slot 61 and makes direct contact with the exposed third substructure 53. Alternatively, the third substructure 53 is disposed within the first slot 61, so that the first trace 41 formed thereon makes direct contact with the surface of the third substructure 53 away from the substrate 1.

[0101] This embodiment indirectly increases the material thickness of the first trace 41 located in the bending region CC by adding a third substructure 53 that is in direct contact with the first trace 41, thereby improving the stress concentration of the signal trace 4 in the bending region CC.

[0102] Optionally, the thickness of the third substructure 53 is greater than or equal to the thickness of the first trace 41. The thickness of the third substructure 53 is 1 to 2 times the thickness of the first trace 41.

[0103] Optionally, the signal traces 4 may include multiple traces, and the first slots 61 may include multiple slots. Each first slot 61 corresponds to one signal trace 4. Each third substructure 53 corresponds to one signal trace 4.

[0104] In some embodiments, FIG12 is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 7. As shown in FIG12, the stress dispersion structure 5 includes a fourth substructure 54 located in the third conductive layer SD3; the signal trace 4 includes a first trace 41 located in the bending region CC, a second trace 42 located in the first transition region BB1, and a third trace 43 located in the bonding region DD; the orthographic projection of the fourth substructure 54 on the substrate 1 overlaps with the orthographic projection of the first trace 41 on the substrate 1; the second insulating layer PLN2 includes a second slot 62 located in the bending region CC; the second slot 62 penetrates the second insulating layer PLN2 along the thickness direction of the second insulating layer PLN2; the first trace 41 and the fourth substructure 54 are in contact through the second slot 62. Specifically, the surface of the fourth substructure 54 near the substrate 1 is in direct contact with the surface of the first trace 41 away from the substrate 1.

[0105] For example, the second slot 62 penetrates the second insulating layer PLN2 along the thickness direction (i.e., the third direction Z) and exposes the first trace 41, so that the fourth substructure 54 formed thereon falls directly into the second slot 62 and directly contacts the exposed first trace 41 away from the surface of the substrate 1.

[0106] This embodiment indirectly increases the material thickness of the first trace 41 located in the bending region CC by adding a fourth substructure 54 that is in direct contact with the first trace 41, thereby improving the stress concentration of the signal trace 4 in the bending region CC.

[0107] Optionally, the thickness of the fourth substructure 54 is greater than or equal to the thickness of the first trace 41. The thickness of the fourth substructure 54 is 1 to 2 times the thickness of the first trace 41.

[0108] Optionally, the signal trace 4 may include multiple traces, and the second slot 62 may include multiple slots. Each second slot 62 corresponds to one signal trace 4. Each fourth substructure 54 corresponds to one signal trace 4.

[0109] In some embodiments, FIG13 is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure under Example 8. The difference between Example 8 and Example 6 is that a fourth substructure 54 is added; the difference between Example 8 and Example 7 is that a third substructure 53 is added. As shown in Figure 13, the stress dispersion structure 5 includes a third substructure 53 located in the first conductive layer SD1 and a fourth substructure 54 located in the third conductive layer SD3. The orthographic projection of the third substructure 53 on the substrate 1 overlaps with the orthographic projection of the first trace 41 on the substrate 1. The orthographic projection of the fourth substructure 54 on the substrate 1 overlaps with the orthographic projection of the first trace 41 on the substrate 1. The first insulating layer PLN1 includes a first slot 61 located in the bending region CC. The first slot 61 penetrates the first insulating layer PLN1 along its thickness direction. The first trace 41 and the third substructure 53 are in contact through the first slot 61. The second insulating layer PLN2 includes a second slot 62 located in the bending region CC. The second slot 62 penetrates the second insulating layer PLN2 along its thickness direction. The first trace 41 and the fourth substructure 54 are in contact through the second slot 62. Specifically, the surface of the third substructure 53 away from the substrate 1 is in direct contact with the surface of the first trace 41 near the substrate 1; the surface of the fourth substructure 54 near the substrate 1 is in direct contact with the surface of the first trace 41 away from the substrate 1.

[0110] This embodiment indirectly increases the material thickness of the first trace 41 located in the bending region CC by adding a third substructure 53 and a fourth substructure 54 that are in direct contact with the first trace 41, thereby improving the stress concentration of the signal trace 4 in the bending region CC.

[0111] Optionally, the first conductive layer SD1, the second conductive layer SD2, and the third conductive layer SD3 have the same thickness. That is, the thicknesses of the third substructure 53, the fourth substructure 54, and the first trace 41 are all equal. This embodiment improves the stress concentration of the trace in the bending region CC by increasing the thickness of the first trace 41 located in the bending region CC by 200%.

[0112] Alternatively, the improvement of stress concentration in the bending area CC trace in this embodiment can also be understood as using the third substructure 53 as a sacrificial layer, or the fourth substructure 54 as a tensile stress sacrificial layer, to ensure the structural integrity of the first trace 41.

[0113] In some embodiments, Figures 14a and 14b are planar schematic diagrams of different types of signal traces and stress dispersion structures under Example 9, respectively, and Figure 14c is a cross-sectional schematic diagram of signal traces and stress dispersion structures under Example 9. As shown in Figures 14a and 14c, the first insulating layer PLN1 includes a plurality of first grooves 71 extending along a first direction X; the first grooves 71 penetrate at least a portion of the first insulating layer PLN1 along the thickness direction (third direction Z) of the second insulating layer PLN2; the first direction X intersects the extension direction (second direction Y) of the signal trace 4, for example, the first direction X is perpendicular to the second direction Y. The plurality of first grooves 71 are arranged side by side along the extension direction of the signal trace 4, and at least a portion of the plurality of first grooves 71 are distributed in the bending region CC. The first grooves 71 extend along the first direction X, and their orthographic projection on the substrate 1 spans the orthographic projection of each signal trace 4 on the substrate 1. The signal trace 4 falls into the first groove 71 in its extension direction, and the signal trace 4 falling into the first groove 71 is multiplexed as the fifth substructure 55 of the stress dispersion structure 5. In this embodiment, by designing a groove in the first insulating layer PLN1, the signal trace 4 is distributed in a serpentine pattern, such as a horizontal "bow" shape, at least within the bending area CC. This increases the length of the signal trace 4, thereby alleviating bending stress. When bending, the stress is concentrated more in the first groove 71 of the first insulating layer PLN1, rather than on the plane of the signal trace 4.

[0114] Optionally, the first groove 71 penetrates a portion of the first insulating layer PLN1 along the third direction Z, that is, the first groove 71 is a blind groove.

[0115] Optionally, as shown in Figure 14c, the first groove 71 penetrates the first insulating layer PLN1 along the third direction Z, that is, the first groove 71 is a through groove.

[0116] Optionally, as shown in Figures 14a and 14b, a plurality of first grooves 71 are evenly distributed in the bending region CC, the first transition region BB1 in a portion of the sub-region near the bending region CC, and the binding region DD in a portion of the sub-region near the bending region CC.

[0117] Optionally, as shown in FIG14c, the first groove 71 includes a first sidewall and a first bottom wall, and the dihedral angle a1 between the extended surface of the first sidewall and the plane where the first bottom wall is located is an acute angle to prevent stress concentration.

[0118] In some embodiments, Figures 15a and 15b are planar schematic diagrams of different types of signal traces and stress dispersion structures under Example 10, respectively, and Figure 15c is a cross-sectional schematic diagram of signal traces and stress dispersion structures under Example 10. As shown in Figures 15a and 15c, the difference from Example 9 is that the stress dispersion structure 5 further includes a sixth substructure 56. Specifically, the second insulating layer PLN2 includes a plurality of second grooves 72 extending along the first direction X; the second grooves 72 penetrate at least a portion of the second insulating layer PLN2 along the thickness direction (third direction Z); the first direction X intersects the extension direction (second direction Y) of the signal trace 4, for example, the first direction X is perpendicular to the second direction Y. The plurality of second grooves 72 are arranged side by side along the extension direction of the signal trace 4, and at least a portion of the plurality of second grooves 72 are distributed in the bending region CC. The second grooves 72 extend along the first direction X, and their orthographic projection on the substrate 1 spans the orthographic projection of each signal trace 4 on the substrate 1. The stress dispersion structure 5 includes a sixth substructure 56 located in the third conductive layer SD3. The orthographic projection of the sixth substructure 56 on the substrate 1 overlaps with the orthographic projection of the signal trace 4 on the substrate 1. In the extension direction of the signal trace 4, the portion of the sixth substructure 56 that falls into the second groove 72 contacts the signal trace 4. In this embodiment, by designing grooves in the first insulating layer PLN1 and the second insulating layer PLN2, the signal trace 4 and the sixth substructure 56 are respectively distributed in a serpentine pattern, such as a horizontal "bow" shape, at least within the bending region CC. This increases the length of the signal trace 4 and also increases the length of the sixth substructure 56, thereby alleviating bending stress. During bending, the stress is concentrated more in the first groove 71 and the second groove 72, rather than in the plane of the signal trace 4.

[0119] Optionally, as shown in Figure 15c, the second groove 72 penetrates the second insulating layer PLN2 along the third direction Z, that is, the second groove 72 is a through groove. The sixth substructure 56 contacts the signal trace 4 through the second groove 72.

[0120] Optionally, a plurality of second grooves 72 are evenly distributed in the bending region CC, the portion of the first transition region BB1 near the bending region CC, and the portion of the binding region DD near the bending region CC.

[0121] Optionally, as shown in Figure 15c, the second groove 72 includes a second sidewall and a second bottom wall, and the dihedral angle a2 between the extended surface of the second sidewall and the plane where the second bottom wall is located is an acute angle to prevent stress concentration.

[0122] Optionally, the sixth substructure 56 is configured in a one-to-one correspondence with the signal trace 4. The extension direction of the sixth substructure 56 is the same as the extension direction of the signal trace 4. The orthographic projection of the sixth substructure 56 on the substrate 1 completely overlaps with the orthographic projection of the signal trace 4 on the substrate 1.

[0123] Optionally, the orthographic projections of the plurality of second grooves 72 and the plurality of first grooves 71 on the substrate 1 are alternately arranged.

[0124] In some embodiments, FIG16 is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 11. As shown in FIG16, the second insulating layer PLN2 includes a plurality of second grooves 72 extending along a first direction X; the second grooves 72 penetrate at least a portion of the second insulating layer PLN2 along the thickness direction (third direction Z); the first direction X intersects the extension direction (second direction Y) of the signal trace 4, for example, the first direction X is perpendicular to the second direction Y. The plurality of second grooves 72 are arranged side by side along the extension direction of the signal trace 4, and at least a portion of the plurality of second grooves 72 are distributed in the bending region CC. The second grooves 72 extend along the first direction X, and their orthographic projection on the substrate 1 spans the orthographic projection of each signal trace 4 on the substrate 1. The stress dispersion structure 5 includes a sixth substructure 56 located in the third conductive layer SD3, the orthographic projection of the sixth substructure 56 on the substrate 1 overlaps with the orthographic projection of the signal trace 4 on the substrate 1; in the extension direction of the signal trace 4, the portion of the sixth substructure 56 falling into the second groove 72 contacts the signal trace 4. In this embodiment, by designing a groove in the second insulating layer PLN2, the sixth substructure 56 is distributed in a serpentine pattern, such as a horizontal "bow" shape, at least within the bending area CC. This increases the length of the sixth substructure 56, thereby alleviating bending stress. When bending, the stress is concentrated more in the second groove 72, rather than in the plane of the signal trace 4.

[0125] In this disclosure, the first groove 71 and / or the second groove 72 can be prepared using a halftone mask (also known as a grayscale mask) process. A halftone mask is formed by attaching a semi-transparent light-blocking film to a photomask so that the light transmittance gradually decreases from the center of the groove to the edge, thereby forming a trapezoidal groove.

[0126] In some embodiments, FIG17 is a cross-sectional schematic diagram of the second conductive layer located in the display area. As shown in FIG17, the second conductive layer SD2 includes a first titanium material layer 81, an aluminum material layer 82, and a second titanium material layer 83 sequentially disposed along the direction away from the substrate 1. The first titanium material layer 81 and the second titanium material layer 83 are both made of titanium; the aluminum material layer 82 is made of aluminum. The lower titanium (Ti) metal layer serves as a barrier layer, effectively preventing electromigration of aluminum and thus extending the lifespan of the light-emitting device 2. The upper titanium (Ti) metal layer serves as an anti-reflection layer, effectively reducing standing wave effects and improving the signal transmission quality and stability of the circuit.

[0127] This embodiment can be combined with any of the above embodiments to further disperse the stress in the bending zone CC by means of the stress dispersion structure 5, thereby improving the crack defect.

[0128] Optionally, the first conductive layer SD1 and the second conductive layer SD2 adopt the same structural design, namely Ti / Al / Ti.

[0129] Optionally, the third conductive layer SD3 and the second conductive layer SD2 adopt the same structural design, namely Ti / Al / Ti.

[0130] In some embodiments, FIG18 is a cross-sectional schematic diagram of a second conductive layer located in the bending region. As shown in FIG18, the first trace 41 of the signal trace 4 in the bending region CC is located in the aluminum material layer 82. That is, the difference between the first trace 41 and the signal trace 4 in the display area AA is that the first trace 41 adopts a single-layer aluminum material layer 82 design, which ensures that the first titanium metal layer in the display area AA can directly contact the active layer of the transistor, and also ensures that only the aluminum material layer 82 is left in the bending region CC. By utilizing the high ductility, bending modulus and variability of the aluminum material layer 82, the cracking defects of the first trace 41 during bending are improved.

[0131] This embodiment can be combined with any of the above embodiments to further disperse the stress in the bending zone CC by means of the stress dispersion structure 5, thereby improving the crack defect.

[0132] Optionally, the first conductive layer SD1 and the second conductive layer SD2 shown in Figure 18 adopt the same structural design. Optionally, the third conductive layer SD3 and the second conductive layer SD2 shown in Figure 18 adopt the same structural design.

[0133] In some embodiments, FIG19 is a cross-sectional schematic diagram of another second conductive layer located in the bending region. As shown in FIG19, the first trace 41 includes a first sub-trace 411 located in the aluminum material layer 82 and a second sub-trace 412 located in the second titanium material layer 83. That is, the difference between the first trace 41 and the signal trace 4 in the display area AA is that it adopts a double-layer design of a lower aluminum material layer 82 and an upper titanium material layer. This ensures that the first titanium metal layer in the display area AA can directly contact the active layer of the transistor, and also ensures that the first titanium material layer 81 is etched away in the bending region CC. By utilizing the high ductility, bending modulus and variability of the aluminum material layer 82, the crack defects of the first trace 41 during bending are improved. At the same time, the second titanium material layer 83 is used as an anti-reflection layer, which can effectively reduce the standing wave effect and improve the signal transmission quality and stability of the circuit.

[0134] This embodiment can be combined with any of the above embodiments to further disperse the stress in the bending zone CC by means of the stress dispersion structure 5, thereby improving the crack defect.

[0135] Optionally, the first conductive layer SD1 and the second conductive layer SD2 shown in Figure 19 adopt the same structural design. Optionally, the third conductive layer SD3 and the second conductive layer SD2 shown in Figure 19 adopt the same structural design.

[0136] Optionally, each sublayer in the second conductive layer SD2 shown in Figures 18 and / or 19 can be formed using a mask process with a specific pattern. Alternatively, it can be formed by etching after coating the entire layer with material.

[0137] In some embodiments, FIG20 is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure in Example 12. As shown in FIG20, the first titanium material layer 81 includes a first opening 91 located in the bending region CC. A portion of the aluminum material layer 82 and a portion of the second titanium material layer 83 located in the bending region CC fall into the first opening 91. The portion of the aluminum material layer 82 and the portion of the second titanium material layer 83 falling into the first opening 91 are reused to form the stress dispersion structure 5. By etching away the first titanium material layer 81 located in the bending region CC to form the first opening 91, only the aluminum material layer 82 and the first titanium material layer 81 are retained in the bending region CC. By utilizing the characteristics of the aluminum material layer 82, stress concentration is improved, thereby improving crack defects.

[0138] In some embodiments, FIG21 is a cross-sectional schematic diagram of the signal trace and the stress dispersion structure under Example 13. As shown in FIG21, the first titanium material layer 81 includes a first opening 91 located in the bending region CC, and the second titanium material layer 83 includes a second opening 92 located in the bending region CC. The second opening 92 exposes a portion of the aluminum material layer 82 located in the bending region CC. The portion of the aluminum material layer 82 located in the bending region CC falls into the first opening 91, and the portion of the aluminum material layer 82 falling into the first opening 91 is reused as the stress dispersion structure 5. The first opening 91 is formed by etching away the first titanium material layer 81 located in the bending region CC; and the second opening 92 is formed by etching away the second titanium material layer 83 located in the bending region CC, so that the upper and lower surfaces of the aluminum material layer 82 located in the bending region CC, which are arranged opposite to each other in the thickness direction, are exposed, ensuring that only the aluminum material layer 82 remains in the bending region CC. By utilizing the advantages of the higher ductility, bending modulus and variability of the aluminum material layer 82, the cracking defects of the first trace 41 during bending are improved.

[0139] As exemplarily shown in FIG4, the display panel further includes a buffer structure layer B1 disposed on the side of the pixel driving circuit 3 near the substrate 1. The buffer structure layer includes a single layer or multiple layers, such as a buffer layer and a barrier layer. The material of the buffer layer can be one or more layers of amorphous silicon (a-Si), silicon nitride (SiNx), and silicon oxide (SiOx).

[0140] For example, as shown in FIG4, the display panel further includes a driving layer disposed on the side of the buffer structure layer B1 away from the substrate 1. The driving layer includes a pixel driving circuit 3, which includes at least a driving transistor TFT and a storage capacitor Cst. The driving transistor TFT includes an active layer, a gate, and source / drain electrodes disposed sequentially along the direction away from the substrate 1. The driving layer also includes a first gate insulating layer G1 disposed between the active layer and the gate, a second gate insulating layer G2 disposed on the side of the gate away from the active layer, and an interlayer insulating layer ILD disposed on the side of the second gate insulating layer G2 away from the first gate insulating layer G1. The source and drain electrodes are both disposed on the side of the interlayer insulating layer ILD away from the second gate insulating layer G2, and the upper and lower electrodes of the storage capacitor Cst are respectively disposed on two opposite sides of the second gate insulating layer G2 in its thickness direction.

[0141] For example, as shown in Figure 4, a first insulating layer PLN1 is disposed on the side of the source / drain electrodes opposite to the interlayer insulating layer ILD, for planarizing the driving layer. A second insulating layer PLN2 is used to planarize the second conductive layer SD2. A third insulating layer is used to planarize the third conductive layer SD3.

[0142] For example, as shown in FIG4, the light-emitting device 2 is an OLED device, including a first electrode 21, a light-emitting functional layer 22, and a second electrode 23 sequentially disposed along the direction away from the substrate 1. One of the first electrode 21 and the second electrode 23 is an anode, and the other is a cathode. This disclosure uses the first electrode 21 as the anode and the second electrode 23 as the cathode as an example for illustration. The light-emitting functional layer 22 can be a single-layer or multi-layer structure, and the light-emitting functional layer 22 includes at least a light-emitting layer.

[0143] It should be noted that the light-emitting device 2 involved in the embodiments of this disclosure may include, but is not limited to, organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), or micro light-emitting diodes (Micro LEDs), etc.

[0144] Optionally, the light-emitting device 2 is an OLED device. The display panel is an OLED display panel.

[0145] Optionally, the light-emitting device 2 is a Micro LED device. The display panel is a Micro LED display panel.

[0146] For example, the substrate material may include, but is not limited to, one of polyimide (PI), polyethylene naphthalene-2,6-dicarboxylate (PEN), polyethylene terephthalate (PET), colorless polyimide (CPI) with flexible properties, thermoplastic polyurethane (TUP), or ultra-thin glass (UTG). In practical applications, a suitable material can be selected according to actual needs.

[0147] In addition, this disclosure also provides a display device, which includes the display panel of any of the above embodiments. This display device can be, for example, any product with a display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of this display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0148] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display panel having a display area, a peripheral area surrounding the display area, a bonding area located on the side of the peripheral area away from the display area, and a bent area connecting the peripheral area and the bonding area; the peripheral area including a first transition area near the bent area; The display panel includes a substrate, signal traces disposed on the substrate, and a stress dispersion structure; wherein... The two ends of the signal trace extend from the bending area to the first transition area and the bonding area, respectively. The stress-dispersing structure is located at least partially in the bending region and is used to disperse the bending stress when the signal trace is bent.

2. The display panel according to claim 1, wherein, The display panel includes a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer disposed sequentially along a direction away from the substrate. The display panel includes light-emitting devices and pixel driving circuits for driving the light-emitting devices; The source and drain of the transistor in the pixel driving circuit are both disposed in at least one of the first conductive layer, the second conductive layer and the third conductive layer; the signal trace is located in the second conductive layer.

3. The display panel according to claim 2, wherein, The orthographic projection of the stress dispersion structure on the substrate lies between the orthographic projections of the adjacent signal traces on the substrate.

4. The display panel according to claim 3, wherein, The stress dispersion structure is disposed on the same layer as the signal trace.

5. The display panel according to claim 3, wherein, The stress dispersion structure is located in the first conductive layer or the third conductive layer.

6. The display panel according to claim 2, wherein, The stress dispersion structure is a first substructure located in the first conductive layer; The orthographic projection of the first substructure onto the substrate at least partially overlaps with the orthographic projection of the signal trace onto the substrate.

7. The display panel according to claim 2, wherein, The stress dispersion structure is a second substructure located in the third conductive layer; The orthographic projection of the second substructure onto the substrate at least partially overlaps with the orthographic projection of the signal trace onto the substrate.

8. The display panel according to claim 2, wherein, The stress dispersion structure includes a first substructure located in the first conductive layer and a second substructure located in the third conductive layer; The first substructure, the second substructure, and the signal trace have at least partial overlap in their orthogonal projections onto the substrate.

9. The display panel according to claim 8, wherein, The two ends of the first substructure are electrically connected to the two ends of the signal trace through two first connection vias penetrating the first insulating layer; the two ends of the second substructure are electrically connected to the two ends of the signal trace through two second connection vias penetrating the second insulating layer.

10. The display panel according to claim 2, wherein, The stress dispersion structure includes a third substructure located in the first conductive layer; the signal trace includes a first trace located in the bending region, a second trace located in the first transition region, and a third trace located in the bonding region; the orthographic projection of the third substructure on the substrate overlaps with the orthographic projection of the first trace on the substrate. The first insulating layer includes a first slot located in the bending region; the first slot penetrates the first insulating layer along its thickness direction. The first trace and the third substructure are in contact through the first slot.

11. The display panel according to claim 2 or 10, wherein, The stress dispersion structure includes a fourth substructure located in the third conductive layer; the signal trace includes a first trace located in the bending region, a second trace located in the first transition region, and a third trace located in the bonding region; the orthographic projection of the fourth substructure on the substrate overlaps with the orthographic projection of the first trace on the substrate. The second insulating layer includes a second slot located in the bending region; The second slot penetrates the second insulating layer along the thickness direction of the second insulating layer; The first trace and the fourth substructure are in contact through the second slot.

12. The display panel according to claim 2, wherein, The first insulating layer includes a plurality of first grooves extending along a first direction; the first grooves penetrate at least a portion of the first insulating layer along the thickness direction of the second insulating layer; the first direction intersects the extension direction of the signal trace; A plurality of first grooves are arranged side by side along the signal trace extension direction, and at least a portion of the plurality of first grooves are distributed in the bending area; The signal trace falls into the first groove in its extension direction, and the signal trace falling into the first groove is multiplexed as the fifth substructure of the stress dispersion structure.

13. The display panel according to claim 12, wherein, The first groove includes a first sidewall and a first bottom wall, and the dihedral angle between the extended surface of the first sidewall and the plane containing the first bottom wall is an acute angle.

14. The display panel according to claim 2 or 12, wherein, The second insulating layer includes a plurality of second grooves extending along a first direction; the second grooves penetrate at least a portion of the second insulating layer along its thickness direction; the first direction intersects the extension direction of the signal trace; A plurality of second grooves are arranged side by side along the signal trace extension direction, and at least a portion of the plurality of second grooves are distributed in the bending area; The stress dispersion structure includes a sixth substructure located in the third conductive layer, and the orthographic projection of the sixth substructure on the substrate overlaps with the orthographic projection of the signal trace on the substrate. In the extension direction of the signal trace, the portion of the sixth substructure that falls into the second groove contacts the signal trace.

15. The display panel according to claim 14, wherein, Multiple second grooves and multiple first grooves are alternately arranged with their orthographic projections on the substrate.

16. The display panel according to claim 2, wherein, The second conductive layer includes a first titanium material layer, an aluminum material layer, and a second titanium material layer sequentially disposed along a direction away from the substrate.

17. The display panel according to claim 16, wherein, The signal trace includes a first trace located in the bending region, a second trace located in the first transition region, and a third trace located in the bonding region; the first trace is located in the aluminum material layer.

18. The display panel according to claim 16, wherein, The signal trace includes a first trace located in the bending area, a second trace located in the first transition area, and a third trace located in the bonding area; The first trace includes a first sub-trace located in the aluminum material layer and a second sub-trace located in the second titanium material layer.

19. The display panel according to claim 16, wherein, The first titanium material layer includes a first opening located in the bending region, and a portion of the aluminum material layer and a portion of the second titanium material layer located in the bending region fall into the first opening. The portion of the aluminum material layer and the portion of the second titanium material layer falling into the first opening are reused as the stress dispersion structure.

20. The display panel according to claim 16, wherein, The first titanium material layer includes a first opening located in the bending region, and the second titanium material layer includes a second opening located in the bending region, the second opening exposing a portion of the aluminum material layer located in the bending region; A portion of the aluminum material layer located in the bending area falls into the first opening, and the portion of the aluminum material layer falling into the first opening is reused as the stress dispersion structure.

21. A display device, wherein, Includes the display panel as described in any one of claims 1 to 20.

Images