Gate drive circuit, anomaly positioning method, display panel, detection method, and device

Abstract

A gate drive circuit and an anomaly positioning method therefor, a display panel and an anomaly detection method therefor, and a display device. The gate drive circuit comprises: a plurality of shift register units (1); first signal lines (2), wherein the plurality of shift register units (1) are connected in parallel by means of the first signal lines (2); second signal lines (3), wherein the plurality of shift register units (1) are sequentially connected in cascade by means of the second signal lines (3); and signal steering units (4) connected in series on the first signal lines (2) between two adjacent shift register units (1), and / or connected in series on the second signal lines (3) between two adjacent shift register units (1), wherein the signal steering units (4) are configured to change the transmission paths of signals on the first signal lines (2) passing through the signal steering units, so as to prevent the signals on the first signal lines (2) from being transmitted to the next shift register unit (1); and / or the signal steering units (4) are configured to change the transmission paths of signals on the second signal lines (3) passing through the signal steering units, so as to prevent the signals on the second signal lines (3) from being transmitted to the next shift register unit (1).

Description

Gate driving circuit and abnormal location method, display panel and detection method and device Technical Field

[0001] This disclosure pertains to the field of display technology, specifically relating to a gate driving circuit and its abnormal location method, a display panel and its abnormal detection method, and a display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) displays have attracted widespread attention due to their advantages such as self-illumination, low power consumption, thinness, flexibility, vibrant colors, high contrast, and fast response speed. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a gate driving circuit, which includes a plurality of shift register units.

[0004] The first signal line is used to connect the plurality of shift register units in parallel.

[0005] The second signal line is used to cascade the plurality of shift register units in sequence.

[0006] A signal steering unit is connected in series on the first signal line between two adjacent shift register units; and / or, is connected in series on the second signal line between two adjacent shift register units;

[0007] The signal redirection unit can change the transmission path of the signal on the first signal line passing through it, so as to prevent the signal on the first signal line from being passed to the next shift register unit.

[0008] And / or, the signal redirection unit can change the transmission path of the signal on the second signal line passing through it, so as to prevent the signal on the second signal line from being passed to the next shift register unit.

[0009] In some embodiments, the signal steering unit includes a first signal steering unit;

[0010] The first signal steering unit includes a first transistor and a second transistor.

[0011] The gates of the first transistor and the second transistor are connected to the first control terminal; the first terminals of the first transistor and the second transistor are connected to the first signal line.

[0012] The second terminal of the first transistor is connected to the first signal line; the second terminal of the second transistor is connected to the first test terminal.

[0013] In some embodiments, the signal steering unit further includes a second signal steering unit;

[0014] The second signal steering unit includes a third transistor and a fourth transistor.

[0015] The gates of the third transistor and the fourth transistor are connected to the second control terminal; the first terminals of the third transistor and the fourth transistor are connected to the second signal line.

[0016] The second terminal of the third transistor is connected to the second signal line; the second terminal of the fourth transistor is connected to the second test terminal.

[0017] In some embodiments, the first transistor and the third transistor are P-type transistors or N-type transistors;

[0018] The second transistor and the fourth transistor are either N-type transistors or P-type transistors.

[0019] In some embodiments, the plurality of shift register units are arranged sequentially along a first direction.

[0020] The first signal steering unit is located between two adjacent shift register units at the middle position along the first direction;

[0021] And / or, the second signal steering unit is located between two adjacent shift register units at the midpoint of the first direction.

[0022] In some embodiments, the first signal line includes a clock signal line, a reset signal line, and a power supply line;

[0023] The second signal line includes cascaded signal lines.

[0024] In some embodiments, the number of the first signal steering units is multiple, and the number of the second signal steering units is multiple;

[0025] There are multiple first signal lines and multiple second signal lines;

[0026] Different first signal lines are connected to different first signal steering units;

[0027] Different second signal lines are connected to different second signal steering units.

[0028] In some embodiments, at least a portion of the first signal steering unit and / or at least a portion of the second signal steering unit are located between different shift register units.

[0029] Secondly, embodiments of this disclosure also provide a display panel, which includes the gate driving circuit described above.

[0030] In some embodiments, a display area and a border area are provided, the border area surrounding the periphery of the display area;

[0031] The display panel also includes multiple pixel units located in the display area and arranged in an array;

[0032] The gate drive circuit includes a first part;

[0033] The first part includes multiple shift register units, which are cascaded in sequence.

[0034] The first part is located in the first side border area surrounding the display area.

[0035] One of the shift register units in the first part is connected to at least one row of pixel units; and / or, one of the shift register units in the first part is connected to at least some of the pixel units in one row.

[0036] In some embodiments, the gate drive circuit further includes a second portion;

[0037] The second part includes a plurality of shift register units, which are cascaded in sequence.

[0038] The second part is located in the second side border area surrounding the display area, and the second side border area is opposite to the first side border area;

[0039] One of the shift register units in the second part is connected to at least one row of pixel units; and / or, one of the shift register units in the second part is connected to at least a portion of the pixel units in one row.

[0040] In some embodiments, the gate driving circuit includes a first gate driving circuit and a second gate driving circuit.

[0041] The first gate driving circuit is used to provide a gate control cascade signal to the pixel unit;

[0042] The second gate driving circuit is used to provide a light emission control cascade signal to the pixel unit.

[0043] In some embodiments, timing control circuitry and flexible printed circuitry are also included;

[0044] The first signal steering unit in the gate driving circuit is connected to the timing control circuit through a first control terminal;

[0045] The first signal steering unit in the gate driving circuit is connected to the flexible printed circuit through the first test terminal.

[0046] The second signal steering unit in the gate driving circuit is connected to the timing control circuit through the second control terminal;

[0047] The second signal steering unit in the gate driving circuit is connected to the flexible printed circuit through the second test terminal.

[0048] Thirdly, embodiments of this disclosure also provide a display device, which includes the aforementioned display panel.

[0049] Fourthly, embodiments of this disclosure also provide a method for anomaly localization in a gate driving circuit, wherein the gate driving circuit includes multiple shift register units.

[0050] The first signal line is used to connect the plurality of shift register units in parallel.

[0051] The second signal line is used to cascade the plurality of shift register units in sequence.

[0052] A signal steering unit is connected in series on the first signal line between two adjacent shift register units; and / or, is connected in series on the second signal line between two adjacent shift register units;

[0053] The anomaly localization method includes:

[0054] The signal redirection unit controls the transmission path of the signal on the first signal line to change, preventing the signal on the first signal line from being transmitted to the next shift register unit, and the first signal line experiences a signal abnormality.

[0055] And / or, control the signal steering unit to change the transmission path of the signal on the second signal line, prevent the signal on the second signal line from being passed to the next shift register unit, and the second signal line will experience a signal abnormality.

[0056] In some embodiments, the signal steering unit includes a first signal steering unit;

[0057] The first signal steering unit includes a first transistor and a second transistor.

[0058] The gates of the first transistor and the second transistor are connected to the first control terminal; the first terminals of the first transistor and the second transistor are connected to the first signal line.

[0059] The second terminal of the first transistor is connected to the first signal line; the second terminal of the second transistor is connected to the first test terminal.

[0060] The anomaly localization method includes: the first control terminal controls the first transistor to turn off, and simultaneously controls the second transistor to turn on; the first signal line is disconnected, and the signal on the first signal line is transmitted to the first test terminal through the second transistor.

[0061] In some embodiments, the signal steering unit further includes a second signal steering unit;

[0062] The second signal steering unit includes a third transistor and a fourth transistor.

[0063] The gates of the third transistor and the fourth transistor are connected to the second control terminal; the first terminals of the third transistor and the fourth transistor are connected to the second signal line.

[0064] The second terminal of the third transistor is connected to the second signal line; the second terminal of the fourth transistor is connected to the second test terminal.

[0065] The anomaly localization method further includes: the second control terminal controls the third transistor to turn off, and simultaneously controls the fourth transistor to turn on, the second signal line is disconnected, and the signal on the second signal line is transmitted to the second test terminal through the fourth transistor.

[0066] Fifthly, embodiments of this disclosure also provide an anomaly detection method for a display panel, wherein the display panel includes the aforementioned gate driving circuit; the anomaly detection method includes:

[0067] The signal steering unit in the gate drive circuit is controlled to change the transmission path of the signal on the first signal line, causing the first signal line to be disconnected, and the display panel exhibits a first abnormality.

[0068] Compare the first abnormality with the abnormal state of the fault display panel to determine whether the first abnormality and the abnormal state of the fault display panel are consistent.

[0069] If yes, then it is determined that the first signal line of the fault display panel is abnormal; if no, then it is determined that the first signal line of the fault display panel is normal.

[0070] And / or, control the signal steering unit in the gate drive circuit to change the transmission path of the signal on the second signal line, causing the second signal line to be disconnected, and the display panel to exhibit a second abnormality;

[0071] Compare the second anomaly with the anomaly state of the fault display panel to determine whether the second anomaly and the anomaly state of the fault display panel are consistent.

[0072] If yes, then it is determined that the second signal line of the fault display panel is abnormal; if no, then it is determined that the second signal line of the fault display panel is normal.

[0073] In some embodiments, there are multiple first signal lines and multiple second signal lines;

[0074] Different first signal lines and different second signal lines are respectively connected to different signal steering units;

[0075] The anomaly detection method includes performing anomaly detection on each of the first signal line and the second signal line.

[0076] In some embodiments, the gate driving circuit includes a first gate driving circuit and a second gate driving circuit.

[0077] The first gate driving circuit provides a gate control cascade signal to the pixel unit;

[0078] The second gate driving circuit provides a light emission control cascade signal to the pixel unit;

[0079] The anomaly detection method includes: performing anomaly detection on each of the first signal lines and the second signal lines in the first gate driving circuit;

[0080] Anomaly detection is performed on each of the first and second signal lines in the second gate drive circuit.

[0081] The gate driving circuit provided in this embodiment of the present disclosure, by setting a signal steering unit, can accurately locate the abnormal signal on the first signal line and / or the second signal line when the first signal line and / or the second signal line is open-circuited, thereby actively reproducing the display defects caused by the abnormal signal, and thus helping analysts to quickly locate the abnormal signal and improve the analysis efficiency of the display defects caused by the abnormal signal.

[0082] The display panel provided in this embodiment employs the gate driving circuit described above. When the signal steering unit in the gate driving circuit causes an open circuit in the first signal line and / or the second signal line, it can accurately locate the abnormal signal on the first signal line and / or the second signal line. This enables the active reproduction of the display defects caused by the abnormal signal, thereby helping analysts quickly locate the abnormal signal and improving the analysis efficiency of the display defects caused by the abnormal signal.

[0083] The display device provided in this embodiment improves the analysis efficiency of display defects by employing the above-described display panel. Attached Figure Description

[0084] The accompanying drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0085] Figure 1a is a circuit diagram of a pixel circuit in the related art.

[0086] Figure 1b is a circuit diagram of a light-emitting control gate driving circuit in the related art.

[0087] Figure 1c is a schematic diagram of the circuit connection of the gate driving circuit in the display panel of the related technology.

[0088] Figure 2a is a schematic diagram of the circuit connection of a gate driving circuit in an embodiment of this disclosure.

[0089] Figure 2b is a schematic diagram of the circuit connection of another gate driving circuit in an embodiment of this disclosure.

[0090] Figure 2c is a schematic diagram of the circuit connection of another gate driving circuit in an embodiment of this disclosure.

[0091] Figure 2d is a schematic diagram of the circuit connection of another gate driving circuit in an embodiment of this disclosure.

[0092] Figure 3a is a circuit diagram of the first signal steering unit in an embodiment of this disclosure.

[0093] Figure 3b is a circuit diagram of the second signal steering unit in an embodiment of this disclosure.

[0094] Figure 3c is a schematic diagram of the circuit connection of another gate driving circuit in an embodiment of this disclosure.

[0095] Figure 4a is a schematic diagram of a display panel according to an embodiment of the present disclosure.

[0096] Figure 4b is a schematic diagram of another display panel in an embodiment of this disclosure.

[0097] Figure 4c is a schematic diagram of another display panel in an embodiment of this disclosure.

[0098] Figure 4d is a schematic diagram of another display panel in an embodiment of this disclosure.

[0099] Figure 4e is a schematic diagram of another display panel in an embodiment of this disclosure.

[0100] Figure 5a is a flowchart of a method for detecting anomalies in the first signal line of a display panel according to an embodiment of this disclosure.

[0101] Figure 5b is a flowchart of the second signal line anomaly detection method in the display panel according to an embodiment of the present disclosure. Detailed Implementation

[0102] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the following describes in further detail, with reference to the accompanying drawings and specific embodiments, a gate driving circuit and its abnormal location method, a display panel and its abnormal detection method, and a display device provided by the embodiments of this disclosure.

[0103] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms and should not be construed as limited to the embodiments set forth in this disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0104] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas, but are not intended to be limiting.

[0105] In related technologies, referring to Figures 1a and 1b, a display panel (such as an OLED display panel) includes a gate driving circuit. The gate driving circuit provides two essential driving signals to the pixel circuit: a Gate signal (gate control signal) and an Emission signal (emission control signal). The Gate signal is used to drive the pixel circuit during the data writing stage, and the Emission signal is used to drive the pixel circuit during the light emission stage. Whether the display panel can display normally is closely related to these two signals. When they malfunction, the display panel may exhibit defects such as Y-lines (horizontal bright lines), screen splitting (inconsistent color or brightness between upper and lower screen areas), or no display (entire screen black).

[0106] The Gate and Emission signals are generated by two different gate drive circuits. The gate drive circuit generating the Gate signal uses GSTV (gate control cascade signal), GCK (first clock signal), and GCB (second clock signal) as inputs. These inputs work together to generate the Gate signal. The gate drive circuit generating the Emission signal uses ESTV (light emission control cascade signal), ECK (third clock signal), and ECB (fourth clock signal) as inputs. These inputs work together to generate the Emission signal. Figure 1c illustrates the positions of these input signals in the gate drive circuit. Since the macroscopic structures of the gate drive circuits generating the Gate and Emission signals are similar (i.e., both consist of multiple cascaded shift register units), for simplicity, GSTV and ESTV are collectively referred to as STV signals in Figure 1c; GCK and ECK are collectively referred to as CK signals; and GCB and ECB are collectively referred to as CB signals.

[0107] During the display panel display process, factors such as electrochemical corrosion and cracking can cause abnormalities in any input signal of the gate drive circuit, affecting the Gate and Emission signals provided by the gate drive circuit and leading to display defects. In related technologies, referring to Figure 1c, the gate drive circuit includes multiple shift register units (gate drive 0 to gate drive n, i.e., GOA0 to GOAn or EOA0 to EOAn)1, which are cascaded to transmit the Gate or Emission signals line by line downwards. However, when the Gate and Emission signals are abnormal, it is impossible to accurately determine which input signal line (GSTV, GCK, GCB, ESTV, ECK, ECB) is causing the abnormality. Currently, in analyzing these display defects, each input signal line is inspected step by step using a microscope. However, some minute anomalies on the input signal lines may be overlooked under long-term observation. Furthermore, currently, reproducing this type of display defect requires using a laser device to precisely target the corresponding input signal line, causing it to disconnect and thus reproducing the display defect due to an open circuit. If the laser device misses and hits another signal line, the display defect reproduction screen will be rendered unusable. This display defect reproduction operation places extremely high demands on the analytical personnel and incurs significant time costs.

[0108] Accurately locating abnormal input signals in the gate drive circuit has become an urgent problem to be solved.

[0109] To address the problems in the related art, in a first aspect, embodiments of this disclosure provide a gate driving circuit, referring to Figures 2a, 2b, 2c, and 2d, comprising a plurality of shift register units 1, a first signal line 2, wherein the plurality of shift register units 1 are connected in parallel via the first signal line 2; a second signal line 3, wherein the plurality of shift register units 1 are cascaded sequentially via the second signal line 3; a signal redirection unit 4, connected in series on the first signal line 2 between two adjacent shift register units 1; and / or, connected in series on the second signal line 3 between two adjacent shift register units 1; the signal redirection unit 4 can change the transmission path of the signal on the first signal line 2 passing through it, so as to prevent the signal on the first signal line 2 from being transmitted to the next shift register unit 1; and / or, the signal redirection unit 4 can change the transmission path of the signal on the second signal line 3 passing through it, so as to prevent the signal on the second signal line 3 from being transmitted to the next shift register unit 1.

[0110] In this circuit, the first signal line 2 refers to any signal line in the gate driving circuit that enables multiple shift register units 1 to be connected in parallel. Examples include clock signal lines, reset signal lines, and power supply lines. The second signal line 3 refers to any signal line in the gate driving circuit that enables multiple shift register units 1 to be connected in cascade. Examples include gate control cascaded signal lines and light emission control cascaded signal lines.

[0111] In this embodiment, Figures 2a and 2b illustrate the first signal line (GCK, GCB) 2 and the second signal line (GSTV) 3 in the gate driving circuit for generating the Gate signal; the gate driving circuit for generating the Gate signal includes multiple shift register units (GOA0 to GOAn) 1. Figures 2c and 2d illustrate the first signal line (ECK, ECB) 2 and the second signal line (ESTV) 3 in the gate driving circuit for generating the Emission signal; the gate driving circuit for generating the Emission signal includes multiple shift register units (EOA0 to EOAn) 1.

[0112] In this embodiment, when the signal redirection unit 4 changes the transmission path of the signal on the first signal line 2 passing through it, it can prevent the signal on the first signal line 2 from being transmitted to the next shift register unit 1, thereby causing the first signal line 2 to be open-circuited, and thus causing the display panel containing the gate driving circuit to experience display defects when the first signal line 2 is open-circuited. Similarly, when the signal redirection unit 4 changes the transmission path of the signal on the second signal line 3 passing through it, it can prevent the signal on the second signal line 3 from being transmitted to the next shift register unit 1, thereby causing the second signal line 3 to be open-circuited, and thus causing the display panel containing the gate driving circuit to experience display defects when the second signal line 3 is open-circuited. In summary, the signal redirection unit 4 enables the display panel containing the gate driving circuit to reproduce the display defects when the first signal line 2 and / or the second signal line 3 are open-circuited.

[0113] In this embodiment, by setting a signal steering unit 4, when the first signal line 2 and / or the second signal line 3 is broken, the abnormal signal on the first signal line 2 and / or the second signal line 3 can be accurately located, thereby enabling the active reproduction of the display failure caused by the abnormal signal, which in turn helps the analyst to quickly locate the abnormal signal and improve the analysis efficiency of the display failure caused by the abnormal signal.

[0114] In some embodiments, referring to FIG3a, the signal steering unit 4 includes a first signal steering unit 41; the first signal steering unit 41 includes a first transistor Ta and a second transistor Tb, the gate of the first transistor Ta and the gate of the second transistor Tb are connected to a first control terminal A; the first electrode of the first transistor Ta and the first electrode of the second transistor Tb are connected to a first signal line 2; the second electrode of the first transistor Ta is connected to the first signal line 2; the second electrode of the second transistor Tb is connected to a first test terminal B.

[0115] In some embodiments, the first transistor Ta is a P-type transistor or an N-type transistor; the second transistor Tb is an N-type transistor or a P-type transistor.

[0116] In some embodiments, the first transistor Ta is a P-type transistor, and the second transistor Tb is an N-type transistor. When the first control terminal A provides a low-level signal through path ①, the first transistor Ta is turned on, the second transistor Tb is turned off, and the signal transmission path on the first signal line 2 remains unchanged, transmitting along the path ④→②, that is, the signal on the first signal line 2 is still transmitted to the next shift register unit 1 through the first signal line 2; when the first control terminal A provides a high-level signal through path ①, the second transistor Tb is turned on, the first transistor Ta is turned off, and the signal transmission path on the first signal line 2 changes, transmitting along the path ④→③, that is, the signal on the first signal line 2 is directly transmitted to the first test terminal B through path ③. At the first test terminal B, the output signal of the first test terminal B can be tested by a detection device to determine whether the first signal redirection unit 41 has changed the signal transmission path on the first signal line 2.

[0117] In some embodiments, referring to FIG3b, the signal redirection unit 4 further includes a second signal redirection unit 42; the second signal redirection unit 42 includes a third transistor Tc and a fourth transistor Td, the gate of the third transistor Tc and the gate of the fourth transistor Td are connected to the second control terminal C; the first terminal of the third transistor Tc and the first terminal of the fourth transistor Td are connected to the second signal line 3; the second terminal of the third transistor Tc is connected to the second signal line 3; and the second terminal of the fourth transistor Td is connected to the second test terminal D.

[0118] In some embodiments, the third transistor Tc is a P-type transistor or an N-type transistor; the fourth transistor Td is an N-type transistor or a P-type transistor.

[0119] In some embodiments, the third transistor Tc is a P-type transistor, and the fourth transistor Td is an N-type transistor. When the second control terminal C provides a low-level signal through path ①, the third transistor Tc is turned on, the fourth transistor Td is turned off, and the signal transmission path on the second signal line 3 remains unchanged, transmitting along the path ④→②, that is, the signal on the second signal line 3 is still transmitted to the next shift register unit 1 through the second signal line 3. When the second control terminal C provides a high-level signal through path ①, the fourth transistor Td is turned on, the third transistor Tc is turned off, and the signal transmission path on the second signal line 3 changes, transmitting along the path ④→③, that is, the signal on the second signal line 3 is directly transmitted to the second test terminal D through path ③. At the second test terminal D, the output signal of the second test terminal D can be tested by a detection device to determine whether the second signal redirection unit 42 has changed the signal transmission path on the second signal line 3.

[0120] In some embodiments, a plurality of shift register units 1 are arranged sequentially along a first direction Z, and a first signal steering unit 41 is located between two adjacent shift register units 1 at the middle position along the first direction Z; and / or, a second signal steering unit 42 is located between two adjacent shift register units 1 at the middle position along the first direction Z.

[0121] This configuration allows the display defects caused by the first signal line 2 being disconnected to be reproduced in the middle area of ​​the display panel, thus facilitating better observation, comparison, and analysis of the display defects; similarly, it allows the display defects caused by the second signal line 3 being disconnected to be reproduced in the middle area of ​​the display panel, thus facilitating better observation, comparison, and analysis of the display defects.

[0122] In some embodiments, referring to FIG3c, the first signal line 2 includes clock signal lines (such as GCK, GCB, ECK, ECB), reset signal lines (such as Reset), and power supply lines (such as VGH, VGL); the second signal line 3 includes cascaded signal lines (such as GSTV, ESTV).

[0123] In some embodiments, there are multiple first signal redirection units 41 and multiple second signal redirection units 42; there are multiple first signal lines 2 and multiple second signal lines 3; different first signal lines 2 are connected to different first signal redirection units 41; different second signal lines 3 are connected to different second signal redirection units 42. This configuration facilitates the location of abnormal signals on multiple first signal lines 2 and multiple second signal lines 3 one by one, thereby enabling the reproduction of display defects caused by abnormal signals on different first signal lines 2 and different second signal lines 3. This helps analysts quickly locate the abnormal signal and improves the analysis efficiency of display defects caused by the abnormal signal.

[0124] In some embodiments, at least some of the first signal redirection units 41 and / or at least some of the second signal redirection units 42 are located between different shift register units 1. This arrangement avoids the situation where multiple first signal redirection units 41 and / or multiple second signal redirection units 42 are all located between the same group of adjacent shift register units 1, thereby avoiding the situation where there is insufficient space between the same group of adjacent shift register units 1, making it difficult to accommodate multiple signal redirection units 4.

[0125] Based on the above structure of the gate driving circuit, this disclosure also provides an abnormality location method for the gate driving circuit, including: a control signal steering unit changing the transmission path of the signal on the first signal line to prevent the signal on the first signal line from being transmitted to the next shift register unit, causing a signal abnormality in the first signal line; and / or, a control signal steering unit changing the transmission path of the signal on the second signal line to prevent the signal on the second signal line from being transmitted to the next shift register unit, causing a signal abnormality in the second signal line.

[0126] In some embodiments, the anomaly localization method includes: a first control terminal controlling a first transistor to turn off, and simultaneously controlling a second transistor to turn on, a first signal line being disconnected, and the signal on the first signal line being transmitted to a first test terminal through the second transistor.

[0127] In some embodiments, the anomaly localization method further includes: the second control terminal controls the third transistor to turn off, and simultaneously controls the fourth transistor to turn on, the second signal line is disconnected, and the signal on the second signal line is transmitted to the second test terminal through the fourth transistor.

[0128] The gate driving circuit provided in this embodiment of the present disclosure, by setting a signal steering unit, can accurately locate the abnormal signal on the first signal line and / or the second signal line when the first signal line and / or the second signal line is open-circuited, thereby actively reproducing the display defects caused by the abnormal signal, and thus helping analysts to quickly locate the abnormal signal and improve the analysis efficiency of the display defects caused by the abnormal signal.

[0129] Secondly, embodiments of this disclosure also provide a display panel, including the gate driving circuit described in the above embodiments.

[0130] By employing the gate driving circuit in the above embodiments, when the signal steering unit in the gate driving circuit causes the first signal line and / or the second signal line to be disconnected, the abnormal signal on the first signal line and / or the second signal line can be accurately located, thereby enabling the active reproduction of the display defects caused by the abnormal signal, which in turn helps analysts quickly locate the abnormal signal and improves the analysis efficiency of the display defects caused by the abnormal signal.

[0131] In some embodiments, referring to Figures 4a, 4b, 4c, 4d, and 4e, the display panel has a display area 100 and a border area 101, the border area 101 surrounding the periphery of the display area 100; the display panel also includes a plurality of pixel units 10 located in the display area 100 and arranged in an array; the gate driving circuit includes a first portion 51; the first portion 51 includes a plurality of shift register units 1, the plurality of shift register units 1 being cascaded in sequence; the first portion 51 is located in a first side border area 101A surrounding the display area 100, one shift register unit 1 in the first portion 51 is connected to at least one row of pixel units 10; and / or, one shift register unit 1 in the first portion 51 is connected to at least some of the pixel units 10 in one row.

[0132] In some embodiments, a shift register unit 1 in the first part 51 may be connected to a row of pixel units 10, or may be connected to multiple rows (such as 2 rows or 4 rows) of pixel units 10; a shift register unit 1 in the first part 51 may be connected to all pixel units 10 in a row, or may be connected to a portion of pixel units 10 in a row, such as a shift register unit 1 in the first part 51 being connected to an odd number or an even number of pixel units 10 in a row; or, a shift register unit 1 in the first part 51 being connected to half the number of pixel units 10 arranged sequentially in a row.

[0133] In some embodiments, if only the first part 51 is provided in the gate driving circuit, the connection method between the first part 51 and the pixel unit 10 corresponds to the gate driving circuit driving the pixel unit array on one side.

[0134] In some embodiments, the gate driving circuit further includes a second portion 52; the second portion 52 includes a plurality of shift register units 1, which are cascaded in sequence; the second portion 52 is located in a second side bezel area 101B surrounding the display area 100, and the second side bezel area 101B is opposite to the first side bezel area 101A; one shift register unit 1 in the second portion 52 is connected to at least one row of pixel units 10; and / or, one shift register unit 1 in the second portion 52 is connected to at least some of the pixel units 10 in one row.

[0135] In some embodiments, a shift register unit 1 in the second part 52 may be connected to a row of pixel units 10, or may be connected to multiple rows (such as 2 rows or 4 rows) of pixel units 10; a shift register unit 1 in the second part 52 may be connected to all pixel units 10 in a row, or may be connected to a portion of pixel units 10 in a row, such as a shift register unit 1 in the second part 52 being connected to an odd number or an even number of pixel units 10 in a row; or, a shift register unit 1 in the second part 52 being connected to half the number of pixel units 10 arranged sequentially in a row.

[0136] In some embodiments, when the gate driving circuit includes a first part 51 and a second part 52, the connection method of the first part 51, the second part 52 and the pixel unit 10 corresponds to the gate driving circuit performing bilateral driving on the pixel unit array.

[0137] In some embodiments, the gate driving circuit includes a first gate driving circuit 8 and a second gate driving circuit 9. The first gate driving circuit 8 is used to provide a gate control cascade signal (Gate) to the pixel unit 10; the second gate driving circuit 9 is used to provide a light emission control cascade signal (EM) to the pixel unit 10.

[0138] In some embodiments, referring to FIG1a, a pixel unit includes a pixel circuit and a light-emitting element D'. The pixel circuit in FIG1a is a 7T1C (7 thin-film transistors and 1 capacitor) circuit, and the light-emitting element D' can be an OLED (organic electroluminescent device). The GLn signal (gate control cascade signal) and GLn-1 signal (gate control cascade signal) in the pixel circuit are provided by the nth shift register unit and the (n-1)th shift register unit in the first gate driving circuit, respectively. The GLn signal and GLn-1 signal are used to drive the pixel circuit during the data writing stage. The EM signal (light emission control cascade signal) in the pixel circuit is provided by the shift register unit in the second gate driving circuit. The EM signal is used to drive the pixel circuit during the light emission stage.

[0139] In some embodiments, referring to Figures 4b-4e, the display panel further includes a timing control circuit 6 and a flexible printed circuit 7; the first signal steering unit 41 in the gate driving circuit is connected to the timing control circuit 6 through a first control terminal A; the first signal steering unit 41 in the gate driving circuit is connected to the flexible printed circuit 7 through a first test terminal B; the second signal steering unit 42 in the gate driving circuit is connected to the timing control circuit 6 through a second control terminal C; the second signal steering unit 42 in the gate driving circuit is connected to the flexible printed circuit 7 through a second test terminal D.

[0140] The first control terminal A and the second control terminal C can be located in the timing control circuit 6. When the first signal switching unit 41 and the second signal switching unit 42 are working, the timing control circuit 6 provides control signals to them through the first control terminal A and the second control terminal C, respectively. The first test terminal B and the second test terminal D can be located in the flexible printed circuit 7. When the first signal switching unit 41 and the second signal switching unit 42 are working, the flexible printed circuit 7 receives the signals on the first signal line 2 and the second signal line 3 through the first test terminal B and the second test terminal D, respectively.

[0141] Based on the above structure of the display panel, this disclosure also provides an abnormality detection method for the display panel. Referring to Figures 5a and 5b, the method includes: step S101: controlling the signal steering unit in the gate drive circuit to change the transmission path of the signal on the first signal line, causing the first signal line to be disconnected, and the display panel to exhibit a first abnormality.

[0142] Step S102: Compare the first abnormality with the abnormal status of the fault display panel to determine whether the first abnormality and the abnormal status of the fault display panel are consistent.

[0143] If yes, proceed to step S103: determine that the first signal line of the fault display panel is abnormal; if no, proceed to step S104: determine that the first signal line of the fault display panel is normal.

[0144] And / or, step S201: the signal steering unit in the control gate drive circuit changes the transmission path of the signal on the second signal line, causing the second signal line to be disconnected, and the display panel exhibits a second abnormality.

[0145] Step S202: Compare the abnormal status of the second abnormality and the fault display panel to determine whether the abnormal status of the second abnormality and the fault display panel are consistent.

[0146] If yes, proceed to step S203: determine that the second signal line of the fault display panel is abnormal; if no, proceed to step S204: determine that the second signal line of the fault display panel is normal.

[0147] In some embodiments, there are multiple first signal lines and multiple second signal lines; different first signal lines and different second signal lines are respectively connected to different signal switching units; the anomaly detection method includes: performing anomaly detection on each of the first signal lines and the second signal lines one by one. This allows for individual anomaly detection on multiple first signal lines and multiple second signal lines, thereby enabling more accurate location of the signal line exhibiting anomalies.

[0148] In some embodiments, the gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first gate driving circuit provides a gate control cascade signal to the pixel unit; the second gate driving circuit provides a light emission control cascade signal to the pixel unit; the anomaly detection method includes: performing anomaly detection on each of the first signal lines and the second signal lines in the first gate driving circuit; and performing anomaly detection on each of the first signal lines and the second signal lines in the second gate driving circuit.

[0149] The display panel provided in this embodiment employs the aforementioned gate driving circuit. When the signal steering unit in the gate driving circuit causes an open circuit in the first signal line and / or the second signal line, it can accurately locate the abnormal signal on the first signal line and / or the second signal line. This enables the active reproduction of the display defects caused by the abnormal signal, thereby helping analysts quickly locate the abnormal signal and improving the analysis efficiency of the display defects caused by the abnormal signal.

[0150] Thirdly, embodiments of this disclosure also provide a display device, including the display panel described in the above embodiments.

[0151] By employing the display panel in the above embodiments, the analysis efficiency of display defects in the display device is improved.

[0152] The display device provided in this disclosure can be any product or component with display function, such as an OLED panel, OLED TV, OLED billboard, monitor, mobile phone, or navigator.

[0153] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A gate driving circuit, wherein, Includes multiple shift register units, The first signal line is used to connect the plurality of shift register units in parallel. The second signal line is used to cascade the plurality of shift register units in sequence. A signal steering unit is connected in series on the first signal line between two adjacent shift register units; and / or, is connected in series on the second signal line between two adjacent shift register units; The signal redirection unit can change the transmission path of the signal on the first signal line passing through it, so as to prevent the signal on the first signal line from being passed to the next shift register unit. And / or, the signal redirection unit can change the transmission path of the signal on the second signal line passing through it, so as to prevent the signal on the second signal line from being passed to the next shift register unit.

2. The gate driving circuit according to claim 1, wherein, The signal steering unit includes a first signal steering unit; The first signal steering unit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are connected to the first control terminal; the first terminals of the first transistor and the second transistor are connected to the first signal line. The second terminal of the first transistor is connected to the first signal line; the second terminal of the second transistor is connected to the first test terminal.

3. The gate driving circuit according to claim 2, wherein, The signal steering unit further includes a second signal steering unit; The second signal steering unit includes a third transistor and a fourth transistor. The gates of the third transistor and the fourth transistor are connected to the second control terminal; the first terminals of the third transistor and the fourth transistor are connected to the second signal line. The second terminal of the third transistor is connected to the second signal line; the second terminal of the fourth transistor is connected to the second test terminal.

4. The gate driving circuit according to claim 3, wherein, The first transistor and the third transistor are either P-type transistors or N-type transistors; The second transistor and the fourth transistor are either N-type transistors or P-type transistors.

5. The gate driving circuit according to claim 3, wherein, The plurality of shift register units are arranged sequentially along the first direction. The first signal steering unit is located between two adjacent shift register units at the middle position along the first direction; And / or, the second signal steering unit is located between two adjacent shift register units at the midpoint of the first direction.

6. The gate driving circuit according to claim 3, wherein, The first signal line includes a clock signal line, a reset signal line, and a power supply line; The second signal line includes cascaded signal lines.

7. The gate driving circuit according to claim 3, wherein, The number of the first signal steering unit is multiple, and the number of the second signal steering unit is multiple; There are multiple first signal lines and multiple second signal lines; Different first signal lines are connected to different first signal steering units; Different second signal lines are connected to different second signal steering units.

8. The gate driving circuit according to claim 7, wherein, At least some of the first signal steering unit and / or at least some of the second signal steering unit are located between different shift register units.

9. A display panel, wherein, Includes the gate drive circuit as described in any one of claims 1-8.

10. The display panel according to claim 9, wherein, It has a display area and a border area, the border area surrounding the periphery of the display area; The display panel also includes multiple pixel units located in the display area and arranged in an array; The gate drive circuit includes a first part; The first part includes multiple shift register units, which are cascaded in sequence. The first part is located in the first side border area surrounding the display area. One of the shift register units in the first part is connected to at least one row of pixel units; and / or, one of the shift register units in the first part is connected to at least some of the pixel units in one row.

11. The display panel according to claim 10, wherein, The gate drive circuit also includes a second part; The second part includes a plurality of shift register units, which are cascaded in sequence. The second part is located in the second side border area surrounding the display area, and the second side border area is opposite to the first side border area; One of the shift register units in the second part is connected to at least one row of pixel units; And / or, one of the shift register units in the second part corresponds to at least a portion of the pixel units in a row.

12. The display panel according to claim 11, wherein, The gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first gate driving circuit is used to provide a gate control cascade signal to the pixel unit; The second gate driving circuit is used to provide a light emission control cascade signal to the pixel unit.

13. The display panel according to claim 9, wherein, It also includes timing control circuits and flexible printed circuits; The first signal steering unit in the gate driving circuit is connected to the timing control circuit through a first control terminal; The first signal steering unit in the gate driving circuit is connected to the flexible printed circuit through the first test terminal. The second signal steering unit in the gate driving circuit is connected to the timing control circuit through the second control terminal; The second signal steering unit in the gate driving circuit is connected to the flexible printed circuit through the second test terminal.

14. A display device, wherein, Includes the display panel as described in any one of claims 9-13.

15. A method for locating an anomaly in a gate drive circuit, wherein, The gate drive circuit includes multiple shift register units. The first signal line is used to connect the plurality of shift register units in parallel. The second signal line is used to cascade the plurality of shift register units in sequence. A signal steering unit is connected in series on the first signal line between two adjacent shift register units; And / or, connected in series on the second signal line between two adjacent shift register units; The anomaly localization method includes: The signal redirection unit controls the transmission path of the signal on the first signal line to change, preventing the signal on the first signal line from being transmitted to the next shift register unit, and the first signal line experiences a signal abnormality. And / or, control the signal steering unit to change the transmission path of the signal on the second signal line, prevent the signal on the second signal line from being passed to the next shift register unit, and the second signal line will experience a signal abnormality.

16. The anomaly localization method according to claim 15, wherein, The signal steering unit includes a first signal steering unit; The first signal steering unit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are connected to the first control terminal; the first terminals of the first transistor and the second transistor are connected to the first signal line. The second terminal of the first transistor is connected to the first signal line; The second terminal of the second transistor is connected to the first test terminal; The anomaly localization method includes: the first control terminal controls the first transistor to turn off, and simultaneously controls the second transistor to turn on; the first signal line is disconnected, and the signal on the first signal line is transmitted to the first test terminal through the second transistor.

17. The anomaly localization method according to claim 16, wherein, The signal steering unit further includes a second signal steering unit; The second signal steering unit includes a third transistor and a fourth transistor. The gates of the third transistor and the fourth transistor are connected to the second control terminal; the first terminals of the third transistor and the fourth transistor are connected to the second signal line. The second terminal of the third transistor is connected to the second signal line; the second terminal of the fourth transistor is connected to the second test terminal. The anomaly localization method further includes: the second control terminal controls the third transistor to turn off, and simultaneously controls the fourth transistor to turn on, the second signal line is disconnected, and the signal on the second signal line is transmitted to the second test terminal through the fourth transistor.

18. A method for detecting anomalies in a display panel, wherein, The display panel includes the gate driving circuit according to any one of claims 1-8; The anomaly detection method includes: The signal steering unit in the gate drive circuit is controlled to change the transmission path of the signal on the first signal line, causing the first signal line to be disconnected, and the display panel will exhibit a first abnormality. Compare the first abnormality with the abnormal status of the fault display panel to determine whether the first abnormality and the abnormal status of the fault display panel are consistent. If yes, then it is determined that the first signal line of the fault display panel is abnormal; if no, then it is determined that the first signal line of the fault display panel is normal. And / or, control the signal steering unit in the gate drive circuit to change the transmission path of the signal on the second signal line, causing the second signal line to be disconnected, and the display panel to exhibit a second abnormality; Compare the second anomaly with the anomaly state of the fault display panel to determine whether the second anomaly and the anomaly state of the fault display panel are consistent. If yes, then it is determined that the second signal line of the fault display panel is abnormal; if no, then it is determined that the second signal line of the fault display panel is normal.

19. The anomaly detection method according to claim 18, wherein, There are multiple first signal lines and multiple second signal lines; Different first signal lines and different second signal lines are respectively connected to different signal steering units; The anomaly detection method includes performing anomaly detection on each of the first signal line and the second signal line.

20. The anomaly detection method according to claim 18, wherein, The gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first gate driving circuit provides a gate control cascade signal to the pixel unit; The second gate driving circuit provides a light emission control cascade signal to the pixel unit; The anomaly detection method includes: performing anomaly detection on each of the first signal lines and the second signal lines in the first gate driving circuit; Anomaly detection is performed on each of the first and second signal lines in the second gate drive circuit.

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