Programming method, apparatus and system, computing-in-memory apparatus, and electronic device
By separating the programming execution and control of the in-memory computing device and the server, the problem of high programming control complexity in the in-memory computing architecture is solved, achieving the effects of reducing costs and improving flexibility.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BEIJING ZHICUN (WITIN) TECH CORP LTD
- Filing Date
- 2025-12-23
- Publication Date
- 2026-07-09
Smart Images
Figure CN2025144851_09072026_PF_FP_ABST
Abstract
Description
Programming methods, apparatus and systems, memory computing devices and electronic devices
[0001] This application claims priority to Chinese Patent Application No. 202411998339.5, filed with the Chinese Patent Office on December 31, 2024, entitled "Programming Method, Apparatus and System, Storage Computing Device and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of electronic technology, and in particular to a programming method, apparatus and system, a storage device and an electronic device. Background Technology
[0003] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.
[0004] In-memory computing (IMC) architecture physically merges storage and computation. This physical fusion includes, for example, integrating storage and computation components close together through packaging processes; integrating processing circuitry within the memory to achieve in-memory processing integration; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. IMC architecture can reduce data transmission requirements, lower transmission latency and energy consumption, and greatly improve data processing efficiency. However, IMC architecture still faces challenges. For example, in applications, IMC architecture requires writing weight data into the storage circuitry; this writing process, known as programming, places high control requirements on the in-memory computing device. Summary of the Invention
[0005] This application provides a programming method, apparatus, and system, as well as a memory computing device and electronic device, to reduce the control requirements of the memory computing device during the programming process.
[0006] In a first aspect, embodiments of this application provide a programming method executed by a memory computing device, the memory computing device including a storage circuit, the method comprising: receiving a first programming instruction from a server, the first programming instruction including first programming parameters; controlling a first write operation according to the first programming parameters, the first write operation being used to write first weight data to the storage circuit; obtaining a first result of the first write operation; sending a first indication message to the server, the first indication message being used to indicate the first result; receiving a second programming instruction from the server, the second programming instruction being generated based on the first result and including second programming parameters; and controlling a second write operation according to the second programming parameters, the second write operation being used to adjust the first weight data written to the storage circuit.
[0007] Optionally, the first and second programming instructions include address information, which is used to indicate the memory cell or set of memory cells to be programmed in the memory circuit; or, the first and second programming instructions include address information and identification information, which are set correspondingly, with the address information indicating the memory cell or set of memory cells in the memory circuit and the identification information indicating the programming status of the corresponding memory cell or set of memory cells.
[0008] Optionally, the first instruction message includes first instruction information and second instruction information, wherein the first instruction information is used to indicate the first result, and the second instruction information is used to indicate the storage unit or storage unit set corresponding to the first result.
[0009] Optionally, the method further includes: receiving a burning start command from the server; and erasing all or part of the storage area of the storage circuit according to the burning start command.
[0010] Optionally, the method further includes: obtaining a second result of the second write; sending a second indication message to the server, the second indication message being used to indicate the second result; and receiving a burning end command from the server, the burning end command being generated based on the second result.
[0011] Optionally, the storage circuit includes multiple sets of storage cells, including a first set of storage cells and a second set of storage cells. The start times of the burning cycles of the first set of storage cells and the second set of storage cells are different and overlap in time.
[0012] Optionally, storage cells in the same storage cell set have the same programming parameter settings; and / or, storage cells in the same storage cell set have independent signal terminals.
[0013] Optionally, the division of multiple sets of storage cells is determined based on one or more of the following factors: the physical location of the storage cells of the storage circuit, the connection method of the storage cells of the storage circuit, the transmission delay, and the interference between storage cells.
[0014] Optionally, the first and second programming instructions are used to write first weight data to the first set of storage cells. The method further includes: receiving a third programming instruction from the server, the third programming instruction including third programming parameters; controlling a third write according to the third programming parameters, the third write being used to write second weight data to the second set of storage cells; obtaining a third result of the third write; sending a third indication message to the server, the third indication message being used to indicate the third result; receiving a fourth programming instruction from the server, the fourth programming instruction being generated based on the third result and including fourth programming parameters; controlling a fourth write according to the fourth programming parameters, the fourth write being used to adjust the second weight data written to the second set of storage cells.
[0015] Secondly, embodiments of this application provide another programming method, which is executed by a server. The method includes: sending a first programming instruction to a memory computing device, the first programming instruction including first programming parameters, the first programming parameters being used to control a first write, the first write being used to write first weight data to a memory circuit; receiving a first indication message from the memory computing device, the first indication message being used to indicate a first result of the first write; generating a second programming instruction based on the first result, the second programming instruction including second programming parameters; and sending the second programming instruction to the memory computing device.
[0016] Optionally, the first and second programming instructions include address information, which is used to indicate the memory cell or set of memory cells to be programmed in the memory circuit; or, the first and second programming instructions include address information and identification information, which are set correspondingly, with the address information indicating the memory cell or set of memory cells in the memory circuit and the identification information indicating the programming status of the corresponding memory cell or set of memory cells.
[0017] Optionally, the first instruction message includes first instruction information and second instruction information, wherein the first instruction information is used to indicate the first result, and the second instruction information is used to indicate the storage unit or storage unit set corresponding to the first result.
[0018] Optionally, the method further includes sending a programming start command to the memory computing device.
[0019] Optionally, the method further includes: receiving a second indication message from the memory device, the second indication message indicating a second result of the second write, the second write being used to adjust the first weight data written to the memory circuit; generating a burning end command based on the second result, and sending the burning end command to the memory device.
[0020] Optionally, the method further includes: based on the current burning state of the storage circuit, dividing the multiple storage cells that have not been burned into at least two storage cell sets, the at least two storage cell sets including a first storage cell set and a second storage cell set, the first storage cell set and the second storage cell set having different start times for their burning cycles and overlapping time periods.
[0021] Optionally, storage cells in the same storage cell set have the same programming parameter settings; and / or, storage cells in the same storage cell set have independent signal terminals.
[0022] Optionally, based on the current burning state of the storage circuit, the multiple storage cells that have not been burned are divided into at least two storage cell sets, including: determining the multiple storage cells that have not been burned based on the current burning state of the storage circuit; and dividing the multiple storage cells into at least two storage cell sets according to one or more of the following factors: the physical location of the storage cells of the storage circuit, the connection method of the storage cells of the storage circuit, the transmission delay, and the interference between the storage cells.
[0023] Optionally, the first programming instruction and the second programming instruction are used to write first weight data to the first set of storage cells. The method further includes: sending a third programming instruction to the in-memory computing device, the third programming instruction including third programming parameters, the third programming parameters being used to control a third write, the third write being used to write second weight data to the second set of storage cells; receiving a third indication message from the in-memory computing device, the third indication message being used to indicate a third result of the third write; generating a fourth programming instruction based on the third result, the fourth programming instruction including fourth programming parameters, the fourth programming parameters being used to control a fourth write, the fourth write being used to adjust the second weight data written to the second set of storage cells; and sending the fourth programming instruction to the in-memory computing device.
[0024] Thirdly, embodiments of this application also provide a programming apparatus, including an interface circuit and at least one processing circuit, wherein the interface circuit is used to communicate with a server, and the at least one processing circuit is used to execute any of the programming methods described in the first aspect above.
[0025] Fourthly, embodiments of this application also provide a programming apparatus, including an interface circuit and at least one processing circuit, wherein the interface circuit is used to communicate with a memory computing device, and the at least one processing circuit is used to execute a programming method as described in any of the second aspects above.
[0026] Fifthly, embodiments of this application also provide a programming system, which includes a memory computing device and a server. The memory computing device is used to execute the programming method as described in any of the first aspects above; the server is used to execute the programming method as described in any of the second aspects above.
[0027] Sixthly, embodiments of this application also provide a storage device, including a programming device and a storage circuit as described in any of the third aspects above.
[0028] In a seventh aspect, embodiments of this application also provide an electronic device, including a storage computing device as described in any of the sixth aspects above.
[0029] The technical solution of this application separates the physical execution and control computation of the programming process onto different devices. The physical execution part of the programming can run on the in-memory computing device, while the programming control part can run on a server-side device different from the in-memory computing device. The programming results can be sent to the server-side device for calculation in the next programming iteration to generate programming instructions. In this way, the physical execution and control of programming can be separated, reducing the programming control requirements of the in-memory computing device, thereby reducing the computing power requirements of the programming control part of the in-memory computing device, and thus reducing the complexity and cost of the in-memory computing device. In addition, this programming method has high flexibility, which can reduce the customization requirements of the programming control part of the in-memory computing device, enabling the in-memory computing device to meet the flexibility requirements of writing data with different weights when used for computation in different business scenarios. Attached Figure Description
[0030] Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.
[0031] Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.
[0032] Figure 3 shows an architecture diagram of a burning system according to an exemplary embodiment of this application.
[0033] Figure 4 shows a flowchart of a programming method according to an exemplary embodiment of this application.
[0034] Figure 5 shows a flowchart of another burning method according to an exemplary embodiment of this application.
[0035] Figure 6 illustrates a schematic diagram of the parallel burning process of a set of storage cells according to an exemplary embodiment of this application.
[0036] Figure 7 shows a schematic diagram of a programming apparatus according to an exemplary embodiment of this application.
[0037] Figure 8 shows a schematic diagram of a programming apparatus according to an exemplary embodiment of this application.
[0038] Figure 9 shows a schematic diagram of an electronic device according to an exemplary embodiment of this application. Detailed Implementation
[0039] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.
[0040] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.
[0041] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.
[0042] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.
[0043] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.
[0044] In in-memory computing technology, storage and computation (or arithmetic) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and a processing circuit (or control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), or phase change memory (PCM).
[0045] For ease of understanding, Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application. This in-memory computing system is described as an example of implementing in-memory computing using memory as a carrier.
[0046] As shown in Figure 1, the in-memory computing system 100 may include a storage circuit (or in-memory computing circuit) 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.
[0047] Storage cells can utilize the conduction capability of semiconductor devices, such as electrical conductance or transconductance, to store weight data. For example, a storage cell may include a resistive storage device or a transistor storage device. For instance, weight data can be stored by controlling the electrical conductance of a resistive storage device, or by controlling the transconductance of a transistor storage device.
[0048] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group can achieve an equivalent multiplication operation. The storage cell array includes one-dimensional arrays, two-dimensional arrays, or three-dimensional arrays, etc., and the storage cell group includes multiple storage cells located in the same row or column, or multiple storage cells located in multiple rows or columns, etc. These multiple storage cells can output their output signals collinearly.
[0049] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).
[0050] As an example, Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.
[0051] As shown in Figure 2, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells S. ij Where i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data W ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:
[0052] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible embodiments, the input signal to the memory cell array 210 may include a digital signal, which is represented by the signal's waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 210.
[0053] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more of the following: signal type conversion, signal magnitude conversion, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For example, if the input signal includes a voltage signal and the output signal includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242. The second conversion may be implemented, for example, through a sampling circuit, and the signal converted by the first conversion circuit 241 can be further provided to the second conversion circuit 242 for the second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert the current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal and provide it to the subsequent circuit. For example, the output circuit may include a sense amplifier (SA), which can sense and amplify the signal obtained from the memory cell array 210 or the first conversion circuit 241. Additionally, in the example of Figure 2, the memory computing system 200 may also include a control circuit 220, which can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.
[0054] Figure 2 is only an example illustrating a connection method of memory cells in a memory cell array 210. Other connection methods can be used besides those shown in Figure 2. For example, the input terminals of the memory cells can be connected collinearly by columns, and the output terminals can be connected collinearly by rows. Furthermore, the input terminal of a memory cell can include the gate of a transistor memory device, or it can include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, the memory cell can include a floating gate transistor (FGT), a memristor, a magnetic tunnel junction (MTJ), or a phase-change structure. Furthermore, a memory cell can include multiple transistors; for example, a memory cell can include a first transistor and a second transistor, where the gate of one transistor is connected to the source or drain of the other transistor, and the charge stored at the gate can be used to characterize weight data. Optionally, the gate can also be connected to a capacitor to increase the stability and duration of the stored charge.
[0055] Programming is the operation of writing weight data into the memory circuit, and it is the main process by which the memory circuit performs in-memory calculations. Unlike writing regular data, writing weight data requires more precise control over the programming result. To achieve more precise programming control, the control circuit, in the programmed state of the memory circuit, controls the writing of weight data through multiple iterations. Each iteration includes the physical execution control of writing the weight data and the calculation of the next programming control instruction. Thus, the programming process consumes a significant amount of the in-memory computing system's computing power for programming control.
[0056] In view of this, embodiments of this application provide a programming method, apparatus, and system that can separate the physical execution and control of programming, reducing the programming control requirements of the in-memory computing system and lowering the computing power requirements of the programming control section, thereby reducing the complexity and cost of the in-memory computing system. Furthermore, this programming method offers high flexibility, reducing the customization requirements for the programming control section of the in-memory computing system, enabling the in-memory computing system to meet the flexibility requirements of writing data with different weights when used for computation in different business scenarios.
[0057] Figure 3 shows an architecture diagram of a programming system according to an exemplary embodiment of this application. As shown in Figure 3, the programming system 300 includes a memory computing device 310 and a server 320. The memory computing device 310 can be used for the physical execution of programming, and the server 320 can be used to generate programming control instructions. By performing programming control calculations on the server 320, the control requirements on the memory computing device 310 are reduced, allowing the control part of the memory computing device 310 to free up more space or computing power for business computing control.
[0058] As shown in Figure 3, the server 320 generates a programming instruction and sends it to the in-memory computing device 310. The in-memory computing device 310 performs the programming operation based on the received programming instruction and reads the programming result. The in-memory computing device 310 sends the programming result back to the server 320. Based on the obtained programming result, the server 320 determines the current programming state and, in conjunction with the programming target, performs programming calculations to obtain a programming instruction. This programming instruction is used to control the next programming operation, ensuring that the programming result moves towards the programming target. This process is repeated multiple times. When the programming result shows that the current programming state has reached the programming target, the programming operation on the current storage unit can be completed, and programming operations on other storage units can continue. In a single programming operation, programming control of one or more storage units can be performed; this embodiment of the application does not impose any limitations.
[0059] The in-memory computing device 310 and the server 320 can communicate via wired or wireless means. Wired communication methods include, but are not limited to, communication methods based on optical fibers or cables. Wireless communication methods include, but are not limited to, cellular communication (e.g., 3G, 4G, 5G, or 6G), wireless sensing communication (e.g., Bluetooth, Starlink, or ZigBee), wireless local area network communication (e.g., WLAN, or WiFi), short-range point-to-point communication, or near field communication (NFC).
[0060] This application does not limit the form of the server 320, which may include a server, a cloud server, a cloud virtual machine, or a burning device, etc. Using a server 320 for burning control can leverage the rich resources of the server to achieve optimized layout of the control algorithm. For example, a cloud server or cloud virtual machine can provide more resources and support flexible control of burning.
[0061] Figure 4 shows a flowchart of a programming method according to an exemplary embodiment of this application. The method can be performed by a memory computing device 310. As shown in Figure 4, the method includes:
[0062] S410. Receive a first burning instruction from the server, the first burning instruction including first burning parameters;
[0063] S420. According to the first programming parameters, control the first write, which is used to write the first weight data to the storage circuit;
[0064] S430, Obtain the first result of the first write;
[0065] S440. Send a first indication message to the server. The first indication message is used to indicate the first result.
[0066] S450. Receive a second burning instruction from the server. The second burning instruction is generated based on the first result and includes second burning parameters.
[0067] S460. According to the second programming parameters, control the second writing. The second writing is used to adjust the first weight data written to the storage circuit.
[0068] Figure 5 shows a flowchart of another programming method according to an exemplary embodiment of this application. This method can be executed by the server 320. As shown in Figure 5, the method includes:
[0069] S510. Send a first programming instruction to the memory computing device. The first programming instruction includes a first programming parameter, which is used to control the first write. The first write is used to write first weight data to the memory circuit.
[0070] S520: Receive a first instruction message from the storage device, the first instruction message being used to indicate the first result of the first write;
[0071] S530. Based on the first result, generate a second programming instruction, which includes second programming parameters;
[0072] S540: Send the second programming command to the memory device.
[0073] In the above programming scheme, the physical execution and control computation of programming are separated and performed on different devices. The physical execution part of programming can run on the in-memory computing device, while the programming control part can run on a server device different from the in-memory computing device. The programming results can be sent to the server device for calculation in the next programming iteration to generate programming instructions. In this way, the physical execution and control of programming can be separated, reducing the programming control requirements of the in-memory computing device, thereby reducing the computing power requirements of the programming control part of the in-memory computing device, and reducing the complexity and cost of the in-memory computing device. In addition, this programming method has high flexibility, which can reduce the customization requirements of the programming control part of the in-memory computing device, enabling the in-memory computing device to meet the flexibility requirements of writing data with different weights when used for computation in different business scenarios.
[0074] The above programming instructions (e.g., the first programming instruction or the second programming instruction) can be transmitted encrypted. When the in-memory computing device is used for artificial intelligence calculations, the weight data can reflect the weight information of at least one network layer of the artificial intelligence model. Separating the control of the weight data programming process can provide security protection for the artificial intelligence model, preventing the acquisition of the model's weight information through reverse engineering or other means. Furthermore, encrypted transmission can further enhance the security of programming control and prevent malicious attacks.
[0075] This application does not limit the content of the programming parameters, as long as the memory computing device can determine the control signal based on the programming parameters, and the control signal is used to control the writing of weight data. For example, the programming parameters may include one or more parameters such as the amplitude, pulse width, area, or duration of the control signal. The programming parameters can affect the charge injected into the memory cell, which can be used to reflect the physical characteristics of the weight data, thereby controlling the writing of the weight data through the input of the control signal. According to some embodiments, the programming parameters (e.g., the first programming parameter or the second programming parameter) may include, for example, one or more of the above parameters of the control signal. According to some embodiments, the programming parameters may include control parameters, which can be used to indicate the adjustment range or adjustment size of the control signal parameters, and the control signal can be adjusted to the target range or size based on the control parameters.
[0076] This application does not limit the content of the written result. Depending on the type of storage circuit, the result can have different content. The result may include signal parameters related to the weight data, such as threshold voltage, node voltage, or readout current.
[0077] Referring to Figure 3, the server 320 generating a programming instruction based on the current programming result (e.g., the first result) may include: determining programming parameters (e.g., a second programming parameter) based on the current programming result and the programming target. This application does not limit the content of the programming target. The programming target may correspond to the result, for example, including a target range such as threshold voltage, node voltage, or readout current. For example, the server may determine the difference between the current programming result and the target based on the current programming result and the programming target, convert this difference into programming parameters, and provide them to the memory computing device 310. The memory computing device 310 may then input control signals to the storage circuit based on the programming parameters to control the writing of weight data to move closer to the target.
[0078] The storage circuit may include multiple storage cells, and the programming of storage cells can be performed independently, or the programming of some storage cells can be performed in parallel. According to some embodiments, the server may specify the storage cells or sets of storage cells to be programmed in the programming instructions.
[0079] According to some embodiments, the memory cell or set of memory cells to be programmed can be indicated by address information. For example, the above programming instructions (e.g., a first programming instruction or a second programming instruction) may include address information. This address information is used to indicate the memory cell or set of memory cells to be programmed in the memory circuit.
[0080] This simplifies the generation of programming instructions and allows for flexible support of changes in the number of memory units to be programmed. For example, an instruction template can be set, and the server can modify the address field in the programming instruction based on the address of the memory unit to be programmed; and modify the programming parameter settings based on the current write result. Furthermore, this programming instruction can instruct the memory units to be programmed through relatively simple field settings, saving communication resources.
[0081] According to some embodiments, the memory cell or set of memory cells to be programmed can be indicated by address information and identification information. The above programming instructions (e.g., a first programming instruction or a second programming instruction) may include address information and identification information, which are configured correspondingly. The address information is used to indicate the memory cell or set of memory cells in the memory circuit; the identification information is used to indicate the programming status of the corresponding memory cell or set of memory cells.
[0082] In this way, based on the range of memory cells that can be programmed in parallel supported by the programming instructions and the address of the memory cell currently being programmed, the identification information field indicating whether programming is being performed on memory cells within that range can be updated. This simplifies the generation process of programming instructions within the range of memory cells to be programmed in parallel, and improves programming efficiency.
[0083] According to some embodiments, the programming order of storage cells or sets of storage cells in the storage circuit can be preset, and the in-memory computing device and the server have the same settings for this programming order. When the in-memory computing device receives a programming instruction or a programming start instruction, it can perform writing based on the preset programming order. In this way, address information or identification information can be avoided, saving transmission resources.
[0084] The above programming method can be applied to the initial programming of the memory computing device; it can also be applied to the updating of weight data during the use of the memory computing device. This simplifies the cost and efficiency of weight data updating, and weight data updating can be achieved through remote control.
[0085] According to some embodiments, the above programming method may further include: the server sending a programming start command to the in-memory computing device. Correspondingly, the in-memory computing device receives the programming start command from the server; and, based on the programming start command, erases all or part of the storage area of the storage circuit.
[0086] A programming start command can be used to instruct the in-memory computing device to begin programming the memory circuit. Optionally, the programming start command can be used solely to initiate the programming of the memory circuit, preparing the memory circuit based on the programming start command, such as erasing all or part of the memory area. Optionally, the programming start command can be similar to the above programming commands, carrying programming parameters, allowing the in-memory computing device to input control signals for writing weight data based on the programming command. Optionally, the programming start command may also include indication information of the memory area (e.g., memory cell or set of memory cells) to be programmed in the memory circuit, such as address information, address information, and identification information.
[0087] After receiving the programming start command, the memory computing device can erase the memory area to be programmed in the memory circuit indicated by the programming start command in order to prepare for the subsequent programming of memory computing units.
[0088] After receiving the first programming instruction from the server, the in-memory computing device can perform a first write operation based on the first programming parameters in the instruction, writing the first weight data into the storage circuit. The in-memory computing device can read or sense the first result of the first write operation and indicate the first result to the server through an instruction message.
[0089] According to some embodiments, the instruction message (e.g., a first instruction message) may include first instruction information and second instruction information, wherein the first instruction information is used to indicate a first result, and the second instruction information is used to indicate the storage unit or set of storage units corresponding to the first result. According to other embodiments, the in-memory computing device performs programming control according to a preset programming sequence, in which case the instruction message may not carry the second instruction information.
[0090] The first write may include writing to all or part of the storage cells in the storage area to be programmed in the memory array. The second indication information may indicate the storage cell or set of storage cells corresponding to the first result of the first write.
[0091] The server receives the first instruction message, determines the first result of the first write based on the first instruction message, and generates a second programming instruction based on the first result. The storage units indicated for programming in the first and second programming instructions can be the same or different. For example, the address information in the first and second programming instructions can be the same or different, or the identification information in the first and second programming instructions can be the same or different. For instance, if none of the storage units in the current set of storage units to be programmed have been completed, the address information in the first and second programming instructions can be the same, or the address information and identification information in the first and second programming instructions can be the same. Alternatively, if some storage units in the current set of storage units to be programmed have been completed, the address information in the first and second programming instructions can be different. For example, the second programming instruction may not include the address information of the storage units that have been programmed; or the address information in the first and second programming instructions can be the same, but the identification information is different. For example, the identification information of the storage units that have been programmed in the second programming instruction may indicate that programming is complete.
[0092] The above programming method allows for iterative programming control via the server during the programming process of the storage circuit, thereby precisely controlling the programming results.
[0093] According to some embodiments, the storage cells of the storage circuit can be divided into multiple sets of storage cells that can be programmed in parallel, thereby improving programming efficiency. Furthermore, during the programming control process, there is a certain transmission delay in the communication between the server and the computing device. Parallel programming can be performed while one set of storage cells is waiting for transmission, reducing the impact of transmission delay and improving programming efficiency.
[0094] For example, according to some embodiments, the storage circuit may include multiple sets of storage cells, the start times of the programming cycles of these multiple sets of storage cells are different, and the programming cycles have overlapping time periods. For example, the multiple sets of storage cells may include a first set of storage cells and a second set of storage cells, the start times of the programming cycles of the first set of storage cells and the second set of storage cells are different, and the programming cycles have overlapping time periods.
[0095] The first and second memory cell sets are only used as examples to illustrate the division and diversity programming of memory cell sets, and do not mean that the memory cell set of the memory circuit can only be divided into two memory cell sets.
[0096] According to some embodiments, storage cells within the same storage cell set have the same programming parameter settings. Grouping storage cells with the same programming parameters into the same storage cell set can simplify the configuration of programming parameters and improve programming efficiency.
[0097] During the programming process, some storage units may disturb each other. Dividing storage units that may disturb each other into different storage unit sets can prevent the programming of the next storage unit set from causing a large disturbance when the programming of the previous storage unit set has reached the target and the programming is completed, thus preventing the programming result of the previous storage unit set from deviating significantly from the target value.
[0098] For example, according to some embodiments, memory cells within the same memory cell set have independent signal terminals. Grouping memory cells with independent signal terminals into the same memory cell set can reduce mutual interference during the programming process. These signal terminals may include, for example, a terminal for inputting control signals when writing weight data, a terminal for inputting signals during calculation, or a terminal for reading out output signals.
[0099] According to some embodiments, the division of storage cell sets can be determined based on one or more of the following factors: the physical location of the storage cells in the storage circuit, the connection method of the storage cells in the storage circuit, transmission delay, and interference between storage cells. For example, dividing storage cells whose physical locations are more than a preset range apart into the same storage cell set can reduce the impact of mutual disturbance between storage cells on programming; furthermore, dividing storage cells that are not connected in a collinear or common terminal manner into the same storage cell set according to the connection method between storage cells can reduce the impact of mutual disturbance between storage cells on programming; furthermore, dividing storage cells whose interference is less than a preset range into the same storage cell set according to the interference between storage cells can reduce the impact of mutual disturbance between storage cells on programming; and furthermore, the number of storage cell sets that can be programmed in parallel can be determined based on transmission delay. Transmission delay can include bidirectional or unidirectional delay for communication between the storage device and the server, and this application embodiment does not impose any limitations.
[0100] The partitioning of memory cell sets in a memory circuit can be done using either static or dynamic diversity methods. In static partitioning, the memory cells within a set remain unchanged regardless of the current programming state. Identification information can be used to indicate whether a set of cells has been completed or not. The programming of a set is considered complete when all cells within it have been programmed. In dynamic partitioning, the memory cells within a set can change. For example, based on the current programming state of the memory circuit, incompletely programmed cells can be divided into multiple sets, and this partitioning can be dynamically adjusted as the programming state of the memory circuit changes. This further improves the programming efficiency of the memory circuit.
[0101] According to some embodiments, the server can divide the unburned storage units into at least two storage unit sets based on the current burning status of the storage circuit.
[0102] According to some embodiments, the server divides the unburned storage units into at least two sets of storage units based on the current burning state of the storage circuit, including: determining the unburned storage units based on the current burning state of the storage circuit; dividing the unburned storage units into at least two sets of storage units according to one or more of the following factors: the physical location of the storage units of the storage circuit, the connection method of the storage units of the storage circuit, the transmission delay, and the interference between storage units, etc.
[0103] According to some embodiments, pipelined programming can be performed between memory cell sets to further improve programming efficiency and reduce the impact of transmission latency. For example, during the programming process of the first memory cell set, while the server and the in-memory computing device are transmitting data, the second memory cell set can be programmed. For instance, the server can generate and calculate programming instructions for the second memory cell set, and the in-memory computing device can perform physical execution control of programming the second memory cell set. In this way, the transmission latency during the programming process can be masked, and the in-memory computing device can remain in a programming state for a macroscopic period of time, thereby improving programming efficiency.
[0104] For example, Figure 6 illustrates a schematic diagram of the parallel programming process of a set of memory cells according to an exemplary embodiment of this application. The programming process of the set of memory cells may include a loop of multiple processes, such as the physical writing process of the memory computing device controlling the memory circuit (Figure 6 shows programming), the communication process between the server and the memory computing device (Figure 6 shows transmission), and the process of the server performing calculations based on the writing results to obtain programming instructions (Figure 6 shows calculation). The communication process may include the transmission of programming instructions or the transmission of instruction messages. As can be seen from Figure 6, during the transmission process of the set of memory cells 1, the set of memory cells 2 can be programmed or calculated, thereby making full use of the transmission latency and improving programming efficiency.
[0105] According to some embodiments, the size of the storage unit set can be determined based on the transmission latency, so that the storage unit set can make full use of the transmission latency and further improve the burning efficiency.
[0106] Taking the programming process of the first and second storage unit sets as an example, according to some embodiments, the first programming instruction and the second programming instruction are used to write first weight data to the first storage unit set. The programming method shown in Figure 4 above may further include: receiving a third programming instruction from the server, the third programming instruction including third programming parameters; controlling a third write according to the third programming parameters, the third write being used to write second weight data to the second storage unit set; obtaining a third result of the third write; sending a third indication message to the server, the third indication message being used to indicate the third result; receiving a fourth programming instruction from the server, the fourth programming instruction being generated based on the third result and including fourth programming parameters; controlling a fourth write according to the fourth programming parameters, the fourth write being used to adjust the second weight data written to the second storage unit set.
[0107] Accordingly, the programming method shown in Figure 5 above further includes: sending a third programming instruction to the in-memory computing device, the third programming instruction including third programming parameters, the third programming parameters being used to control a third write, the third write being used to write second weight data to the second set of storage cells; receiving a third indication message from the in-memory computing device, the third indication message being used to indicate a third result of the third write; generating a fourth programming instruction based on the third result, the fourth programming instruction including fourth programming parameters, the fourth programming parameters being used to control a fourth write, the fourth write being used to adjust the second weight data written to the second set of storage cells; and sending the fourth programming instruction to the in-memory computing device.
[0108] According to some embodiments, the server can notify the in-memory computing device to complete the burning process when the writing result reaches the burning target. For example, taking the second result of the second writing as an example of reaching the burning target, the above burning method further includes: the in-memory computing device obtaining the second result of the second writing; sending a second indication message to the server, the second indication message indicating the second result; and receiving a burning end command from the server, the burning end command being generated based on the second result. Accordingly, the server receives the second indication message, generates a burning end command based on the second result in the second indication message, and sends the burning end command to the in-memory computing device. For example, the server generates a burning end command when it determines that the current burning state has reached the burning target based on the second result.
[0109] The burning process in this embodiment is an iterative process. The first burning instruction, the second burning instruction, the first burning parameter, the second burning parameter, the first write, the second write, the first result, the second result, etc. in this embodiment do not refer to the order and can include any two adjacent burning processes in the burning process.
[0110] During the iteration process, the server can determine whether the burning target has been reached based on the current writing result. If the burning target has been reached, a burning end command is generated; if the burning target has not been reached, the next round of burning process continues.
[0111] This application also provides a programming apparatus, which may be located within a memory computing device, for example, integrated into the control circuit of the memory computing system or independent of the control circuit. The programming apparatus may include units or means for performing the programming method described above by the memory computing device.
[0112] Figure 7 shows a schematic diagram of a programming apparatus according to an exemplary embodiment of this application. As shown in Figure 7, the programming apparatus 700 includes an interface circuit 710 and at least one processing circuit 720. The interface circuit 710 is used to communicate directly or indirectly with a server, and the at least one processing circuit 720 is used to execute a programming method as performed by any of the memory computing devices in the embodiments of this application.
[0113] Figure 8 shows a schematic diagram of a programming apparatus according to an exemplary embodiment of this application. As shown in Figure 8, the programming apparatus 800 includes an interface circuit 810 and at least one processing circuit 820. The interface circuit 810 is used to communicate with a memory computing device, and the at least one processing circuit 820 is used to execute a programming method executed by a server as described in any of the embodiments of this application.
[0114] According to some embodiments, the processing circuit is a circuit with signal processing capabilities. For example, the processing circuit may be a circuit with instruction reading and execution capabilities. In other possible embodiments, the processing circuit can implement its functions through the logical relationship of hardware circuits, which may be fixed or reconfigurable. For example, the processing circuit may include hardware circuits implemented by ASICs or PLDs, such as field-programmable gate arrays (FPGAs). In reconfigurable hardware circuits, the process of the processing circuit loading a configuration document and implementing the hardware circuit configuration can be understood as the process of the processing circuit loading instructions to implement the functions of some or all of the above units. This application does not limit the type of processing circuit, such as a central processing unit (CPU), microcontroller unit (MCU), graphics processing unit (GPU), or digital signal processor. Alternatively, it may be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), tensor processing unit (TPU), deep learning processing unit (DPU), etc.
[0115] In some possible embodiments, the units in the above-described programming apparatus may be integrated together in whole or in part, or may be implemented independently. In some embodiments, these units are integrated together and implemented as a system on chip (SOC).
[0116] This application also provides a programming system, which may include: a memory computing device and a server.
[0117] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause any of the burning methods described in the above embodiments to be executed.
[0118] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause any of the programming methods described in the above embodiments to be executed.
[0119] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0120] This application also provides a memory computing device, including a programming device and a storage circuit, wherein the programming device is used to execute any of the programming methods performed by the memory computing device described above.
[0121] This application also provides an electronic device, as shown in FIG. 9. FIG. 9 illustrates a schematic diagram of an electronic device according to an exemplary embodiment of this application. As shown in FIG. 9, the electronic device 900 may include any of the above-described in-memory computing devices 910 for processing data of the electronic device. The electronic device may also include an input / output device 920 for receiving user input or outputting processing results. This application does not limit the input type and output type; for example, input may include voice input, text input, image input, or video input, etc. The output may include text output, voice output, image output, or video output, etc. The electronic device may also include a processor 930, which may process data provided to the in-memory computing device 910 or process the output data of the in-memory computing device 910. The output of the input / output device 920 may be based on the output of the processor 930 or the output of the in-memory computing device 910. This application does not limit the type of processor; for example, the above description of the processing circuit can be referred to.
[0122] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.
[0123] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.
Claims
1. A programming method, characterized in that, Performed by a memory computing device, the memory computing device including storage circuitry, the method includes: Receive a first burning instruction from the server, the first burning instruction including a first burning parameter; Based on the first programming parameters, the first write is controlled, and the first write is used to write first weight data to the storage circuit; Obtain the first result of the first write; Send a first indication message to the server, the first indication message being used to indicate the first result; Receive a second burning instruction from the server, the second burning instruction being generated based on the first result and including a second burning parameter; Based on the second programming parameters, a second write operation is controlled, which is used to adjust the first weight data written to the storage circuit.
2. The method according to claim 1, characterized in that, The first and second programming instructions include address information, which is used to indicate the memory cell or set of memory cells to be programmed in the memory circuit; or, The first programming instruction and the second programming instruction include address information and identification information, which are set correspondingly. The address information is used to indicate the storage cell or storage cell set in the storage circuit, and the identification information is used to indicate the programming status of the corresponding storage cell or storage cell set.
3. The method according to claim 1 or 2, characterized in that, The first indication message includes first indication information and second indication information. The first indication information is used to indicate the first result, and the second indication information is used to indicate the storage unit or storage unit set corresponding to the first result.
4. The method according to any one of claims 1-3, characterized in that, Also includes: Receive the burning and startup command from the server; According to the burning start command, erase all or part of the storage area of the storage circuit.
5. The method according to any one of claims 1-4, characterized in that, Also includes: Obtain the second result of the second write; Send a second indication message to the server, the second indication message being used to indicate the second result; The server receives a burning end command, which is generated based on the second result.
6. The method according to any one of claims 1-5, characterized in that, The storage circuit includes multiple sets of storage cells, including a first set of storage cells and a second set of storage cells. The start times of the burning cycles of the first set of storage cells and the second set of storage cells are different and overlap in time.
7. The method according to claim 6, characterized in that, Storage cells within the same storage cell set have the same programming parameter settings; and / or Storage cells within the same storage unit group have independent signal terminals.
8. The method according to claim 6 or 7, characterized in that, The division of the multiple sets of storage cells is determined based on one or more of the following factors: the physical location of the storage cells of the storage circuit, the connection method of the storage cells of the storage circuit, the transmission delay, and the interference between storage cells.
9. The method according to any one of claims 6-8, characterized in that, The first programming instruction and the second programming instruction are used to write the first weight data to the first storage cell set, and the method further includes: Receive a third burning instruction from the server, the third burning instruction including third burning parameters; According to the third programming parameters, the third write is controlled, and the third write is used to write the second weight data to the second storage cell set; Obtain the third result of the third write; Send a third indication message to the server, the third indication message being used to indicate the third result; The server receives a fourth burning instruction, which is generated based on the third result and includes fourth burning parameters. According to the fourth programming parameters, the fourth write is controlled, and the fourth write is used to adjust the second weight data written to the second storage cell set.
10. A programming method, characterized in that, Executed by the server, the method includes: Send a first programming instruction to the in-memory computing device. The first programming instruction includes a first programming parameter. The first programming parameter is used to control a first write. The first write is used to write first weight data to the storage circuit. Receive a first indication message from the storage device, the first indication message being used to indicate the first result of the first write; Based on the first result, a second programming instruction is generated, the second programming instruction including a second programming parameter; Send the second programming command to the memory computing device.
11. The method according to claim 10, characterized in that, The first and second programming instructions include address information, which is used to indicate the memory cell or set of memory cells to be programmed in the memory circuit; or, The first programming instruction and the second programming instruction include address information and identification information, which are set correspondingly. The address information is used to indicate the storage cell or storage cell set in the storage circuit, and the identification information is used to indicate the programming status of the corresponding storage cell or storage cell set.
12. The method according to claim 10 or 11, characterized in that, The first indication message includes first indication information and second indication information. The first indication information is used to indicate the first result, and the second indication information is used to indicate the storage unit or storage unit set corresponding to the first result.
13. The method according to any one of claims 10-12, characterized in that, Also includes: Send a programming start command to the memory computing device.
14. The method according to any one of claims 10-13, characterized in that, Also includes: Receive a second indication message from the storage device, the second indication message being used to indicate a second result of the second write, the second write being used to adjust the first weight data written to the storage circuit; Based on the second result, a programming end command is generated and sent to the memory computing device.
15. The method according to any one of claims 10-14, characterized in that, Also includes: Based on the current burning status of the storage circuit, the multiple storage cells that have not been burned are divided into at least two storage cell sets. The at least two storage cell sets include a first storage cell set and a second storage cell set. The first storage cell set and the second storage cell set have different start times for their burning cycles and have overlapping time periods.
16. The method according to claim 15, characterized in that, Storage cells within the same storage cell set have the same programming parameter settings; and / or Storage cells within the same storage unit group have independent signal terminals.
17. The method according to claim 15 or 16, characterized in that, Based on the current programming state of the storage circuit, the multiple storage cells that have not yet been programmed are divided into at least two storage cell sets, including: Based on the current burning status of the storage circuit, identify multiple storage cells that have not been burned. The plurality of memory cells that have not been programmed are divided into at least two memory cell sets based on one or more of the following factors: the physical location of the memory cells of the memory circuit, the connection method of the memory cells of the memory circuit, the transmission delay, and the interference between memory cells.
18. The method according to any one of claims 15-17, characterized in that, The first programming instruction and the second programming instruction are used to write the first weight data to the first storage cell set, and the method further includes: Send a third programming instruction to the in-memory computing device. The third programming instruction includes a third programming parameter, which is used to control a third write. The third write is used to write second weight data to the second storage unit set. Receive a third indication message from the storage device, the third indication message being used to indicate the third result of the third write; Based on the third result, a fourth programming instruction is generated. The fourth programming instruction includes a fourth programming parameter, which is used to control a fourth write. The fourth write is used to adjust the second weight data written to the second storage cell set. Send the fourth programming instruction to the memory computing device.
19. A programming device, characterized in that, It includes an interface circuit and at least one processing circuit, the interface circuit being used to communicate with a server, and the at least one processing circuit being used to execute the burning method as described in any one of claims 1-9.
20. A programming device, characterized in that, It includes an interface circuit and at least one processing circuit, the interface circuit being used to communicate with a memory computing device, and the at least one processing circuit being used to perform the programming method as described in any one of claims 10-18.
21. A programming system, characterized in that, Includes in-memory computing devices and server-side components; The storage device is used to perform the burning method as described in any one of claims 1-9; The server is used to execute the burning method as described in any one of claims 10-18.
22. A storage computing device, characterized in that, Includes the programming device and storage circuit as described in claim 19.
23. An electronic device comprising the memory computing device as described in claim 22.