Ternary inverter comprising heterojunction transistor

Abstract

One embodiment of a ternary inverter is provided. The ternary inverter comprises a gate electrode. The gate electrode overlaps with a first tellurium oxide layer in a P-type transistor area. An n-type oxide semiconductor layer and a second tellurium oxide layer, which form a PN junction overlapping with the gate electrode, are arranged in a heterojunction transistor area. A high dielectric constant gate insulating film is arranged between the gate electrode and the first tellurium oxide layer, between the gate electrode and the n-type oxide semiconductor layer, and between the gate electrode and the second tellurium oxide layer. A first electrode connected to the first tellurium oxide layer, a second electrode connected to both the first tellurium oxide layer and the second tellurium oxide layer, and a third electrode connected to the n-type oxide semiconductor layer are arranged.

Description

A ternary inverter including a heterojunction transistor

[0001] The present invention relates to a semiconductor device, and specifically to an inverter.

[0002] The rapid development of information and communication technologies, including artificial intelligence (AI), big data, and the Internet of Things (IoT), is creating a massive demand for exponentially increasing computing and memory capacity. This increase in computing speed and memory capacity can significantly increase the energy consumption of systems including memory and processing units composed of binary devices based on CMOS technology.

[0003] Therefore, there is a growing need for multi-valued logic devices that can achieve enhanced data processing capabilities, significantly simplify circuit design, and reduce power consumption.

[0004] The problem that the present invention aims to solve is to provide a ternary inverter capable of outputting three logic values.

[0005] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0006] To achieve the above objective, an embodiment of a ternary inverter is provided. The ternary inverter comprises a gate electrode. In a P-type transistor region, the gate electrode and a first tellurium oxide layer overlap. In a heterojunction transistor region, an n-type oxide semiconductor layer and a second tellurium oxide layer are disposed to form a PN junction overlapped with the gate electrode. A high dielectric constant gate insulating film is disposed between the gate electrode and the first tellurium oxide layer, between the gate electrode and the n-type oxide semiconductor layer, and between the gate electrode and the second tellurium oxide layer. A first electrode connected to the first tellurium oxide layer, a second electrode connected to both the first tellurium oxide layer and the second tellurium oxide layer, and a third electrode connected to the n-type oxide semiconductor layer are disposed.

[0007] It may further include a passivation layer disposed on a first tellurium oxide layer exposed between the first electrode and the second electrode. The passivation layer may be a metal oxide insulating film. The passivation layer may be an Al2O3, HfO2, or ZrO2 layer.

[0008] The thickness of the first tellurium oxide layer may be thinner than the thickness of the second tellurium oxide layer. The thickness of the first tellurium oxide layer may be 2 nm or more and less than 5 nm, and the thickness of the second tellurium oxide layer may be greater than 4 nm and less than or equal to 10 nm.

[0009] The gate insulating film may be a double layer of a hafnium oxide film located adjacent to the gate electrode and an aluminum oxide film located adjacent to the n-type oxide semiconductor layer and the tellurium oxide layers.

[0010] The above n-type oxide semiconductor layer may be an IGTO (In-Ga-Sn-O) layer.

[0011] The n-type oxide semiconductor layer forming the PN junction and the second tellurium oxide layer may be arranged such that the n-type oxide semiconductor layer overlaps a portion of the upper part of the second tellurium oxide layer. The first to third electrodes may be ITO electrodes.

[0012] To achieve the above objective, another embodiment of a samjin inverter is provided. The samjin inverter comprises a P-type transistor and a heterojunction transistor. The P-type transistor comprises a first gate electrode, a first tellurium oxide layer, a high dielectric constant gate insulating film disposed between the first gate electrode and the first tellurium oxide layer, and a first electrode and a second electrode respectively connected to both ends of the first tellurium oxide layer. The heterojunction transistor comprises a second gate electrode to which an input voltage (Vin) identical to that of the first gate electrode is applied, an n-type oxide semiconductor layer and a second tellurium oxide layer forming a PN junction, a high dielectric constant gate insulating film disposed between the second gate electrode and the n-type oxide semiconductor layer and between the gate electrode and the second tellurium oxide layer, the second electrode also connected to the second tellurium oxide layer, and a third electrode connected to the n-type oxide semiconductor layer. A power supply voltage (V) to the first electrode DD ) is applied, a reference voltage is applied to the third electrode or grounded, and the second electrode is an output terminal (Vout).

[0013] According to embodiments of the present invention, a ternary inverter can output three logic values, allowing for the design of more complex logic circuits with fewer transistors compared to a binary inverter, and thereby increasing computational processing speed even with low power consumption.

[0014] Furthermore, the ternary inverter according to one embodiment of the present invention can exhibit a reduction in driving voltage by using a high dielectric constant gate insulating film, and accordingly, power consumption can be further reduced. In addition, the off-current of the P-type transistor can be reduced by forming the thickness of the first tellurium oxide layer included in the P-type transistor thinner than the thickness of the second tellurium oxide layer included in the heterojunction transistor. Furthermore, the off-current of the P-type transistor can be further reduced by forming a passivation layer on the first tellurium oxide layer. The logic state "0" of the ternary inverter can be efficiently generated.

[0015] However, the effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below.

[0016] FIG. 1 is a plan view showing a triad inverter according to one embodiment of the present invention.

[0017] Figure 2 is a cross-sectional view taken along the cutting line II′ of Figure 1.

[0018] Figure 3 is an equivalent circuit diagram of the ternary inverter shown in Figures 1 and 2.

[0019] FIG. 4 is a cross-sectional view showing a triad inverter according to another embodiment of the present invention.

[0020] Figure 5 is a graph showing the IV characteristics of a heterojunction transistor.

[0021] Figure 6 is a graph showing the IV characteristics of a triad inverter according to one embodiment of the present invention.

[0022] Figure 7 is a graph showing the Vout-Vin characteristics of a samjin inverter according to one embodiment of the present invention.

[0023] FIG. 8 is a schematic diagram showing a heterojunction transistor according to heterojunction transistor manufacturing example 1.

[0024] FIG. 9 is a graph showing the IV characteristics of heterojunction transistors according to heterojunction transistor manufacturing examples 1 to 3.

[0025] FIG. 10 is a graph showing the IV characteristics of heterojunction transistors according to heterojunction transistor manufacturing examples 4 to 5.

[0026] FIGS. 11a, FIGS. 11b, FIGS. 11c, and FIGS. 11d are graphs showing the IV characteristics of heterojunction transistors according to heterojunction transistor manufacturing examples 6 to 9.

[0027] FIG. 12a is a schematic diagram showing the case where the positions of the source and drain of a heterojunction transistor manufactured according to Example 1 of heterojunction transistor manufacturing are swapped, and FIG. 12b is a graph showing the IV characteristics according to this.

[0028] FIG. 13a is a schematic diagram showing a heterojunction transistor manufactured according to Example 10 of the heterojunction transistor manufacturing process, and FIG. 13b is a graph showing the IV characteristics according to the same.

[0029] Figures 14a and 14b are graphs showing the IV characteristics of P-type transistors according to P-type transistor manufacturing examples 1 and 2, respectively.

[0030] Figure 15 shows graphs representing the IV characteristics of P-type transistors according to P-type transistor manufacturing examples 1, 3, and 4.

[0031] FIG. 16 is a schematic diagram showing a samjin inverter element according to an example of manufacturing a samjin inverter element.

[0032] Figure 17 is a graph showing the IV characteristics of a heterojunction transistor and a P-type transistor included in a Samjin inverter according to the Samjin inverter manufacturing example.

[0033] FIG. 18 shows the V of the Samjin inverter according to the Samjin inverter manufacturing example. out -V in This is a graph showing the characteristics.

[0034] Hereinafter, preferred embodiments according to the present invention will be described in more detail with reference to the accompanying drawings in order to explain the present invention more specifically. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. In the drawings, where a layer is referred to as being "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed between them. In these embodiments, "first," "second," or "third" are not intended to impose any limitations on the components, but should be understood merely as terms to distinguish the components.

[0035]

[0036] FIG. 1 is a plan view showing a ternary inverter according to one embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the cutting line II′ of FIG. 1, and FIG. 3 is an equivalent circuit diagram of the ternary inverter shown in FIG. 1 and FIG. 2. FIG. 4 is a cross-sectional view showing a ternary inverter according to another embodiment of the present invention.

[0037] Referring to FIGS. 1, 2, and 3, a lower insulating film (not shown) may be disposed on a substrate (not shown). The lower insulating film may serve to prevent the inflow of impurities from the substrate, or it may be an insulating film covering other elements formed on the substrate. The substrate may be a semiconductor, metal, glass, or polymer substrate. The substrate may be divided into a region where a P-type transistor (100) is formed and a region where a heterojunction transistor (200) is formed.

[0038] A gate electrode (30) extending in one direction can be formed on a substrate on which the lower insulating film is formed or is not formed. The gate electrode (30) can be formed of a metal or a conductive oxide. As an example, the metal may be Al, Cr, Cu, Ta, Ti, Mo, W, Si, or an alloy thereof, and the conductive oxide may be ITO (indium tin oxide), IZO (indium zinc oxide), ITZO (indium zinc oxide), or ICO (indium cesium oxide). The gate electrode (30) may be formed separately in a P-type transistor region and a heterojunction transistor region, without being limited to those illustrated.

[0039] A gate insulating film (40) can be formed on a gate electrode (30). The gate insulating film (40) may be a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a hafnium oxide film, a zirconium oxide film, or a composite film thereof. In one example, the gate insulating film (40) may be a high dielectric constant insulating film having a higher dielectric constant than that of a silicon oxide film. Specifically, the gate insulating film (40) may have a first gate insulating film (41) and a second gate insulating film (43) having different dielectric constants or dielectric constants. The first gate insulating film (41) may be a hafnium oxide film having a high dielectric constant, which can reduce leakage current and reduce driving voltage. The hafnium oxide film may be formed to a thickness of 10 to 20 nm. The second gate insulating film (43) may be an aluminum oxide film that has a smaller dielectric constant than the first gate insulating film (41) but has low reactivity to the semiconductor layers (51, 52, 53) described later, thereby forming a stable interface. The aluminum oxide film may be formed with a lower thickness than the hafnium oxide film, for example, 3 to 7 nm.

[0040] Specifically, the gate insulating film (40) above, specifically the hafnium oxide film and the aluminum oxide film, can be formed using ALD, specifically PEALD (Plasma Enhanced Atomic Layer Deposition). At this time, the aluminum oxide film is deposited in a mixed atmosphere of oxygen and an inert gas, and the oxygen partial pressure is deposited at about 3 to 7 vol% so that the aluminum oxide film can be in an oxygen-deficient state.

[0041] Afterwards, a first p-type semiconductor layer (51) superimposed with a gate electrode (30) can be formed on the gate insulating film (40) of the above-mentioned p-type transistor region. The first p-type semiconductor layer (51) is metallic Te, i.e., Te 0 A first tellurium oxide layer (TeOx, 0) containing TeO2 <x<2)일 수 있다. 제1 텔루륨 산화물층 내에서 Te 4+ Contrast Te 0 The content of may be greater. The thickness of the first tellurium oxide layer may be 2 nm or more and less than 5 nm, specifically 3 to 4.5 nm, more specifically 3.5 to 4.3 nm. The first p-type semiconductor layer (51) may be formed using a sputtering method and heat-treated at 100 to 200°C after formation. When the first p-type semiconductor layer (51) is formed using a sputtering method, the oxygen partial pressure may be 10 to 20 vol%, specifically 14 to 18 vol%.

[0042] An n-type semiconductor layer (53) superimposed with a gate electrode (30) can be formed on the gate insulating film (40) of the heterojunction transistor region. The n-type semiconductor layer (53) may be an n-type oxide semiconductor layer, for example, an IGTO (In-Ga-Sn-O) layer. Specifically, the IGTO (In-Ga-Sn-O) layer may contain In:Ga:Sn in an atomic ratio of 100-xy:x:y, where x is 21 to 25 and y is 1 or 3. The n-type semiconductor layer (53) may be formed using a sputtering method and heat-treated at 100 to 200°C after formation. When the n-type semiconductor layer (53) is formed using a sputtering method, the oxygen partial pressure may be 3 to 7 vol%.

[0043] A second p-type semiconductor layer (52) can be formed on the gate insulating film (40) of the heterojunction transistor region where the n-type semiconductor layer (53) is formed, adjacent to the first p-type semiconductor layer (51), and forming a PN junction with the n-type semiconductor layer (53). In one example, the upper surface of the n-type semiconductor layer (53) and the lower surface of the second p-type semiconductor layer (52) may partially overlap. The second p-type semiconductor layer (52) is made of metallic Te, i.e., Te 0 A second tellurium oxide layer (TeO2) containing TeO2 x , 0 <x<2)일 수 있다. 제2 텔루륨 산화물층 내에서 Te 4+ Contrast Te 0The content of may be greater. The thickness of the second tellurium oxide layer may be thicker than the first tellurium oxide layer, which is the first p-type semiconductor layer (51). As an example, the thickness of the second tellurium oxide layer may be greater than 4 nm and less than or equal to 10 nm, specifically 4.2 to 8 nm, more specifically 4.5 to 5.5 nm or 4.7 to 5.3 nm. The second p-type semiconductor layer (52) may be formed using a sputtering method and heat-treated at 100 to 200°C after formation. When the second p-type semiconductor layer (52) is formed using a sputtering method, the oxygen partial pressure may be 5 to 16 vol%, specifically 6 to 8 vol%. In one example, the oxygen partial pressure when forming the second p-type semiconductor layer (52) may be lower than the oxygen partial pressure when forming the first p-type semiconductor layer (51).

[0044] In this embodiment, after forming an n-type semiconductor layer (53) in the heterojunction transistor region, a second p-type semiconductor layer (52) is formed that overlaps with an upper part of the n-type semiconductor layer (53); however, this is not limited thereto, and as shown in FIG. 4, after forming a second p-type semiconductor layer (52), an n-type semiconductor layer (53) that overlaps with an upper part of the second p-type semiconductor layer (52) may also be formed.

[0045] Additionally, the n-type semiconductor layer (53) and the second p-type semiconductor layer (52) may not be formed such that the upper surface of one layer and the lower surface of the other layer overlap, but rather the sides of the two layers may come into contact to form a PN junction.

[0046] The semiconductor layers (51, 52, 53) can be formed using various methods used in the field of technology in addition to sputtering, and as an example, can be formed using chemical vapor deposition methods such as chemical vapor deposition and atomic layer deposition, and can also be patterned using various methods used in the field of technology.

[0047] Afterwards, a first electrode (61) connected to the first p-type semiconductor layer (51), a second electrode (62) connected to both the first p-type semiconductor layer (51) and the second p-type semiconductor layer (52), and a third electrode (63) connected to the n-type semiconductor layer (53) can be formed to be spaced apart from each other. The distance between the first electrode (61) and the second electrode (62) can be viewed as the channel length of the P-type transistor (100), and the distance between the second electrode (62) and the third electrode (63) can be viewed as the channel length of the heterojunction transistor (200). The above electrodes (61, 62, 63) can be formed using at least one metal among aluminum (Al), neodymium (Nd), silver (Ag), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo), or an alloy containing these, or a metal oxide conductive film, as an example, ITO (Indium Tin Oxide).

[0048] A passivation layer (55) can be formed on a first p-type semiconductor layer (51) exposed between the first electrode (61) and the second electrode (62). The passivation film may be a metal oxide insulating film such as Al2O3, HfO2, ZrO2, or a metal film such as Ta, Ti, Al, or Zn. In this case, the heat applied during the process of forming the passivation film causes the passivation film to take away oxygen from the tellurium oxide layer, inducing a reduction reaction to Te 0 It can help Hexagonal-Te crystallization by increasing the state.

[0049] The gate electrode (30), gate insulating film (40), first p-type semiconductor layer (51), and first electrode (61) and second electrode (62) connected to each of the two ends of the first p-type semiconductor layer (51) respectively constitute a P-type transistor (100), and the gate electrode (30), gate insulating film (40), PN-junction n-type semiconductor layer (53) and second p-type semiconductor layer (52), and the second electrode (62) connected to the second p-type semiconductor layer (52) and the third electrode (63) connected to the n-type semiconductor layer (53) may constitute a heterojunction transistor (200), and the P-type transistor (100) and the heterojunction transistor (200) may constitute a triangular inverter. Here, the gate electrode (30) may be shared between the P-type transistor (100) and the heterojunction transistor (200) as an input terminal. However, not limited thereto, the P-type transistor (100) and the heterojunction transistor (200) may each be provided with separate gate electrodes, namely a first gate electrode and a second gate electrode, and the same input voltage (Vin) may be applied to these gate electrodes. The first electrode (61) has a power supply voltage (V DD ) is applied, and a reference voltage may be applied to the third electrode (63) or grounded. The second electrode (62) connected to both the first p-type semiconductor layer (51) and the second p-type semiconductor layer (52) may be an output terminal (Vout).

[0050] In the example above, a thin-film transistor with a bottom-gate / top-contact structure was used as an example; however, this is not limited to this and can be applied to thin-film transistors with bottom-gate / bottom-contact structures, top-gate / top-contact structures, or top-gate / bottom-contact structures. Here, a top-gate structure refers to a structure in which the semiconductor layer overlaps below the gate electrode, and a bottom-gate structure refers to a structure in which the source and drain electrodes are electrically connected below the semiconductor layer.

[0051]

[0052] Figure 5 is a graph showing the IV characteristics of a heterojunction transistor.

[0053] Referring to Fig. 5, the heterojunction transistor V GS At Vth,n or higher, current flows through the n-type semiconductor layer (53), specifically the IGZO layer, and V GS At approximately Vth,p or lower, the second p-type semiconductor layer (52), specifically the second TeO x Current flows through the layer, allowing it to operate as an anti-ambipolar transistor, such as by exhibiting an on-state bias range (△Von(Vth,p-Vth,n)). Additionally, the heterojunction transistor V peak At peak current (I peak reached ), and V GS As increases further, the drain current may decrease, at which point PVR (Peak to Valley Ratio, I peak / I valley ) can be defined. In this way, a heterojunction transistor can induce a rapid increase and decrease in current, i.e., a negative differential transconductance (NDT), by supplying a gate bias voltage.

[0054] A heterojunction transistor according to one embodiment of the present invention can operate as a semi-bipolar transistor having a negative differential transconductance (NDT) by having a PN junction structure of an n-type oxide semiconductor, IGTO, which has stable electrical characteristics even with low-temperature heat treatment, and a p-type 2D semiconductor, Tellurium, which has excellent electrical characteristics.

[0055]

[0056] FIG. 6 is a graph showing the IV characteristics of a ternary inverter according to one embodiment of the present invention, and FIG. 7 is a graph showing the Vout-Vin characteristics of a ternary inverter according to one embodiment of the present invention.

[0057] Referring simultaneously to FIGS. 6 and FIGS. 7, the heterojunction transistor V peak At peak current (I peak reached ), and V GS As increases further, the drain current decreases, and V GS When the threshold voltage of the P-type transistor is lower than or equal to the first p-type semiconductor layer (51), specifically the first TeO x Current flows in the layer. The heterojunction transistor and the P-type transistor (P_Tr) g m V before matching GS In the range of, that is, in region I, the drain current of the P-type transistor (P_Tr) is higher than the drain current of the heterojunction transistor, so the conducting path is V DD and output terminal (V out Formed between ) V DD A high voltage close to the value is output at the output terminal (V out Output was generated from ), creating a logic state "2". The heterojunction transistor and the P-type transistor (P_Tr) g m Matching V GS In the range of, that is, in region II, the drain current of the P-type transistor (P_Tr) and the drain current of the heterojunction transistor have similar values, so the conductive path is V DD It is formed between and ground, and V DD The output terminal (V) is divided between two transistors out An intermediate voltage value was output from ), generating a logic state "1". The heterojunction transistor and the P-type transistor (P_Tr) g m V after the matching ends GS In the range of, that is, in region III, the drain current of the heterojunction transistor is higher than the drain current of the P-type transistor (P_Tr), so the conduction path is to the output terminal (V out A low voltage close to the ground voltage is formed between ) and ground, and is output at the output terminal (V out It was output from ) and a logical state "0" was generated.

[0058] As such, the ternary inverter according to one embodiment of the present invention can output three logic values, allowing for the design of more complex logic circuits with fewer transistors compared to a binary inverter, and accordingly, the processing speed can be increased even with low power consumption.

[0059] Furthermore, the triad inverter according to one embodiment of the present invention can exhibit a reduction in driving voltage by using a high dielectric constant gate insulating film, and accordingly, power consumption can be further reduced. In addition, the thickness of the first tellurium oxide layer, which is the first p-type semiconductor layer (51) included in the P-type transistor, is formed thinner than the thickness of the second tellurium oxide layer, which is the second p-type semiconductor layer (52) included in the heterojunction transistor, and the off-current of the P-type transistor can be lowered by forming a passivation layer (55) on the first tellurium oxide layer, which is the first p-type semiconductor layer (51). As a result, in region III of FIG. 6, the drain current of the P-type transistor can be reduced relative to the drain current of the heterojunction transistor, thereby efficiently generating a logic state "0".

[0060]

[0061] Hereinafter, preferred experimental examples are presented to aid in understanding the present invention. However, the following experimental examples are intended only to aid in understanding the present invention, and the present invention is not limited by the following experimental examples.

[0062]

[0063] Heterojunction Transistor Preparation Example 1

[0064] FIG. 8 is a schematic diagram showing a heterojunction transistor according to heterojunction transistor manufacturing example 1.

[0065] Referring to Fig. 8, a 15 nm HfO2 layer was deposited on a p-type Si wafer serving as the gate electrode using PEALD (Plasma Enhanced Atomic Layer Deposition) under conditions of oxygen partial pressure 10 vol%, argon partial pressure 90 vol%, and plasma power 100 W, and a 5 nm Al2O3 layer was deposited on the HfO2 layer using PEALD under conditions of oxygen partial pressure 5 vol%, argon partial pressure 95 vol%, and plasma power 50 W to form an HfO2 / Al2O3 double-layer gate insulating film.

[0066] A shadow mask was placed on the gate insulating film, and an IGTO semiconductor layer (In:Ga:Sn = 75:23:2 at%) having a width of approximately 40 μm, a length of approximately 180 μm, and a thickness of approximately 8 nm was formed by sputtering using an IGTO target (In:Ga:Sn = 75:23:2 at%) under conditions of an oxygen partial pressure of 5 vol% and an argon partial pressure of 95 vol%, and then heat-treated at 150 °C in an ambient air atmosphere. Subsequently, a shadow mask was placed on the IGTO semiconductor layer, and a TeO layer having a width of approximately 60 μm, a length of approximately 180 μm, and a thickness of approximately 5 nm was formed by sputtering using a Te target under conditions of an oxygen partial pressure of 7 vol% (the remainder being argon). x After depositing the layer, it was heat-treated at 150 ℃ in an ambient air atmosphere. The above IGTO semiconductor layer and TeO x The layers were formed so that they overlap by approximately 80 μm (length) and 40 μm (width).

[0067] The above IGTO semiconductor layer and TeO x A shadow mask is placed on the layer, and electrodes having a thickness of approximately 100 nm are deposited by sputtering using an ITO target under an Ar atmosphere, wherein the first electrode among the electrodes is connected to the IGTO semiconductor layer and the second electrode is the TeO xIt was formed to be connected to the layer. The length between the first electrode and the second electrode, i.e., the channel length, was 180 μm.

[0068]

[0069] Heterojunction Transistor Preparation Example 2

[0070] TeO with a thickness of approximately 6 nm x A heterojunction transistor was manufactured using the same method as in Example 1 of heterojunction transistor manufacturing, except that a layer was deposited.

[0071]

[0072] Heterojunction Transistor Preparation Example 3

[0073] TeO with a thickness of approximately 8 nm x A heterojunction transistor was manufactured using the same method as in Example 1 of heterojunction transistor manufacturing, except that a layer was deposited.

[0074]

[0075] Heterojunction Transistor Preparation Example 4

[0076] A heterojunction transistor was prepared using the same method as in Example 1 of heterojunction transistor preparation, except that 5 nm of Al2O3 was deposited under conditions of oxygen partial pressure 10 vol%, argon partial pressure 90 vol%, and plasma power 50 W.

[0077]

[0078] Heterojunction Transistor Preparation Example 5

[0079] A heterojunction transistor was prepared using the same method as in Example 1 of heterojunction transistor preparation, except that 5 nm of Al2O3 was deposited under conditions of oxygen partial pressure 20 vol%, argon partial pressure 80 vol%, and plasma power 50 W.

[0080]

[0081] Heterojunction Transistor Preparation Example 6

[0082] A p-type Si wafer serving as the gate electrode was thermally oxidized to grow a 100 nm SiO2 layer serving as the gate insulating film on the p-type Si wafer. The gate insulating film was formed. A shadow mask was placed on the gate insulating film, and an IGTO semiconductor layer (In:Ga:Sn = 75:23:2 at%) having a width of approximately 200 μm, a length of approximately 900 μm, and a thickness of approximately 8 nm was formed by sputtering using an IGTO target (In:Ga:Sn = 75:23:2 at%) under conditions of an oxygen partial pressure of 5 vol% and an argon partial pressure of 95 vol%, and then heat-treated at 150 °C in ambient air. Subsequently, a shadow mask was placed on the IGTO semiconductor layer, and TeO with a width of approximately 400 μm, a length of approximately 900 μm, and a thickness of approximately 5 nm was produced by sputtering using a Te target under conditions of an oxygen partial pressure of 7 vol% (the remainder being argon). x After depositing the layer, heat treatment was performed at 150 ℃ in an ambient air atmosphere. The above IGTO semiconductor layer and TeO x The layers were formed to overlap by approximately 500 μm. The IGTO semiconductor layer and TeO x A shadow mask is placed on the layer, and electrodes having a thickness of approximately 100 nm are deposited by sputtering using an ITO target under an Ar atmosphere, wherein the first electrode among the electrodes is connected to the IGTO semiconductor layer and the second electrode is the TeO x It was formed to be connected to a layer. The length between the first electrode and the second electrode, i.e., the channel length, was 900 μm.

[0083]

[0084] Heterojunction Transistor Preparation Example 7

[0085] A heterojunction transistor was manufactured using the same method as in Example 6 of heterojunction transistor manufacturing, except that instead of an IGTO semiconductor layer, an IGZO semiconductor layer (In:Ga:Zn = 1:1:1) having a width of about 200 μm, a length of about 900 μm, and a thickness of about 8 nm was formed by sputtering using an IGZO target (In:Ga:Zn = 1:1:1) under conditions of oxygen partial pressure 5 vol% and argon partial pressure 95 vol%, and then heat-treated in ambient air at 400 ℃.

[0086]

[0087] Heterojunction Transistor Preparation Example 8

[0088] A heterojunction transistor was manufactured using the same method as in Example 6 of heterojunction transistor manufacturing, except that instead of an IGTO semiconductor layer, an IGO semiconductor layer (In:Ga = 8:2) having a width of about 200 μm, a length of about 900 μm, and a thickness of about 8 nm was formed by sputtering using an IGO target (In:Ga = 8:2) under conditions of oxygen partial pressure 5 vol% and argon partial pressure 95 vol%, and then heat-treated at 400 °C in an ambient air atmosphere.

[0089]

[0090] Heterojunction Transistor Preparation Example 9

[0091] A heterojunction transistor was manufactured using the same method as in Example 6 of heterojunction transistor manufacturing, except that instead of an IGTO semiconductor layer, an In2O3 semiconductor layer having a width of about 200 μm, a length of about 900 μm, and a thickness of about 8 nm was formed by sputtering using an In2O3 target under conditions of oxygen partial pressure 5 vol% and argon partial pressure 95 vol%, and then heat-treated in ambient air at 400 ℃.

[0092]

[0093] Heterojunction Transistor Manufacturing Example 10

[0094] TeO on the gate insulating filmx A heterojunction transistor was manufactured using the same method as in Example 1 of heterojunction transistor manufacturing, except that a layer was deposited and heat-treated at 150°C in ambient air, an IGTO semiconductor layer (In:Ga:Sn = 75:23:2) was formed and heat-treated at 150°C in ambient air.

[0095] Table 1 below summarizes the conditions used in the methods according to heterojunction transistor manufacturing examples 1 to 9.

[0096] Gate Insulator N-type Semiconductor Layer P-type Semiconductor Layer N-type-P-type Overlap Length Channel Length Heterojunction Transistor Preparation Example 115nm HfO 25nm Al2O3 (Oxygen Partial Pressure 5 vol%) 40 µm x 180 µm, 8nm Thickness IGTO 60 µm x 180 µm, 5nm Thickness TeO x 80 µm 180 µm Heterojunction Transistor Preparation Example 215nm HfO 25nm Al2O3 (Oxygen Partial Pressure 5 vol%) 40 µm x 180 µm, 8nm Thickness IGTO 60 µm x 180 µm, 6nm Thickness TeO x 80 µm 180 µm Heterojunction Transistor Preparation Example 315nm HfO 25nm Al2O3 (Oxygen Partial Pressure 5 vol%) 40 µm x 180 µm, 8nm Thickness IGTO 60 µm x 180 µm, 8nm Preparation Example of a heterojunction transistor with thickness TeO x 80 μm x 180 μm 415 nm HfO 25 nm Al2O3 (oxygen partial pressure 10 vol%) 40 μm x 180 μm, 8 nm thick IGTO 60 μm x 180 μm, 5 nm thick TeO x 80 μm x 180 μm heterojunction transistor 515 nm HfO 25 nm Al2O3 (oxygen partial pressure 20 vol%) 40 μm x 180 μm, 8 nm thick IGTO 60 μm x 180 μm, 5 nm thick TeO x 80 μm x 180 μm heterojunction transistor 6100 nm SiO2 200 μm x 900 μm, 8 nm thick IGTO 400 μm x 900 μm, 5 nm thick TeO x 500 μm x 900 μm heterojunction transistor Example of preparation of a heterojunction transistor: 7100nm SiO2 200 µm x 900 µm, 8nm thick IGZO 400 µm x 900 µm, 5m thick TeO x 500 µm 900 µm 8100nm SiO2 200 µm x 900 µm, 8nm thick IGO ​​400 µm x 900 µm, 5m thick TeO x 500 µm 900 µm Example of preparation of a heterojunction transistor: 9100nm SiO2 200 µm x 900 µm, 8nm thick In2O3 400 µm x 900 µm, 5m thick TeO x 500 µm 900 µm

[0097] FIG. 9 is a graph showing the IV characteristics of heterojunction transistors according to heterojunction transistor manufacturing examples 1 to 3. At this time, VDS was 1V. Referring to FIG. 9, it can be seen that the heterojunction transistors according to heterojunction transistor fabrication examples 1 to 3 all operate as semi-bipolar transistors exhibiting NDT (negative differential transconductance) characteristics. In addition, TeO, which is a p-type semiconductor layer x It can be seen that the absolute value of NDT increases as the layer thickness decreases. In particular, TeO x When the layer thickness was 5 nm, an NDT of -5 μS appeared, △Von(Vth,p-Vth,n) was 1.2 V, and PVR (Peak to Valley Ratio, I peak / I valley ) is 2x10 3 Excellent electrical characteristics such as... could be secured. Therefore, TeO, a P-type semiconductor layer applied to heterojunction transistors x The thickness of the layer may be less than 6 nm and greater than 4 nm, specifically 5 nm may be preferred.

[0098]

[0099] FIG. 10 is a graph showing the IV characteristics of heterojunction transistors according to heterojunction transistor manufacturing examples 4 to 5.

[0100] Referring to FIG. 10, the n-type semiconductor layer is an IGTO layer and the p-type semiconductor layer is a TeO layer. x When forming Al2O3 in contact with the lower part of the layer, the NDT value is similar even if the oxygen partial pressure changes, but as the oxygen partial pressure decreases, the peak current value (I peak It can be seen that ) increases. Therefore, it can be seen that an oxygen partial pressure of 5 vol% when forming Al2O3 is appropriate.

[0101]

[0102] FIGS. 11a, FIGS. 11b, FIGS. 11c, and FIGS. 11d are graphs showing the IV characteristics of heterojunction transistors according to heterojunction transistor manufacturing examples 6 to 9, respectively.

[0103] Referring to FIGS. 11a, 11b, 11c, and 11d, a heterojunction transistor having an IGTO layer as an n-type semiconductor layer manufactured according to Example 6 has the highest peak current value (I peak It can be seen that it indicates ). Therefore, it can be understood that a heterojunction transistor equipped with an IGTO layer as an n-type semiconductor layer exhibits the best characteristics. In addition, while IGZO, IGO, and In2O3, which are n-type semiconductor layers used in Manufacturing Examples 7 to 9, all require heat treatment at 400 ℃, it can be seen that IGTO can exhibit excellent performance even with heat treatment at 250 ℃ or lower, specifically at 150 ℃.

[0104] Meanwhile, referring to FIG. 9 and FIG. 11a, FIG. 11b, FIG. 11c, and FIG. 11d simultaneously, compared to FIG. 1, a heterojunction transistor prepared with an HfO2 / Al2O3 double-layer gate insulating film, FIG. 6, a heterojunction transistor prepared with a SiO2 gate insulating film, operates at a high gate voltage, indicating that the driving voltage is considerably high. Therefore, it can be seen that using an HfO2 / Al2O3 double-layer gate insulating film is desirable in terms of reducing power consumption.

[0105]

[0106] FIG. 12a is a schematic diagram showing the case where the positions of the source and drain of a heterojunction transistor manufactured according to Example 1 of heterojunction transistor manufacturing are swapped, and FIG. 12b is a graph showing the IV characteristics according to this.

[0107] Referring to Figures 12a and 12b, it can be seen that it operates as an anti-ambipolar transistor even though the positions where the drain voltage and source voltage are applied have been changed compared to Figure 8.

[0108]

[0109] FIG. 13a is a schematic diagram showing a heterojunction transistor manufactured according to Example 10 of the heterojunction transistor manufacturing process, and FIG. 13b is a graph showing the IV characteristics according to the same.

[0110] Referring to Figs. 13a and 13b, TeO when compared to Fig. 8 x It can be seen that it operates as an anti-ambipolar transistor even when the order in which the layer and the IGTO layer are formed is reversed.

[0111]

[0112] P-type transistor manufacturing example 1

[0113] A 15 nm HfO2 layer was deposited on a p-type Si wafer serving as the gate electrode using PEALD under conditions of oxygen partial pressure 10 vol%, argon partial pressure 90 vol%, and plasma power 100 W, and a 5 nm Al2O3 layer was deposited on the HfO2 layer using PEALD under conditions of oxygen partial pressure 5 vol%, argon partial pressure 95 vol%, and plasma power 50 W to form an HfO2 / Al2O3 double-layer gate insulating film.

[0114] A shadow mask is placed on the gate insulating film, and a TeO having a width of approximately 100 μm, a length of approximately 30 μm, and a thickness of approximately 4 nm is produced by sputtering using a Te target under conditions of an oxygen partial pressure of 16 vol% (the remainder being argon). x After depositing the layer, heat treatment was performed at 150°C in ambient air.

[0115] The above TeO x A shadow mask is placed on the layer, and the TeO is formed through sputtering using an ITO target under an Ar atmosphere. x Electrodes having a thickness of approximately 100 nm were deposited, each connected to both ends of the layer. The length between the electrodes, i.e., the channel length, was 180 µm. The exposed TeO between the electrodes xA passivation layer was deposited by depositing 10 nm of Al2O3 on a layer using PEALD under conditions of oxygen partial pressure 10 vol%, argon partial pressure 90 vol%, and plasma power 50 W.

[0116]

[0117] P-type transistor manufacturing example 2

[0118] A P-type transistor was manufactured using the same method as in Example 1 of P-type transistor manufacturing, except that a passivation layer was not deposited.

[0119]

[0120] P-type transistor manufacturing example 3

[0121] TeO with a thickness of approximately 5 nm x A P-type transistor was manufactured using the same method as in Example 1 of P-type transistor manufacturing, except that a layer was deposited.

[0122]

[0123] P-type transistor manufacturing example 4

[0124] TeO with a thickness of approximately 6 nm x A P-type transistor was manufactured using the same method as in Example 1 of P-type transistor manufacturing, except that a layer was deposited.

[0125]

[0126] Figures 14a and 14b are graphs showing the IV characteristics of P-type transistors according to P-type transistor manufacturing examples 1 and 2, respectively.

[0127] Referring to Figs. 14a and 14b, TeO x It can be seen that a lower off-current value is exhibited when a passivation layer is deposited on the layer.

[0128]

[0129] Figure 15 shows graphs representing the IV characteristics of P-type transistors according to P-type transistor manufacturing examples 1, 3, and 4.

[0130] Referring to Fig. 15, TeO x It can be seen that the lowest off-current value is exhibited when the layer has a thickness of about 4 nm.

[0131]

[0132] Example of manufacturing a Samjin inverter element

[0133] FIG. 16 is a schematic diagram showing a samjin inverter element according to an example of manufacturing a samjin inverter element.

[0134] Referring to Fig. 16, a 15 nm HfO2 layer was deposited on a p-type Si wafer serving as the gate electrode using PEALD under conditions of oxygen partial pressure 10 vol%, argon partial pressure 90 vol%, and plasma power 100 W, and a 5 nm Al2O3 layer was deposited on the HfO2 layer using PEALD under conditions of oxygen partial pressure 5 vol%, argon partial pressure 95 vol%, and plasma power 50 W to form an HfO2 / Al2O3 double-layer gate insulating film.

[0135] A shadow mask exposing a P-type transistor region is placed on the gate insulating film, and a first TeO having a width of approximately 100 μm, a length of approximately 30 μm, and a thickness of approximately 4 nm is produced by sputtering using a Te target under conditions of an oxygen partial pressure of 16 vol% (the remainder being argon). x After depositing the layer, heat treatment was performed at 150°C in ambient air.

[0136] A shadow mask exposing a portion of the heterojunction transistor region was placed on the gate insulating film, and an IGTO semiconductor layer (In:Ga:Sn = 75:23:2 at%) having a width of approximately 40 μm, a length of approximately 180 μm, and a thickness of approximately 8 nm was formed by sputtering using an IGTO target (In:Ga:Sn = 75:23:2 at%) under conditions of an oxygen partial pressure of 5 vol% and an argon partial pressure of 95 vol%, followed by heat treatment in ambient air at 150 °C. Subsequently, a shadow mask exposing a portion of the heterojunction transistor region was placed on the IGTO semiconductor layer, and a second TeO having a width of approximately 60 μm, a length of approximately 180 μm, and a thickness of approximately 5 nm was formed by sputtering using a Te target under conditions of an oxygen partial pressure of 7 vol% (the remainder being argon). x After depositing the layer, heat treatment was performed at 150 ℃ in ambient air. The above IGTO semiconductor layer and the second TeO x The layers were formed to overlap by approximately 80 μm.

[0137] The above IGTO semiconductor layer and TeO x First TeO on layers x One end of the layer, the first TeO x The other end of the layer and the second TeO adjacent thereto x A shadow mask is placed to expose one end of the layer and the end of the IGTO semiconductor layer, and first to third electrodes having a thickness of about 100 nm are deposited by sputtering using an ITO target under an Ar atmosphere, wherein the first electrode among the electrodes is a first TeO x Connected to one end of the layer, and the second electrode is the first TeO x The other end of the layer and the second TeO adjacent thereto xThe first electrode was connected to one end of the layer, and the third electrode was formed to be connected to the end of the IGTO semiconductor layer. The length between the first electrode and the second electrode, i.e., the channel length of the P-type transistor, was 180 μm, and the length between the second electrode and the third electrode, i.e., the channel length of the heterojunction transistor, was 180 μm.

[0138] The first TeO exposed between the first electrode and the second electrode x A passivation layer was deposited by depositing 10 nm of Al2O3 on a layer using PEALD under conditions of oxygen partial pressure 10 vol%, argon partial pressure 90 vol%, and plasma power 50 W.

[0139]

[0140] Figure 17 is a graph showing the IV characteristics of a heterojunction transistor and a P-type transistor included in a Samjin inverter according to the Samjin inverter manufacturing example.

[0141] Referring to FIG. 17, the heterojunction transistor (AAT) V GS Current flows in the IGTO when V is approximately 0 V (Vth, n) or higher, and V GS The second TeO at approximately 1.2 V (Vth, p) or less x As current flowed in the layer, △Von(Vth,p-Vth,n) was 1.2 V. In addition, the heterojunction transistor (AAT) V GS Peak value (I) when V is approximately 0.3 V peak reached ), and V GS As increased further, the drain current decreased (negative differential transconductance). Meanwhile, the P-type transistor (PT) V GS The first TeO at approximately 1.2 V or less x Electric current flowed through the floor.

[0142] Heterojunction transistors (AAT) and P-type transistors (PT) are V GS In the region where α is 0.3 to 1 V (Region II), the drain current value is similar, so gm (Transconductance) Matching appears.

[0143]

[0144] FIG. 18 shows the V of the Samjin inverter according to the Samjin inverter manufacturing example. out -V in This is a graph showing the characteristics.

[0145] Referring simultaneously to FIGS. 17 and FIGS. 18, the heterojunction transistor and the P-type transistor g m V before matching GS In the range of, that is, in region I, the drain current of the P-type transistor is higher than that of the heterojunction transistor, so the conducting path is V DD and output terminal (V out Formed between ) V DD A high voltage close to the value is output at the output terminal (V out Output was generated from ), creating a logic state "2". The heterojunction transistor and the P-type transistor g m Matching V GS In the range of, that is, in region II, the drain current of the P-type transistor and the drain current of the heterojunction transistor have similar values, so the conductive path is V DD It is formed between and ground, and V DD The output terminal (V) is divided between two transistors out An intermediate voltage value was output from ), generating a logic state "1". The heterojunction transistor and the P-type transistor g m V after the matching ends GS In the range of, that is, in region III, the drain current of the heterojunction transistor is higher than the drain current of the P-type transistor, so the conduction path is to the output terminal (V out A low voltage close to the ground voltage is formed between ) and ground, and is output at the output terminal (V out Output from ) generated a logical state "0". Additionally, maximum values ​​of voltage gain appear at approximately 3 V / V and approximately 1.7 V / V.

[0146] In this way, the ternary inverter according to the ternary inverter manufacturing example can output three logic values, so it is possible to design more complex logic circuits with fewer transistors compared to binary inverters.

[0147]

[0148] Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and changes are possible by those skilled in the art within the technical spirit and scope of the present invention.

Claims

1. Gate electrode; A first tellurium oxide layer superimposed with the gate electrode in a P-type transistor region; An n-type oxide semiconductor layer and a second tellurium oxide layer that overlap with the gate electrode and form a PN junction in a heterojunction transistor region; A high dielectric constant gate insulating film disposed between the gate electrode and the first tellurium oxide layer, between the gate electrode and the n-type oxide semiconductor layer, and between the gate electrode and the second tellurium oxide layer; and A triangular inverter comprising a first electrode connected to the first tellurium oxide layer, a second electrode connected to both the first tellurium oxide layer and the second tellurium oxide layer, and a third electrode connected to the n-type oxide semiconductor layer.

2. In Paragraph 1, A triangular inverter further comprising a passivation layer disposed on a first tellurium oxide layer exposed between the first electrode and the second electrode.

3. In Paragraph 2, The above passivation layer is a metal oxide insulating film, a Samjin inverter.

4. In Paragraph 3, The above passivation layer is a trivalent inverter comprising an Al2O3, HfO2, or ZrO2 layer.

5. In Paragraph 1, The thickness of the first tellurium oxide layer is thinner than the thickness of the second tellurium oxide layer, in a triangular inverter.

6. In Paragraph 5, A triangular inverter in which the thickness of the first tellurium oxide layer is 2 nm or more and less than 5 nm, and the thickness of the second tellurium oxide layer is greater than 4 nm and less than or equal to 10 nm.

7. In Paragraph 1, The gate insulating film is a double layer of a hafnium oxide film located adjacent to the gate electrode and an aluminum oxide film located adjacent to the n-type oxide semiconductor layer and the tellurium oxide layers, in a triangular inverter.

8. In Paragraph 1, The above n-type oxide semiconductor layer is an IGTO (In-Ga-Sn-O) layer, a triangular inverter.

9. In Paragraph 1, A triangular inverter in which the n-type oxide semiconductor layer forming the PN junction and the second tellurium oxide layer are arranged such that the n-type oxide semiconductor layer overlaps a portion of the upper part of the second tellurium oxide layer.

10. In Paragraph 1, The above first to third electrodes are ITO electrodes, in a triangular inverter.

11. A P-type transistor comprising a first gate electrode, a first tellurium oxide layer, a high dielectric constant gate insulating film disposed between the first gate electrode and the first tellurium oxide layer, and a first electrode and a second electrode respectively connected to both ends of the first tellurium oxide layer; and A heterojunction transistor comprising: a second gate electrode to which an input voltage (Vin) identical to that of a first gate electrode is applied; an n-type oxide semiconductor layer and a second tellurium oxide layer forming a PN junction; a high dielectric constant gate insulating film disposed between the second gate electrode and the n-type oxide semiconductor layer and between the gate electrode and the second tellurium oxide layer; the second electrode also connected to the second tellurium oxide layer; and a third electrode connected to the n-type oxide semiconductor layer. Power supply voltage (V) to the first electrode above DD A ternary inverter in which ) is applied, a reference voltage is applied to or grounded to the third electrode, and the second electrode is an output terminal (Vout).

12. In Paragraph 11, A triangular inverter further comprising a passivation layer disposed on a first tellurium oxide layer exposed between the first electrode and the second electrode.

13. In Paragraph 12, The above passivation layer is a metal oxide insulating film, a Samjin inverter.

14. In Paragraph 13, The above passivation layer is a trivalent inverter comprising an Al2O3, HfO2, or ZrO2 layer.

15. In Paragraph 11, The thickness of the first tellurium oxide layer is thinner than the thickness of the second tellurium oxide layer, in a triangular inverter.

16. In Paragraph 15, A triangular inverter in which the thickness of the first tellurium oxide layer is 2 nm or more and less than 5 nm, and the thickness of the second tellurium oxide layer is greater than 4 nm and less than or equal to 10 nm.

17. In Paragraph 11, The gate insulating film is a double layer of a hafnium oxide film located adjacent to the gate electrode and an aluminum oxide film located adjacent to the n-type oxide semiconductor layer and the tellurium oxide layers, in a triangular inverter.

18. In Paragraph 11, The above n-type oxide semiconductor layer is an IGTO (In-Ga-Sn-O) layer, a triangular inverter.

19. In Paragraph 11, The above first to third electrodes are ITO electrodes, in a triangular inverter.

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