Display device and electronic device comprising same

Abstract

This display device comprises: a pixel including a first sub-pixel including a first pixel circuit, a second sub-pixel including a second pixel circuit, and a third sub-pixel including a third pixel circuit; a first emission control line connected to the first pixel circuit; a second emission control line connected to the second pixel circuit and the third pixel circuit; and first power lines connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit, and arranged in a first direction and extending in a second direction in a display area, wherein the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged in the first direction, the first pixel circuit overlaps one of the first power lines, and the second pixel circuit and the third pixel circuit overlap another one of the first power lines and have symmetrical shapes with each other.

Description

Display device and electronic device including the same

[0001] Embodiments of the present invention relate to a display device and an electronic device including the same.

[0002] As the information society develops, the demand for display devices to display images is increasing in various forms. For example, display devices are integrated into various electronic devices and used as the display screens for these devices. In response to this, various types of display devices, including light-emitting displays, are being developed.

[0003] The problem that the present invention aims to solve is to provide a display device capable of efficiently arranging pixel circuits and wiring in a display area, and an electronic device including the same.

[0004] The problems of the present invention are not limited to the technical problems mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0005] A display device according to one embodiment comprises: a pixel including a first subpixel including a first pixel circuit, a second subpixel including a second pixel circuit, and a third subpixel including a third pixel circuit, which is disposed in a display area where an image is displayed; a first light-emitting control line electrically connected to the first pixel circuit; a second light-emitting control line electrically connected to the second pixel circuit and the third pixel circuit; and first power lines electrically connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit, arranged in a first direction in the display area, each extending in a second direction, wherein the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged in the first direction in the display area, and the first pixel circuit overlaps with one of the first power lines, and the second pixel circuit and the third pixel circuit overlap with another of the first power lines and may have a symmetrical shape.

[0006] In one embodiment, the second pixel circuit and the third pixel circuit are commonly connected to the other first power line and may have a shape symmetrical to each other with respect to the other first power line.

[0007] In one embodiment, the display area may further include data lines arranged in the first direction and including a first data line electrically connected to the first pixel circuit, a second data line electrically connected to the second pixel circuit, and a third data line electrically connected to the third pixel circuit.

[0008] In one embodiment, each of the first pixel circuit, the second pixel circuit, and the third pixel circuit may include: a first transistor configured to control a driving current in response to a data voltage transmitted from the first data line, the second data line, or the third data line; and a second transistor electrically connected between the first data line, the second data line, or the third data line and the first transistor.

[0009] In one embodiment, the first transistor may include an active layer, a gate electrode overlapping a portion of the active layer, and a source electrode and a drain electrode electrically connected to different portions of the active layer.

[0010] In one embodiment, the first transistors of the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged sequentially along the first direction, and the drain electrode of the first transistor included in the first pixel circuit and the source electrode of the first transistor included in the second pixel circuit are adjacent to each other in the first direction, and the drain electrode of the first transistor included in the second pixel circuit and the drain electrode of the first transistor included in the third pixel circuit may be adjacent to each other in the first direction.

[0011] In one embodiment, the size of the first transistor included in the first pixel circuit may be different from the size of the first transistor included in each of the second pixel circuit and the third pixel circuit.

[0012] In one embodiment, each of the first pixel circuit, the second pixel circuit, and the third pixel circuit further includes a third transistor and a fourth transistor comprising an oxide semiconductor, which are commonly connected to the gate electrode of the first transistor through a first connecting electrode, and the third transistor and the fourth transistor of the second pixel circuit may be arranged adjacent to the third transistor and the fourth transistor of the third pixel circuit in the first direction.

[0013] In one embodiment, the first power line covers the first transistor, the third transistor, and the fourth transistor included in the first pixel circuit, and the other first power line can cover the first transistors, the third transistors, and the fourth transistors included in the second pixel circuit and the third pixel circuit.

[0014] In one embodiment, the first light emission control line and the second light emission control line are adjacent to each other in the second direction, and each may extend in the first direction.

[0015] In one embodiment, each of the first pixel circuit, the second pixel circuit, and the third pixel circuit may further include a fifth transistor and a sixth transistor, each comprising an active layer intersecting the first light emission control line and the second light emission control line, and a gate electrode overlapping a portion of each of the active layers.

[0016] In one embodiment, the active layer of the fifth transistor extends from one end of the active layer of the first transistor and has a U- or Y-shape around the first light-emitting control line and the second light-emitting control line and intersects the first light-emitting control line and the second light-emitting control line, and the active layer of the sixth transistor extends from the other end of the active layer of the first transistor and can be electrically connected to a light-emitting element disposed on top of the first pixel circuit, the second pixel circuit or the third pixel circuit.

[0017] In one embodiment, one end of the active layer of the fifth transistor may be electrically connected to the one first power line or the other first power line.

[0018] In one embodiment, the second subpixel and the third subpixel further include a second connecting electrode extending in the first direction in an area where the second pixel circuit and the third pixel circuit are arranged, overlapping with the other first power line, and the active layers of the fifth transistors included in the second pixel circuit and the third pixel circuit are commonly connected to the second connecting electrode and can be electrically connected to the other first power line through the second connecting electrode.

[0019] In one embodiment, the gate electrodes of the fifth transistor and the sixth transistor included in the first pixel circuit are formed as a single conductive pattern that overlaps with the first light emission control line, and the single conductive pattern can be electrically connected to the first light emission control line through a contact hole disposed between the fifth transistor and the sixth transistor.

[0020] In one embodiment, the gate electrodes of the fifth and sixth transistors included in the second pixel circuit and the third pixel circuit are formed as a single conductive pattern that overlaps with the second light emission control line, and the single conductive pattern can be electrically connected to the second light emission control line through a contact hole disposed between the second pixel circuit and the third pixel circuit.

[0021] In one embodiment, the first data line is positioned between the first power line and the data line electrically connected to the third subpixel of another pixel adjacent to the first subpixel in the first direction, the second data line is positioned between the first power line and the other first power line, and the third data line may be positioned between the other first power line and the data line electrically connected to the first subpixel of another pixel adjacent to the third subpixel in the first direction.

[0022] In one embodiment, the first subpixel further includes a first light-emitting element electrically connected to the first pixel circuit through a first anode contact hole that overlaps with the first pixel circuit, the second subpixel further includes a second light-emitting element electrically connected to the second pixel circuit through a second anode contact hole that overlaps with the second pixel circuit, the third subpixel further includes a third light-emitting element electrically connected to the third pixel circuit through a third anode contact hole that overlaps with the third pixel circuit, and the other first power line may pass through the area between the second anode contact hole and the third anode contact hole.

[0023] In one embodiment, the display device further includes a second power line disposed between the first pixel circuit and the second pixel circuit, or between another pixel adjacent to the pixel in the first direction and the pixel, and the second power line may be electrically connected to the first light-emitting element, the second light-emitting element, and the third light-emitting element through a cathode contact hole.

[0024] An electronic device according to one embodiment may include a display device including a display area where an image is displayed. The display device comprises: a pixel including a first subpixel including a first pixel circuit, a second subpixel including a second pixel circuit, and a third subpixel including a third pixel circuit, which is disposed in the display area where the image is displayed; a first light-emitting control line electrically connected to the first pixel circuit; a second light-emitting control line electrically connected to the second pixel circuit and the third pixel circuit; and first power lines electrically connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit, which are arranged in a first direction in the display area and each extend in a second direction, wherein the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged in the first direction in the display area, and the first pixel circuit overlaps with one of the first power lines, and the second pixel circuit and the third pixel circuit overlap with another of the first power lines and may have a symmetrical shape.

[0025] Specific details of other embodiments are included in the detailed description and drawings.

[0026] According to the display device and the electronic device including the same according to the embodiments, the design structure of the display area can be improved. For example, by designing the second subpixel and the third subpixel among the first subpixel, second subpixel, and third subpixel forming a single pixel to be symmetrically flipped, pixel circuits and wiring can be efficiently arranged in the display area. Accordingly, the design structure of the display area can be optimized, and additional design space can be secured.

[0027] In some embodiments, a second power line may be placed in the space secured by efficiently arranging the pixel circuits and wiring. Accordingly, a voltage drop of the driving voltage applied to the common electrode through the second power line can be prevented, and the image quality and power consumption of the display device can be improved.

[0028] In some embodiments, the first subpixel and the second and third subpixels may be connected to different light emission control lines. Accordingly, the light emission period of the first subpixel and the light emission periods of the second and third subpixels can be controlled independently or individually. For example, the driving current of the first subpixel and the driving current of the second and third subpixels can be appropriately adjusted or differentiated according to the optimal consumption efficiency of the light-emitting elements included in the subpixels, and the light emission period of the first subpixel and the light emission period of the second and third subpixels can be adjusted according to each driving current to maintain the brightness of the subpixels uniformly. Accordingly, the lifespan, image quality, and power consumption of the display device can be improved.

[0029] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification.

[0030] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0031] FIG. 2 is a plan view showing a display panel according to one embodiment.

[0032] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0033] FIG. 4 is an equivalent circuit diagram showing a subpixel according to one embodiment.

[0034] FIG. 5 is a waveform diagram showing driving signals of a subpixel according to one embodiment.

[0035] FIG. 6 is a plan view showing pixel circuits, signal lines, and power lines disposed within the backplane layer of a display panel according to one embodiment.

[0036] FIG. 7 is a plan view showing pixel circuits, signal lines, and power lines disposed within the backplane layer of a display panel according to one embodiment.

[0037] FIG. 8 is a plan view showing pixel circuits, signal lines, and power lines disposed within the backplane layer of a display panel according to one embodiment.

[0038] FIG. 9 is a layout diagram showing a backplane layer of a display panel according to one embodiment.

[0039] FIG. 10 is a layout diagram showing the first pixel circuit of FIG. 9 in detail.

[0040] Figure 11 is a layout diagram showing the second pixel circuit of Figure 9 in detail.

[0041] FIG. 12 is a layout diagram showing the third pixel circuit of FIG. 9 in detail.

[0042] FIG. 13 is a layout diagram showing patterns included in the first semiconductor layer, the first gate conductive layer, the second semiconductor layer, and the third gate conductive layer of a backplane layer according to one embodiment.

[0043] FIG. 14 is a layout diagram showing patterns included in a first gate conductive layer and a second gate conductive layer according to one embodiment.

[0044] FIG. 15 is a layout diagram showing patterns included in the first source-drain conductive layer and the second source-drain conductive layer of a backplane layer according to one embodiment.

[0045] FIG. 16 is a layout diagram showing in detail a part of a first pixel circuit, a second pixel circuit, and a third pixel circuit according to one embodiment.

[0046] FIG. 17 is a layout diagram showing in detail a part of a first pixel circuit, a second pixel circuit, and a third pixel circuit according to one embodiment.

[0047] FIG. 18 is a layout diagram showing a light-emitting element layer of a display panel according to one embodiment.

[0048] FIG. 19 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the X1-X1' line of FIG. 9 and FIG. 18.

[0049] FIG. 20 is a cross-sectional view showing the A2 region of FIG. 19 in detail.

[0050] FIG. 21 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the X2-X2' line and the X3-X3' line of FIG. 9 and FIG. 18.

[0051] FIG. 22 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the X1-X1' line of FIG. 9 and FIG. 18.

[0052] FIG. 23 is an example drawing showing a smart watch including a display device according to one embodiment.

[0053] FIGS. 24 and FIGS. 25 are exemplary drawings showing a head-mounted display device including a display device according to one embodiment.

[0054] FIG. 26 is an exemplary drawing showing a head-mounted display device including a display device according to one embodiment.

[0055] FIG. 27 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment.

[0056] FIG. 28 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0057] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0058] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0059] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0060] Specific embodiments will be described below with reference to the attached drawings.

[0061] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0062] Referring to FIG. 1, the display device (10) is a device for displaying video or still images and can be used as a display screen in various electronic devices such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet personal computers, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs). Additionally, the display device (10) can be included in other electronic devices such as virtual reality (VR) devices or augmented reality (AR) devices and used to display images in said electronic devices. In one embodiment, the electronic device including the display device (10) may further include a display device housing in which the display device (10) is housed, and / or a case or cover for protecting said display device (10).

[0063] In one embodiment, the display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Hereinafter, the display device (10) has been described with a focus on being a micro light-emitting display device, but the present invention is not limited thereto. Meanwhile, for convenience of explanation, a micro light-emitting diode has been described as a light-emitting element below.

[0064] The display device (10) may include a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply unit (500) (for example, a power supply circuit).

[0065] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) that intersects the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed rounded or at a right angle. The planar shape of the display panel (100) is not limited to a rectangular shape and may be formed in other polygonal shapes, circular shapes, or elliptical shapes. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include curved portions formed at the left and right ends that have a constant curvature or a changing curvature. In one embodiment, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0066] The display panel (100) may include a main area (MA) and a sub-area (SBA).

[0067] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) that is a surrounding area of ​​the display area (DA). The display area (DA) may include pixels that display an image. Each pixel may include a plurality of subpixels. For example, each pixel may include a first subpixel emitting light of a first color (or first light), a second subpixel emitting light of a second color (or second light), and a third subpixel emitting light of a third color (or third light), but the embodiments of the present specification are not limited thereto.

[0068] A sub-region (SBA) may protrude from one side of a main region (MA) in a second direction (DR2) (for example, the vertical direction of the display panel (100)). Although FIG. 1 illustrates a sub-region (SBA) unfolded, the sub-region (SBA) may be bent, in which case it may be placed on the lower surface of the display panel (100). When the sub-region (SBA) is bent, it may overlap with the main region (MA) in a third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be placed in the sub-region (SBA).

[0069] The display driving circuit (250) can generate signals and voltages to drive the display panel (100). The display driving circuit (250) may be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (250) may be attached to the circuit board (300) using a COF (chip on film) method.

[0070] A circuit board (300) can be attached to one end of a sub-region (SBA) of a display panel (100). As a result, the circuit board (300) can be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) can receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0071] The power supply unit (500) can generate panel driving voltages according to the power voltage supplied from the outside. The power supply unit (500) can be formed as an integrated circuit (IC) and attached to the circuit board (300) in a COF manner.

[0072] FIG. 2 is a plan view showing a display panel according to one embodiment. FIG. 2 illustrates a sub-region (SBA) that is unfolded without being bent.

[0073] Referring to FIGS. 1 and FIGS. 2, the display panel (100) may include a main area (MA) and a sub-area (SBA).

[0074] The main area (MA) may include a display area (DA) that displays images and a non-display area (NDA) that is the surrounding area of ​​the display area (DA). The display area (DA) may occupy most of the main area (MA). The display area (DA) may be positioned in the center of the main area (MA).

[0075] A display area (DA) includes pixels (PX) for displaying an image, and each pixel (PX) may include a plurality of subpixels (SPX). A pixel (PX) may be defined as a group of subpixels of the smallest unit capable of expressing a white gradation.

[0076] The non-display area (NDA) may be positioned adjacent to the display area (DA). The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0077] The first scan driver (SDC1) and the second scan driver (SDC2) may be placed in the non-display area (NDA). The first scan driver (SDC1) may be placed on one side (e.g., the left side) of the display panel (100), and the second scan driver (SDC2) may be placed on the other side (e.g., the right side) of the display panel, but is not limited thereto. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may be electrically connected to the display driver circuit (250) through scan fan-out lines. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may receive a scan control signal from the display driver circuit (250), generate scan signals according to the scan control signal, and output them to the scan lines.

[0078] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). The length of the second direction (DR2) of the sub-region (SBA) may be shorter than the length of the second direction (DR2) of the main region (MA). The length of the first direction (DR1) of the sub-region (SBA) may be shorter than the length of the first direction (DR1) of the main region (MA) or substantially equal to the length of the first direction (DR1) of the main region (MA). The sub-region (SBA) may be bent and positioned below the main region (MA). In this case, the sub-region (SBA) may overlap with the main region (MA) in a third direction (DR3).

[0079] The sub-region (SBA) may include a connection region (CA), a pad region (PA), and a bending region (BA).

[0080] The connection area (CA) is an area protruding in a second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) is in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0081] The pad area (PA) is an area where pads (PDs) and a display driving circuit (250) are placed. The display driving circuit (250) can be attached to the driving pads of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PDs) of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area (PA) may be in contact with the bending area (BA).

[0082] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) may be positioned below the connecting area (CA) and below the main area (MA). The bending area (BA) may be positioned between the connecting area (CA) and the pad area (PA). One side of the bending area (BA) is in contact with the connecting area (CA), and the other side of the bending area (BA) may be in contact with the pad area (PA).

[0083] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0084] Referring to FIG. 3, the display area (DA) may include pixels (PX), scan lines (SL), light emission control lines (EL), and data lines (DL).

[0085] Pixels (PX) can be arranged in a first direction (DR1) and a second direction (DR2). For example, pixels (PX) can be arranged in a matrix form in the first direction (DR1) and the second direction (DR2). Scan lines (SL) and light emission control lines (EL) extend in the first direction (DR1) and can be arranged or positioned in the second direction (DR2). Data lines (DL) extend in the second direction (DR2) and can be arranged or positioned in the first direction (DR1). Scan lines (SL) may include write scan lines (GWL), initialization scan lines (GIL), control scan lines (GCL), and bias scan lines (GBL). The configuration or number of scan lines (SL) may vary depending on the structure or driving method of the pixels (PX).

[0086] Each of the pixels (PX) may include a plurality of subpixels (SPX). For example, each of the pixels (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). The first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may each emit light of a first color, light of a second color, and light of a third color. The light of the first color, the light of the second color, and the light of the third color may each be red light (for example, light in the red wavelength band with a main peak wavelength of approximately 600 nm to 750 nm), green light (for example, light in the green wavelength band with a main peak wavelength of approximately 480 nm to 560 nm), and blue light (for example, light in the blue wavelength band with a main peak wavelength of approximately 370 nm to 460 nm), but are not limited thereto. In one embodiment, the first subpixel (SPX1), second subpixel (SPX2), and third subpixel (SPX3) of each of the pixels (PX) may be arranged in a first direction (DR1). The number, type, arrangement structure, and / or emission wavelength of the subpixels (SPX) included in each of the pixels (PX) may be varied according to the embodiments.

[0087] Each of the plurality of subpixels (SPX) may be connected to any one of the write scan lines (GWL), any one of the initialization scan lines (GIL), any one of the control scan lines (GCL), any one of the bias scan lines (GBL), any one of the light emission control lines (EL), and any one of the data lines (DL). In describing the embodiments, the term “connection” may include the meaning of “physical connection” and / or “electrical connection”.

[0088] Each of the plurality of subpixels (SPX) receives a data voltage of a data line (DL) according to a write scan signal of a write scan line (GWL), and can emit light from a light-emitting element according to said data voltage. The plurality of subpixels (SPX) included in each pixel (PX) can be connected to different data lines (DL). For example, the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) can be connected to the first data line (DLr), the second data line (DLg), and the third data line (DLb), respectively. Accordingly, the luminous brightness of each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) can be controlled individually.

[0089] In one embodiment, each pixel (PX) is connected to two or more light emission control lines (EL), and the light emission period (or on-duty ratio) of at least two subpixels (SPX) among a plurality of subpixels (SPX) included in each pixel (PX) can be controlled independently and / or individually by different light emission control signals supplied to different light emission control lines (EL). For example, in each horizontal line (e.g., each pixel row) of a display area (DA), a first light emission control line (EL1) and a second light emission control line (EL2) connected to different subpixels (SPX) among the subpixels (SPX) included in the pixels (PX) placed on the corresponding horizontal line may be disposed. For example, a first light-emitting control line (EL1) may be connected to first subpixels (SPX1) of pixels (PX) arranged on the horizontal line, and a second light-emitting control line (EL2) may be connected to second subpixels (SPX2) and third subpixels (SPX3) included in pixels (PX) of the horizontal line.

[0090] The first subpixel (SPX1) can emit light during a first light emission period in response to a first light emission control signal supplied through the first light emission control line (EL1). The first light emission period may be a period during which a driving current can flow through the first subpixel (SPX1) by the first light emission control signal. The second subpixel (SPX2) and the third subpixel (SPX3) can emit light during a second light emission period in response to a second light emission control signal supplied through the second light emission control line (EL2). The second light emission period may be a period during which a driving current can flow through the second subpixel (SPX2) and the third subpixel (SPX3) by the second light emission control signal. The first light emission period and the second light emission period may be controlled independently or individually, and may or may not overlap in time.

[0091] In one embodiment, the duration of the first light emission period and the duration of the second light emission period may be different. For example, the duration of the first light emission period may correspond to an on-duty ratio adjusted so that the first subpixel (SPX1) emits light at a target brightness, in accordance with a driving current optimized for the light emission efficiency of the first subpixel (SPX1) (for example, a driving current that falls within the range in which the light-emitting element of the first subpixel (SPX1) exhibits optimal consumption efficiency). The duration of the second light emission period may correspond to an on-duty ratio adjusted so that the second subpixel (SPX2) and the third subpixel (SPX3) emit light at a target brightness, in accordance with a driving current optimized for the light emission efficiency of the second subpixel (SPX2) and the third subpixel (SPX3) (for example, a driving current that falls within the range in which the light-emitting elements of the second subpixel (SPX2) and the third subpixel (SPX3) exhibit optimal consumption efficiency). In this case, the light emission control signal output unit (615) included in the first scan drive unit (SDC1) and the second scan drive unit (SDC2) can output light emission control signals having different pulse widths to the first light emission control line (EL1) and the second light emission control line (EL2).

[0092] A first scan drive unit (SDC1), a second scan drive unit (SDC2), and a display drive circuit (250) may be disposed in the non-display area (NDA).

[0093] Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) may include a write scan signal output unit (611), an initialization scan signal output unit (612), a control scan signal output unit (613), a bias scan signal output unit (614), and a light emission control signal output unit (615). Each of the write scan signal output unit (611), the initialization scan signal output unit (612), the control scan signal output unit (613), the bias scan signal output unit (614), and the light emission control signal output unit (615) may receive a scan timing control signal (SCS) from the timing control unit (251).

[0094] The write scan signal output unit (611) can generate write scan signals according to the scan timing control signal (SCS) and output them sequentially to the write scan lines (GWL).

[0095] The initialization scan signal output unit (612) can generate initialization scan signals according to the scan timing control signal (SCS) and output them sequentially to the initialization scan lines (GIL).

[0096] The control scan signal output unit (613) can generate control scan signals according to the scan timing control signal (SCS) and output them sequentially to the control scan lines (GCL).

[0097] The bias scan signal output unit (614) can generate bias scan signals according to the scan timing control signal (SCS) and output them sequentially to the bias scan lines (GBL).

[0098] The light emission control signal output unit (615) can generate light emission control signals according to the scan timing control signal (SCS) and output them sequentially to the light emission control lines (EL). When the subpixels (SPX) of each horizontal line are divided and connected to a plurality of light emission control lines (EL) (for example, a first light emission control line (EL1) and a second light emission control line (EL2) of each horizontal line), the light emission control signal output unit (615) can output each light emission control signal to the plurality of light emission control lines (EL) for each horizontal period.

[0099] The display driving circuit (250) may include a timing control unit (251) (for example, a timing control circuit) and a data driving unit (252) (for example, a data driving circuit).

[0100] The data driver (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control unit (251). The data driver (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs them to the data lines (DL). In this case, subpixels (SPX) are selected by the write scan signals of the first scan driver (SDC1) and the second scan driver (SDC2), and data voltages can be supplied to the selected subpixels (SPX).

[0101] The timing control unit (251) can receive digital video data (DATA) and timing signals from the outside. The timing control unit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) to control the display panel (100) according to the timing signals. The timing control unit (251) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control unit (251) can output the digital video data (DATA) and the data timing control signal (DCS) to the data driving unit (252).

[0102] The power supply unit (500) can generate panel driving voltages according to the power voltage supplied from the outside. For example, the power supply unit (500) can generate a first driving voltage (VDD), a second driving voltage (VSS), a third driving voltage (VINT), a fourth driving voltage (VAINT), and a fifth driving voltage (VOBS) and supply them to the display panel (100). The first driving voltage (VDD), the second driving voltage (VSS), the third driving voltage (VINT), the fourth driving voltage (VAINT), and the fifth driving voltage (VOBS) can be supplied to subpixels (SPX) and used to drive the subpixels (SPX). Depending on the structure or operation method of the subpixels (SPX), the number and / or type of panel driving voltages output from the power supply unit (500) may be changed.

[0103] FIG. 4 is an equivalent circuit diagram showing a subpixel according to one embodiment. For example, FIG. 4 may be an equivalent circuit diagram showing one of the subpixels (SPX) of FIG. 2 and FIG. 3. In one embodiment, the circuit configuration of a plurality of subpixels (SPX) forming each pixel (PX) may be substantially identical to one another. For example, the equivalent circuit diagrams of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) of FIG. 3 may be identical to one another.

[0104] FIG. 5 is a waveform diagram showing driving signals of a subpixel according to one embodiment. For example, FIG. 5 shows a write scan signal (GW), a control scan signal (GC), an initialization scan signal (GI), a bias scan signal (GB), and a light emission control signal (EM) supplied to the scan lines (SL) and light emission control line (EL) of FIG. 4.

[0105] Referring to FIGS. 4 and FIGS. 5 in addition to FIGS. 1 to 3, each of the subpixels (SPX) may include a pixel circuit (PXC) and a light-emitting element (LE) electrically connected to the pixel circuit (PXC).

[0106] A subpixel (SPX) can be connected to at least one scan driver through scan lines (SL) and a light emission control line (EL). For example, the subpixel (SPX) can be connected to a first scan driver (SDC1) and a second scan driver (SDC2) through a write scan line (GWL), an initial scan line (GIL), a control scan line (GCL), a bias scan line (GBL), and a light emission control line (EL). The first scan driver (SDC1) and the second scan driver (SDC2) can output a write scan signal (GW), an initial scan signal (GI), a control scan signal (GC), a bias scan signal (GB), and a light emission control signal (EM), respectively, through the write scan line (GWL), the initial scan line (GIL), the control scan line (GCL), the bias scan line (GBL), and the light emission control line (EL).

[0107] When the subpixel (SPX) is the first subpixel (SPX1), the subpixel (SPX) is connected to the first light emission control line (EL1) placed on the corresponding horizontal line and can receive a light emission control signal (EM) (also referred to as the "first light emission control signal") from the first light emission control line (EL1). When the subpixel (SPX) is the second subpixel (SPX2) or the third subpixel (SPX3), the subpixel (SPX) is connected to the second light emission control line (EL2) placed on the corresponding horizontal line and can receive a light emission control signal (EM) (also referred to as the "second light emission control signal") from the second light emission control line (EL2).

[0108] The subpixel (SPX) can be connected to the data driver (252) via the data line (DL). The data driver (252) can output a data voltage (Vdata) corresponding to the image data of each frame via the data line (DL).

[0109] If the subpixel (SPX) is the first subpixel (SPX1), the subpixel (SPX) may be connected to the first data line (DLr) placed in the corresponding pixel column. If the subpixel (SPX) is the second subpixel (SPX2), the subpixel (SPX) may be connected to the second data line (DLg) placed in the corresponding pixel column. If the subpixel (SPX) is the third subpixel (SPX3), the subpixel (SPX) may be connected to the third data line (DLb) placed in the corresponding pixel column.

[0110] A subpixel (SPX) can be connected to a power supply unit (500) via power lines (PL). For example, the subpixel (SPX) can be connected to a power supply unit (500) via a first power line (VDL), a second power line (VSL), a third power line (VIL), a fourth power line (VAIL), and a fifth power line (VOBL). The power supply unit (500) can supply a first driving voltage (VDD), a second driving voltage (VSS), a third driving voltage (VINT), a fourth driving voltage (VAINT), and a fifth driving voltage (VOBS), respectively, to the first power line (VDL), the second power line (VSL), the third power line (VIL), the fourth power line (VAIL), and the fifth power line (VOBL). In one embodiment, the first driving voltage (VDD), the second driving voltage (VSS), the third driving voltage (VINT), the fourth driving voltage (VAINT), and the fifth driving voltage (VOBS) may each be a high-potential pixel voltage (e.g., anode voltage), a low-potential pixel voltage (e.g., cathode voltage or common voltage), a first initialization voltage (e.g., gate initialization voltage), a second initialization voltage (e.g., anode initialization voltage), and a bias voltage.

[0111] The pixel circuit (PXC) can control the driving current (Ids) supplied to the light-emitting element (LE) in response to driving signals supplied to the subpixel (SPX) (e.g., write scan signal (GW), initialization scan signal (GI), control scan signal (GC), bias scan signal (GB), light emission control signal (EM), and data voltage (Vdata)). The pixel circuit (PXC) can control the light emission timing and brightness of the light-emitting element (LE).

[0112] The pixel circuit (PXC) may include pixel transistors (PXT) and a storage capacitor (Cst). In one embodiment, the pixel circuit (PXC) may further include a boosting capacitor (Cbst).

[0113] In one embodiment, the pixel transistors (PXT) may include first to eighth transistors (T1 to T8). The first transistor (T1) may be a driving transistor of a subpixel (SPX). The second to eighth transistors (T2 to T8) may be switching transistors of a subpixel (SPX).

[0114] In one embodiment, the subpixel (SPX) may include heterogeneous pixel transistors (PXT). For example, the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) may be P-type transistors (e.g., P-type polycrystalline silicon transistors including each active layer formed of polycrystalline silicon), and the third and fourth transistors (T3, T4) may be N-type transistors (e.g., N-type oxide transistors including each active layer formed of an oxide semiconductor). In one embodiment, the active layers of the P-type transistors (e.g., active layers formed of polycrystalline silicon) and the active layers of the N-type transistors (e.g., active layers formed of an oxide semiconductor) may be disposed on different layers within the display panel (100) (e.g., the backplane layer of the display panel (100)).

[0115] The first transistor (T1) can be connected between the fifth transistor (T5) and the sixth transistor (T6). The first transistor (T1) can be connected to the first power line (VDL) via the fifth transistor (T5) and to the light-emitting element (LE) via the sixth transistor (T6). The gate electrode of the first transistor (T1) can be connected to the first node (N1). The first transistor (T1) can control the driving current (Ids) flowing to the subpixel (SPX) according to the voltage of the first node (N1) applied to the gate electrode (for example, a voltage corresponding to the data voltage (Vdata)).

[0116] The second transistor (T2) may be connected between the data line (DL) and the first electrode of the first transistor (T1) (for example, the source electrode of the first transistor (T1) connected to the fifth transistor (T5)). The gate electrode of the second transistor (T2) may be connected to the write scan line (GWL). The second transistor (T2) may be turned on by a write scan signal (GW) of a gate-on voltage supplied from the write scan line (GWL) (for example, a low-level voltage at which the second transistor (T2) can be turned on). When the second transistor (T2) is turned on, a data voltage (Vdata) supplied from the data line (DL) may be delivered to the first electrode (for example, the source electrode) of the first transistor (T1).

[0117] The third transistor (T3) can be connected between the second electrode of the first transistor (T1) (for example, the drain electrode of the first transistor (T1) connected to the sixth transistor (T6)) and the first node (N1). The gate electrode of the third transistor (T3) can be connected to a control scan line (GCL). The third transistor (T3) can be turned on by a control scan signal (GC) of a gate-on voltage supplied from the control scan line (GCL) (for example, a high-level voltage at which the third transistor (T3) can be turned on) to connect the gate electrode of the first transistor (T1) and the second electrode. When the third transistor (T3) is turned on, the first transistor (T1) can be driven as a diode, and a voltage corresponding to a data voltage (Vdata) can be applied to the first node (N1).

[0118] The fourth transistor (T4) can be connected between the first node (N1) and the third power line (VIL). The gate electrode of the fourth transistor (T4) can be connected to the initialization scan line (GIL). The fourth transistor (T4) can be turned on by an initialization scan signal (GI) of a gate-on voltage supplied from the initialization scan line (GIL) (for example, a high-level voltage at which the fourth transistor (T4) can be turned on) to connect the first node (N1) to the third power line (VIL). When the fourth transistor (T4) is turned on, the voltage of the first node (N1) can be initialized to the third driving voltage (VINT) of the third power line (VIL).

[0119] The fifth transistor (T5) can be connected between the first power line (VDL) and the first electrode of the first transistor (T1). The gate electrode of the fifth transistor (T5) can be connected to a light emission control line (EL) (for example, the first light emission control line (EL1) or the second light emission control line (EL2) of FIG. 3). The fifth transistor (T5) can be turned on by a light emission control signal (EM) of a gate-on voltage supplied from the light emission control line (EL) (for example, a low-level voltage at which the fifth transistor (T5) can be turned on) to connect the first electrode of the first transistor (T1) to the first power line (VDL). When the fifth transistor (T5) is turned on, the first power line (VDL) can be connected to the first electrode of the first transistor (T1).

[0120] The sixth transistor (T6) can be connected between the second electrode of the first transistor (T1) and the light-emitting element (LE). The gate electrode of the sixth transistor (T6) can be connected to the light-emitting control line (EL). The sixth transistor (T6) can be turned on by a light-emitting control signal (EM) of a gate-on voltage supplied from the light-emitting control line (EL) (for example, a low-level voltage at which the sixth transistor (T6) can be turned on) to connect the second electrode of the first transistor (T1) to the light-emitting element (LE).

[0121] The seventh transistor (T7) can be connected between the first electrode of the light-emitting element (LE) (for example, the anode electrode connected to the sixth transistor (T6)) and the fourth power line (VAIL). The gate electrode of the seventh transistor (T7) can be connected to the bias scan line (GBL). The seventh transistor (T7) can be turned on by a bias scan signal (GB) of a gate-on voltage supplied from the bias scan line (GBL) (for example, a low-level voltage at which the seventh transistor (T7) can be turned on) to connect the first electrode of the light-emitting element (LE) to the fourth power line (VAIL). When the seventh transistor (T7) is turned on, the voltage of the first electrode of the light-emitting element (LE) can be initialized to the fourth driving voltage (VAINT) of the fourth power line (VAIL).

[0122] The eighth transistor (T8) can be connected between the fifth power line (VOBL) and the first electrode of the first transistor (T1). The gate electrode of the eighth transistor (T8) can be connected to the bias scan line (GBL). The eighth transistor (T8) can be turned on by a bias scan signal (GB) of a gate-on voltage supplied from the bias scan line (GBL) to connect the first electrode of the first transistor (T1) to the fifth power line (VOBL). When the eighth transistor (T8) is turned on, the voltage of the first electrode of the first transistor (T1) can be initialized to the fifth driving voltage (VOBS) of the fifth power line (VOBL). In one embodiment, the fifth driving voltage (VOBS) may be a bias voltage having a voltage level suitable for compensating for the hysteresis characteristics of the first transistor (T1).

[0123] A storage capacitor (Cst) can be connected between a first node (N1) and a first power line (VDL). The storage capacitor (Cst) can be charged to a voltage corresponding to a data voltage (Vdata) applied to the first node (N1).

[0124] A boosting capacitor (Cbst) can be connected between the first node (N1) and the write scan line (GWL). By stabilizing the voltage of the first node (N1) through the coupling action of the boosting capacitor (Cbst), the operation of the first transistor (T1) can be stabilized. The boosting capacitor (Cbst) may be formed by a parasitic capacitance formed between the first node (N1) and the write scan line (GWL), or it may be designed separately.

[0125] A subpixel (SPX) can emit light for a portion of the frame period corresponding to the on-duty ratio and can be non-emitting for the remainder of the frame period. The emission and non-emitting periods of the subpixel (SPX) can be controlled by an emission control signal (EM).

[0126] The period during which the fifth transistor (T5) and the sixth transistor (T6) are turned off (for example, the period during which a high-level light emission control signal (EM) is supplied to the subpixel (SPX)) may be a non-luminous period of the subpixel (SPX). The non-luminous period of the subpixel (SPX) may include an initialization period for initializing the voltage of a specific node of the subpixel (SPX) (for example, the first node (N1), etc.), and a data writing and storage period for charging a storage capacitor (Cst) with a voltage corresponding to the data voltage (Vdata). In one embodiment, an initialization scan signal (GI), a control scan signal (GC), a write scan signal (GW), and a bias scan signal (GB) of the gate-on voltage may be supplied during the non-luminous period of the subpixel (SPX). In one embodiment, the initialization scan signal (GI), the control scan signal (GC), and the bias scan signal (GB) of the gate-on voltage may be supplied sequentially during the non-luminous period of the subpixel (SPX). The periods during which the initialization scan signal (GI) and the control scan signal (GC) of the gate-on voltage are supplied may overlap, but are not limited thereto. During the period during which the control scan signal (GC) of the gate-on voltage is supplied, the write scan signal (GW) of the gate-on voltage may be supplied.

[0127] The period during which the fifth transistor (T5) and the sixth transistor (T6) are turned on (for example, the period during which a low-level light emission control signal (EM) is supplied to the subpixel (SPX)) may be the light emission period of the subpixel (SPX). During the light emission period of the subpixel (SPX), the first transistor (T1) may supply a driving current (Ids) corresponding to the voltage of the first node (N1) to the light-emitting element (LE).

[0128] The light-emitting element (LE) can be connected between the pixel circuit (PXC) and the second power line (VSL). For example, the first electrode of the light-emitting element (LE) (e.g., an anode electrode or a pixel electrode) can be connected to a node between the sixth transistor (T6) and the seventh transistor (T7), and the second electrode of the light-emitting element (LE) (e.g., a cathode electrode or a common electrode) can be connected to the second power line (VSL). The light-emitting element (LE) can emit light in response to a driving current (Ids) supplied from the pixel circuit (PXC).

[0129] In one embodiment, the subpixel (SPX) may include a single light-emitting element (LE), but is not limited thereto. For example, the subpixel (SPX) may include at least two light-emitting elements (LE). The at least two light-emitting elements (LE) may be connected in a series, parallel, or series-parallel structure between the pixel circuit (PXC) and the second power line (VSL).

[0130] In one embodiment, the light-emitting element (LE) may be a micro light-emitting diode containing an inorganic compound such as a nitride-based or phosphide-based semiconductor material, but is not limited thereto. For example, the light-emitting element (LE) may be an organic light-emitting element, a quantum dot light-emitting element, or other types of light-emitting elements. Additionally, the size or shape of the light-emitting element (LE) may vary depending on the embodiments.

[0131] FIG. 6 is a plan view showing pixel circuits, signal lines, and power lines disposed within a backplane layer of a display panel according to one embodiment. FIG. 7 is a plan view showing pixel circuits, signal lines, and power lines disposed within a backplane layer of a display panel according to one embodiment. FIG. 8 is a plan view showing pixel circuits, signal lines, and power lines disposed within a backplane layer of a display panel according to one embodiment.

[0132] For example, FIGS. 6, 7, and 8 show the approximate arrangement of pixel circuits (PXC), signal lines, and power lines (PL) placed within the backplane layer (BPL) of a display panel (100) in a part of a display area (DA) that includes four pixel regions (PXA) in which four pixels (PX) are arranged along a first direction (DR1) and a second direction (DR2). FIGS. 6, 7, and 8 show different embodiments with respect to the second power line (VSL). For convenience, in FIGS. 6, 7, and 8, reference numerals are indicated only for subpixels (SPX) placed in one pixel region (PXA) and the pixel (PX) including them.

[0133] Referring to FIGS. 6 through 8 in addition to FIGS. 1 through 5, pixel circuits (PXC) of a pixel (PX) placed in the corresponding pixel area (PXA) of a display area (DA) may be disposed therein. For example, a pixel circuit (PXC) of a first sub-pixel (SPX1) (hereinafter referred to as "first pixel circuit (PXC1)"), a pixel circuit (PXC) of a second sub-pixel (SPX2) (hereinafter referred to as "second pixel circuit (PXC2)"), and a pixel circuit (PXC) of a third sub-pixel (SPX3) (hereinafter referred to as "third pixel circuit (PXC3)") may be disposed in each pixel area (PXA).

[0134] Signal lines and power lines (PL) electrically connected to subpixels (SPX) placed in the corresponding pixel area (PXA) may be disposed in each pixel area (PXA) and / or around the display area (DA). The signal lines of the display area (DA) may include scan lines (SL), light emission control lines (EL), and data lines (DL). The power lines (PL) of the display area (DA) may include a first power line (VDL), a third power line (VIL), a fourth power line (VAIL), and a fifth power line (VOBL). The power lines (PL) of the display area (DA) may or may not include a second power line (VSL).

[0135] In one embodiment, the power lines (PL) of the display area (DA) may further include a horizontal power line (HVDL) connected to a first power line (VDL) and extending in a first direction (DR1). The first power line (VDL) and the horizontal power line (HVDL) may be electrically connected to each other inside and / or outside the display area (DA).

[0136] In one embodiment, a plurality of first power lines (VDL) arranged in a first direction (DR1) may be disposed in a display area (DA). For example, the plurality of first power lines (VDL) may be electrically connected to each other inside and / or outside the display area (DA) to form a single electrical wiring, but may have a form in which they branch into multiple wirings within the display area (DA). Each of the first power lines (VDL) of the display area (DA) may extend in a second direction (DR2).

[0137] The first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3) may be arranged in a first direction (DR1) in a display area (DA). For example, the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3) may be arranged sequentially along the first direction (DR1) in their respective pixel areas (PXA).

[0138] In one embodiment, the second pixel circuit (PXC2) and the third pixel circuit (PXC3) of each pixel (PX) may share a single first power line (VDL). The second pixel circuit (PXC2) and the third pixel circuit (PXC3) may be placed in close proximity. For example, the second pixel circuit (PXC2) and the third pixel circuit (PXC3) may be placed substantially adjacent to each other in the portion where the first power line (VDL) is placed, and the separation distance between the second pixel circuit (PXC2) and the third pixel circuit (PXC3) may be reduced or eliminated. Accordingly, the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3) can be efficiently placed in the pixel area (PXA) assigned to each pixel (PX), and the design structure and / or space utilization of the pixel area (PXA) can be improved.

[0139] In one embodiment, each of the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3) may overlap with one first power line (VDL). For example, two first power lines (VDL) may be placed in each pixel area (PXA). The first pixel circuit (PXC1) may overlap with one of the two first power lines (VDL), and the second pixel circuit (PXC2) and the third pixel circuit (PXC3) may overlap with the other first power line (VDL). Accordingly, the space utilization and / or integration density of the backplane layer (BPL) can be improved.

[0140] In one embodiment, the power lines (PL) of the display area (DA) may further include a second power line (VSL) as illustrated in FIGS. 6 and 7. For example, the second power line (VSL) may be placed in the space secured by closely positioning the second pixel circuit (PXC2) and the third pixel circuit (PXC3). The second power line (VSL) may be electrically connected to a common electrode placed on the backplane layer (BPL) in the interior of the display area (DA) and / or the non-display area (NDA). The common electrode may be placed in at least the display area (DA). For example, the common electrode may be placed in the display area (DA) and may also be placed in a portion of the non-display area (NDA) located around the display area (DA). The common electrode may be electrically connected to light-emitting elements (LE) in the display area (DA) and electrically connected to the second power line (VSL) in the interior of the display area (DA) and / or the non-display area (NDA).

[0141] In another embodiment, the power lines (PL) of the display area (DA) may not include a second power line (VSL) as illustrated in FIG. 8. For example, the second power line (VSL) (or the bus line to which the second driving voltage (VSS) is applied) may be placed only in the non-display area (NDA) and may be electrically connected to a common electrode around the display area (DA). The second power line (VSL) may be placed inside the backplane layer (BPL) and / or on top of the backplane layer (BPL) in the non-display area (NDA).

[0142] Scan lines (SL) and light emission control lines (EL) may be extended in a first direction (DR1) and arranged or positioned in a second direction (DR2). In one embodiment, in each horizontal line where a row of pixels (PX) is positioned, a write scan line (GWL), an initialization scan line (GIL), a control scan line (GCL), a bias scan line (GBL), a first light emission control line (EL1), and a second light emission control line (EL2) connected to subpixels (SPX) of the corresponding horizontal line may be positioned.

[0143] The location and / or arrangement order of the write scan line (GWL), initialization scan line (GIL), control scan line (GCL), bias scan line (GBL), first light emission control line (EL1), and second light emission control line (EL2) may vary depending on the design structure of each pixel circuit (PXC). For example, the write scan line (GWL) may be placed at a location corresponding to the second transistor (T2) of each pixel circuit (PXC). As an example, the write scan line (GWL) may overlap with or be placed around the second transistor (T2) of each pixel circuit (PXC). The initialization scan line (GIL) may be placed at a location corresponding to the fourth transistor (T4) of each pixel circuit (PXC). The control scan line (GCL) may be placed at a location corresponding to the third transistor (T3) of each pixel circuit (PXC). The bias scan line (GBL) can be positioned at locations corresponding to the seventh and eighth transistors (T7, T8) of each pixel circuit (PXC). The first light emission control line (EL1) and the second light emission control line (EL2) can be positioned at locations corresponding to the fifth and sixth transistors (T5, T6) of each pixel circuit (PXC). The first light emission control line (EL1) and the second light emission control line (EL2) of each horizontal line can be adjacent to each other in the second direction (DR2).

[0144] Data lines (DL) may be extended in a second direction (DR2) and arranged or positioned in a first direction (DR1). In one embodiment, in each pixel column (or vertical line) where a column of pixels (PX) is positioned, a first data line (DLr), a second data line (DLg), and a third data line (DLb) connected to subpixels (SPX) of the corresponding pixel column may be positioned.

[0145] A first data line (DLr) may be placed at a position corresponding to the second transistor (T2) of each of the first pixel circuits (PXC1). For example, the first data line (DLr) may overlap with or be placed around the second transistor (T2) of each of the first pixel circuits (PXC1). A second data line (DLg) may be placed at a position corresponding to the second transistor (T2) of each of the second pixel circuits (PXC2). A third data line (DLb) may be placed at a position corresponding to the second transistor (T2) of each of the third pixel circuits (PXC3).

[0146] In one embodiment, the first data line (DLr), the second data line (DLg), and the third data line (DLb) may each be located at one edge of the first pixel circuits (PXC1), the second pixel circuits (PXC2), and the third pixel circuits (PXC3) of the corresponding pixel column. For example, the first data line (DLr) and the second data line (DLg) may each be placed at the left edge of the first pixel circuits (PXC1) and the second pixel circuits (PXC2) of the corresponding pixel column. In one embodiment, the second data line (DLg) and the third data line (DLb) may be placed at opposite positions relative to the first power line (VDL) located at the boundary between the second pixel circuits (PXC2) and the third pixel circuits (PXC3) of the corresponding pixel column. For example, the third data line (DLb) may be placed at the right edge of the third pixel circuits (PXC3) of the corresponding pixel column.

[0147] In the embodiments, the data lines (DL) of the subpixels (SPX) can be placed around different wirings. For example, in the embodiment of FIG. 6, a first data line (DLr) placed in each pixel column is placed between a third data line (DLb) of an adjacent pixel column and a first power line (VDL) of the corresponding pixel column (for example, the first first power line (VDL) that overlaps with the first pixel circuit (PXC1) among the two first power lines (VDL) placed in each pixel column), and a second data line (DLg) is placed between a second power line (VSL) placed in the corresponding pixel column and a first power line (VDL) (for example, the second first power line (VDL) that overlaps with the second and third pixel circuits (PXC2, PXC3) among the two first power lines (VDL) placed in each pixel column), and a third data line (DLb) is placed between a first power line (VDL) placed in the corresponding pixel column (for example, the second first power line (VDL) of each pixel column) and a first data line (DLr) of an adjacent pixel column. It can be placed in between. In the embodiment of FIG. 7, a first data line (DLr) placed in each pixel column is placed between a second power line (VSL) and a first power line (VDL) (for example, the first first power line (VDL) of each pixel column), a second data line (DLg) is placed between two first power lines (VDL) of the corresponding pixel column, and a third data line (DLb) can be placed between a first power line (VDL) (for example, the second first power line (VDL) of each pixel column) and a second power line (VSL).In the embodiment of FIG. 8, a first data line (DLr) placed in each pixel column may be placed between a third data line (DLb) of an adjacent pixel column and a first power line (VDL) of the corresponding pixel column (for example, the first first power line (VDL) of each pixel column), a second data line (DLg) may be placed between two first power lines (VDL) of the corresponding pixel column, and a third data line (DLb) may be placed between a first power line (VDL) of the corresponding pixel column (for example, the second first power line (VDL) of each pixel column) and a first data line (DLr) of an adjacent pixel column.

[0148] A first power line (VDL) is placed in each pixel column and can extend in a second direction (DR2). In one embodiment, a plurality of first power lines (VDL) may be placed in each pixel column. For example, in each pixel column, one first power line (VDL) may be placed that overlaps with and is connected to the first pixel circuits (PXC1) of the corresponding pixel column, and another first power line (VDL) may be placed that overlaps with and is connected to the second and third pixel circuits (PXC2, PXC3) of the corresponding pixel column. The first power line (VDL) may overlap with the first transistor (T1) and storage capacitor (Cst), etc., of each pixel circuit (PXC). In one embodiment, the width of the first power line (VDL) connected to the second and third pixel circuits (PXC2, PXC3) may be greater than the width of the first power line (VDL) connected to the first pixel circuits (PXC1), but is not limited thereto.

[0149] In describing the embodiments, the first power lines (VDL) spaced apart from each other in at least a portion of the display area (DA) have been referred to as a plurality, but lines to which the same voltage or signal is applied may be considered as a single wire. For example, the first power lines (VDL) arranged in the first direction (DR1) in FIG. 6 may be electrically connected to each other and thus form substantially one power line. For example, the first power lines (VDL) shown in FIG. 6 may be parts branched from substantially one power line and may be different parts of said power line.

[0150] A horizontal power line (HVDL) intersects the first power lines (VDL) and can be positioned at a location corresponding to the storage capacitor (Cst) of each pixel circuit (PXC). For example, the horizontal power line (HVDL) can be positioned on each horizontal line and extend in a first direction (DR1). In one embodiment, the horizontal power line (HVDL) can be formed integrally with one electrode of the storage capacitor (Cst) included in the pixel circuit (PXC) positioned on the horizontal line (for example, the electrode connected to the first power line (VDL) in FIG. 4).

[0151] The third power line (VIL) is placed on each horizontal line and can be extended in the first direction (DR1). The third power line (VIL) can be placed at a position corresponding to the fourth transistor (T4) of each pixel circuit (PXC).

[0152] The fourth power line (VAIL) is placed on each horizontal line and can be extended in the first direction (DR1). The fourth power line (VAIL) can be placed at a position corresponding to the seventh transistor (T7) of each pixel circuit (PXC).

[0153] The fifth power line (VOBL) is placed on each horizontal line and can be extended in the first direction (DR1). The fifth power line (VOBL) can be placed at a position corresponding to the eighth transistor (T8) of each pixel circuit (PXC).

[0154] As illustrated in FIGS. 6 and 7, in embodiments comprising a second power line (VSL) disposed in a display area (DA) with a backplane layer (BPL), the second power line (VSL) may extend in a second direction (DR2). In one embodiment, a plurality of second power lines (VSL) may be disposed in the display area (DA), disposed between each pixel column or between two adjacent pixel columns. The second power lines (VSL) may be arranged or disposed in a first direction (DR1).

[0155] Each of the second power lines (VSL) may be positioned between the first pixel circuit (PXC1) and the second and third pixel circuits (PXC2, PXC3). For example, each of the second power lines (VSL) may be positioned between the first pixel circuit (PXC1) and the second pixel circuit (PXC2) included in each pixel (PX) as shown in FIG. 6, or between two adjacent pixels (PX) in the first direction (DR1) as shown in FIG. 7 (for example, between the third pixel circuit (PXC3) of the pixel (PX) positioned on the left and the first pixel circuit (PXC1) of the pixel (PX) positioned on the right). For example, each of the second power lines (VSL) may be positioned between the first power line (VDL) and the second data line (DLg) in the area where the first pixel circuit (PXC1) is positioned, as shown in FIG. 6, or between the adjacent third data line (DLb) and the first data line (DLr) in the first direction (DR1), as shown in FIG. 7.

[0156] In one embodiment, the second power lines (VSL) may not intersect with the data lines (DL) and the first power lines (VDL) at least in the display area (DA), and may be placed on the same layer as the data lines (DL) and / or the first power lines (VDL). For example, the conductive layer placed at the top of the conductive layers included in the backplane layer (BPL) of the display panel (100) may include the data lines (DL), the first power lines (VDL), and the second power lines (VSL) spaced apart from each other in the first direction (DR1).

[0157] In describing the embodiments, the second power lines (VSL) spaced apart from each other in the display area (DA) have been referred to as a plurality, but the second power lines (VSL) may be electrically connected to each other to substantially form a single power line. For example, the second power lines (VSL) shown in FIGS. 6 and 7 may be parts branched from a single power line and may be different parts of the single power line.

[0158] According to the embodiments of FIGS. 6 and 7, by placing a second power line (VSL) between pixel circuits (PXC), the voltage drop of the second driving voltage (VSS) can be reduced or minimized. For example, the second power line (VSL) can be formed within the backplane layer (BPL) of the display panel (100) using a low-resistance material with low sheet resistance together with the first power line (VDL), etc. Accordingly, the voltage drop of the second driving voltage (VSS) applied to the pixels (PX) through the second power line (VSL) can be reduced or minimized.

[0159] As illustrated in FIG. 8, in an embodiment in which the backplane layer (BPL) does not include a second power line (VSL) placed in the display area (DA), the second power line (VSL) may be placed in the non-display area (NDA) of the backplane layer (BPL). For example, the second power line (VSL) may not be placed in the display area (DA) but only in the non-display area (NDA) and may be electrically connected to a common electrode placed on the backplane layer. Alternatively, the second power line (VSL) may be placed in the display area (DA) as well, but in the display area (DA), it may be placed on the upper part of the backplane layer (BPL).

[0160] According to the embodiment of FIG. 8, the design space secured between the pixel circuits (PXC) can be utilized as a space for placing other wiring or conductive patterns other than the second power line (VSL), or can be utilized to improve electrical stability by securing a spacing distance between patterns placed around the space.

[0161] In the embodiments of FIGS. 6 to 8, the signal lines and power lines (PL) are each illustrated as extending in a straight line along a first direction (DR1) or a second direction (DR2), but the embodiments are not limited thereto. For example, FIGS. 6 to 8 illustrate the overall shape, extension direction, and arrangement direction of each of the signal lines and power lines (PL), and the shape, position, arrangement direction, and / or size of each of the signal lines and power lines (PL) may be adjusted or changed in consideration of circuit density, minimization of interference between circuits, defect avoidance, and / or arrangement of subpixels (SPX). For example, each of the signal lines and power lines (PL) may extend entirely or substantially along a first direction (DR1) or a second direction (DR2), but at least some of the lines of the signal lines and power lines (PL) may have a shape such as being partially bent or folded.

[0162] FIG. 9 is a layout diagram showing a backplane layer of a display panel according to one embodiment. For example, FIG. 9 shows a layout example of a backplane layer (BPL) for a portion of a display area (DA) corresponding to the A1 area of ​​FIG. 6. The A1 area of ​​FIG. 6 and FIG. 9 may include a pixel area (PXA) comprising a first pixel circuit (PXC1), a second pixel circuit (PXC2), and a third pixel circuit (PXC3), and the periphery of the pixel area (PXA).

[0163] FIG. 10 is a layout diagram showing the first pixel circuit of FIG. 9 in detail. FIG. 11 is a layout diagram showing the second pixel circuit of FIG. 9 in detail. FIG. 12 is a layout diagram showing the third pixel circuit of FIG. 9 in detail.

[0164] Referring to FIGS. 9 through 12 in addition to FIGS. 3 through 8, each of the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3) may include first through eighth transistors (T1 to T8), a storage capacitor (Cst), and a boosting capacitor (Cbst).

[0165] The first transistor (T1) may include a first active layer (ACT1) and a first gate electrode (GE1). The first gate electrode (GE1) may overlap with a portion of the first active layer (ACT1). In one embodiment, the first transistor (T1) may further include a source electrode (SE1) and a drain electrode (DE1). The source electrode (SE1) and the drain electrode (DE1) may be electrically connected to different portions of the first active layer (ACT1), for example, the source region and the drain region of the first active layer (ACT1), respectively.

[0166] The first active layer (ACT1) may include a channel region that overlaps with the first gate electrode (GE1), and source and drain regions located on both sides of the channel region. Although the source and drain regions included in the active layers of each transistor, including the first active layer (ACT1), are not separately illustrated in FIGS. 9 to 12, depending on the type of each transistor (e.g., P-type or N-type) and the voltage applied across each transistor, one part of the active layer included in each transistor may be a source region and the other part may be a drain region.

[0167] The source region of the first active layer (ACT1) may be electrically connected to the second, fifth, and eighth active layers (ACT2, ACT5, ACT8) included in the second, fifth, and eighth transistors (T2, T5, T8). For example, the first active layer (ACT1), the second active layer (ACT2), the fifth active layer (ACT5), and the eighth active layer (ACT8) may be formed integrally, and the source region of the first active layer (ACT1) may be electrically connected to a part (for example, a drain region) of each of the second, fifth, and eighth active layers (ACT2, ACT5, ACT8). The drain region of the first active layer (ACT1) may be electrically connected to the third and sixth active layers (ACT3, ACT6) included in the third and sixth transistors (T3, T6). For example, the drain region of the first active layer (ACT1) may be electrically connected to a drain electrode (DE1) through at least one second contact hole (CH2) and may be electrically connected to a part of the third active layer (ACT3) (for example, a drain region) through the drain electrode (DE1). The first active layer (ACT1) may also be formed integrally with the sixth and seventh active layers (ACT6, ACT7). The drain region of the first active layer (ACT1) may be electrically connected to a part of the sixth active layer (ACT6) (for example, a source region).

[0168] The source electrode (SE1) can be electrically connected to a part of the first active layer (ACT1) through at least one first contact hole (CH1). For example, the source electrode (SE1) can be electrically connected to a source region of the first active layer (ACT1) through a plurality of first contact holes (CH1).

[0169] The drain electrode (DE1) may be electrically connected to another part of the first active layer (ACT1) through at least one second contact hole (CH2). For example, the drain electrode (DE1) may be electrically connected to the drain region of the first active layer (ACT1) through a plurality of second contact holes (CH2). The drain electrode (DE1) may be electrically connected to the third transistor (T3) through a third contact hole (CH3). For example, the drain electrode (DE1) may be electrically connected to a part of the third active layer (ACT3) (for example, the drain region of the third active layer (ACT3)) through the third contact hole (CH3).

[0170] The first gate electrode (GE1) can be electrically connected to the first electrode (SCE1) of the storage capacitor (Cst). For example, the first gate electrode (GE1) and the first electrode (SCE1) of the storage capacitor (Cst) can be formed integrally and can substantially form a single conductive pattern. The first gate electrode (GE1) can be electrically connected to the first connection electrode (CNE1) through the fourth contact hole (CH4) and can be electrically connected to the third and fourth transistors (T3, T4) through the first connection electrode (CNE1). The first connection electrode (CNE1) can be electrically connected to a portion (for example, a source or drain region) of each of the third and fourth active layers (ACT3, ACT4) included in the third and fourth transistors (T3, T4) through the fifth contact hole (CH5).

[0171] In one embodiment, the backplane layer (BPL) of the display panel (100) may further include a light-blocking pattern (not shown) disposed below the first active layer (ACT1). For example, the backplane layer (BPL) may further include a lower conductive layer (e.g., a bottom metal layer) disposed between the first semiconductor layer on which the first active layer (ACT1) is disposed and the substrate, and the lower conductive layer may include a lower pattern that overlaps with the channel region of the first active layer (ACT1). The lower pattern can block light incident from the lower part of the first active layer (ACT1) (e.g., the lower part of the backplane layer (BPL)) toward the channel region of the first active layer (ACT1). Accordingly, the operating characteristics of the first transistor (T1) can be stabilized. In addition, the lower pattern can disperse charges accumulated around the first transistor (T1).

[0172] A storage capacitor (Cst) may include a first electrode (SCE1) and a second electrode (SCE2) that overlap each other. The first electrode (SCE1) of the storage capacitor (Cst) may be formed integrally with the first gate electrode (GE1). The second electrode (SCE2) of the storage capacitor (Cst) may be formed integrally with the horizontal power line (HVDL) and may be electrically connected to the first power line (VDL). For example, the second electrode (SCE2) of the storage capacitor (Cst) may be electrically connected to the second connecting electrode (CNE2) through the sixth contact hole (CH6) and may be electrically connected to the first power line (VDL) through the second connecting electrode (CNE2). The second connecting electrode (CNE2) may be electrically connected to the first power line (VDL) through the first via hole (VH1) (or contact hole). Additionally, the second connecting electrode (CNE2) can be electrically connected to a part (e.g., a source region) of the fifth active layer (ACT5) included in the fifth transistor (T5) through the seventh contact hole (CH7).

[0173] The second transistor (T2) may include a second active layer (ACT2) and a second gate electrode (GE2). The second gate electrode (GE2) may overlap with a portion of the second active layer (ACT2).

[0174] The second active layer (ACT2) may include a channel region overlapping with the second gate electrode (GE2), and source and drain regions located on both sides of the channel region. The source region of the second active layer (ACT2) may be electrically connected to a data line (DL). For example, the source region of the second active layer (ACT2) may be electrically connected to a third connection electrode (CNE3) through an eighth contact hole (CH8) and may be electrically connected to a data line (DL) of each subpixel (SPX) (for example, a first data line (DLr), a second data line (DLg), or a third data line (DLb)) through the third connection electrode (CNE3). The third connection electrode (CNE3) may be electrically connected to a data line (DL) of each subpixel (SPX) through a second via hole (VH2) (or contact hole). The drain region of the second active layer (ACT2) may be electrically connected to the first, fifth, and eighth active layers (ACT1, ACT5, ACT8) included in the first, fifth, and eighth transistors (T1, T5, T8). For example, the drain region of the second active layer (ACT2) may be electrically connected to the source region of the first active layer (ACT1) and the drain region of each of the fifth and eighth active layers (ACT5, ACT8).

[0175] The second gate electrode (GE2) can be electrically connected to the write scan line (GWL). For example, the second gate electrode (GE2) and the write scan line (GWL) can be formed integrally and can substantially form a single conductive pattern. In this case, a portion of the write scan line (GWL) that overlaps with the second active layer (ACT2) can function as the second gate electrode (GE2).

[0176] The third transistor (T3) may include a third active layer (ACT3) and a third gate electrode (GE3). The third gate electrode (GE3) may overlap with a portion of the third active layer (ACT3).

[0177] The third active layer (ACT3) may include a channel region overlapping with the third gate electrode (GE3), and source and drain regions located on both sides of the channel region. The source region of the third active layer (ACT3) may be electrically connected to the first gate electrode (GE1) of the first transistor (T1) and the fourth active layer (ACT4) of the fourth transistor (T4). For example, the source region of the third active layer (ACT3) may be electrically connected to the first connection electrode (CNE1) through the fifth contact hole (CH5) and electrically connected to the first gate electrode (GE1) of the first transistor (T1) through the first connection electrode (CNE1). Additionally, the third active layer (ACT3) and the fourth active layer (ACT4) may be formed integrally, and the source region of the third active layer (ACT3) may be electrically connected to the drain region of the fourth active layer (ACT4). The drain region of the third active layer (ACT3) can be electrically connected to the first active layer (ACT1) of the first transistor (T1). For example, the drain region of the third active layer (ACT3) can be connected to the drain electrode (DE1) of the first transistor (T1) through the third contact hole (CH3), and can be electrically connected to the drain region of the first active layer (ACT1) through the drain electrode (DE1) of the first transistor (T1).

[0178] The third gate electrode (GE3) can be electrically connected to the control scan line (GCL). For example, the third gate electrode (GE3) and the control scan line (GCL) can be formed integrally and can substantially form a single conductive pattern. In this case, a portion of the control scan line (GCL) that overlaps with the third active layer (ACT3) can function as the third gate electrode (GE3).

[0179] In one embodiment, the backplane layer (BPL) of the display panel (100) may further include a first light-blocking pattern (LBP1) disposed below the third active layer (ACT3). The first light-blocking pattern (LBP1) extends in a first direction (DR1) and may overlap with the channel region and control scan line (GCL) of the third active layer (ACT3). The first light-blocking pattern (LBP1) can block light incident from the bottom of the third active layer (ACT3) toward the channel region of the third active layer (ACT3). Accordingly, the operating characteristics of the third transistor (T3) can be stabilized.

[0180] The fourth transistor (T4) may include a fourth active layer (ACT4) and a fourth gate electrode (GE4). The fourth gate electrode (GE4) may overlap with a portion of the fourth active layer (ACT4).

[0181] The fourth active layer (ACT4) may include a channel region overlapping with the fourth gate electrode (GE4), and source and drain regions located on both sides of the channel region. The source region of the fourth active layer (ACT4) may be electrically connected to the third power line (VIL). For example, the source region of the fourth active layer (ACT4) may be electrically connected to the third power line (VIL) through the ninth contact hole (CH9). Additionally, the drain region of the fourth active layer (ACT4) may be electrically connected to the first gate electrode (GE1) of the first transistor (T1) and the third active layer (ACT3) of the third transistor (T3). For example, the drain region of the third active layer (ACT3) may be electrically connected to the first gate electrode (GE1) of the first transistor (T1) through the first connection electrode (CNE1) and may be formed integrally with the source region of the third active layer (ACT3). For example, the third active layer (ACT3) and the fourth active layer (ACT4) of the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3), respectively, can be formed as a single semiconductor pattern that is integral with each other. In one embodiment, the third active layer (ACT3) and the fourth active layer (ACT4) may include an oxide semiconductor. Accordingly, leakage current of the subpixels (SPX) can be reduced or prevented.

[0182] The fourth gate electrode (GE4) can be electrically connected to the initialization scan line (GIL). For example, the fourth gate electrode (GE4) and the initialization scan line (GIL) can be formed integrally and can substantially form a single conductive pattern. In this case, a portion of the initialization scan line (GIL) that overlaps with the fourth active layer (ACT4) can function as the fourth gate electrode (GE4).

[0183] In one embodiment, the backplane layer (BPL) of the display panel (100) may further include a second light-blocking pattern (LBP2) disposed below the fourth active layer (ACT4). The second light-blocking pattern (LBP2) extends in a first direction (DR1) and may overlap with the channel region and initialization scan line (GIL) of the fourth active layer (ACT4). The first light-blocking pattern (LBP1) and the second light-blocking pattern (LBP2) may be disposed on the same layer within the backplane layer (BPL), but are not limited thereto. The second light-blocking pattern (LBP2) can block light incident from below the fourth active layer (ACT4) toward the channel region of the fourth active layer (ACT4). Accordingly, the operating characteristics of the fourth transistor (T4) can be stabilized.

[0184] In one embodiment, the third and fourth active layers (ACT3, ACT4) of the third and fourth transistors (T3, T4) may overlap with the write scan line (GWL). A boosting capacitor (Cbst) may be formed between the third and fourth active layers (ACT3, ACT4) and the write scan line (GWL).

[0185] The boosting capacitor (Cbst) may include a first electrode (BCE1) and a second electrode (BCE2) that overlap each other. The first electrode (BCE1) of the boosting capacitor (Cbst) may be formed integrally with the write scan line (GWL). The second electrode (BCE2) of the boosting capacitor (Cbst) may be formed integrally with a portion (e.g., a source or drain region) of each of the third and fourth active layers (ACT3, ACT4). In one embodiment, the capacitance of the boosting capacitor (Cbst) can be adjusted by controlling the size of the region where the third and fourth active layers (ACT3, ACT4) and the write scan line (GWL) overlap. For example, at the intersection of the third and fourth active layers (ACT3, ACT4) and the write scan line (GWL), the width of the third and fourth active layers (ACT3, ACT4) and / or the write scan line (GWL) can be widened to increase the capacitance of the boosting capacitor (Cbst).

[0186] The fifth transistor (T5) may include a fifth active layer (ACT5) and a fifth gate electrode (GE5). The fifth gate electrode (GE5) may overlap with a portion of the fifth active layer (ACT5).

[0187] The fifth active layer (ACT5) may include a channel region overlapping with the fifth gate electrode (GE5), and source and drain regions located on both sides of the channel region. The source region of the fifth active layer (ACT5) may be electrically connected to the first power line (VDL). For example, the source region of the fifth active layer (ACT5) may be electrically connected to the second connection electrode (CNE2) through the seventh contact hole (CH7) and electrically connected to the first power line (VDL) through the second connection electrode (CNE2). The drain region of the fifth active layer (ACT5) may be electrically connected to the first, second, and eighth active layers (ACT1, ACT2, ACT8) included in the first, second, and eighth transistors (T1, T2, T8). For example, the drain region of the fifth active layer (ACT5) can be electrically connected to the source region of the first active layer (ACT1) and the drain region of the second and eighth active layers (ACT2, ACT8), respectively.

[0188] In one embodiment, the fifth active layer (ACT5) may intersect with a first light emission control line (EL1) and a second light emission control line (EL2) that are electrically connected to subpixels (SPX) of the corresponding pixel (PX). For example, the fifth active layer (ACT5) may have a roughly "U" or "Y" shape around the first light emission control line (EL1) and the second light emission control line (EL2) and may intersect with the first light emission control line (EL1) and the second light emission control line (EL2).

[0189] The fifth gate electrode (GE5) may be electrically connected to either of the light emission control lines (EL). For example, the fifth gate electrode (GE5) may be electrically connected to the first light emission control line (EL1) or the second light emission control line (EL2) placed on the corresponding horizontal line through the tenth contact hole (CH10_1 or CH10_2). For example, the fifth gate electrode (GE5) included in the first pixel circuit (PXC1) may be electrically connected to the first light emission control line (EL1) through the tenth contact hole (CH10_1) which overlaps with the first light emission control line (EL1), and the fifth gate electrode (GE5) included in each of the second and third pixel circuits (PXC2, PXC3) may be electrically connected to the second light emission control line (EL2) through the tenth contact hole (CH10_2) which overlaps with the second light emission control line (EL2).

[0190] The sixth transistor (T6) may include a sixth active layer (ACT6) and a sixth gate electrode (GE6). The sixth gate electrode (GE6) may overlap with a portion of the sixth active layer (ACT6).

[0191] The sixth active layer (ACT6) may include a channel region overlapping with the sixth gate electrode (GE6), and source and drain regions located on both sides of the channel region. The source region of the sixth active layer (ACT6) may be electrically connected to the first and third active layers (ACT1, ACT3) included in the first and third transistors (T1, T3). For example, the source region of the sixth active layer (ACT6) may be electrically connected to the drain region of each of the first and third active layers (ACT1, ACT3). The drain region of the sixth active layer (ACT6) may be electrically connected to a light-emitting element (LE). For example, the drain region of the sixth active layer (ACT6) may be electrically connected to the fourth connecting electrode (CNE4) through the eleventh contact hole (CH11) and electrically connected to the pixel electrode of each subpixel (SPX) through the fourth and fifth connecting electrodes (CNE4, CNE5). The fourth connecting electrode (CNE4) can be electrically connected to the fifth connecting electrode (CNE5) through the third via hole (VH3) (or contact hole). The fifth connecting electrode (CNE5) can be electrically connected to the pixel electrode of each subpixel (SPX) through the anode contact hole (ANH) of each subpixel (SPX) (or the cathode contact hole in the case of a display panel with a common-anode structure). For example, the fifth connecting electrode (CNE5) of the first pixel circuit (PXC1) can be electrically connected to the first pixel electrode connected to the light-emitting element (LE) of the first subpixel (SPX1) through the first anode contact hole (ANH1) that overlaps with the first pixel circuit (PXC1). The fifth connection electrode (CNE5) of the second pixel circuit (PXC2) can be electrically connected to the second pixel electrode connected to the light-emitting element (LE) of the second subpixel (SPX2) through a second anode contact hole (ANH2) that overlaps with the second pixel circuit (PXC2).The fifth connection electrode (CNE5) of the third pixel circuit (PXC3) can be electrically connected to the third pixel electrode connected to the light-emitting element (LE) of the third sub-pixel (SPX3) through a third anode contact hole (ANH3) that overlaps with the third pixel circuit (PXC3). In one embodiment, the sixth active layer (ACT6) can intersect with the first light-emitting control line (EL1) and the second light-emitting control line (EL2) that are electrically connected to the corresponding pixel (PX).

[0192] The sixth gate electrode (GE6) may be electrically connected to either of the light emission control lines (EL). For example, the sixth gate electrode (GE6) may be electrically connected to the first light emission control line (EL1) or the second light emission control line (EL2) placed on the corresponding horizontal line through the tenth contact hole (CH10_1 or CH10_2). For example, the sixth gate electrode (GE6) included in the first pixel circuit (PXC1) may be electrically connected to the first light emission control line (EL1) through the tenth contact hole (CH10_1) which overlaps with the first light emission control line (EL1), and the sixth gate electrode (GE6) included in each of the second and third pixel circuits (PXC2, PXC3) may be electrically connected to the second light emission control line (EL2) through the tenth contact hole (CH10_2) which overlaps with the second light emission control line (EL2).

[0193] In one embodiment, the fifth and sixth gate electrodes (GE5, GE6) of the first pixel circuit (PXC1) are formed as a single conductive pattern that overlaps with the first light emission control line (EL1), and can be electrically connected to the first light emission control line (EL1) through a single tenth contact hole (CH10_1) disposed between the fifth gate electrode (GE5) and the sixth gate electrode (GE6) of the first pixel circuit (PXC1). Additionally, the fifth and sixth gate electrodes (GE5, GE6) of the second and third pixel circuits (PXC2, PXC3) are formed as a single conductive pattern that overlaps with the second light emission control line (EL2), and can be electrically connected to the second light emission control line (EL2) through a single tenth contact hole (CH10_2) disposed between the second and third pixel circuits (PXC2, PXC3). Accordingly, the design structure of the pixel circuits (PXC) can be further simplified or optimized.

[0194] The seventh transistor (T7) may include a seventh active layer (ACT7) and a seventh gate electrode (GE7). The seventh gate electrode (GE7) may overlap with a portion of the seventh active layer (ACT7).

[0195] The seventh active layer (ACT7) may include a channel region overlapping with the seventh gate electrode (GE7), and source and drain regions located on both sides of the channel region. The source region of the seventh active layer (ACT7) may be electrically connected to the sixth active layer (ACT6) and the light-emitting element (LE). For example, the sixth and seventh active layers (ACT6, ACT7) may be formed integrally, and the source region of the seventh active layer (ACT7) may be electrically connected to the drain region of the sixth active layer (ACT6). Additionally, the source region of the seventh active layer (ACT7) may be electrically connected to the fourth connecting electrode (CNE4) through the eleventh contact hole (CH11), and may be electrically connected to the pixel electrode of each subpixel (SPX) through the fourth and fifth connecting electrodes (CNE4, CNE5). The drain region of the seventh active layer (ACT7) may be electrically connected to the fourth power line (VAIL). For example, the drain region of the seventh active layer (ACT7) can be electrically connected to the sixth connecting electrode (CNE6) through the twelfth contact hole (CH12) and can be electrically connected to the fourth power line (VAIL) through the sixth connecting electrode (CNE6). The sixth connecting electrode (CNE6) can be electrically connected to the fourth power line (VAIL) through the thirteenth contact hole (CH13).

[0196] The seventh gate electrode (GE7) can be electrically connected to the bias scan line (GBL). For example, the seventh gate electrode (GE7) and the bias scan line (GBL) can be formed integrally and can substantially form a single conductive pattern. In this case, a portion of the bias scan line (GBL) that overlaps with the seventh active layer (ACT7) can function as the seventh gate electrode (GE7).

[0197] The eighth transistor (T8) may include an eighth active layer (ACT8) and an eighth gate electrode (GE8). The eighth gate electrode (GE8) may overlap with a portion of the eighth active layer (ACT8).

[0198] The eighth active layer (ACT8) may include a channel region overlapping with the eighth gate electrode (GE8), and source and drain regions located on both sides of the channel region. The source region of the eighth active layer (ACT8) may be electrically connected to the fifth power line (VOBL). For example, the source region of the eighth active layer (ACT8) may be electrically connected to the seventh connecting electrode (CNE7) through the 14th contact hole (CH14) and electrically connected to the fifth power line (VOBL) through the seventh connecting electrode (CNE7). The seventh connecting electrode (CNE7) may be electrically connected to the fifth power line (VOBL) through the 15th contact hole (CH15). The drain region of the eighth active layer (ACT8) may be electrically connected to the first, second, and fifth active layers (ACT1, ACT2, ACT5) included in the first, second, and fifth transistors (T1, T2, T5). For example, the drain region of the eighth active layer (ACT8) can be electrically connected to the source region of the first active layer (ACT1) and the drain region of the second and fifth active layers (ACT2, ACT5), respectively.

[0199] In one embodiment, the first active layer (ACT1), second active layer (ACT2), fifth active layer (ACT5), sixth active layer (ACT6), seventh active layer (ACT7), and eighth active layer (ACT8) of the first pixel circuit (PXC1), second pixel circuit (PXC2), and third pixel circuit (PXC3), respectively, may be formed integrally and may be formed substantially as a single semiconductor pattern. The first active layer (ACT1), second active layer (ACT2), fifth active layer (ACT5), sixth active layer (ACT6), seventh active layer (ACT7), and eighth active layer (ACT8) may each comprise the same semiconductor material, for example, polycrystalline silicon.

[0200] The eighth gate electrode (GE8) can be electrically connected to the bias scan line (GBL). For example, the eighth gate electrode (GE8) and the bias scan line (GBL) can be formed integrally and can substantially form a single conductive pattern. In this case, a portion of the bias scan line (GBL) that overlaps with the eighth active layer (ACT8) can function as the eighth gate electrode (GE8).

[0201] As in the embodiments of FIGS. 9 to 12, if the backplane layer (BPL) further includes a second power line (VSL) disposed in a display area (DA), the second power line (VSL) may be electrically connected to a common electrode on the backplane layer (BPL). For example, the second power line (VSL) may be electrically connected to a common electrode disposed in an emitting element layer (EDL) on the backplane layer (BPL) through a cathode contact hole (CDH) disposed in each pixel area (PXA) (anode contact hole in the case of a common-cathode structure display panel), and may be electrically connected to the emitting elements (LE) of subpixels (SPX) through the common electrode. In one embodiment, a cathode contact hole (CDH) is formed for each pixel area (PXA) and may overlap with the second pixel circuit (PXC2), but is not limited thereto. The number or location of cathode contact holes (CDH) placed in each pixel area (PXA) or display area (DA) may vary depending on the embodiments.

[0202] The signal lines and power lines (PL) of the backplane layer (BPL) may be positioned around the circuit elements to which each line is connected. In one embodiment, the first power line (VDL) may have a relatively large width at a location corresponding to the first transistor (T1), the third transistor (T3), and the fourth transistor (T4), and may cover at least a portion of each of the first transistor (T1), the third transistor (T3), and the fourth transistor (T4). For example, the first power line (VDL) may cover the channel region of each of the first transistor (T1), the third transistor (T3), and the fourth transistor (T4) wholly or partially. For example, a first power line (VDL) overlapping with a first pixel circuit (PXC1) may cover the channel regions of the first transistor (T1), the third transistor (T3), and the fourth transistor (T4) of the first pixel circuit (PXC1), and a first power line (VDL) overlapping with second and third pixel circuits (PXC2, PXC3) may cover the channel regions of the first transistors (T1), the third transistors (T3), and the fourth transistors (T4) of the second and third pixel circuits (PXC2, PXC3). Accordingly, light incident from the top of the backplane layer (BPL) toward the channel regions of the first transistor (T1), the third transistor (T3), and the fourth transistor (T4) can be blocked or reduced. Accordingly, the operating characteristics of the first transistor (T1), the third transistor (T3), and the fourth transistor (T4) can be stabilized. In addition, by covering at least a portion of the first transistors (T1), the third transistors (T3), and the fourth transistors (T4) with a first power line (VDL) disposed on the first transistors (T1), the third transistors (T3), and the fourth transistors (T4), the operating characteristics of the subpixels (SPX) can be improved without placing a separate light-blocking pattern on top of the first transistors (T1), the third transistors (T3), and the fourth transistors (T4).For example, the first power line (VDL) can be formed integrally with a light-blocking pattern placed on top of the first transistors (T1), the third transistors (T3), and the fourth transistors (T4). Accordingly, the design structure of the backplane layer (BPL) can be further optimized, and space can be secured between the patterns included in the backplane layer (BPL).

[0203] In one embodiment, subpixels (SPX) may be driven with a differential or optimized driving current (Ids) according to the optimal consumption efficiency of light-emitting elements (LE). Additionally, pixel transistors (PXT) located in the current path through which the driving current (Ids) flows in the subpixels (SPX) may have a differential size according to each driving current (Ids). For example, the sizes of the first transistors (T1) of at least two of the first subpixels (SPX) among the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) (e.g., the ratio of channel width to channel length) may differ from each other.

[0204] In one embodiment, corresponding to the data voltage (Vdata) of each grayscale, the first subpixel (SPX1) may be driven with a larger driving current (Ids) than the second subpixel (SPX2) and the third subpixel (SPX3). In this case, the size of the first transistor (T1) of the first subpixel (SPX1) may be larger than the size of the first transistor (T1) of each of the second subpixel (SPX2) and the third subpixel (SPX3). For example, the ratio of the channel width to the channel length of the first transistor (T1) of the first subpixel (SPX1) may be larger than the ratio of the channel width to the channel length of the first transistor (T1) of each of the second subpixel (SPX2) and the third subpixel (SPX3). Similarly, the size of the fifth transistor (T5) of the first subpixel (SPX1) (e.g., the ratio of channel width to channel length) is larger than the size of the fifth transistor (T5) of each of the second subpixel (SPX2) and the third subpixel (SPX3) (e.g., the ratio of channel width to channel length), and the size of the sixth transistor (T6) of the first subpixel (SPX1) may be larger than the size of the sixth transistor (T6) of each of the second subpixel (SPX2) and the third subpixel (SPX3). Accordingly, the current processing capability of the first transistor (T1) included in the first subpixel (SPX1) can be increased.

[0205] When the subpixels (SPX) are driven with an optimized driving current (Ids) according to the optimal consumption efficiency of each light-emitting element (LE), the consumption efficiency and lifespan of the light-emitting elements (LE) can be improved. Accordingly, the power consumption and lifespan of the display device (10) can be improved.

[0206] FIG. 13 is a layout diagram showing patterns included in a first semiconductor layer, a first gate conductive layer, a second semiconductor layer, and a third gate conductive layer of a backplane layer according to one embodiment. For example, FIG. 13 shows in detail the patterns of a first semiconductor layer (SCL1), a first gate conductive layer (GCDL1), a second semiconductor layer (SCL2), and a third gate conductive layer (GCDL3) disposed in region A1 of FIG. 9.

[0207] FIG. 14 is a layout diagram showing patterns included in a first gate conductive layer and a second gate conductive layer according to one embodiment. For example, FIG. 14 shows in detail the patterns of a first gate conductive layer (GCDL1) and a second gate conductive layer (GCDL2) disposed in region A1 of FIG. 9.

[0208] FIG. 15 is a layout diagram showing patterns included in the first source-drain conductive layer and the second source-drain conductive layer of a backplane layer according to one embodiment. For example, FIG. 15 shows in detail the patterns of the first source-drain conductive layer (SCDL1) and the second source-drain conductive layer (SCDL2) disposed in region A1 of FIG. 9.

[0209] Referring to FIGS. 13 to 15 in addition to FIGS. 9 to 12, circuit elements and wiring of the backplane layer (BPL) may be arranged in a plurality of semiconductor layers and conductive layers. For example, the circuit elements and wiring of the backplane layer (BPL) may be formed in patterns of a first semiconductor layer (SCL1), a first gate conductive layer (GCDL1), a second gate conductive layer (GCDL2), a second semiconductor layer (SCL2), a third gate conductive layer (GCDL3), a first source-drain conductive layer (SCDL1), and a second source-drain conductive layer (SCDL2) of the backplane layer (BPL).

[0210] The first semiconductor layer (SCL1) may include first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8).

[0211] The first gate conductive layer (GCDL1) may include first, second, fifth, sixth, seventh, and eighth gate electrodes (GE1, GE2, GE5, GE6, GE7, GE8), a write scan line (GWL), a bias scan line (GBL), a first electrode (SCE1) of a storage capacitor (Cst), and a first electrode (BCE1) of a boosting capacitor (Cbst).

[0212] In each subpixel (SPX), the region where the first active layer (ACT1) and the first gate electrode (GCDL1) overlap may include the channel region of the first transistor (T1). In one embodiment, the first subpixel (SPX1) may be driven with a larger driving current (Ids) than the second subpixel (SPX2), and the ratio (W1 / L1) of the width (W1) and length (L1) of the channel region of the first transistor (T1) included in the first subpixel (SPX1) may be greater than the ratio (W2 / L2) of the width (W2) and length (L2) of the channel region of the first transistor (T1) included in the second subpixel (SPX2). For example, compared to the first active layer (ACT1) of the second subpixel (SPX2), the first active layer (ACT1) of the first subpixel (SPX1) may have a reduced size in the first direction (DR1) corresponding to the length direction of the channel region and an expanded size in the second direction (DR2) corresponding to the width direction of the channel region. Accordingly, compared to the first transistor (T1) of the second subpixel (SPX2), the first transistor (T1) of the first subpixel (SPX1) may have a reduced size in the first direction (DR1) and an expanded size in the second direction (DR2). In one embodiment, as the width (W1) of the channel region of the first transistor (T1) in the first subpixel (SPX1) is expanded, the first transistor (T1) and the third and fourth transistors (T3, T4) may be placed closer together.

[0213] Similarly, the first subpixel (SPX1) can be driven with a larger driving current (Ids) than the third subpixel (SPX3), and the ratio (W1 / L1) of the width (W1) and length (L1) of the channel area of ​​the first transistor (T1) included in the first subpixel (SPX1) may be greater than the ratio of the width and length of the channel area of ​​the first transistor (T1) included in the third subpixel (SPX3). In one embodiment, the first transistor (T1) of the second subpixel (SPX2) and the first transistor (T1) of the third subpixel (SPX3) may have substantially the same size and may have a shape symmetrical to each other, but are not limited thereto.

[0214] In one embodiment, as the first subpixel (SPX1) is driven with a larger driving current (Ids) compared to the second and third subpixels (SPX2, SPX3), the size of the fifth and sixth transistors (T5, T6) of the first subpixel (SPX1) may also be increased. For example, the ratio of the width to the length of the channel regions of the fifth and sixth transistors (T5, T6) of the first subpixel (SPX1) may be greater than the ratio of the width to the length of the channel regions of the fifth and sixth transistors (T5, T6) of the second and third subpixels (SPX2, SPX3), respectively. For example, in the first subpixel (SPX1), the operating characteristics of the first subpixel (SPX1) can be improved by extending the width of the channel region of the fifth and sixth active layers (ACT5, ACT6) that overlap with the fifth and sixth gate electrodes (GE5, GE6) (for example, the horizontal length according to the first direction (DR1)).

[0215] The second gate conductive layer (GCDL2) may include a first light-blocking pattern (LBP1), a second light-blocking pattern (LBP2), a second electrode (SCE2) of a storage capacitor (Cst), a horizontal power line (HVDL), and a fourth power line (VAIL).

[0216] The second semiconductor layer (SCL2) may include third and fourth active layers (ACT3, ACT4) and the second electrode (BCE2) of the boosting capacitor (Cbst).

[0217] The third gate conductive layer (GCDL3) may include third and fourth gate electrodes (GE3, GE4), an initialization scan line (GIL), a control scan line (GCL), and a fifth power line (VOBL).

[0218] The first source-drain conductive layer (SCDL1) may include first, second, third, fourth, sixth, and seventh connecting electrodes (CNE1, CNE2, CNE3, CNE4, CNE6, CNE7), first and second light emission control lines (EL1, EL2), source and drain electrodes (SE1, DE1) of the first transistor (T1), and a third power line (VIL).

[0219] The second source-drain conductive layer (SCDL2) may include a fifth connecting electrode (CNE5), first, second, and third data lines (DLr, DLg, DLb), and first and second power lines (VDL, VSL).

[0220] FIG. 16 is a layout diagram showing in detail a portion of a first pixel circuit, a second pixel circuit, and a third pixel circuit according to one embodiment. For example, FIG. 16 shows in detail the first to fourth transistors (T1, T2, T3, T4), a storage capacitor (Cst), and a boosting capacitor (Cbst) of each of the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3).

[0221] FIG. 17 is a layout diagram showing in detail a portion of a first pixel circuit, a second pixel circuit, and a third pixel circuit according to one embodiment. For example, FIG. 17 shows in detail the fifth to eighth transistors (T5, T6, T7, T8) of each of the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3).

[0222] Referring to FIGS. 16 and FIGS. 17 in addition to FIGS. 9 through 15, the second pixel circuit (PXC2) and the third pixel circuit (PXC3) may have a shape that is symmetric to each other. For example, the second pixel circuit (PXC2) and the third pixel circuit (PXC3) may share a first power line (VDL) and may be arranged in a flip shape with respect to the first power line (VDL). For example, the second pixel circuit (PXC2) and the third pixel circuit (PXC3) may be commonly connected to a first power line (VDL) in their respective pixel regions (PXA) and may have a shape that is symmetric to each other with respect to the first power line (VDL).

[0223] In one embodiment, the second pixel circuit (PXC2) and the third pixel circuit (PXC3) may be designed symmetrically so as to be in contact with each other in an area where a first power line (VDL) is placed and have a substantially symmetrical and / or inverted shape with respect to the first power line (VDL). For example, the second pixel circuit (PXC2) and the third pixel circuit (PXC3) may have a substantially symmetrical shape with respect to the central axis of the first power line (VDL) (for example, a vertical central axis extending in the second direction (DR2)).

[0224] Specifically, the first to eighth transistors (T1, T2, T3, T4, T5, T6, T7, T8), storage capacitor (Cst), and boosting capacitor (Cbst) of the second pixel circuit (PXC2) may each be positioned facing the first to eighth transistors (T1, T2, T3, T4, T5, T6, T7, T8), storage capacitor (Cst), and boosting capacitor (Cbst) of the third pixel circuit (PXC3) in the first direction (DR1). Additionally, the first to eighth transistors (T1, T2, T3, T4, T5, T6, T7, T8), storage capacitor (Cst), and boosting capacitor (Cbst) of the second pixel circuit (PXC2), and the first to eighth transistors (T1, T2, T3, T4, T5, T6, T7, T8), storage capacitor (Cst), and boosting capacitor (Cbst) of the third pixel circuit (PXC3) may have a shape that is substantially symmetric to each other with respect to the boundary between the second pixel circuit (PXC2) and the third pixel circuit (PXC3).

[0225] In one embodiment, the first transistors (T1) of the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3) may be arranged sequentially along a first direction (DR1). When the second pixel circuit (PXC2) and the third pixel circuit (PXC3) have a shape that is symmetrical to each other, the drain electrode (DE1) of the first transistor (T1) included in the second pixel circuit (PXC2) and the drain electrode (DE1) of the first transistor (T1) included in the third pixel circuit (PXC3) may be arranged adjacent to each other in the first direction (DR1). The drain electrode (DE1) of the first transistor (T1) included in the first pixel circuit (PXC1) and the source electrode (SE1) of the first transistor (T1) included in the second pixel circuit (PXC2) may be arranged adjacent to each other in the first direction (DR1). The source electrode (SE1) of the first transistor (T1) included in the first pixel circuit (PXC1) may be adjacent to the source electrode (SE1) of the first transistor (T1) included in the third pixel circuit (PXC3) of another pixel (PX) adjacent in the first direction (DR1). The source electrode (SE1) of the first transistor (T1) included in the third pixel circuit (PXC3) may be adjacent to the source electrode (SE1) of the first transistor (T1) included in the first pixel circuit (PXC1) of another pixel (PX) adjacent in the first direction (DR1).

[0226] In one embodiment, the third and fourth transistors (T3, T4) of the second pixel circuit (PXC2) and the third and fourth transistors (T3, T4) of the third pixel circuit (PXC3) may be arranged adjacently in a first direction (DR1). For example, the third and fourth transistors (T3, T4) of the second pixel circuit (PXC2) and the third and fourth transistors (T3, T4) of the third pixel circuit (PXC3) may be arranged around the boundary between the second pixel circuit (PXC2) and the third pixel circuit (PXC3).

[0227] The first power line (VDL) shared by the second pixel circuit (PXC2) and the third pixel circuit (PXC3) may have a wider width in the central part of the second and third pixel circuits (PXC2, PXC3) so as to overlap with the first, third, and fourth transistors (T1, T3, T4) of the second and third pixel circuits (PXC2, PXC3). Additionally, the first power line (VDL) shared by the second pixel circuit (PXC2) and the third pixel circuit (PXC3) may be placed in the area between the second anode contact hole (ANH2) and the third anode contact hole (ANH3), and may extend in a second direction (DR2) between the second anode contact hole (ANH2) and the third anode contact hole (ANH3). For example, a first power line (VDL) shared by a second pixel circuit (PXC2) and a third pixel circuit (PXC3) may pass through an area between a second anode contact hole (ANH2) and a third anode contact hole (ANH3) (for example, the center between a second anode contact hole (ANH2) and a third anode contact hole (ANH3)).

[0228] Each of the first and second light emission control lines (EL1, EL2) may intersect or overlap with the fifth and sixth active layers (ACT5, ACT6) included in the fifth and sixth transistors (T5, T6) of the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3), respectively. However, the first and second light emission control lines (EL1, EL2) and the fifth and sixth gate electrodes (GE5, GE6) included in the fifth and sixth transistors (T5, T6) of the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3), respectively, may be disposed on different conductive layers. For example, the first and second light-emitting control lines (EL1, EL2) may be placed in the first source-drain conductive layer (SCDL1), and the fifth and sixth gate electrodes (GE5, GE6) may be placed in the first gate conductive layer (GCDL1).

[0229] The fifth and sixth gate electrodes (GE5, GE6) of the first pixel circuit (PXC1) can overlap with the first light emission control line (EL1) and can be electrically connected to the first light emission control line (EL1) through a tenth contact hole (CH10_1). For example, the tenth contact hole (CH10_1) of the first pixel circuit (PXC1) can be placed between the fifth gate electrode (GE5) and the sixth gate electrode (GE6) of the first pixel circuit (PXC1).

[0230] The fifth and sixth gate electrodes (GE5, GE6) of the second pixel circuit (PXC2) and the fifth and sixth gate electrodes (GE5, GE6) of the third pixel circuit (PXC3) can overlap with the second light emission control line (EL2) and can be electrically connected to the second light emission control line (EL2) through a single tenth contact hole (CH10_2). In one embodiment, the fifth and sixth gate electrodes (GE5, GE6) of the second pixel circuit (PXC2) and the fifth and sixth gate electrodes (GE5, GE6) of the third pixel circuit (PXC3) can be formed into a single integrally formed conductive pattern and can share a single tenth contact hole (CH10_2). For example, the 10th contact hole (CH10_2) of the second and third pixel circuits (PXC2, PXC3) may be placed between the 5th and 6th gate electrodes (GE5, GE6) of the second pixel circuit (PXC2) and the 5th and 6th gate electrodes (GE5, GE6) of the third pixel circuit (PXC3) (for example, between the 6th gate electrode (GE6) of the second pixel circuit (PXC2) and the 6th gate electrode (GE6) of the third pixel circuit (PXC3).

[0231] The fifth and eighth active layers (ACT5, ACT8) of each pixel circuit (PXC) may extend downward from one end of the first active layer (ACT1) of each pixel circuit (PXC). For example, the fifth and eighth active layers (ACT5, ACT8) of each of the first pixel circuit (PXC1) and the second pixel circuit (PXC2) may be formed from a portion of a semiconductor pattern extending downward from the left end of the first active layer (ACT1) of each of the first pixel circuit (PXC1) and the second pixel circuit (PXC2), and may be disposed in the lower left portion of each of the first pixel circuit (PXC1) and the second pixel circuit (PXC2). On the other hand, the fifth and eighth active layers (ACT5, ACT8) of the third pixel circuit (PXC3) may be formed from another part of a semiconductor pattern extending downward from the right end of the first active layer (ACT1) of the third pixel circuit (PXC3) and may be placed in the lower right part of the third pixel circuit (PXC3). A part of the semiconductor pattern extending from one end of the first active layer (ACT1) of each pixel circuit (PXC) (for example, the end connected to the source electrode (SE1)) to the fifth and eighth active layers (ACT5, ACT8) may have a roughly "U" or "Y" shape around the first and second light emission control lines (EL1, EL2) and may intersect or overlap with the first and second light emission control lines (EL1, EL2). Another part of the semiconductor pattern extending from the other end of the first active layer (ACT1) of each pixel circuit (PXC) (for example, the end connected to the drain electrode (DE1)) to the sixth active layer (ACT6) has a shape that extends approximately in the second direction (DR2) around the first and second light emission control lines (EL1, EL2) and may intersect or overlap with the first and second light emission control lines (EL1, EL2).As the first and second light-emitting control lines (EL1, EL2) are placed in a different conductive layer from the fifth and sixth gate electrodes (GE5, GE6), the semiconductor pattern of the first semiconductor layer (SCL1), which includes the first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8) of each pixel circuit (PXC), overlaps with both the first and second light-emitting control lines (EL1, EL2), but by adjusting the position of the fifth and sixth gate electrodes (GE5, GE6), the position where the fifth and sixth transistors (T5, T6) are formed in each subpixel (SPX) can be appropriately adjusted or selected.

[0232] The semiconductor pattern of the first semiconductor layer (SCL1) included in each of the pixel circuits (PXC) can be electrically connected to the second connection electrode (CNE2) in the vicinity of the first transistor (T1). Additionally, the semiconductor pattern of the first semiconductor layer (SCL1) included in each of the pixel circuits (PXC) can be electrically connected to the first power line (VDL) through the second connection electrode (CNE2). In one embodiment, the second connection electrode (CNE2) of each of the pixel circuits (PXC) can be adjacent to the first and second light emission control lines (EL1, EL2). Accordingly, the size of the semiconductor pattern of the first semiconductor layer (SCL1) can be reduced or minimized, and the design structure of the pixel circuits (PXC) can be improved.

[0233] In one embodiment, the second and third pixel circuits (PXC2, PXC3) may share a single second connecting electrode (CNE2). For example, the second connecting electrode (CNE2) of the second and third pixel circuits (PXC2, PXC3) may be formed as a single conductive pattern.

[0234] In one embodiment, the second connection electrode (CNE2) of the second and third pixel circuits (PXC2, PXC3) may overlap with the first transistors (T1) and the first power line (VDL) of the second and third pixel circuits (PXC2, PXC3) and may have a shape that extends in a first direction (DR1) in the area where the second and third pixel circuits (PXC2, PXC3) are placed. The second connection electrode (CNE2) of the second and third pixel circuits (PXC2, PXC3) may be electrically connected to the second electrode (SCE2) of the storage capacitor (Cst) and the horizontal power line (HVDL) through a sixth contact hole (CH6). Additionally, the second connection electrode (CNE2) of the second and third pixel circuits (PXC2, PXC3) can be commonly connected to the fifth active layer (ACT5) of the fifth transistor (T5) included in the second and third pixel circuits (PXC2, PXC3).

[0235] According to the embodiments described above, pixel circuits (PXC) of subpixels (SPX) can be efficiently arranged in each pixel area (PXA). For example, a second pixel circuit (PXC2) and a third pixel circuit (PXC3) can be arranged in a flip configuration, and data lines (DL) and power lines (PL), etc., can be appropriately arranged according to the configuration of the second pixel circuit (PXC2) and the third pixel circuit (PXC3). Accordingly, space can be secured for arranging additional wiring, etc. For example, there may be space for at least one wiring to be placed between the first pixel circuit (PXC1) included in each pixel (PX) and the second and third pixel circuits (PXC2, PXC3), and between the pixel circuits (PXC) of two adjacent pixels (PX) in the first direction (DR1) (for example, between the third pixel circuit (PXC3) of the pixel (PX) located on the left and the first pixel circuit (PXC1) of the pixel (PX) located on the right).

[0236] In one embodiment, a second power line (VSL) may be placed in the space. In one embodiment, the second power line (VSL) may be electrically connected to a common electrode (CE) within the display area (DA). For example, the second power line (VSL) may be electrically connected to a common electrode (CE) placed on a backplane layer (BPL) through a cathode contact hole (CDH) formed for at least one horizontal line. Accordingly, the second power line (VSL) and the common electrode (CE) may form a mesh-shaped power line in the display area (DA). Accordingly, the voltage drop of the second driving voltage (VSS) may be reduced or minimized, and the power consumption of the display device (10) may be reduced or improved. In some embodiments, as the voltage drop of the second driving voltage (VSS) is reduced, the width of the power bus line connected to the second power line (VSL) around the display area (DA) may be reduced. Accordingly, the width of the non-display area (NDA) can be reduced, or the space utilization rate and / or design structure of the non-display area (NDA) can be optimized.

[0237] In one embodiment, the size of the first transistor (T1) included in the first pixel circuit (PXC1) may be different from the size of the first transistor (T1) included in each of the second subpixel (SPX2) and the third subpixel (SPX3). For example, when the first subpixel (SPX1) is driven with a larger driving current (Ids) than the second subpixel (SPX2) and the third subpixel (SPX3) in response to the data voltage (Vdata) of each grayscale, the ratio (e.g., W1 / L1) of the channel width (e.g., W1 in FIG. 13) and channel length (e.g., L1 in FIG. 13) of the first transistor (T1) of the first subpixel (SPX1) may be larger than the ratio (e.g., W2 / L2) of the channel width (e.g., W2 in FIG. 13) and channel length (e.g., L2 in FIG. 13) of the second subpixel (SPX2) and the third subpixel (SPX3), respectively. For example, the size of the area (e.g., area) where the first active layer (ACT1) and the first gate electrode (GE1) overlap in each of the subpixels (SPX) can be adjusted to differentiate or optimize the size of the first transistor (T1) of each of the subpixels (SPX) according to the driving current (Ids) of each of the subpixels (SPX). Similarly, the ratio of the channel width to the channel length of the fifth transistor (T5) of the first subpixel (SPX1) may be greater than the ratio of the channel width to the channel length of the fifth transistor (T5) of each of the second subpixel (SPX2) and the third subpixel (SPX3), and the ratio of the channel width to the channel length of the sixth transistor (T6) of the first subpixel (SPX1) may be greater than the ratio of the channel width to the channel length of the sixth transistor (T6) of each of the second subpixel (SPX2) and the third subpixel (SPX3). Accordingly, the operation of the subpixels (SPX) can be stabilized, and the power consumption of the display device (10) can be improved.

[0238] FIG. 18 is a layout diagram showing a light-emitting element layer of a display panel according to one embodiment. For example, FIG. 18 shows light-emitting elements (LE), pixel electrodes (PXE), and a common electrode (CE) included in subpixels (SPX) in a part of a display area (DA) where two adjacent pixels (PX) are arranged in a second direction (DR2).

[0239] Referring to FIG. 18 in addition to FIG. 3 to 17, each of the subpixels (SPX) may include a pixel electrode (PXE) and a light-emitting element (LE) disposed in a light-emitting region (EA). In one embodiment, if the light-emitting element (LE) is a flip-chip type or lateral type micro LED, each of the subpixels (SPX) may further include a common electrode (CE) disposed on one side (e.g., a bottom surface or a top surface) of the light-emitting element (LE) together with the pixel electrode (PXE).

[0240] Although FIG. 18 shows that the size of the light-emitting regions (EA) of the subpixels (SPX) is the same, the embodiments are not limited thereto. For example, the size of the light-emitting regions (EA) of the subpixels (SPX) may be differentiated or optimized according to the light-emitting characteristics or target brightness of each light-emitting element (LE) and / or subpixel (SPX).

[0241] Additionally, although FIG. 18 illustrates that the pixel electrodes (PXE) are located only within each light-emitting region (EA), the embodiments are not limited thereto. For example, at least one portion of a pixel electrode (PXE) may be placed in a non-light-emitting region surrounding the light-emitting region (EA). For example, the size, shape, and / or placement direction of the pixel electrodes (PXE) may vary depending on the embodiments.

[0242] In one embodiment, the subpixels (SPX) of each pixel (PX) may be arranged in a first direction (DR1). Additionally, the subpixels (SPX) of each pixel (PX) may share a common electrode (CE). For example, the common electrode (CE) extends in the first direction (DR1) from each horizontal line of the display area (DA), and the subpixels (SPX) of the pixels (PX) arranged on the corresponding horizontal line may share a common electrode (CE).

[0243] The first subpixel (SPX1) may include a first pixel electrode (PXE1), a first light-emitting element (LE1), and a common electrode (CE) (or a part of the common electrode (CE)) disposed in a first light-emitting region (EA1). The first light-emitting region (EA1) may refer to the light-emitting region (EA) of the first subpixel (SPX1). The first pixel electrode (PXE1) may refer to the pixel electrode (PXE) of the first subpixel (SPX1). The first light-emitting element (LE1) may refer to the light-emitting element (LE) of the first subpixel (SPX1).

[0244] The second subpixel (SPX2) may include a second pixel electrode (PXE2), a second light-emitting element (LE2), and a common electrode (CE) disposed in a second light-emitting region (EA2). The second light-emitting region (EA2) may refer to the light-emitting region (EA) of the second subpixel (SPX2). The second pixel electrode (PXE2) may refer to the pixel electrode (PXE) of the second subpixel (SPX2). The second light-emitting element (LE2) may refer to the light-emitting element (LE) of the second subpixel (SPX2).

[0245] The third subpixel (SPX3) may include a third pixel electrode (PXE3), a third light-emitting element (LE3), and a common electrode (CE) disposed in a third light-emitting region (EA3). The third light-emitting region (EA3) may refer to the light-emitting region (EA) of the third subpixel (SPX3). The third pixel electrode (PXE3) may refer to the pixel electrode (PXE) of the third subpixel (SPX3). The third light-emitting element (LE3) may refer to the light-emitting element (LE) of the third subpixel (SPX3).

[0246] In each pixel (PX), the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may be arranged in a first direction (DR1). The first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may be spaced apart from the common electrode (CE) in a second direction (DR2).

[0247] Pixel electrodes (PXE) can be electrically connected to each pixel circuit (PXC) through each anode contact hole (ANH). For example, a first pixel electrode (PXE1) can be electrically connected to a first pixel circuit (PXC1) through a first anode contact hole (ANH1). A second pixel electrode (PXE2) can be electrically connected to a second pixel circuit (PXC2) through a second anode contact hole (ANH2). A third pixel electrode (PXE3) can be electrically connected to a third pixel circuit (PXC3) through a third anode contact hole (ANH3).

[0248] Light-emitting elements (LE) may be placed between each pixel electrode (PXE) and a common electrode (CE). For example, a first light-emitting element (LE1) may be placed on the first pixel electrode (PXE1) and the common electrode (CE), with one part of the first light-emitting element (LE1) overlapping with the first pixel electrode (PXE1) and another part of the first light-emitting element (LE1) overlapping with the common electrode (CE). The first light-emitting element (LE1) may be electrically connected between the first pixel electrode (PXE1) and the common electrode (CE). A second light-emitting element (LE2) may be placed on the second pixel electrode (PXE2) and the common electrode (CE), with one part of the second light-emitting element (LE2) overlapping with the second pixel electrode (PXE2) and another part of the second light-emitting element (LE2) overlapping with the common electrode (CE). The second light-emitting element (LE2) may be electrically connected between the second pixel electrode (PXE2) and the common electrode (CE). The third light-emitting element (LE3) is positioned on the third pixel electrode (PXE3) and the common electrode (CE), and a portion of the third light-emitting element (LE3) may overlap with the third pixel electrode (PXE3) and another portion of the third light-emitting element (LE3) may overlap with the common electrode (CE). The third light-emitting element (LE3) may be electrically connected between the third pixel electrode (PXE3) and the common electrode (CE).

[0249] Each of the light-emitting elements (LE) can emit light of a specific color (e.g., red light, green light, blue light, or white light). In one embodiment, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can emit light of different colors. For example, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can each emit light of a first color (e.g., red light), light of a second color (e.g., green light), and light of a third color (e.g., blue light).

[0250] In one embodiment, the light-emitting elements (LE) of at least two subpixels (SPX) may have different sizes. For example, the size of the first light-emitting element (LE1) may be larger than the size of the second light-emitting element (LE2) and the third light-emitting element (LE3), respectively.

[0251] In one embodiment, the light-emitting elements (LE) may have a differentiated or optimized size depending on the light-emitting efficiency of the light-emitting elements (LE). For example, depending on the light-emitting efficiency of each of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3), at least two of the light-emitting elements (LE) among the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may have different sizes. For example, based on the same size and shape, if the light-emitting efficiency of the first light-emitting element (LE1) is lower than the light-emitting efficiency of the second light-emitting element (LE2) and the third light-emitting element (LE3), the size of the first light-emitting element (LE1) may be larger than the size of the second light-emitting element (LE2) and the third light-emitting element (LE3). Accordingly, the light-emitting efficiency of the first light-emitting element (LE1) can be improved, and the difference in light-emitting efficiency between the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can be reduced or prevented.

[0252] In another embodiment, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may emit light of the same color. In this case, on at least one light-emitting element (LE) among the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3), at least one of a light conversion layer (e.g., a light conversion layer including wavelength conversion particles such as quantum dots) and a color filter may be disposed to convert the light emitted from the light-emitting element (LE) of the corresponding subpixel (SPX) into light corresponding to the light emission color of the corresponding subpixel (SPX). When the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) emit light of the same color, the sizes of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may be the same or different from each other. For example, depending on the light conversion efficiency of the light conversion layer, at least one of the size of the light-emitting elements (LE) of the subpixels (SPX) and the area of ​​the light-emitting regions (EA) of the subpixels (SPX) may be differentiated.

[0253] Meanwhile, FIG. 18 discloses an embodiment in which the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) each include a single light-emitting element (LE), but the embodiments are not limited thereto. For example, at least one of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may include a plurality of light-emitting elements (LE).

[0254] The common electrode (CE) can be electrically connected to the second power line (VSL). A second driving voltage (VSS) can be applied to the common electrode (CE) and the second power line (VSL).

[0255] In one embodiment, as illustrated in FIGS. 6 and FIGS. 9, etc., when the backplane layer (BPL) includes a second power line (VSL) disposed within the display area (DA), a common electrode (CE) may be electrically connected to the second power line (VSL) of the backplane layer (BPL) through a cathode contact hole (CDH) within the display area (DA). In one embodiment, the cathode contact hole (CDH) may be disposed in each pixel area (PXA), but is not limited thereto. A mesh-shaped power line may be formed in the display area (DA) by the second power line (VSL) of the backplane layer (BPL) and the common electrode (CE) of the light-emitting element layer (EDL). Accordingly, the voltage drop of the second driving voltage (VSS) can be reduced or minimized.

[0256] In one embodiment, the common electrode (CE) may extend to a non-display area (NDA) around a display area (DA) and may be electrically connected to a power bus line (e.g., a bus line to which a second driving voltage (VSS) is applied) placed in the non-display area (NDA). As the second power line (VSL) is placed inside the backplane layer (BPL) in the display area (DA), if the resistance of the second power line (VSL) is reduced, the width of the power bus line to which the second driving voltage (VSS) is applied may be reduced. Accordingly, the wiring area of ​​the non-display area (NDA) may be reduced.

[0257] FIG. 19 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the line X1-X1' of FIG. 9 and FIG. 18. For example, FIG. 19 shows an example of a cross-section of a display panel (100) corresponding to a part of a first subpixel (SPX1). In one embodiment, the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may have substantially the same or similar cross-sectional structures. For example, the corresponding circuit elements of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) (for example, the first transistors (T1) of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3)) are placed on substantially the same layer and may have substantially the same or similar cross-sectional structures.

[0258] FIG. 20 is a cross-sectional view showing the A2 region of FIG. 19 in detail. In one embodiment, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may have substantially the same or similar cross-sectional structures.

[0259] FIG. 21 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the X2-X2' line and the X3-X3' line of FIG. 9 and FIG. 18.

[0260] Referring to FIGS. 19 through 21 in addition to FIGS. 9 through 18, a display panel (100) may include a substrate (SUB) and a backplane layer (BPL) and an emitting element layer (EDL) disposed on the substrate (SUB). In one embodiment, the display panel (100) may further include a color filter layer (CFL) disposed on the emitting element layer (EDL). The backplane layer (BPL), the emitting element layer (EDL), and the color filter layer (CFL) may be sequentially disposed on the substrate (SUB) along a third direction (DR3).

[0261] The substrate (SUB) may be made of an insulating material such as glass or a polymer resin. If the substrate (SUB) is made of a polymer resin, it may be a stretchable flexible substrate. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0262] A substrate (SUB) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include pixel areas (PXA) where pixels (PX) are arranged. Each pixel area (PXA) may include light-emitting areas (EA) of sub-pixels (SPX).

[0263] The backplane layer (BPL) may include circuit elements included in the pixel circuits (PXC) of the subpixels (SPX) and wiring connected to the subpixels (SPX). In one embodiment, the backplane layer (BPL) may be formed entirely on one side of the substrate (SUB).

[0264] The backplane layer (BPL) may include at least one semiconductor layer, conductive layers, and insulating layers. In one embodiment, if the pixel circuits (PXC) include at least two types of pixel transistors (PXT) formed of different materials, the backplane layer (BPL) may include a plurality of semiconductor layers.

[0265] For example, the backplane layer (BPL) comprises a barrier layer (BR) (or buffer layer), a first semiconductor layer (SCL1) (e.g., a polycrystalline silicon semiconductor layer), a first insulating layer (INS1) (e.g., a first inorganic insulating layer), a first gate conductive layer (GCDL1) (or a first conductive layer), a second insulating layer (INS2) (e.g., a second inorganic insulating layer), a second gate conductive layer (GCDL2) (or a second conductive layer), a third insulating layer (INS3) (e.g., a third inorganic insulating layer), a second semiconductor layer (SCL2) (e.g., an oxide semiconductor layer), a fourth insulating layer (INS4) (e.g., a fourth inorganic insulating layer), a third gate conductive layer (GCDL3) (or a third conductive layer), a fifth insulating layer (INS5) (e.g., a fifth inorganic insulating layer), a first source-drain conductive layer (SCDL1) (or a fourth conductive layer), and a sixth It may include an insulating layer (INS6) (e.g., a first organic insulating layer), a second source-drain conductive layer (SCDL2) (or a fifth conductive layer) and a seventh insulating layer (INS7) (e.g., a second organic insulating layer).

[0266] A barrier layer (BR) may be disposed on a substrate (SUB). The barrier layer (BR) can protect circuit elements of the backplane layer (BPL) and light-emitting elements (LE) on the backplane layer (BPL) from moisture penetrating through the substrate (SUB), which is susceptible to moisture permeability. In one embodiment, the barrier layer (BR) may be composed of a plurality of inorganic films.

[0267] Circuit elements of the backplane layer (BPL) may be disposed on the barrier layer (BR). For example, on the barrier layer (BR), pixel transistors (PXT), storage capacitors (Cst), and boosting capacitors (Cbst) of each pixel circuit (PXC) included in the corresponding pixel (PX) may be disposed in each pixel region (PXA). Additionally, wiring of the backplane layer (BPL) may be disposed on the barrier layer (BR). For example, a write scan line (GWL), an initialization scan line (GIL), a control scan line (GCL), a bias scan line (GBL), a first light emission control line (EL1), a second light emission control line (EL2), a first data line (DLr), a second data line (DLg), a third data line (DLb), a first power line (VDL), a second power line (VSL), a third power line (VIL), a fourth power line (VAIL), a fifth power line (VOBL), and a horizontal power line (HVDL) may be arranged on the barrier layer (BR).

[0268] In one embodiment, each pixel circuit (PXC) may include a first type of transistor and a second type of transistor. The first type of transistor and the second type of transistor may be placed on different layers within the backplane layer (BPL).

[0269] For example, each pixel circuit (PXC) may include first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) of P-type and third and fourth transistors (T3, T4) of N-type. The first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8) of the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) and the third and fourth active layers (ACT3, ACT4) of the third and fourth transistors (T3, T4) may be disposed on different semiconductor layers included in the backplane layer (BPL). In one embodiment, the first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8) of the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) and the third and fourth active layers (ACT3, ACT4) of the third and fourth transistors (T3, T4) may include different semiconductor materials, but are not limited thereto. Additionally, the first, second, fifth, sixth, seventh, and eighth gate electrodes (GE1, GE2, GE5, GE6, GE7, GE8) of the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) and the third and fourth active layers (ACT3, ACT4) of the third and fourth transistors (T3, T4) may be placed on different conductive layers included in the backplane layer (BPL).

[0270] Specifically, a first semiconductor layer (SCL1) may be disposed on the barrier layer (BR). The first semiconductor layer (SCL1) may include an active layer for each of the first type of transistors. For example, the first semiconductor layer (SCL1) may include the first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8) of the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8). FIGS. 19 and 21 show only some of the pixel transistors (PXT) included in each pixel circuit (PXC), and FIGS. 19 and 21 show the first active layer (ACT1) and the sixth active layer (ACT6) among the active layers included in the first semiconductor layer (SCL1). In one embodiment, the first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8) of each pixel circuit (PXC) may be integrally formed using the same semiconductor material. For example, as shown in FIGS. 9 to 17, the first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8) of each of the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3) may be formed as a single semiconductor pattern connected to each other.

[0271] Patterns of the first semiconductor layer (SCL1) (for example, the first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8)) may include a first semiconductor material. In one embodiment, the first semiconductor material may be polycrystalline silicon (for example, low-temperature polycrystalline silicon), but is not limited thereto. For example, the first semiconductor material may be an oxide semiconductor (for example, at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium-gallium oxide (IGO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), indium-tin-gallium-zinc oxide (ITGZO), or other oxide semiconductors) or single-crystal silicon.

[0272] A first insulating layer (INS1) may be disposed on the first semiconductor layer (SCL1). The first insulating layer (INS1) may comprise at least one insulating material (e.g., silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), titanium oxide (TiOx), aluminum oxide (AlOx), or other inorganic insulating material) and may be composed of a single layer or multiple layers.

[0273] A first gate conductive layer (GCDL1) may be disposed on the first insulating layer (INS1). The first gate conductive layer (GCDL1) may include the gate electrodes of each of the first type of transistors. For example, the first gate conductive layer (GCDL1) may include the first, second, fifth, sixth, seventh, and eighth gate electrodes (GE1, GE2, GE5, GE6, GE7, GE8) of the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8). The first gate conductive layer (GCDL1) may further include at least one conductive pattern and / or wiring. For example, the first gate conductive layer (GCDL1) may further include a first electrode (SCE1) of a storage capacitor (Cst), a first electrode (BCE1) of a boosting capacitor (Cbst), a write scan line (GWL), and a bias scan line (GBL). In FIGS. 19 and 21, among the patterns of the first gate conductive layer (GCDL1), the first gate electrode (GE1), the sixth gate electrode (GE6), the first electrode (SCE1) of the storage capacitor (Cst), the first electrode (BCE1) of the boosting capacitor (Cbst), and the write scan line (GWL) are shown.

[0274] In one embodiment, the first gate electrode (GE1) of each pixel circuit (PXC) and the first electrode (SCE1) of the storage capacitor (Cst) are formed integrally, and the second gate electrode (GE2), the first electrode (BCE1) of the boosting capacitor (Cbst), and the write scan line (GWL) (for example, the write scan line (GWL) connected to the subpixels (SPX) of the corresponding horizontal line) may be formed integrally. Additionally, the seventh gate electrode (GE7), the eighth gate electrode (GE8), and the bias scan line (GBL) (for example, the bias scan line (GBL) connected to the subpixels (SPX) of the corresponding horizontal line) may be formed integrally.

[0275] Patterns of the first gate conductive layer (GCDL1) (for example, first, second, fifth, sixth, seventh, and eighth gate electrodes (GE1, GE2, GE5, GE6, GE7, GE8), the first electrode (SCE1) of the storage capacitor (Cst), the first electrode (BCE1) of the boosting capacitor (Cbst), the write scan line (GWL) and the bias scan line (GBL)) may include the same conductive material.

[0276] A second insulating layer (INS2) may be disposed on the first gate conductive layer (GCDL1). The second insulating layer (INS2) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0277] A second gate conductive layer (GCDL2) may be disposed on the second insulating layer (INS2). The second gate conductive layer (GCDL2) may include a second electrode (SCE2) of a storage capacitor (Cst). The first electrode (SCE1) and the second electrode (SCE2) of the storage capacitor (Cst) may overlap with the first insulating layer (INS1) in between. The second electrode (SCE2) of the storage capacitor (Cst) may be open at the portion where the first electrode (SCE1) of the storage capacitor (Cst) is connected to the first connecting electrode (CNE1) (for example, the fourth contact hole (CH4) and its surroundings). The second gate conductive layer (GCDL2) may further include at least one conductive pattern and / or wiring. For example, the second gate conductive layer (GCDL2) may further include a first light-blocking pattern (LBP1), a second light-blocking pattern (LBP2), a horizontal power line (HVDL), and a fourth power line (VAIL). In FIGS. 19 and 21, among the patterns of the second gate conductive layer (GCDL2), the second electrode (SCE2) of the storage capacitor (Cst), the first light-blocking pattern (LBP1), the second light-blocking pattern (LBP2), and the fourth power line (VAIL) are illustrated.

[0278] In one embodiment, the first light-blocking patterns (LBP1) of the subpixels (SPX) arranged in each horizontal line may be formed integrally, and the second light-blocking patterns (LBP2) of the subpixels (SPX) arranged in each horizontal line may be formed integrally. Additionally, the second electrodes (SCE2) of the storage capacitors (Cst) of the subpixels (SPX) arranged in each horizontal line and the horizontal power line (HVDL) may be formed integrally.

[0279] Patterns of the second gate conductive layer (GCDL2) (for example, the second electrode (SCE2) of the storage capacitor (Cst), the first light-blocking pattern (LBP1), the second light-blocking pattern (LBP2), the horizontal power line (HVDL), and the fourth power line (VAIL)) may include the same conductive material.

[0280] A third insulating layer (INS3) may be disposed on the second gate conductive layer (GCDL2). The third insulating layer (INS3) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0281] A second semiconductor layer (SCL2) may be disposed on the third insulating layer (INS3). The second semiconductor layer (SCL2) may include the active layer of each of the second type of transistors. For example, the second semiconductor layer (SCL2) may include the third and fourth active layers (ACT3, ACT4) of the third and fourth transistors (T3, T4). In one embodiment, the third and fourth active layers (ACT3, ACT4) of each pixel circuit (PXC) may be integrally formed using the same semiconductor material. For example, as shown in FIGS. 9 to 13, the third and fourth active layers (ACT3, ACT4) of the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3), respectively, may be formed as a single semiconductor pattern connected to each other. In one embodiment, the second semiconductor layer (SCL2) further includes a second electrode (BCE2) of a boosting capacitor (Cbst), and the second electrode (BCE2) of the boosting capacitor (Cbst) may be formed integrally with the third and fourth active layers (ACT3, ACT4).

[0282] Patterns of the second semiconductor layer (SCL2) (for example, the third and fourth active layers (ACT3, ACT4), the second electrode (BCE2) of the boosting capacitor (Cbst)) may include a second semiconductor material. In one embodiment, the second semiconductor material may be an oxide semiconductor, but is not limited thereto. For example, the second semiconductor material may be polycrystalline silicon or single-crystal silicon.

[0283] A fourth insulating layer (INS4) may be disposed on the second semiconductor layer (SCL2). The fourth insulating layer (INS4) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0284] A third gate conductive layer (GCDL3) may be disposed on the fourth insulating layer (INS4). The third gate conductive layer (GCDL3) may include the gate electrodes of each of the second type of transistors. For example, the third gate conductive layer (GCDL3) may include the third and fourth gate electrodes (GE3, GE4) of the third and fourth transistors (T3, T4). The third gate conductive layer (GCDL3) may further include at least one conductive pattern and / or wiring. For example, the third gate conductive layer (GCDL3) may further include an initialization scan line (GIL), a control scan line (GCL), and a fifth power line (VOBL). In FIGS. 19 and 21, the third gate electrode (GE3) and the fourth gate electrode (GE4) among the patterns of the third gate conductive layer (GCDL3) are illustrated.

[0285] In one embodiment, the third gate electrode (GE3) and the control scan line (GCL) (for example, the control scan line (GCL) connected to the subpixels (SPX) of the corresponding horizontal line) may be formed integrally. Additionally, the fourth gate electrode (GE4) and the initialization scan line (GIL) (for example, the initialization scan line (GIL) connected to the subpixels (SPX) of the corresponding horizontal line) may be formed integrally.

[0286] Patterns of the third gate conductive layer (GCDL3) (for example, third and fourth gate electrodes (GE3, GE4), initialization scan line (GIL), control scan line (GCL) and fifth power line (VOBL)) may include the same conductive material.

[0287] A fifth insulating layer (INS5) may be disposed on the third gate conductive layer (GCDL3). The fifth insulating layer (INS5) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0288] A first source-drain conductive layer (SCDL1) may be disposed on the fifth insulating layer (INS5). The first source-drain conductive layer (SCDL1) may include at least one electrode, a conductive pattern, and / or wiring. For example, the first source-drain conductive layer (SCDL1) may include source and drain electrodes (SE1, DE1) of the first transistor (T1), first, second, third, fourth, sixth, and seventh connecting electrodes (CNE1, CNE2, CNE3, CNE4, CNE6, CNE7), first and second light emission control lines (EL1, EL2), and a third power line (VIL). In FIGS. 19 and 21, the source and drain electrodes (SE1, DE1) of the first transistor (T1), the first and fourth connection electrodes (CNE1, CNE4), the first and second light emission control lines (EL1, EL2) and the third power line (VIL) are shown among the patterns of the first source-drain conductive layer (SCDL1).

[0289] Patterns of the first source-drain conductive layer (SCDL1) (for example, source and drain electrodes (SE1, DE1) of the first transistor (T1), first, second, third, fourth, sixth, and seventh connecting electrodes (CNE1, CNE2, CNE3, CNE4, CNE6, CNE7), first and second light emission control lines (EL1, EL2) and third power line (VIL)) may include the same conductive material.

[0290] A sixth insulating layer (INS6) may be disposed on the first source-drain conductive layer (SCDL1). The sixth insulating layer (INS6) may comprise at least one insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating material) and may be composed of a single layer or multiple layers.

[0291] A second source-drain conductive layer (SCDL2) may be disposed on the sixth insulating layer (INS6). The second source-drain conductive layer (SCDL2) may include at least one electrode, a conductive pattern, and / or wiring. For example, the second source-drain conductive layer (SCDL2) may include a fifth connection electrode (CNE5), first, second, and third data lines (DLr, DLg, DLb), and first and second power lines (VDL, VSL). In FIGS. 19 and 21, the fifth connection electrode (CNE5), the first power line (VDL), and the second power line (VSL) are shown among the patterns of the second source-drain conductive layer (SCDL2).

[0292] Patterns of the second source-drain conductive layer (SCDL2) (for example, the fifth connecting electrode (CNE5), the first, second, and third data lines (DLr, DLg, DLb), and the first and second power lines (VDL, VSL)) may include the same conductive material.

[0293] A seventh insulating layer (INS7) may be disposed on the second source-drain conductive layer (SCDL2). The seventh insulating layer (INS7) comprises at least one insulating material (e.g., an organic insulating material) and may be composed of a single layer or multiple layers.

[0294] Patterns included in each of the conductive layers of the backplane layer (BPL) may include at least one conductive material. For example, electrodes, conductive patterns, and / or wiring included in each of the first gate conductive layer (GCDL1), the second gate conductive layer (GCDL2), the third gate conductive layer (GCDL3), the first source-drain conductive layer (SCDL1), and the second source-drain conductive layer (SCDL2) may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials. In one embodiment, electrodes, conductive patterns, and / or wiring disposed in the same conductive layer may be formed simultaneously using the same conductive material. At least two of the conductive layers of the backplane layer (BPL) may contain the same conductive material or different conductive materials.

[0295] In one embodiment, the patterns included in each of the conductive layers of the backplane layer (BPL) may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns, and / or wirings included in each of the first gate conductive layer (GCDL1), the second gate conductive layer (GCDL2), the third gate conductive layer (GCDL3), the first source-drain conductive layer (SCDL1), and the second source-drain conductive layer (SCDL2) may have a single-layer or multi-layer structure. At least two of the conductive layers of the backplane layer (BPL) may have the same cross-sectional structure or different cross-sectional structures.

[0296] In one embodiment, the patterns of the second source-drain conductive layer (SCDL2) may comprise a metal (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, or an alloy thereof) and may have a single-layer or multi-layer structure. For example, the electrodes, conductive patterns, and / or wiring included in the second source-drain conductive layer (SCDL2) may be low-resistance patterns formed with a triple-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). Alternatively, the patterns of the second source-drain conductive layer (SCDL2) may comprise other low-resistance materials and / or structures. When the resistance of the patterns included in the second source-drain conductive layer (SCDL2) is reduced or minimized, the resistance of the first power line (VDL) and the second power line (VSL), through which the driving current (Ids) of each subpixel (SPX) flows, can be reduced or minimized. Accordingly, the image quality of the display device (10) can be standardized and power consumption improved.

[0297] A light-emitting element layer (EDL) may be disposed on the seventh insulating layer (INS7). The light-emitting element layer (EDL) may include pixel electrodes (PXE), light-emitting elements (LE), and a common electrode (CE) included in subpixels (SPX). Additionally, the light-emitting element layer (EDL) may further include insulating layers. In one embodiment, the insulating layers of the light-emitting element layer (EDL) may include eighth, ninth, and tenth insulating layers (INS8, INS9, INS10), a capping layer (CPL), and a first overcoat layer (OC1).

[0298] A pixel electrode layer including pixel electrodes (PXE) of subpixels (SPX) may be disposed on the seventh insulating layer (INS7). For example, the pixel electrode layer may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3). In one embodiment, the light-emitting element (LE) may be a flip-chip type micro LED. A flip-chip type micro LED refers to an LED having first and second contact electrodes (CTE1, CTE2) formed on one side (e.g., the bottom side) of the light-emitting element (LE). When the light-emitting element (LE) is a flip-chip type micro LED, the pixel electrode layer may further include a common electrode (CE). For example, the pixel electrodes (PXE) of subpixels (SPX) and the common electrode (CE) may be disposed on the same layer and may be formed simultaneously using the same conductive material.

[0299] The first pixel electrode (PXE1) of the first subpixel (SPX1) can be electrically connected to the fifth connecting electrode (CNE5) of the first subpixel (SPX1) through a first anode contact hole (ANH1) (for example, a contact hole that penetrates the seventh insulating layer (INS7) and exposes the fifth connecting electrode (CNE5) of the first subpixel (SPX1). The second pixel electrode (PXE2) of the second subpixel (SPX2) can be electrically connected to the fifth connecting electrode (CNE5) of the second subpixel (SPX2) through a second anode contact hole (ANH2) (for example, a contact hole that penetrates the seventh insulating layer (INS7) and exposes the fifth connecting electrode (CNE5) of the second subpixel (SPX2). The third pixel electrode (PXE3) of the third subpixel (SPX3) can be electrically connected to the fifth connecting electrode (CNE5) of the third subpixel (SPX3) through a third anode contact hole (ANH3) (for example, a contact hole that penetrates the seventh insulating layer (INS7) to expose the fifth connecting electrode (CNE5) of the third subpixel (SPX3). Accordingly, the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) are electrically connected to the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3), respectively, and the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3) can control the voltage applied to the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3).

[0300] A common electrode (CE) shared by the first, second, and third subpixels (SPX1, SPX2, SPX3) can be electrically connected to the second power line (VSL) of the backplane layer (BPL) through a cathode contact hole (CDH) (for example, a contact hole that penetrates the seventh insulating layer (INS7) to expose the second power line (VSL) of the backplane layer (BPL). Accordingly, a second driving voltage (VSS) applied to the second power line (VSL) can be transmitted to the common electrode (CE).

[0301] In one embodiment, the patterns of the pixel electrode layer (e.g., pixel electrodes (PXE) and common electrode (CE)) may include the same conductive material. In one embodiment, the patterns of the pixel electrode layer (e.g., pixel electrodes (PXE) and common electrode (CE)) may include the same conductive material. In one embodiment, the patterns of the pixel electrode layer may include a metal (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, or an alloy thereof) and may have a single-layer or multi-layer structure. For example, the patterns of the pixel electrode layer may be low-resistance patterns formed with a triple-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). Alternatively, the patterns of the pixel electrode layer may include other low-resistance materials (e.g., copper (Cu)) and / or structures. When the resistance of the patterns included in the pixel electrode layer is reduced or minimized, the first driving voltage (VDD) and the second driving voltage (VSS) can be stably transmitted to the light-emitting elements (LE) of the subpixels (SPX).

[0302] An eighth insulating layer (INS8) may be disposed on the pixel electrodes (PXE) and the common electrode (CE). The eighth insulating layer (INS8) serves to temporarily fix or adhere the light-emitting elements (LE) to prevent them from tilting or falling over during the process of transferring the light-emitting elements (LE) to the display panel (100). For example, the eighth insulating layer (INS8) may be a film for temporarily adhering the light-emitting elements (LE) to each pixel electrode (PXE) and the common electrode (CE). To facilitate temporary adhesion, the thickness of the eighth insulating layer (INS8) may be greater than the thickness of each pixel electrode (PXE) and the common electrode (CE), and greater than the thickness of each of the first and second contact electrodes (CTE1, CTE2) of the light-emitting elements (LE).

[0303] Although FIGS. 19 to 21 illustrate that the eighth insulating layer (INS8) is placed over the entire display area (DA), the embodiments are not limited thereto. For example, the eighth insulating layer (INS8) may be placed only on a portion of the pixel electrodes (PXE) and common electrode (CE) that overlap with the light-emitting elements (LE), and may expose other portions of the pixel electrodes (PXE) and common electrode (CE).

[0304] The eighth insulating layer (INS8) may include at least one insulating material, for example, an organic insulating material. For example, the eighth insulating layer (INS8) may be a photosensitive organic film such as a photoresist. Alternatively, the eighth insulating layer (INS8) may be formed from an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0305] Light-emitting elements (LE) may be disposed on the eighth insulating layer (INS8). For example, a first light-emitting element (LE1) may be disposed on the first pixel electrode (PXE1) and the common electrode (CE) of a first subpixel (SPX1). A second light-emitting element (LE2) may be disposed on the second pixel electrode (PXE2) and the common electrode (CE) of a second subpixel (SPX2). A third light-emitting element (LE3) may be disposed on the third pixel electrode (PXE3) and the common electrode (CE) of a third subpixel (SPX3).

[0306] In one embodiment, each of the light-emitting elements (LE) may be a micro LED comprising an inorganic material. For example, each of the light-emitting elements (LE) may be formed of an inorganic material such as gallium nitride (GaN), and the length of the first direction (DR1), the length of the second direction (DR2), and the length of the third direction (DR3) of each of the light-emitting elements (LE) may each be several μm to several hundred μm. For example, the length of the first direction (DR1), the length of the second direction (DR2), and the length of the third direction (DR3) of each of the light-emitting elements (LE) may each be approximately 100 μm or less.

[0307] Light-emitting elements (LE) can be formed by growing on a semiconductor substrate, such as a silicon substrate or a sapphire substrate. Light-emitting elements (LE) can be transferred directly from the semiconductor substrate onto the pixel electrodes (PXE) and common electrode (CE) of the display panel (100). Alternatively, light-emitting elements (LE) can be transferred onto the pixel electrodes (PXE) and common electrode (CE) of the display panel (100) via an electrostatic method using an electrostatic head or a stamping method using an elastic polymer material, such as PDMS or silicon, as a transfer substrate.

[0308] The light-emitting element (LE) may include a conductive layer (E1), a semiconductor stack (STC), contact electrodes (CTE1, CTE2), and a protective film (PRL). The semiconductor stack (STC) may include a first semiconductor layer (SEM1), an active layer (MQW) (e.g., a light-emitting layer), and a second semiconductor layer (SEM2) arranged sequentially in a third direction (DR3). In one embodiment, the semiconductor stack (STC) may further include a third semiconductor layer (SEM3) on the second semiconductor layer (SEM2).

[0309] A conductive layer (E1) may be disposed on the lower surface of a first semiconductor layer (SEM1). Although FIG. 20 illustrates a case where the conductive layer (E1) covers the entire lower surface of the first semiconductor layer (SEM1), the embodiments of this specification are not limited thereto. As an example, the conductive layer (E1) may be disposed on a part of the lower surface of the first semiconductor layer (SEM1). The conductive layer (E1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a transparent conductive material such as a metal oxide.

[0310] The first semiconductor layer (SEM1) can be placed on the conductive layer (E1). The first semiconductor layer (SEM1) may be made of a semiconductor material layer doped with a first conductive type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc., for example, gallium nitride (GaN).

[0311] An active layer (MQW) may be disposed on a first semiconductor layer (SEM1). The active layer (MQW) may include the same semiconductor material as the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2). For example, if the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2) include gallium nitride (GaN), the active layer (MQW) may also include gallium nitride (GaN). For example, the active layer (MQW) may include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). The active layer (MQW) may emit light by the recombination of electron-hole pairs according to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0312] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer (MQW) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, or it may include different Group 3 to Group 5 semiconductor materials depending on the wavelength of the emitted light.

[0313] When the active layer (MQW) contains indium gallium nitride (InGaN), the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer shifts to a red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer shifts to a blue wavelength band. For example, the content of indium (In) in the active layer (MQW) of a light-emitting device (LE) that emits a third color of light (blue light) may be approximately 10 wt% to 20 wt%.

[0314] The second semiconductor layer (SEM2) can be disposed on the active layer (MQW). The second semiconductor layer (SEM2) may be a semiconductor material layer doped with a second conductivity type dopant, such as silicon (Si), germanium (Ge), tin (Sn), etc., for example, gallium nitride (GaN).

[0315] A third semiconductor layer (SEM3) may be disposed on a second semiconductor layer (SEM2). The third semiconductor layer (SEM3) is a semiconductor material layer in which the n-type dopant is lower than a predetermined threshold value and may be referred to as an un-doped semiconductor layer. For example, the third semiconductor layer (SEM3) may be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), or indium nitride (InN), in which the n-type dopant is lower than a predetermined threshold value.

[0316] An electron blocking layer may be placed between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer designed to suppress or prevent too many electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be AlGaN or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0317] A superlattice layer may be disposed between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of InGaN or GaN. The superlattice layer may be omitted.

[0318] A protective film (PRL) may be disposed on the side of the first semiconductor layer (SEM1), the side of the active layer (MQW), and the side of the second semiconductor layer (SEM2). The protective film (PRL) may be a film for protecting the side of the light-emitting element (LE). The protective film (PRL) may be formed of an inorganic material, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), titanium oxide (TiOx), aluminum oxide (AlOx), or other inorganic insulating material.

[0319] FIG. 20 illustrates a protective film (PRL) disposed on the sides of the first semiconductor layer (SEM1), the sides of the active layer (MQW), and the sides of the second semiconductor layer (SEM2) of the semiconductor stack (STC), but not on the sides of the third semiconductor layer (SEM3), but embodiments are not limited thereto. In one example, the protective film (PRL) may be disposed on the sides of the first semiconductor layer (SEM1), the sides of the active layer (MQW), the sides of the second semiconductor layer (SEM2), and the sides of the third semiconductor layer (SEM3) of the semiconductor stack (STC).

[0320] A hole (LEH) may be formed that penetrates the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the light-emitting element (LE) to expose the second semiconductor layer (SEM2). The hole (LEH) may have a circular planar shape, but the embodiments of this specification are not limited thereto. As an example, the hole (LEH) may have a polygonal planar shape such as an ellipse or a square.

[0321] A protective film (PRL) may be disposed on the sidewall of the conductive layer (E1) exposed in the hole (LEH), the sidewall of the first semiconductor layer (SEM1), and the sidewall of the active layer (MQW). The protective film (PRL) may not cover the second semiconductor layer (SEM2) in the hole (LEH). Accordingly, the second semiconductor layer (SEM2) may be exposed without being covered by the protective film (PRL).

[0322] The first contact electrode (CTE1) may be disposed on at least one side of the semiconductor stack (STC) and on at least one side of the conductive layer (E1) and on the lower surface. The first contact electrode (CTE1) may be disposed on the lower surface of the conductive layer (E1) that is exposed and not covered by a protective film (PRL). Therefore, the first contact electrode (CTE1) may be electrically connected to the conductive layer (E1).

[0323] The second contact electrode (CTE2) may be disposed on at least one side of the semiconductor stack (STC), at least one side of the conductive layer (E1), and on the lower surface. In this case, while the first contact electrode (CTE1) is disposed on the first side of the semiconductor stack (STC) and the first side of the conductive layer (E1), the second contact electrode (CTE2) may be disposed on the second side of the semiconductor stack (STC) and the second side of the conductive layer (E1).

[0324] The second contact electrode (CTE2) can be placed on a protective film (PRL) placed in the hole (LEH) and on a second semiconductor layer (SEM2) exposed in the hole (LEH) without being covered by the protective film (PRL). Therefore, the second contact electrode (CTE2) can be electrically connected to the second semiconductor layer (SEM2) in the hole (LEH).

[0325] FIGS. 19 and 20 illustrate that the first contact electrode (CTE1) and the second contact electrode (CTE2) of each of the light-emitting elements (LE) are disposed on the eighth insulating layer (INS8), but the embodiments of this specification are not limited thereto. As an example, the eighth insulating layer (INS8) may be disposed on the lower surface and part of the side of the first contact electrode (CTE1) of each of the light-emitting elements (LE) and on the lower surface and part of the side of the second contact electrode (CTE2). Alternatively, the eighth insulating layer (INS8) may be disposed on the sides of the conductive layer (E1) of each of the light-emitting elements (LE). Alternatively, the eighth insulating layer (INS8) may be disposed on the sides of the first semiconductor layer (SEM1), the sides of the active layer (MQW), and the sides of the second semiconductor layer (SEM2) of each of the light-emitting elements (LE). In this case, the eighth insulating layer (INS8) may be disposed on a part of each of the sides of the second semiconductor layer (SEM2).

[0326] Each of the first contact electrode (CTE1) and the second contact electrode (CTE2) may be placed on three sides of the semiconductor stack (STC). For example, if the semiconductor stack (STC) includes first to fourth sides, the first contact electrode (CTE1) may be placed on the first side, the second side, and the third side, and the second contact electrode (CTE2) may be placed on the second side, the third side, and the fourth side.

[0327] Each of the first contact electrode (CTE1) and the second contact electrode (CTE2) may include at least one conductive material, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). In one embodiment, the first contact electrode (CTE1) and the second contact electrode (CTE2) may be formed with a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of ITO (Indium Tin Oxide), silver (Ag), and ITO (Indium Tin Oxide) to increase reflectivity.

[0328] When the first contact electrode (CTE1) and the second contact electrode (CTE2) are each formed of a metal with high reflectivity, light emitted from the active layer (MQW) of the light-emitting element (LE) that travels in the lateral direction of the light-emitting element (LE) can be reflected by the first contact electrode (CTE1) and the second contact electrode (CTE2) and emitted to the upper surface of the light-emitting element (LE). Therefore, since the loss of light from the light-emitting element (LE) can be reduced, the light efficiency of the light-emitting element (LE) can be increased. To increase the light efficiency of the light-emitting element (LE), the first contact electrode (CTE1) and the second contact electrode (CTE2) can be arranged to cover most of the side of the semiconductor stack (STC).

[0329] The first bridge electrode (BE1) (or the eighth connecting electrode) connects the first contact electrode (CTE1) of the light-emitting element (LE) to each pixel electrode (PXE). For example, the first bridge electrode (BE1) of the first subpixel (SPX1) can connect the first contact electrode (CTE1) of the first light-emitting element (LE1) to the first pixel electrode (PXE1). Similarly, the first bridge electrode (BE1) of the second subpixel (SPX2) can connect the first contact electrode (CTE1) of the second light-emitting element (LE2) to the second pixel electrode (PXE2), and the first bridge electrode (BE1) of the third subpixel (SPX3) can connect the first contact electrode (CTE1) of the third light-emitting element (LE3) to the third pixel electrode (PXE3).

[0330] The first bridge electrode (BE1) can be connected to each exposed pixel electrode (PXE) through a first connection hole (BH1) penetrating the eighth insulating layer (INS8). Additionally, the first bridge electrode (BE1) can be placed on the upper surface of the eighth insulating layer (INS8) and on the first contact electrode (CTE1) of the light-emitting element (LE). In another embodiment, if the eighth insulating layer (INS8) is placed only on a portion of the pixel electrode (PXE) that overlaps with the light-emitting element (LE), the first connection hole (BH1) may be unnecessary. For example, the first bridge electrode (BE1) may be placed directly on the pixel electrode (PXE) exposed around the light-emitting element (LE).

[0331] The second bridge electrode (BE2) (or the ninth connecting electrode) connects the second contact electrode (CTE2) of the light-emitting element (LE) to the common electrode (CE). For example, the second bridge electrode (BE2) of the first subpixel (SPX1) can connect the second contact electrode (CTE2) of the first light-emitting element (LE1) to the common electrode (CE). Similarly, the second bridge electrode (BE2) of the second subpixel (SPX2) can connect the second contact electrode (CTE2) of the second light-emitting element (LE2) to the common electrode (CE), and the second bridge electrode (BE2) of the third subpixel (SPX3) can connect the second contact electrode (CTE2) of the third light-emitting element (LE3) to the common electrode (CE). In another embodiment, if the eighth insulating layer (INS8) is placed only on a portion of the common electrode (CE) that overlaps with the light-emitting element (LE), the second connecting hole (BH2) may be unnecessary. For example, the second bridge electrode (BE2) may be placed directly on the common electrode (CE) exposed around the light-emitting element (LE).

[0332] The second bridge electrode (BE2) can be connected to a common electrode (CE) exposed through a second connection hole (BH2) penetrating the eighth insulating layer (INS8). Additionally, the second bridge electrode (BE2) can be placed on the upper surface of the eighth insulating layer (INS8) and on the second contact electrode (CTE2).

[0333] Each of the first bridge electrode (BE1) and the second bridge electrode (BE2) may comprise at least one conductive material, for example, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, each of the first bridge electrode (BE1) and the second bridge electrode (BE2) may be made of a transparent conductive material such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide) (for example, Transparent Conductive Oxide (TCO)).

[0334] When the first bridge electrode (BE1) and the second bridge electrode (BE2) are each made of a highly reflective metallic material such as aluminum (Al), light emitted from the active layer (MQW) of the light-emitting element (LE) that travels in the lateral direction of the light-emitting element (LE) can be reflected by the connecting electrodes (BE) and travel in the upper direction of the light-emitting element (LE). Accordingly, the loss of light from the light-emitting element (LE) can be reduced, thereby increasing the light efficiency of the light-emitting element (LE).

[0335] As shown in FIGS. 19 and 20, the conductive layer (E1) of the light-emitting element (LE) can be electrically connected to each pixel electrode (PXE) through a first contact electrode (CTE1) and a first bridge electrode (BE1). Additionally, the second semiconductor layer (SEM2) of the light-emitting element (LE) can be electrically connected to a common electrode (CE) through a second contact electrode (CTE2) and a second bridge electrode (BE2) formed in a hole (LEH). Meanwhile, the pixel electrodes (PXE) may be referred to as the anode electrode or the first electrode, and the common electrode (CE) may also be referred to as the cathode electrode or the second electrode.

[0336] The ninth insulating layer (INS9) may be disposed on the eighth insulating layer (INS8). The ninth insulating layer (INS9) may be disposed to cover a portion of the side of the light-emitting elements (LE). Additionally, the ninth insulating layer (INS9) may be disposed to cover the first and second bridge electrodes (BE1, BE2), but at least a portion of the first and second bridge electrodes (BE1, BE2) may be exposed and not covered by the ninth insulating layer (INS9).

[0337] The 10th insulating layer (INS10) may be disposed on the 9th insulating layer (INS9). The 10th insulating layer (INS10) may be disposed to cover a portion of the side of each of the light-emitting elements (LE). The 10th insulating layer (INS10) may be disposed on at least a portion of the first and second bridge electrodes (BE1, BE2) that are exposed and not covered by the 9th insulating layer (INS9). The upper surface of each of the light-emitting elements (LE) may be exposed and not covered by the 10th insulating layer (INS10).

[0338] The ninth insulating layer (INS9) and the tenth insulating layer (INS10) may include at least one insulating material, for example, an organic insulating material. For example, each of the ninth insulating layer (INS9) and the tenth insulating layer (INS10) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0339] The ninth insulating layer (INS9) and the tenth insulating layer (INS10) can flatten the step difference caused by the light-emitting elements (LE). If the height of the ninth insulating layer (INS9) is positioned to cover most of the side of each of the light-emitting elements (LE), the tenth insulating layer (INS10) may be omitted.

[0340] A capping layer (CPL) may be disposed on light-emitting elements (LE), a ninth insulating layer (INS9), and a tenth insulating layer (INS10). The capping layer (CPL) may comprise at least one insulating material, for example, an inorganic insulating material.

[0341] In one embodiment, when the light-emitting element (LE) of each subpixel (SPX) emits light of a color corresponding (e.g., matching) to the light-emitting color (or light-emitting wavelength) of the corresponding subpixel (SPX), the display panel (100) may not include a light conversion layer. For example, a first overcoat layer (OC1) may be placed directly on the capping layer (CPL).

[0342] When subpixels (SPX) include light-emitting elements (LE) that emit light corresponding to each light-emitting color, the light emitted from the light-emitting elements (LE) can be utilized more efficiently. For example, the degradation of light efficiency of the subpixels (SPX) due to light conversion can be prevented. In addition, the color purity of the light emitted from the subpixels (SPX) can be increased, and the color reproduction rate of the subpixels (SPX) can be improved.

[0343] In another embodiment, if a light-emitting element (LE) of at least one subpixel (SPX) emits light of a color different from the light-emitting color (or light-emitting wavelength) of the subpixel (SPX), a light-converting layer may be further disposed on top of the light-emitting element (LE). For example, if the first light-emitting element (LE1) emits blue light and the first subpixel (SPX1) is a red subpixel that emits red light, a light-converting layer covering the first light-emitting element (LE1) may be disposed on the capping layer (CPL). The light-converting layer may include light-converting particles (e.g., red quantum dots) that convert blue light incident from the first light-emitting element (LE1) into red light. If the subpixels (SPX) include light-emitting elements (LE) that emit light of the same color, the manufacturing efficiency of the light-emitting element layer (EDL) and the display panel (100) including it can be increased and the manufacturing cost reduced.

[0344] The first overcoat layer (OC1) may be disposed on a capping layer (CPL) (or light conversion layer). The first overcoat layer (OC1) may be an organic film comprising an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin), and the upper surface of the first overcoat layer (OC1) may be substantially flat. However, the embodiments are not limited thereto. For example, the first overcoat layer (OC1) may be an inorganic film comprising an inorganic insulating material, and the first overcoat layer (OC1) may be formed with a sufficient thickness to include a substantially flat upper surface or may be flattened through a separate flattening process. Accordingly, the upper surface of the first overcoat layer (OC1) may be substantially flat.

[0345] A color filter layer (CFL) may be disposed on the first overcoat layer (OC1). The color filter layer (CFL) may further include color filters (CF) disposed in the light-emitting regions (EA) of the subpixels (SPX), and a second overcoat layer (OC2) covering the color filters (CF).

[0346] The color filter layer (CFL) may include color filters (CF) that selectively transmit light corresponding to the emission color (or emission wavelength) of each subpixel (SPX). For example, if the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) are subpixels (SPX) that emit red light, green light, and blue light, respectively, a red color filter, a green color filter, and a blue color filter may be disposed in the first emission region (EA1) of the first subpixel (SPX1), the second emission region (EA2) of the second subpixel (SPX2), and the third emission region (EA3) of the third subpixel (SPX3), respectively. In one embodiment, the color filters (CF) of the subpixels (SPX) may overlap each other in a non-emission region surrounding the emission regions (EA) of the subpixels (SPX) to form a light-blocking pattern.

[0347] The second overcoat layer (OC2) may be disposed on the color filters (CF). The second overcoat layer (OC2) may be an organic film containing an organic insulating material, and the upper surface of the second overcoat layer (OC2) may be substantially flat. However, the embodiments are not limited thereto. For example, the second overcoat layer (OC2) may be an inorganic film containing an inorganic insulating material, and the second overcoat layer (OC2) may be formed with a sufficient thickness to include a substantially flat upper surface or may be flattened through a separate flattening process. Accordingly, the upper surface of the second overcoat layer (OC2) may be substantially flat.

[0348] FIG. 22 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the X1-X1' line of FIG. 9 and FIG. 18. For example, FIG. 22 shows an embodiment of a cross-section of a display panel (100) corresponding to a portion of a first subpixel (SPX1). Compared to FIG. 19, FIG. 22 shows an embodiment in which the display panel (100) further includes a lower conductive layer (BCDL).

[0349] Referring to FIG. 22 in addition to FIG. 9 to 21, the display panel (100) may further include a lower conductive layer (BCDL) disposed on a substrate (SUB). For example, the backplane layer (BPL) may include a lower conductive layer (BCDL) disposed between the substrate (SUB) and the barrier layer (BR).

[0350] The lower conductive layer (BCDL) may include a lower pattern (BML) disposed below the first transistor (T1). The lower pattern (BML) may cover the lower surface of the first active layer (ACT1) wholly or partially. For example, the lower pattern (BML) may be disposed below the first active layer (ACT1) to overlap with the channel region of the first active layer (ACT1) (for example, a part of the first active layer (ACT1) that overlaps with the first gate electrode (GE1)).

[0351] In one embodiment, the lower conductive layer (BCDL) may include a light-blocking material. For example, the lower conductive layer (BCDL) may include a metal, and the lower pattern (BML) may be formed as a lower metal pattern. In one embodiment, the lower pattern (BML) may be electrically connected to a power line to which a positive voltage is applied (for example, a first power line (VDL)). In one embodiment, the lower pattern (BML) may be formed in the display area (DA) as a pattern that extends or connects along at least one of the first direction (DR1) and the second direction (DR2) when viewed on a plane defined by the first direction (DR1) and the second direction (DR2), but is not limited thereto.

[0352] The lower pattern (BML) can block external light from being incident on the channel region of the first active layer (ACT1) or the lower part of the first transistor (T1). Additionally, the lower pattern (BML) can disperse charges that accumulate around the first transistor (T1). Accordingly, the operating characteristics of the first transistor (T1) can be stabilized.

[0353] According to the embodiments described with reference to FIGS. 3 to 22, the design structure of the display area (DA) in which pixels (PX) are arranged can be improved. For example, by designing the second sub-pixel (SPX2) and the third sub-pixel (SPX3) symmetrically in a flip form, pixel circuits (PXC) and wiring can be efficiently arranged in the display area (DA), and the integration density of the pixels (PX) can be improved. Accordingly, the design structure of the display area (DA) (for example, the design structure of the backplane layer (BPL)) can be optimized, and space can be secured for arranging additional wiring, etc.

[0354] For example, even if each of the pixel circuits (PXC) includes a large number of circuit elements, at least two light-emitting control lines (EL) can be placed on each horizontal line, and additional design space can be secured between adjacent pixel circuits (PXC) (for example, between the first pixel circuit (PXC1) and the second pixel circuit (PXC2) adjacent in the first direction (DR1), or between the third pixel circuit (PXC3) and the first pixel circuit (PXC1) adjacent in the first direction (DR1)).

[0355] In some embodiments, a second power line (VSL) may be placed in the space secured by efficiently arranging the pixel circuits (PXC) and wiring. For example, the second power line (VSL) may be placed between the first subpixel (SPX1) and the second and third subpixels (SPX2, SPX3), or between two adjacent pixels (PX) (for example, between two adjacent pixels (PX) in the first direction (DR1)). The second power line (VSL) may be electrically connected to a common electrode (CE) placed on the backplane layer (BPL). Accordingly, a voltage drop of the second driving voltage (VSS) applied to the common electrode (CE) through the second power line (VSL) can be prevented, and the image quality and power consumption of the display device (10) can be improved.

[0356] In some embodiments, the light emission control lines (EL) of at least two subpixels (SPX) among the subpixels (SPX) forming a single pixel (PX) can be separated. For example, the first subpixel (SPX1) and the second and third subpixels (SPX2, SPX3) can be connected to different light emission control lines (EL). Accordingly, the light emission period of the first subpixel (SPX1) and the light emission period of the second and third subpixels (SPX2, SPX3) can be controlled independently or individually. For example, the driving current (Ids) of the first subpixel (SPX1) and the driving current (Ids) of the second and third subpixels (SPX2, SPX3) can be appropriately adjusted or differentiated according to the optimal consumption efficiency of the light-emitting elements (LE) included in the subpixels (SPX), and the light-emitting periods of the first subpixel (SPX1) and the second and third subpixels (SPX2, SPX3) can be individually adjusted according to each driving current (Ids) to maintain the brightness of the subpixels (SPX) uniformly. Accordingly, the lifespan, image quality, and power consumption of the display device (10) can be improved.

[0357] FIG. 23 is an example drawing showing a smart watch including a display device according to one embodiment. Referring to FIG. 23, the display device (10_1) according to one embodiment can be applied to a smart watch (1000_1), which is one of the smart devices.

[0358] FIGS. 24 and 25 are exemplary drawings showing a head-mounted display device including a display device according to one embodiment. FIGS. 24 and 25 show a virtual reality device as a head-mounted display device (1000_2) to which a display device (10_2, 10_3) according to one embodiment is applied.

[0359] Referring to FIGS. 24 and 25, a head-mounted display device (1000_2) according to one embodiment includes a first display device (10_2), a second display device (10_3), a display device storage unit (1100), a storage unit cover (1200), a first eyepiece (1210), a second eyepiece (1220), a head-mounted band (1300), a middle frame (1400), a first optical member (1510), a second optical member (1520), and a control circuit board (1600).

[0360] The first display device (10_2) provides an image to the user's left eye, and the second display device (10_3) provides an image to the user's right eye. Each of the first display device (10_2) and the second display device (10_3) may be a display device (10) according to at least one of the embodiments described above. Accordingly, the description of the first display device (10_2) and the second display device (10_3) is omitted.

[0361] The first optical member (1510) may be positioned between the first display device (10_2) and the first eyepiece (1210). The second optical member (1520) may be positioned between the second display device (10_3) and the second eyepiece (1220). Each of the first optical member (1510) and the second optical member (1520) may include at least one convex lens.

[0362] The middle frame (1400) is positioned between the first display device (10_2) and the control circuit board (1600), and may be positioned between the second display device (10_3) and the control circuit board (1600). The middle frame (1400) serves to support and fix the first display device (10_2), the second display device (10_3), and the control circuit board (1600).

[0363] The control circuit board (1600) may be placed between the middle frame (1400) and the display device housing (1100). The control circuit board (1600) may be connected to the first display device (10_2) and the second display device (10_3) through a connector. The control circuit board (1600) may convert an image source input from the outside into digital video data (DATA) and transmit the digital video data (DATA) to the first display device (10_2) and the second display device (10_3) through the connector.

[0364] The control circuit board (1600) can transmit digital video data (DATA) corresponding to a left-eye image optimized for the user's left eye to the first display device (10_2) and digital video data (DATA) corresponding to a right-eye image optimized for the user's right eye to the second display device (10_3). Alternatively, the control circuit board (1600) can transmit the same digital video data (DATA) to the first display device (10_2) and the second display device (10_3).

[0365] The display device housing (1100) serves to house the first display device (10_2), the second display device (10_3), the middle frame (1400), the first optical member (1510), the second optical member (1520), and the control circuit board (1600). The housing cover (1200) is positioned to cover an open side of the display device housing (1100). The housing cover (1200) may include a first eyepiece (1210) in which the user's left eye is positioned and a second eyepiece (1220) in which the user's right eye is positioned. Although FIGS. 24 and 25 illustrate the first eyepiece (1210) and the second eyepiece (1220) being positioned separately, the embodiments of this specification are not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0366] The first eyepiece (1210) is aligned with the first display device (10_2) and the first optical member (1510), and the second eyepiece (1220) can be aligned with the second display device (10_3) and the second optical member (1520). Accordingly, the user can view an image of the first display device (10_2) magnified into a virtual image by the first optical member (1510) through the first eyepiece (1210), and can view an image of the second display device (10_3) magnified into a virtual image by the second optical member (1520) through the second eyepiece (1220).

[0367] The head mounting band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be maintained in a state where they are positioned on the user's left and right eyes, respectively. When the display device storage unit (1100) is implemented as a lightweight and compact unit, the head-mounted display device (1000_2) may be equipped with an eyeglass frame as shown in FIG. 26 instead of the head mounting band (1300).

[0368] In addition, the head-mounted display device (1000_2) may further be equipped with a battery for supplying power, an external memory slot for storing external memory, an external connection port for receiving video sources, and a wireless communication module. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0369] FIG. 26 is an exemplary drawing showing a head-mounted display device including a display device according to one embodiment. FIG. 26 shows a virtual reality device (or augmented reality device) as a head-mounted display device to which a display device (10_4) according to one embodiment is applied.

[0370] Referring to FIG. 26, a head-mounted display device (1000_3) according to one embodiment may be a device in the form of glasses. A head-mounted display device (1000_3) according to one embodiment may have a display device (10_4), a left eye lens (10a), a right eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device storage portion (50).

[0371] FIG. 26 illustrates a head-mounted display device (1000_3) that is an eyeglass-type display device including eyeglass frame temples (30a, 30b). That is, the head-mounted display device (1000_3) according to one embodiment is not limited to that shown in FIG. 26 and can be applied in various forms in various other electronic devices.

[0372] The display device housing (50) may include a display device (10_4) and a reflective member (40). An image displayed on the display device (10_4) may be reflected from the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user can view a virtual reality image displayed on the display device (10_4) through the right eye. For example, the user can view an augmented reality image in which a virtual image displayed on the display device (10_4) through the right eye is combined with a real image seen through the right eye lens (10b).

[0373] FIG. 26 illustrates that the display device housing (50) is positioned at the right end of the support frame (20), but the embodiments of this specification are not limited thereto. For example, the display device housing (50) may be positioned at the left end of the support frame (20), in which case the image displayed on the display device (10_4) may be reflected from the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user can view the virtual reality image displayed on the display device (10_4) through the left eye. Alternatively, the display device housing (50) may be positioned at both the left end and the right end of the support frame (20), in which case the user can view the virtual reality image displayed on the display device (10_4) through both the left eye and the right eye.

[0374] FIG. 27 is an exemplary drawing showing an automobile instrument panel and a center fascia including display devices according to one embodiment. FIG. 27 shows an automobile with display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment applied.

[0375] Referring to FIG. 27, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to an instrument panel of a vehicle, to a center fascia of a vehicle, or to a Center Information Display (CID) placed on the dashboard of a vehicle. Additionally, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0376] FIG. 28 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0377] Referring to FIG. 28, a display device (10_5) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light simultaneously. Therefore, a user located in front of the transparent display device can not only view the image (IM) displayed on the display device (10_5) but also see an object (RS) or background located on the back of the transparent display device. When the display device (10_5) is applied to a transparent display device, the substrate of the display device (10_5) may include a light-transmitting portion capable of transmitting light or be formed of a material capable of transmitting light.

[0378] In FIGS. 23 to 28, examples of electronic devices that may include display devices (10, 10_1, 10_2, 10_3, 10_4, 10_5, 10_a, 10_b, 10_c, 10_d, 10_e) according to embodiments are illustrated, such as a smart watch (1000_1), a head-mounted display device (1000_2, 1000_3), an automobile instrument panel and center fascia, and a transparent display device, but the embodiments are not limited thereto. For example, a display device (10) according to at least one of the embodiments described above may be included in an electronic device of a different type or structure in addition to the electronic devices illustrated in FIGS. 23 to 28.

[0379] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

1. A pixel disposed in a display area where an image is displayed, comprising a first subpixel including a first pixel circuit, a second subpixel including a second pixel circuit, and a third subpixel including a third pixel circuit; A first light-emitting control line electrically connected to the first pixel circuit; A second light-emitting control line electrically connected to the second pixel circuit and the third pixel circuit; and The first pixel circuit, the second pixel circuit, and the third pixel circuit are electrically connected and include first power lines arranged in a first direction in the display area, each of which extends in a second direction. The first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged in the first direction in the display area, The first pixel circuit above overlaps with one of the first power lines, and A display device in which the second pixel circuit and the third pixel circuit overlap with another first power line among the first power lines and have a shape symmetric to each other.

2. In Paragraph 1, A display device in which the second pixel circuit and the third pixel circuit are commonly connected to the other first power line and have a shape symmetric to each other with respect to the other first power line.

3. In Paragraph 1, A display device further comprising data lines arranged in the first direction in the above display area, including a first data line electrically connected to the first pixel circuit, a second data line electrically connected to the second pixel circuit, and a third data line electrically connected to the third pixel circuit.

4. In Paragraph 3, Each of the above first pixel circuit, the above second pixel circuit, and the above third pixel circuit is, A first transistor configured to regulate a driving current in response to a data voltage transmitted from the first data line, the second data line, or the third data line; and A display device comprising a second transistor electrically connected between the first data line, the second data line or the third data line and the first transistor.

5. In Paragraph 4, A display device comprising the first transistor, the active layer, a gate electrode overlapping a portion of the active layer, and a source electrode and a drain electrode electrically connected to different portions of the active layer.

6. In Paragraph 5, The first transistors of the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged sequentially along the first direction, The drain electrode of the first transistor included in the first pixel circuit and the source electrode of the first transistor included in the second pixel circuit are adjacent to each other in the first direction, A display device in which the drain electrode of the first transistor included in the second pixel circuit and the drain electrode of the first transistor included in the third pixel circuit are adjacent to each other in the first direction.

7. In Paragraph 4, A display device in which the size of the first transistor included in the first pixel circuit is different from the size of the first transistor included in each of the second pixel circuit and the third pixel circuit.

8. In Paragraph 4, Each of the above first pixel circuit, the above second pixel circuit, and the above third pixel circuit further includes a third transistor and a fourth transistor comprising an oxide semiconductor, which are commonly connected to the gate electrode of the first transistor through a first connecting electrode. A display device in which the third transistor and the fourth transistor of the second pixel circuit are arranged adjacent to the third transistor and the fourth transistor of the third pixel circuit in the first direction.

9. In Paragraph 8, The above-mentioned first power line covers the first transistor, the third transistor, and the fourth transistor included in the first pixel circuit, and The other first power line above covers the first transistors, third transistors, and fourth transistors included in the second pixel circuit and the third pixel circuit, a display device.

10. In Paragraph 4, A display device in which the first light-emitting control line and the second light-emitting control line are adjacent to each other in the second direction, and each extends in the first direction.

11. In Paragraph 10, A display device comprising, wherein each of the first pixel circuit, the second pixel circuit, and the third pixel circuit further comprises a fifth transistor and a sixth transistor, each comprising an active layer intersecting the first light emission control line and the second light emission control line, and a gate electrode overlapping a portion of each of the active layers.

12. In Paragraph 11, The active layer of the fifth transistor extends from one end of the active layer of the first transistor, has a U-shape or Y-shape around the first light emission control line and the second light emission control line, and intersects the first light emission control line and the second light emission control line. A display device in which the active layer of the sixth transistor extends from the other end of the active layer of the first transistor and is electrically connected to a light-emitting element disposed on top of the first pixel circuit, the second pixel circuit, or the third pixel circuit.

13. In Paragraph 12, A display device in which one end of the active layer of the fifth transistor is electrically connected to the one first power line or the other first power line.

14. In Paragraph 13, The second subpixel and the third subpixel further include a second connecting electrode that overlaps with the other first power line and extends in the first direction in the area where the second pixel circuit and the third pixel circuit are arranged. A display device in which the active layers of the fifth transistors included in the second pixel circuit and the third pixel circuit are commonly connected to the first second connection electrode and are electrically connected to the other first power line through the second connection electrode.

15. In Paragraph 11, The gate electrodes of the fifth and sixth transistors included in the first pixel circuit are formed as a single conductive pattern that overlaps with the first light emission control line, and A display device in which the above-mentioned challenge pattern is electrically connected to the first light-emitting control line through a contact hole disposed between the fifth transistor and the sixth transistor.

16. In Paragraph 11, The gate electrodes of the fifth and sixth transistors included in the second pixel circuit and the third pixel circuit are formed as a single conductive pattern that overlaps with the second light emission control line, and A display device in which the above-mentioned challenge pattern is electrically connected to the second light-emitting control line through a contact hole disposed between the second pixel circuit and the third pixel circuit.

17. In Paragraph 3, The first data line is positioned between a data line electrically connected to a third subpixel of another pixel adjacent to the first subpixel in the first direction and the first power line, and The second data line is positioned between the first power line and the other first power line, and A display device wherein the third data line is positioned between the other first power line and a data line electrically connected to the first subpixel of another pixel adjacent to the third subpixel in the first direction.

18. In Paragraph 1, The first subpixel further includes a first light-emitting element electrically connected to the first pixel circuit through a first anode contact hole that overlaps with the first pixel circuit, and The second subpixel further includes a second light-emitting element electrically connected to the second pixel circuit through a second anode contact hole that overlaps with the second pixel circuit, and The third subpixel further includes a third light-emitting element electrically connected to the third pixel circuit through a third anode contact hole that overlaps with the third pixel circuit, and The other first power line above passes through the area between the second anode contact hole and the third anode contact hole, a display device.

19. In Paragraph 18, It further includes a second power line disposed between the first pixel circuit and the second pixel circuit, or between another pixel adjacent to the pixel in the first direction and the pixel, and A display device in which the second power line is electrically connected to the first light-emitting element, the second light-emitting element, and the third light-emitting element through a cathode contact hole.

20. A display device including a display area where an image is displayed, and The above display device is, A pixel disposed in the above-mentioned display area and comprising a first subpixel including a first pixel circuit, a second subpixel including a second pixel circuit, and a third subpixel including a third pixel circuit; A first light-emitting control line electrically connected to the first pixel circuit; A second light-emitting control line electrically connected to the second pixel circuit and the third pixel circuit; and The first pixel circuit, the second pixel circuit, and the third pixel circuit are electrically connected and include first power lines arranged in a first direction in the display area, each of which extends in a second direction. The first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged in the first direction in the display area, The first pixel circuit above overlaps with one of the first power lines, and An electronic device in which the second pixel circuit and the third pixel circuit overlap with another first power line among the first power lines and have a shape symmetric to each other.

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