Display module and display apparatus

Abstract

A display module and a display apparatus. The display module comprises a display panel; a drive circuit chip (1), bonded to a chip pad (2), the drive circuit chip (1) comprising a chip body (1-1) and a plurality of chip pins (1-2), the chip pins (1-2) being disposed on the surface of the side of the chip body (1-1) close to the chip pad (2), and the chip pins (1-2) being configured to be connected to the chip pad (2); and a conductive film (3), disposed between the drive circuit chip (1) and the chip pad (2), the conductive film (3) being configured to allow the drive circuit chip (1) to be bonded to the chip pad (2). The thickness of the chip body (1-1) is H1, and the thickness of the chip pins (1-2) is h1, where the thickness of the chip body (1-1) and the thickness of the chip pins (1-2) satisfy the relational expression: h1 / H1=1.5%-2.5%.

Description

Display modules, display devices Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display module and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Micro-OLEDs (Micro-Organic Light-Emitting Diodes) are microdisplays that have emerged in recent years, with silicon-based OLEDs being one type. Silicon-based OLEDs not only enable active pixel addressing but also allow for the fabrication of pixel driving circuits and other structures on silicon substrates, which helps reduce system size and achieve lightweight design. Silicon-based OLEDs are fabricated using mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology, offering advantages such as small size, high resolution (Pixels Per Inch, PPI), and high refresh rate. They are widely used in near-eye displays for Virtual Reality (VR) and Augmented Reality (AR). Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On the one hand, this disclosure provides a display module, including:

[0006] A display panel includes a display area and a bonding area located on one side of the display area, the bonding area including chip pads;

[0007] A driver circuit chip is bonded to a chip pad. The driver circuit chip includes a chip body and a plurality of chip pins. The chip pins are disposed on the surface of the chip body near the chip pad and are configured to connect to the chip pad.

[0008] A conductive film is disposed between the driving circuit chip and the chip pad, and the conductive film is configured to bond the driving circuit chip to the chip pad.

[0009] The thickness of the chip body is H1, and the thickness of the chip pin is h1. The thickness of the chip body and the thickness of the chip pin satisfy the relationship: h1 / H1 = 1.5%~2.5%.

[0010] In an exemplary embodiment, the thickness of the chip body ranges from 300µm to 600µm.

[0011] In an exemplary embodiment, the thickness of the chip pins ranges from 9µm to 15µm.

[0012] In an exemplary embodiment, a cover plate is also included, which is disposed on the light-emitting side of the display area of ​​the display panel. The thickness of the cover plate is H4, and the thickness of the cover plate and the thickness of the chip body satisfy the relationship: H1 < H4.

[0013] In an exemplary embodiment, the thickness of the cover plate ranges from H4 to 420 μm to 840 μm.

[0014] In an exemplary embodiment, the chip pad includes a pad body and a plurality of bonding pins. The bonding pins are disposed on the surface of the pad body near the driver circuit chip. The bonding pins are disposed corresponding to the chip pins and are configured to be bonded to the corresponding chip pins.

[0015] In an exemplary embodiment, the thickness of the pad body is H2, and the thickness of the pad body and the thickness of the chip body satisfy the relationship: H2 > H1.

[0016] In an exemplary embodiment, the thickness of the pad body is H2, and the thickness of the pad body ranges from 700um to 850um.

[0017] In an exemplary embodiment, the thickness of the pad body is H2, the thickness of the bonding pin is h2, and the thickness of the bonding pin and the thickness of the pad body satisfy the relationship: h2 / H2 = 0.01% to 0.03%.

[0018] In an exemplary embodiment, the thickness of the bonding pin is h2, and the thickness of the bonding pin ranges from 0.1µm to 0.2µm.

[0019] In an exemplary embodiment, the conductive film includes an insulating body and a plurality of conductive particles disposed within the insulating body. The insulating body is disposed between the driving circuit chip and the chip pad. The plurality of conductive particles include a first particle located in the insulating body between the chip pin and the bonding pin. The first particle is connected to the chip pin and the bonding pin respectively.

[0020] In an exemplary embodiment, the thickness of the insulating body is H3, and the thickness of the insulating body and the thickness of the chip body satisfy the relationship: H3 < H1; and / or, the thickness of the insulating body and the thickness of the pad body satisfy the relationship: H3 < H2.

[0021] In an exemplary embodiment, the thickness of the insulating body is H3, the thickness of the bonding pin is h2, and the thicknesses of the insulating body, the chip pin, and the bonding pin satisfy the relationship: H3 > h1 + h2.

[0022] In an exemplary embodiment, the thickness of the insulating body is H3, and the thickness of the insulating body ranges from 12µm to 25µm.

[0023] In an exemplary embodiment, the driving circuit chip further includes a chip recess disposed between adjacent chip pins, and the chip pad further includes a pad recess disposed between adjacent bonding pins. The chip recess and the pad recess are correspondingly disposed. The distance between the bottom wall of the chip recess and the bottom wall of the corresponding pad recess is L1, and the thickness of the insulating body is H3. The distance between the bottom wall of the chip recess and the bottom wall of the corresponding pad recess and the thickness of the insulating body satisfy the relationship: H3 > L1.

[0024] In an exemplary embodiment, the distance between the bottom wall of the chip recess and the bottom wall of the corresponding pad recess and the thickness of the insulating body satisfy the following relationship: H3-L1>3um~5um.

[0025] In an exemplary embodiment, the diameter of the first particle in the direction perpendicular to the display panel is d3, and the distance between the diameter of the first particle in the direction perpendicular to the display panel and the distance between the bottom wall of the chip groove and the bottom wall of the corresponding pad groove satisfies the relationship: L1 > d3.

[0026] In an exemplary embodiment, the diameter of the first particle in the direction perpendicular to the display panel and the distance between the bottom wall of the chip recess and the bottom wall of the corresponding pad recess satisfy the following relationship: d3 / L1 = 20%~25%.

[0027] In an exemplary embodiment, the diameter of the first particle in the direction perpendicular to the display panel is d3, and the distance between the chip pin and the corresponding bonding pin is L2. The diameter of the first particle in the direction perpendicular to the display panel and the distance between the chip pin and the corresponding bonding pin satisfy the relationship: L2 < d3.

[0028] In an exemplary embodiment, the diameter of the first particle in the direction perpendicular to the display panel is d3, and the range of the diameter of the first particle in the direction perpendicular to the display panel is: d3 = 3um to 5um.

[0029] In an exemplary embodiment, the driving circuit chip further includes a chip recess disposed between adjacent chip pins, and the chip pad further includes a pad recess disposed between adjacent bonding pins. The chip recess and the pad recess are correspondingly disposed. The plurality of conductive particles include second particles located in an insulating body between the chip recess and the pad recess. The second particles are spaced apart along a first direction. The length of the chip recess in the first direction is d1, and the diameter of the second particle in the first direction is d2. The length of the chip recess in the first direction and the diameter of the second particle in the first direction satisfy the relationship: d1 / d2 > 2~5.

[0030] On the other hand, this disclosure also provides a display device including the aforementioned display module.

[0031] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0032] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0033] Figure 1 is a schematic cross-sectional view of the driver circuit chip and chip pads in the relevant display module;

[0034] Figure 2 is a schematic diagram of a display module;

[0035] Figure 3 is a planar schematic diagram of a display module;

[0036] Figure 4 is a cross-sectional schematic diagram of a display module;

[0037] Figure 5 is a schematic diagram of the planar structure of a display panel according to an exemplary embodiment of the present disclosure;

[0038] Figure 6 is a schematic diagram of the planar structure of a display module after the driving circuit chip and the chip pad are bonded together, according to an exemplary embodiment of the present disclosure.

[0039] Figure 7 is a schematic cross-sectional view of a display module after the driving circuit chip and chip pads are bonded together, according to an exemplary embodiment of the present disclosure.

[0040] Figure 8 is a cross-sectional view of a driving circuit chip in a display module according to an exemplary embodiment of the present disclosure;

[0041] Figure 9 is a schematic cross-sectional view of a chip pad in a display module according to an exemplary embodiment of the present disclosure;

[0042] Figure 10 is a schematic cross-sectional view of a conductive film in a display module according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0044] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0045] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0046] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0047] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0048] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0049] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0050] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0051] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0052] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0053] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0054] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0055] Figure 1 is a cross-sectional view of the driving circuit chip and chip pads in the relevant display module. As shown in Figure 1, the relevant display module includes a display panel, a conductive film 3', and a driving circuit chip 1'. The display panel includes a display area and a bonding area disposed on one side of the display area. The bonding area includes at least a chip pad 2', which includes multiple bonding pins 2-2'. The driving circuit chip 1' includes a chip body 1-1' and chip pins 1-2'. The chip pins 1-2' of the chip body 1-1' are electrically connected to the bonding pins 2-2' of the chip pad 2'. The conductive film 3' is disposed between the driving circuit chip 1' and the chip pad 2', and is configured to bond the chip pins 1-2' to the bonding pins 2-2'.

[0056] The inventors of this application have discovered that after the driving circuit chip 1' is bonded to the chip pad 2' through the conductive film 3', the thickness of the driving circuit chip 1' and the thickness of the conductive film 3' cannot be completely matched. As a result, the conductive film 3' cannot completely fill the gap between adjacent chip pins 1-2', causing air bubbles 40' to exist in the gap between adjacent chip pins 1-2'. The air bubbles 40' will affect the impedance and electrical connection between the driving circuit chip 1' and the chip pad 2', which can easily cause problems such as black screen and high current in the display module.

[0057] This disclosure provides a display module, including:

[0058] A display panel includes a display area and a bonding area located on one side of the display area, the bonding area including chip pads;

[0059] A driver circuit chip is bonded to a chip pad. The driver circuit chip includes a chip body and multiple chip pins. The chip pins are disposed on the surface of the chip body near the chip pad and are configured to connect to the chip pad.

[0060] A conductive film is disposed between the driving circuit chip and the chip pad, and the conductive film is configured to electrically connect the driving circuit chip and the chip pad;

[0061] The thickness of the chip body is H1, and the thickness of the chip pin is h1. The thickness of the chip body and the thickness of the chip pin satisfy the relationship: h1 / H1 = 1.5%~2.5%.

[0062] In an exemplary embodiment, the thickness of the chip body ranges from 300µm to 600µm.

[0063] In an exemplary embodiment, the thickness of the chip pins ranges from 9µm to 15µm.

[0064] Figure 2 is a schematic diagram of a display module. As shown in Figure 2, the display module includes a display panel 10, a flexible printed circuit board 20 (FPC), and a cover plate 30. The display panel 10 includes a display area, a bonding area on one side of the display area, and a border area on the other sides of the display area. The display area is configured to display an image. The cover plate 30 is disposed on the light-emitting side of the display panel 10. The orthographic projection of the cover plate 30 onto the plane of the display panel 10 is located within the display panel 10, and the orthographic projection of the cover plate 30 onto the plane of the display panel 10 covers the display area. The cover plate 30 is configured to protect the display panel 10. The flexible printed circuit board 20 is bonded to the bonding area of ​​the display panel 10. The flexible printed circuit board 20 is configured to connect the display panel 10 to external electrical devices to realize the transmission of external signals. The light-emitting side of the display panel 10 refers to the side of the display area of ​​the display panel 10 from which light rays are emitted.

[0065] In an exemplary embodiment, the cover plate 30 may be made of glass, or of a flexible plastic such as colorless polyimide with a light transmittance greater than 90%.

[0066] Figure 3 is a plan view of a display module; Figure 4 is a cross-sectional view of a display module. Figure 4 can be a cross-sectional view along the A-A' direction in Figure 3. As shown in Figures 3 and 4, the display module includes a display panel 10 and a cover plate 30 disposed on the light-emitting side of the display panel 10. In a direction perpendicular to the plane of the display panel 10, the display panel 10 includes a substrate 101, a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, a first encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101, a color filter structure layer 105 disposed on the side of the first encapsulation layer 104 away from the substrate 101, and a second encapsulation layer 106 disposed on the side of the color filter structure layer 105 away from the substrate 101. The cover plate 30 is disposed on the side of the second encapsulation layer 106 away from the substrate 101. In some possible implementations, the display module may include other film layers, such as a touch structure layer, which is not limited herein.

[0067] In an exemplary embodiment, the substrate 101 can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 can be fabricated on the substrate 101 using silicon semiconductor processes (e.g., CMOS processes). For example, the driving circuit layer 102 can be fabricated on the substrate 101 using 180nm or 110nm silicon semiconductor processes, and the driving circuit layer 102 can include a pixel driving circuit. The light-emitting structure layer 103 includes a first electrode layer 11, an organic light-emitting layer 13, and a second electrode layer 12 sequentially disposed along a direction away from the substrate 101. The first electrode layer 11 includes a first electrode, and the second electrode layer 12 includes a second electrode. The corresponding first electrode, organic light-emitting layer 13, and second electrode form a light-emitting device. The organic light-emitting layer 13 emits light under the drive of the first and second electrodes. The first encapsulation layer 104 and the second encapsulation layer 106 can employ thin-film encapsulation (TFE) to ensure that external moisture cannot enter the light-emitting structure layer. The first encapsulation layer 104 and the second encapsulation layer 106 can be made of inorganic or organic materials, such as silicon oxide or silicon nitride. The color filter structure layer 105 may include a black matrix (BM) and color filters (CF). The positions of the color filters may correspond to the positions of the light-emitting devices. The black matrix may be located between adjacent color filters. The color filters are configured to filter the light emitted from the light-emitting devices into red (R) light, green (G) light, and blue (B) light, forming red sub-pixels, green sub-pixels, and blue sub-pixels. The black matrix is ​​configured to block light transmission, preventing crosstalk between adjacent sub-pixels.

[0068] In an exemplary embodiment, in a direction parallel to the plane of the display panel 10, the orthogonal projection of the cover plate 30 on the substrate 101 covers the orthogonal projections of the first electrode layer 11, the organic light-emitting layer 13, and the color filter structure layer 105 on the substrate 101; the orthogonal projection of the color filter structure layer 105 on the substrate 101 covers the orthogonal projections of the first electrode layer 11 and the organic light-emitting layer 13 on the substrate 101; and the orthogonal projection of the organic light-emitting layer 13 on the substrate 101 covers the orthogonal projection of the first electrode layer 11 on the substrate 101.

[0069] Figure 5 is a schematic diagram of the planar structure of a display panel according to an exemplary embodiment of the present disclosure. In the exemplary embodiment, as shown in Figure 5, the display panel of the present disclosure includes a display area 100, a binding area 200 located on one side of the display area 100, and border areas 300 located on other sides of the display area 100. The display area 100 is the effective area (AA) for image display and may include a plurality of sub-pixels constituting a pixel array. The border area 300 may include corresponding signal lines configured to transmit required signals to the display area 100.

[0070] In an exemplary embodiment, a sub-pixel of the display area 100 may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is configured to output a corresponding current to the light-emitting device. The light-emitting devices in the sub-pixel are respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0071] In an exemplary embodiment, the pixel driving circuit may include multiple transistors and a storage capacitor. The transistors may include a control electrode G, a first electrode S, and a second electrode D. The control electrode G, the first electrode S, and the second electrode D can be connected to corresponding connection electrodes via tungsten-filled vias (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (such as traces) via the connection electrodes.

[0072] In an exemplary embodiment, the light-emitting device may include a first electrode, an organic light-emitting layer, and a second electrode. The first electrode is connected to the second electrode (D) of a transistor via a connecting electrode. The organic light-emitting layer is connected to the first electrode, and the second electrode is connected to the organic light-emitting layer. The organic light-emitting layer emits light under the drive of the first and second electrodes. The first electrode may be referred to as the anode, and may be made of indium tin oxide (ITO). The second electrode may be referred to as the cathode, and may be made of at least one of magnesium and silver, or an alloy of at least one of magnesium and silver. The second electrodes of all sub-pixels may be a common layer connected together.

[0073] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). The organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0074] In an exemplary embodiment, the display area 100 includes a plurality of pixel units, each pixel unit including a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. The first sub-pixel may be a red sub-pixel emitting red (R) light, the second sub-pixel may be a blue sub-pixel emitting blue (B) light, and the third sub-pixel may be a green sub-pixel emitting green (G) light. In an exemplary embodiment, the shape of the sub-pixels may be any one or more of triangles, squares, rectangles, rhombuses, trapezoids, parallelograms, pentagons, hexagons, and other polygons, and may be arranged in a horizontal parallel, vertical parallel, X-shaped, cross-shaped, triangular, square, diamond-shaped, or delta-shaped manner, etc., without limitation herein.

[0075] In an exemplary embodiment, a pixel unit may include four sub-pixels, which is not limited herein.

[0076] In an exemplary embodiment, the bonding area 200 may include a chip pad 2, which is connected to the signal transmission line of the display area 100 and is configured to be bonded to a driver circuit chip.

[0077] Figure 6 is a planar structural diagram of a display module after the driving circuit chip and chip pads are bonded, according to an exemplary embodiment of the present disclosure; Figure 7 is a cross-sectional structural diagram of a display module after the driving circuit chip and chip pads are bonded, according to an exemplary embodiment of the present disclosure. Figure 7 can be a cross-sectional view along the B-B' direction in Figure 6. In an exemplary embodiment, as shown in Figures 6 and 7, the display module of this embodiment includes a display panel, a driving circuit chip 1, and a conductive film 3. The bonding area of ​​the display panel includes at least chip pads 2, and the driving circuit chip 1 is bonded to the chip pads 2 via the conductive film 3.

[0078] In an exemplary embodiment, in a direction parallel to the display panel, the chip pad 2 is in the shape of a rectangular block. In a direction perpendicular to the display panel (the third direction Z), the chip pad 2 includes a pad body 2-1 and a plurality of bonding pins 2-2. The pad body 2-1 includes a plurality of connecting leads configured to be connected to the display area 100. The plurality of bonding pins 2-2 are provided on the surface of the pad body 2-1 on the side close to the driving circuit chip 1. The bonding pins 2-2 are in the shape of rectangular protrusions, and the bonding pins 2-2 protrude from the surface of the pad body 2-1 on the side close to the driving circuit chip 1. One end of the bonding pin 2-2 far from the driving circuit chip 1 is correspondingly connected to the plurality of connecting leads of the pad body 2-1, and one end of the bonding pin 2- near the driving circuit chip 1 is bonded and connected to the chip pin 1-2 of the driving circuit chip 1.

[0079] In an exemplary embodiment, in a direction parallel to the display panel, the plurality of bonding pins 2-2 arranged at intervals along the first direction X can be referred to as a bonding pin row, and the plurality of bonding pins 2-2 arranged at intervals along the second direction Y can be referred to as a bonding pin column. Among them, both the first direction X and the second direction Y are parallel to the plane where the display panel is located, and the first direction X and the second direction Y intersect with each other. For example, the first direction X and the second direction Y are perpendicular to each other.

[0080] In an exemplary embodiment, the bonding pin 2-2 can be in the same film layer as the first electrode of the display area and is prepared by the same material through the same preparation process. After the first electrode of the display area and the bonding pin 2-2 of the bonding area are prepared simultaneously, a protective layer is first formed on the bonding pin 2-2 in the bonding area. Subsequently, the front-end process (such as forming the second electrode and the encapsulation layer, etc.) is continued in the display area; after the front-end process is completed, the protective layer on the bonding pin 2-2 is removed to expose the bonding pin 2-2; subsequently, the driving circuit chip 1 is bonded and connected to the bonding pin 2-2.

[0081] In an exemplary embodiment, the chip pad 2 further includes a pad groove 2-3. The pad groove 2-3 is provided between adjacent bonding pins 2-2 in the bonding pin row. The bottom wall of the pad groove 2-3 is the surface of the pad body 2-1 on the side close to the driving circuit chip 1, and the side wall of the pad groove 2-3 is the side wall of adjacent bonding pins 2-2 in the bonding pin row. The plurality of bonding pins 2-2 and the plurality of pad grooves 2-3 in the bonding pin row are alternately arranged along the first direction X to form a first concavo-convex structure on the surface of the pad body 2-1 on the side close to the driving circuit chip 1.

[0082] In some embodiments, the bonding pins can be recesses along the direction away from the driving circuit chip, and the chip pins of the driving circuit chip are connected to the bonding pins, thereby separating the conductive particles of the conductive film corresponding to the bonding pins from the conductive particles of the conductive film corresponding to the adjacent pad recesses, thus improving the insulation formation between adjacent bonding pins.

[0083] In an exemplary embodiment, in the direction parallel to the display panel, the driving circuit chip 1 is rectangular in shape. The orthographic projection of the driving circuit chip 1 onto the plane of the display panel at least partially overlaps with the orthographic projection of the chip pad 2 onto the plane of the display panel; for example, the orthographic projection of the driving circuit chip 1 onto the plane of the display panel completely overlaps with the orthographic projection of the chip pad 2 onto the plane of the display panel. In the direction perpendicular to the display panel (third direction Z), the driving circuit chip 1 includes a chip body 1-1 and a plurality of chip pins 1-2. The chip body 1-1 includes a display driver integrated circuit configured to drive the light emission of the light-emitting devices in the display area. The plurality of chip pins 1-2 are disposed on the surface of the chip body 1-1 near the chip pad 2. The chip pins 1-2 are rectangular protrusions extending from the surface of the chip body 1-1 near the chip pad 2. The end of the chip pin 1-2 away from the chip pad 2 is connected to the display driver circuit of the chip body 1-1, and the end of the chip pin 1-2 near the chip pad 2 is bonded to the bonding pin 2-2 of the chip pad 2.

[0084] In an exemplary embodiment, a plurality of chip pins 1-2 arranged at intervals along the first direction X in a direction parallel to the display panel can be referred to as a chip pin row, and the chip pins 1-2 in the chip pin row are connected to the bonding pins 2-2 in the bonding pin row; a plurality of chip pins 1-2 arranged at intervals along the second direction Y can be referred to as a chip pin column, and the chip pins 1-2 in the chip pin column are connected to the bonding pins 2-2 in the bonding pin column.

[0085] In an exemplary embodiment, the driving circuit chip 1 further includes chip recesses 1-3, which are disposed between adjacent chip pins 1-2 in the chip pin row. The chip recesses 1-3 are recessed in a direction away from the chip pad 2. The bottom wall of the chip recesses 1-3 is the surface of the chip body 1-1 near the chip pad 2, and the side walls of the chip recesses 1-3 are the side walls of adjacent chip pins 1-2 in the chip pin row. Multiple chip pins 1-2 and multiple chip recesses 1-3 in the chip pin row are alternately arranged along the first direction X, forming a second uneven structure on the surface of the chip body 1-1 near the chip pad 2.

[0086] In an exemplary embodiment, the orthographic projection of chip pin 1-2 on the plane of the display panel at least partially overlaps with the orthographic projection of the corresponding bonding pin 2-2 on the plane of the display panel. For example, the orthographic projection of chip pin 1-2 on the plane of the display panel completely overlaps with the orthographic projection of the corresponding bonding pin 2-2 on the plane of the display panel. Multiple chip recesses 1-3 are correspondingly disposed with multiple pad recesses 2-3, and the orthographic projection of chip recesses 1-3 on the plane of the display panel at least partially overlaps with the orthographic projection of the corresponding pad recesses 2-3 on the plane of the display panel. For example, the orthographic projection of chip recesses 1-3 on the plane of the display panel completely overlaps with the orthographic projection of the corresponding pad recesses 2-3 on the plane of the display panel.

[0087] In an exemplary embodiment, the driving circuit chip 1 can be a display driver integrated circuit (DDIC) chip.

[0088] In an exemplary embodiment, in the direction parallel to the display panel, the conductive film 3 is rectangular in shape. The orthographic projection of the conductive film 3 onto the plane of the display panel overlaps at least partially with the orthographic projections of the driving circuit chip 1 and the chip pad 2 onto the plane of the display panel. For example, the orthographic projection of the conductive film 3 onto the plane of the display panel completely covers the orthographic projections of the driving circuit chip 1 and the chip pad 2 onto the plane of the display panel. In the direction perpendicular to the display panel (third direction Z), the conductive film 3 is stacked between the driving circuit chip 1 and the chip pad 2. The conductive film 3 located between the chip pin 1-2 and the bonding pin 2-2 is configured to electrically connect the chip pin 1-2 and the bonding pin 2-2, and the conductive film 3 located between the chip recess 1-3 and the pad recess 2-3 is configured to insulate the chip pin 1-2 and the bonding pin 2-2 from each other. The conductive film 3 located between the chip groove 1-3 and the pad groove 2-3 is a solid structure, which fills the chip groove 1-3 and the pad groove 2-3 respectively, so that there are no air bubbles in the chip groove 1-3 and the pad groove 2-3.

[0089] In an exemplary embodiment, the conductive film 3 can be an anisotropic conductive film (ACF). The conductive film 3 includes an insulating body 3-1 and a plurality of conductive particles 3-2 disposed within the insulating body 3-1. The insulating body 3-1 is disposed between the driving circuit chip 1 and the chip pad 2, and the material of the insulating body 3-1 includes a polymer. The plurality of conductive particles 3-2 are arranged at intervals along a first direction X to form a conductive structure. The plurality of conductive particles 3-2 in the conductive structure are located in the middle of the insulating body 3-1 in the direction perpendicular to the display substrate. Adjacent conductive particles 3-2 in the conductive structure are isolated from each other by the insulating body 3-1, so that the conductive particles 3-2 corresponding to the chip pin 1-2 are mutually insulated from the conductive particles 3-2 corresponding to the chip groove 1-3 adjacent to the chip pin 1-2, and the conductive particles 3-2 corresponding to the bonding pin 2-2 are mutually insulated from the conductive particles 3-2 corresponding to the bonding pad groove 2-3 adjacent to the bonding pin 2-2, thereby preventing short circuits between adjacent chip pins 1-2 and adjacent bonding pins 2-2. The material of the conductive particles 3-2 may include metal nanoparticles.

[0090] In an exemplary embodiment, the plurality of conductive particles 3-2 include a first particle 3-2-1 and a second particle 3-2-2. The first particle 3-2-1 is located in an insulating body 3-1 between chip pin 1-2 and bonding pin 2-2. One end of the first particle 3-2-1 in the third direction Z is connected to the chip pin 1-2, and the other end of the first particle 3-2-1 in the third direction Z is connected to the bonding pin 2-2, so that the corresponding chip pin 1-2 and bonding pin 2-2 are electrically connected through the first particle 3-2-1 located between them. The second particle 3-2-2 is located in an insulating body 3-1 between chip recess 1-3 and pad recess 2-3. One end of the second particle 3-2-2 in the third direction Z is isolated from the chip body 1-1 through the insulating body 3-1, so that the second particle 3-2-2 is insulated from the chip body 1-1. The other end of the second particle 3-2-2 in the third direction Z is isolated from the pad body 2-1 through the insulating body 3-1, so that the second particle 3-2-2 is insulated from the pad body 2-1.

[0091] In this embodiment of the display module, the conductive film 3 has conductivity in a direction perpendicular to the display substrate through conductive particles 3-2, which electrically connects the chip pins 1-2 of the driving circuit chip 1 to the bonding pins 2-2 of the chip pad 2; and the adjacent conductive particles 3-2 are insulated by the insulating body 3-1, so that the conductive film 3 is insulated in a direction parallel to the display substrate, thereby preventing short circuits between adjacent chip pins 1-2 and adjacent bonding pins 2-2.

[0092] Figure 8 is a cross-sectional view of a driving circuit chip in a display module according to an exemplary embodiment of the present disclosure. The driving circuit chip shown in Figure 8 can be the same as the driving circuit chip shown in Figure 7. In an exemplary embodiment, as shown in Figures 7 and 8, the thickness of the chip body 1-1 of the driving circuit chip 1 is H1, and the thickness of the chip pins 1-2 of the driving circuit chip 1 is h1. The thickness H1 of the chip body 1-1 and the thickness h1 of the chip pins 1-2 satisfy the following relationship: h1 / H1 = 1.5% to 2.5% (inclusive). For example, the thickness H1 of the chip body 1-1 and the thickness h1 of the chip pins 1-2 satisfy the following relationship: h1 / H1 = 1.8% - 2.2%. The thickness of the chip body 1-1 is the average dimension of the chip body 1-1 in the direction perpendicular to the display panel; the thickness of the chip pins 1-2 is the average dimension of the chip pins 1-2 in the direction perpendicular to the display panel.

[0093] This embodiment of the disclosure shows that by adjusting the percentage of the thickness h1 of the chip pin 1-2 to the thickness H1 of the chip body 1-1 to 1.5% to 2.5%, the driving circuit chip 1 is bonded to the chip pad 2 through the conductive film 3. The conductive film 3 can completely fill the chip groove 1-3 of the driving circuit chip 1 and the pad groove 2-3 of the chip pad 2, so that there are no air bubbles in the chip groove 1-3 and the pad groove 2-3, thus ensuring the electrical connection between the driving circuit chip 1 and the chip pad 2.

[0094] In an exemplary embodiment, the thickness H1 of the chip body 1-1 ranges from 300µm to 600µm (inclusive). For example, the thickness H1 of the chip body 1-1 ranges from 400µm to 500µm (inclusive).

[0095] This embodiment of the disclosure shows that the module ensures the electrical connection between the driving circuit chip 1 and the chip pad 2 through the conductive film 3 by making the thickness H1 of the chip body 1-1 equal to 300 micrometers to 600 micrometers. When the thickness H1 of the chip body 1-1 is less than 300 micrometers, the thickness of the driving circuit chip 1 is too thin, affecting the strength of the driving circuit chip 1; when the thickness H1 of the chip body 1-1 is greater than 600 micrometers, the thickness of the driving circuit chip 1 is too thick, reducing the heat dissipation performance of the driving circuit chip 1.

[0096] In an exemplary embodiment, the thickness h1 of chip pins 1-2 ranges from 9µm to 15µm (inclusive). For example, the thickness h1 of chip pins 1-2 ranges from 12µm to 13µm (inclusive).

[0097] In an exemplary embodiment, as shown in Figures 4 and 8, the display module of this disclosure further includes a cover plate 30 disposed on the light-emitting side of the display area of ​​the display panel. The thickness of the cover plate 30 is H4, and the thickness H1 of the chip body 1-1 and the thickness H4 of the cover plate satisfy the relationship: H1 < H4. For example, the thickness H1 of the chip body 1-1 and the thickness H4 of the cover plate 30 satisfy the relationship: H4 - H1 = 120um ~ 240um (inclusive). The thickness of the cover plate 30 is the average dimension of the cover plate 30 in the direction perpendicular to the display panel.

[0098] This embodiment of the disclosure shows that by making the thickness H1 of the chip body 1-1 less than the thickness H4 of the cover plate 30, the driving circuit chip 1 and the cover plate 30 will not interfere with each other.

[0099] In an exemplary embodiment, the thickness H4 of the cover plate ranges from 420 μm to 840 μm (inclusive). For example, the thickness H4 of the cover plate ranges from 700 μm to 800 μm (inclusive).

[0100] Figure 9 is a schematic cross-sectional view of a chip pad in a display module according to an exemplary embodiment of this disclosure. The chip pad shown in Figure 9 can be the same as the chip pad shown in Figure 7. In the exemplary embodiment, as shown in Figures 7 and 9, the thickness of the pad body 2-1 of the chip pad 2 is H2, and the thickness H2 of the pad body 2-1 and the thickness H1 of the chip body 1-1 of the driving circuit chip 1 satisfy the relationship: H2 > H1. The thickness of the pad body 2-1 is the average dimension of the pad body 2-1 in the direction perpendicular to the display panel.

[0101] This embodiment of the disclosure shows that the thickness H2 of the pad body 2-1 is greater than the thickness H1 of the chip body 1-1, so that when the driving circuit chip 1 is bonded to the chip pad 2, the chip pad 2 will not break.

[0102] In an exemplary embodiment, the thickness H2 of the pad body 2-1 ranges from 700um to 850um (inclusive). For example, the thickness H2 of the pad body 2-1 ranges from 750um to 800um (inclusive).

[0103] In an exemplary embodiment, the thickness of the bonding pin 2-2 of the chip pad 2 is h2, and the thickness h2 of the bonding pin 2-2 and the thickness H2 of the pad body 2-1 satisfy the relationship: h2 / H2 = 0.01% to 0.03% (inclusive). For example, the thickness h2 of the bonding pin 2-2 and the thickness H2 of the pad body 2-1 satisfy the relationship: h2 / H2 = 0.015% to 0.025% (inclusive). Here, the thickness of the bonding pin 2-2 is the average dimension of the bonding pin 2-2 in the direction perpendicular to the display panel.

[0104] In an exemplary embodiment, the thickness h2 of the bonding pin 2-2 and the thickness h1 of the chip pin 1-2 satisfy the relationship: h2 / h1 = 0.6% to 2.3% (inclusive). For example, the thickness h2 of the bonding pin 2-2 and the thickness h1 of the chip pin 1-2 satisfy the relationship: h2 / h1 = 1% to 2% (inclusive).

[0105] In an exemplary embodiment, the thickness h2 of the bonding pin 2-2 ranges from 0.1µm to 0.2µm (inclusive). For example, the thickness h2 of the bonding pin 2-2 ranges from 0.13µm to 0.17µm (inclusive).

[0106] Figure 10 is a cross-sectional structural diagram of a conductive film in a display module according to an exemplary embodiment of the present disclosure. The conductive film shown in Figure 10 can be the conductive film shown in Figure 7. In an exemplary embodiment, as shown in Figures 7 and 10, the thickness of the insulating body 3-1 in the conductive film 3 is H3. The thickness H3 of the insulating body 3-1, the thickness h1 of the chip pin 1-2, and the thickness h2 of the bonding pin 2-2 satisfy the relationship: H3 > h1 + h2. The thickness of the insulating body 3-1 is the average dimension of the insulating body 3-1 in the direction perpendicular to the display panel.

[0107] This embodiment of the module shows that the thickness H3 of the insulating body 3-1 is greater than the sum of the thickness h1 of the chip pin 1-2 and the thickness h2 of the bonding pin 2-2. This ensures that the insulating body 3-1 can fully fill the gap between the chip recess 1-3 and the pad recess 2-3, so that the insulating body 3-1 can make complete contact with the inner wall of the chip recess 1-3 and the inner wall of the pad recess 2-3, thus avoiding air bubbles in the chip recess 1-3 and the pad recess 2-3.

[0108] In an exemplary embodiment, the thickness H3 of the insulating body 3-1 and the thickness H1 of the chip body 1-1 satisfy the relationship: H3 < H1. The thickness H3 of the insulating body 3-1 and the thickness H2 of the pad body 2-1 satisfy the relationship: H3 < H2.

[0109] In an exemplary embodiment, the thickness H3 of the insulating body 3-1 and the thickness H1 of the chip body 1-1 satisfy the following relationship: H3 / H1 = 2% to 8.5% (inclusive). The thickness H3 of the insulating body 3-1 and the thickness H2 of the pad body 2-1 satisfy the following relationship: H3 / H2 = 1.4% to 3.6% (inclusive).

[0110] In an exemplary embodiment, the distance between the bottom wall of the chip recess 1-3 and the bottom wall of the corresponding pad recess 2-3 is L1. The distance L1 between the bottom wall of the chip recess 1-3 and the bottom wall of the corresponding pad recess 2-3 satisfies the relationship H3 of the insulating body 3-1: H3 > L1. Wherein, the distance L1 between the bottom wall of the chip recess 1-3 and the bottom wall of the corresponding pad recess 2-3 is the average distance between the bottom walls of the chip recess 1-3 and the bottom walls of the corresponding pad recess 2-3 in the direction perpendicular to the display panel (third direction Z).

[0111] This embodiment of the module shows that the thickness H3 of the insulating body 3-1 is greater than the distance L1 between the bottom wall of the chip recess 1-3 and the bottom wall of the corresponding pad recess 2-3. This ensures that the insulating body 3-1 can fully fill the gap between the chip recess 1-3 and the pad recess 2-3, so that the insulating body 3-1 can fully contact the inner wall of the chip recess 1-3 and the inner wall of the pad recess 2-3, thus avoiding the formation of air bubbles in the chip recess 1-3 and the pad recess 2-3.

[0112] In an exemplary embodiment, the distance L1 between the bottom wall of the chip recess 1-3 and the bottom wall of the corresponding pad recess 2-3 satisfies the relationship H3 of the insulating body 3-1: H3-L1 > 3um to 5um. For example, the distance L1 between the bottom wall of the chip recess 1-3 and the bottom wall of the corresponding pad recess 2-3 satisfies the relationship H3 of the insulating body 3-1: H3-L1 > 3.5um to 4.5um.

[0113] In an exemplary embodiment, the thickness H3 of the insulating body 3-1 ranges from 12µm to 25µm (inclusive). For example, the thickness H3 of the insulating body 3-1 ranges from 17µm to 20µm (inclusive).

[0114] In an exemplary embodiment, the length of the chip groove 1-3 of the driving circuit chip 1 in the first direction X is d1, and the diameter of the second particle 3-2-2 in the first direction X is d2. The length d1 of the chip groove 1-3 in the first direction X and the diameter d2 of the second particle 3-2-2 in the first direction X satisfy the relationship: d1 / d2 > 2 to 5 (including the end value). For example, the length d1 of the chip groove 1-3 in the first direction X and the diameter d2 of the second particle 3-2-2 in the first direction X satisfy the relationship: d1 / d2 > 3 to 4 (including the end value). Wherein, the length of the chip groove 1-3 in the first direction X is the average distance in the first direction X between the sidewall of one chip pin 1-2 closest to the other chip pin 1-2 and the sidewall of the other chip pin 1-2 closest to one chip pin 1-2; the diameter of the second particle 3-2-2 in the first direction X is the maximum size of the conductive particle 3-2 in the first direction X.

[0115] This embodiment of the disclosure shows that the module ensures that at least two second particles 3-2-2 are arranged along the first direction X between adjacent chip pins 1-2 by having a ratio of the length d1 of the chip groove 1-3 in the first direction X to the diameter d2 of the second particle 3-2-2 in the first direction X greater than 2 to 5. The at least two second particles 3-2-2 are mutually insulated, thereby ensuring that adjacent chip pins 1-2 are mutually insulated and avoiding short circuits.

[0116] In an exemplary embodiment, the diameter d2 of the second particle 3-2-2 in the first direction X ranges from d2 = 3 μm to 5 μm (inclusive). For example, the diameter d2 of the second particle 3-2-2 in the first direction X ranges from d2 = 3.5 μm to 4.5 μm (inclusive).

[0117] In an exemplary embodiment, the diameter of the first particle 3-2-1 in the direction perpendicular to the display panel (third direction Z) is d3, and the distance between chip pin 1-2 and the corresponding bonding pin 2-2 is L2. The diameter d3 of the first particle 3-2-1 in the direction perpendicular to the display panel (third direction Z) and the distance L2 between chip pin 1-2 and the corresponding bonding pin 2-2 satisfy the relationship: L2 < d3. Wherein, the distance L2 between chip pin 1-2 and the corresponding bonding pin 2-2 is the average distance between the end of chip pin 1-2 closest to the corresponding bonding pin 2-2 and the end of the corresponding bonding pin 2-2 closest to chip pin 1-2 in the direction perpendicular to the display panel (third direction Z); the diameter of the first particle 3-2-1 in the direction perpendicular to the display panel (third direction Z) is the maximum size of the first particle 3-2-1 in the direction perpendicular to the display panel (third direction Z).

[0118] In this embodiment of the display module, the distance L2 between the chip pin 1-2 and the corresponding bonding pin 2-2 is less than the diameter d3 of the first particle 3-2-1 in the direction perpendicular to the display panel (third direction Z). This allows the first particle 3-2-1 to be compressed by the chip pin 1-2 and the bonding pin 2-2, so that the first particle 3-2-1 contacts the chip pin 1-2 and the bonding pin 2-2 respectively in the direction perpendicular to the display panel (third direction Z), ensuring that the first particle 3-2-1 electrically connects the chip pin 1-2 and the bonding pin 2-2.

[0119] In an exemplary embodiment, the diameter d3 of the first particle 3-2-1 in the direction perpendicular to the display panel (third direction Z) and the distance L1 between the bottom wall of the chip groove 1-3 and the bottom wall of the corresponding pad groove 2-3 satisfy the relationship: L1 > d3.

[0120] In this embodiment of the display module, the distance L1 between the bottom wall of the chip recess 1-3 and the bottom wall of the corresponding pad recess 2-3 is greater than the diameter d3 of the first particle 3-2-1 in the direction perpendicular to the display panel (third direction Z). This ensures that the bottom wall of the chip recess 1-3 and the bottom wall of the corresponding pad recess 2-3 are mutually insulated, thereby preventing the bottom wall of the chip recess 1-3 and the bottom wall of the corresponding pad recess 2-3 from being electrically connected through the first particle 3-2-1.

[0121] In an exemplary embodiment, the diameter d3 of the first particle 3-2-1 in the direction perpendicular to the display panel (third direction Z) and the distance L1 between the bottom wall of the chip recess 1-3 and the bottom wall of the corresponding pad recess 2-3 satisfy the relationship: d3 / L1 = 20%~25% (inclusive). For example, the diameter d3 of the first particle 3-2-1 in the direction perpendicular to the display panel (third direction Z) and the distance L1 between the bottom wall of the chip recess 1-3 and the bottom wall of the corresponding pad recess 2-3 satisfy the relationship: d3 / L1 = 22%~23% (inclusive).

[0122] In this embodiment of the display module, the diameter d3 of the first particle 3-2-1 in the direction perpendicular to the display panel (third direction Z) and the distance L1 between the bottom wall of the chip groove 1-3 and the bottom wall of the corresponding pad groove 2-3 are 20% to 25%, which ensures that the bottom wall of the chip groove 1-3 and the bottom wall of the corresponding pad groove 2-3 are mutually insulated, thereby avoiding electrical connection between the bottom wall of the chip groove 1-3 and the bottom wall of the corresponding pad groove 2-3 through the first particle 3-2-1.

[0123] In an exemplary embodiment, the diameter d3 of the first particle 3-2-1 in the direction perpendicular to the display panel (third direction Z) ranges from 3µm to 5µm (inclusive). For example, the diameter d3 of the first particle 3-2-1 in the direction perpendicular to the display panel (third direction Z) ranges from 3.5µm to 4.5µm (inclusive).

[0124] In an exemplary embodiment, the bonding process between the driver circuit chip and the chip pad in the module may include the following operations.

[0125] (1) Provide the above-mentioned display panel, conductive film 3 and driving circuit chip 1. The display panel includes a bonding area, and the bonding area includes chip pads 2.

[0126] (2) Place the display panel, conductive film 3 and driving circuit chip 1 in the bonding machine, so that the conductive film 3 covers the chip pad 2 of the display panel, and place the driving circuit chip 1 on the side of the conductive film 3 away from the chip pad 2; then, place the buffer layer on the pressure head of the bonding machine.

[0127] (3) Adjust the parameters of the bonding machine, including at least one of temperature, pressure and bonding time; then, control the pressure head of the bonding machine to move toward the drive circuit chip 1; then, under the action of the pressure head of the bonding machine, the drive circuit chip 1 is bonded to the chip pad 2 through the conductive film 3.

[0128] This disclosure also provides a display device, including the aforementioned display module. The display device can be a near-eye display device, such as an AR / VR head-mounted display device. The display device can also be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0129] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display module, comprising: A display panel includes a display area and a bonding area located on one side of the display area, the bonding area including chip pads; A driver circuit chip is bonded to a chip pad. The driver circuit chip includes a chip body and a plurality of chip pins. The chip pins are disposed on the surface of the chip body near the chip pad and are configured to connect to the chip pad. A conductive film is disposed between the driving circuit chip and the chip pad, and the conductive film is configured to bond the driving circuit chip to the chip pad. The thickness of the chip body is H1, and the thickness of the chip pin is h1. The thickness of the chip body and the thickness of the chip pin satisfy the relationship: h1 / H1 = 1.5%~2.5%.

2. The display module according to claim 1, wherein, The thickness of the chip body ranges from H1 to 300um to 600um.

3. The display module according to claim 1, wherein, The thickness of the chip pins ranges from 9µm to 15µm.

4. The display module according to claim 1 further includes a cover plate, the cover plate being disposed on the light-emitting side of the display area of ​​the display panel, the thickness of the cover plate being H4, and the thickness of the cover plate satisfying the relationship between the thickness of the chip body and the thickness of the chip body: H1 < H4.

5. The display module according to claim 4, wherein, The thickness of the cover plate ranges from H4 to 420 μm to 840 μm.

6. The display module according to any one of claims 1 to 5, wherein, The chip pad includes a pad body and multiple bonding pins. The bonding pins are disposed on the surface of the pad body near the driver circuit chip. The bonding pins are disposed corresponding to the chip pins and are configured to be bonded to the corresponding chip pins.

7. The display module according to claim 6, wherein, The thickness of the pad body is H2, and the thickness of the pad body and the thickness of the chip body satisfy the relationship: H2 > H1.

8. The display module according to claim 6, wherein, The thickness of the pad body is H2, and the thickness range of the pad body is: H2 = 700um to 850um.

9. The display module according to claim 6, wherein, The thickness of the pad body is H2, and the thickness of the bonding pin is h2. The thickness of the bonding pin and the thickness of the pad body satisfy the following relationship: h2 / H2 = 0.01% to 0.03%.

10. The display module according to claim 6, wherein, The thickness of the bonding pin is h2, and the thickness range of the bonding pin is: h2 = 0.1um to 0.2um.

11. The display module according to claim 6, wherein, The conductive film includes an insulating body and a plurality of conductive particles disposed within the insulating body. The insulating body is disposed between the driving circuit chip and the chip pad. The plurality of conductive particles include a first particle, which is located in the insulating body between the chip pin and the bonding pin. The first particle is connected to the chip pin and the bonding pin respectively.

12. The display module according to claim 11, wherein, The thickness of the insulating body is H3, and the thickness of the insulating body and the thickness of the chip body satisfy the relationship: H3 < H1; and / or, the thickness of the insulating body and the thickness of the pad body satisfy the relationship: H3 < H2.

13. The display module according to claim 11, wherein, The thickness of the insulating body is H3, the thickness of the bonding pin is h2, and the thicknesses of the insulating body, the chip pin, and the bonding pin satisfy the relationship: H3 > h1 + h2.

14. The display module according to claim 11, wherein, The thickness of the insulating body is H3, and the thickness range of the insulating body is: H3 = 12um to 25um.

15. The display module according to claim 11, wherein, The driving circuit chip further includes a chip recess, which is disposed between adjacent chip pins. The chip pad further includes a pad recess, which is disposed between adjacent bonding pins. The chip recess and the pad recess are correspondingly disposed. The distance between the bottom wall of the chip recess and the bottom wall of the corresponding pad recess is L1. The thickness of the insulating body is H3. The distance between the bottom wall of the chip recess and the bottom wall of the corresponding pad recess and the thickness of the insulating body satisfy the relationship: H3 > L1.

16. The display module according to claim 15, wherein, The distance between the bottom wall of the chip groove and the bottom wall of the corresponding pad groove and the thickness of the insulating body satisfy the following relationship: H3-L1>3um~5um.

17. The display module according to claim 15, wherein, The diameter of the first particle in the direction perpendicular to the display panel is d3. The diameter of the first particle in the direction perpendicular to the display panel and the distance between the bottom wall of the chip groove and the bottom wall of the corresponding pad groove satisfy the relationship: L1 > d3.

18. The display module according to claim 17, wherein, The diameter of the first particle in the direction perpendicular to the display panel and the distance between the bottom wall of the chip recess and the bottom wall of the corresponding pad recess satisfy the following relationship: d3 / L1 = 20%~25%.

19. The display module according to claim 11, wherein, The diameter of the first particle in the direction perpendicular to the display panel is d3, and the distance between the chip pin and the corresponding bonding pin is L2. The diameter of the first particle in the direction perpendicular to the display panel and the distance between the chip pin and the corresponding bonding pin satisfy the relationship: L2 < d3.

20. The display module according to claim 11, wherein, The diameter of the first particle in the direction perpendicular to the display panel is d3, and the range of the diameter of the first particle in the direction perpendicular to the display panel is: d3 = 3um to 5um.

21. The display module according to claim 11, wherein, The driving circuit chip further includes a chip recess, which is disposed between adjacent chip pins. The chip pad further includes a pad recess, which is disposed between adjacent bonding pins. The chip recess and the pad recess are correspondingly disposed. The plurality of conductive particles include a second particle, which is located in the insulating body between the chip recess and the pad recess. The second particles are spaced apart along a first direction. The length of the chip recess in the first direction is d1, and the diameter of the second particle in the first direction is d2. The length of the chip recess in the first direction and the diameter of the second particle in the first direction satisfy the relationship: d1 / d2 > 2~5.

22. A display device comprising a display module as described in any one of claims 1 to 21.

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