Process for the monolithic fabrication of a double-gate bidirectional power transistor with alternative control

Abstract

The invention relates to a process for fabricating an integrated circuit (IC) comprising a bidirectional field-effect transistor (1), comprising the following steps: (I) providing a stack of layers (EC) deposited on a substrate (SUB); (II) fabricating the bidirectional transistor (T1) by forming: • at least two gates (G1, G2) in the barrier layer (C1); • a first source (S1) and a second source (S2); • and a channel region (ZC) formed in the channel layer (C2); (III) fabricating, on the same stack of layers (EC), a first bias transistor (Ta) and a second bias transistor (Tb), the bidirectional transistor, the first bias transistor (Ta) and the second bias transistor (Tb) being monolithic; (IV) electrically connecting: the source (Sa) of the first bias transistor (Ta) to the substrate, and the source (Sb) of the second bias transistor (Tb) to the substrate (SUB).

Description

DESCRIPTION Monolithic manufacturing process for a bidirectional double-gate power transistor with alternating control Scope

[0001] The invention relates to the monolithic integration of common-drain, heterojunction, bidirectional power transistors on a single substrate. More particularly, the invention relates to a method for manufacturing such transistors with alternating bias of the bidirectional transistor's sources to the substrate.

[0002] The invention is particularly applicable to electrical power conversion circuits and systems, notably in the field of electric vehicles, where high-performance power electronics components are required to minimize losses and operate efficiently at high frequencies. In this context, power electronics components based on GaN-on-silicon technology are among the most promising solutions in terms of performance and cost. This technology relies on the epitaxial growth of GaN layers on silicon substrates, a well-established technological process that allows for the production of GaN layers of optimal thickness at low cost. The physical properties of GaN, particularly its low specific resistance, allow for higher densities than silicon, thus significantly improving component efficiency.High electron mobility field-effect transistors (HEMTs), based on the AIGaN / GaN heterojunction, are distinguished by their enhanced performance, making them well-suited for power electronics. They enable high switching frequencies, allowing for smaller passive components and increased power density. Furthermore, high-frequency, high-power systems often utilize HEMT-type side structures. These structures allow for the integration of a second gate region within the transistor without complicating the design or fabrication. Dual-gate HEMTs thus enable the use of compact and efficient matrix topologies, offering excellent conversion efficiency.

[0003] To better understand the technical problem raised, Figure 1 illustrates a cross-sectional view of a state-of-the-art, dual-gate, common-drain power transistor T1'. The transistor T1' is fabricated on a silicon substrate SUB' which acts as a support. The transistor T1' comprises the following stack of layers, starting from the substrate SUB': - a C3' buffer layer to adjust the crystal structure during epitaxial growth. For example, the C3 buffer layer is made of gallium nitride alloy with aluminum GaN / AIGaN. - a C2' channel layer corresponding to the transistor channel. It is made of a high electron mobility semiconductor material, such as gallium nitride GaN. - a confinement layer C1' to generate charge carriers in the channel layer. The confinement layer C1' is made of a semiconductor material having a larger energy gap than the semiconductor material of the channel layer C2'. For example, the confinement layer C1' is made of a quaternary alloy of type III-V semiconductors.

[0004] The confinement layer C1' forms a heterojunction with the channel layer C2'. The band gap difference creates a quantum well at their interface. Electrons are confined within this quantum well to form a two-dimensional electron gas (2DEG) which constitutes the conduction channel located at this interface. The transistor T1' comprises two laterally spaced ohmic electrodes, S1 and S2. Two control electrodes, commonly called gates, G1 and G2 respectively, are positioned between the two ohmic electrodes S1 and S2. The central node between the two gates G1 and G2 constitutes a common drain. Following the chosen common-drain architecture, both current and voltage are therefore controlled by a single channel.

[0005] In the case of dual-gate heterojunction transistors as illustrated in Figure 1, the silicon substrate SUB' must be connected to one of two sources S1, S2 depending on the direction of the blocked electric field. In this context, dual-gate power transistors fabricated on a common semiconductor substrate are subject to gate-back effects leading to current collapse and degraded operating characteristics depending on the bias of the applied substrate. Therefore, proper substrate biasing is essential to ensure efficient and symmetrical bidirectional operation, particularly in the state-of-the-art T1' transistor architecture.

[0006] French patent FR3053832 proposes a common-drain, two-gate power transistor in which the substrate's rear face features an aperture filled with a dielectric material separating two PN diodes fabricated within the substrate by doping. Each diode is configured to connect the substrate to an associated source contact of the transistor. The drawback of this solution is its complexity and the resulting fragility of the structure. Indeed, the solution proposed by this patent requires etching operations on the transistor's rear face and doping operations also performed on the rear face opposite the transistor. This makes the process more complex and necessitates inverting the semiconductor wafer, thus introducing greater reliability risks during manufacturing.Furthermore, creating openings in the substrate body for each transistor in an integrated circuit significantly weakens the overall circuit's reliability from both a mechanical and electronic standpoint. Moreover, the presence of the dielectric-filled opening makes biasing the entire substrate impossible. See also US patents 2012 / 217542 and 2009 / 206363.

[0007] To overcome the limitations of existing solutions, the invention proposes a method for manufacturing a common-drain, two-gate power transistor in which a first biasing transistor connects the first source to the substrate, and a second biasing transistor connects the second source to the substrate. The biasing transistors dynamically adapt the substrate bias of the bidirectional two-gate transistor by automatically connecting it to the active source (S1 or S2) depending on the current direction. The biasing transistors are monolithically integrated with the bidirectional transistor and are manufactured concurrently with the bidirectional transistor during the same fabrication process.This monolithic solution simplifies manufacturing by integrating the biasing transistors directly with the transistor, eliminating back-etching and back-doping steps, thereby improving mechanical and electrical robustness. The device according to the invention also optimizes substrate biasing, reducing on-state resistance (RON) by 20% and enabling faster, higher-frequency operation compared to conventional solutions.

[0008] The invention relates to a method for manufacturing an integrated circuit comprising a bidirectional field-effect transistor comprising the following steps: (I) providing a stack of layers deposited on a substrate in a stacking direction orthogonal to the plane of the substrate; the stack of layers comprising: a barrier layer made of a first type III-V semiconductor material disposed on a channel layer made of a second type III-V semiconductor material having an energy gap lower than that of the first semiconductor material; the interface between the barrier layer and the channel layer forming a heterojunction; - (He) manufactures the bidirectional transistor by forming: at least two grids in the barrier layer; o a first source and a second source; o and a channel zone formed in the channel layer; the two grids being arranged between, on the one hand, the first source and, on the other hand, the second source; - (Ill) fabricate, on the same stack of layers, a first biasing transistor having a gate, a source and a drain; and fabricate, on the same stack of layers, a second biasing transistor having a gate, a source and a drain so that the bidirectional transistor, the first biasing transistor and the second biasing transistor are monolithic; - (IV) connect electrically: o the source of the first biasing transistor to the substrate; o the source of the second biasing transistor to the substrate; o the drain of the first bias transistor to the first source; o and the drain of the second bias transistor to the second source.

[0009] According to a particular aspect of the invention, in step (III), an ohmic contact adjacent to the first gate forms the first source of the bidirectional transistor, an ohmic contact adjacent to the second gate forms the second source of the bidirectional transistor, an ohmic contact adjacent to the first source forms the drain of the first biasing transistor, and an ohmic contact adjacent to the second source forms the drain of the second biasing transistor. Thus, an integrated circuit is obtained that allows the ohmic contacts of the biasing transistors to be formed independently of the ohmic contacts of the bidirectional transistor. The ohmic contacts of the biasing transistors can therefore be formed with dimensions distinct from those of the ohmic contacts of the bidirectional transistor.Advantageously, the ohmic contacts of the biasing transistors can be formed with smaller dimensions than those of the bidirectional transistor, for example, to use less material for their fabrication. Advantageously, the ohmic contacts of the biasing transistors can be positioned and / or oriented more freely relative to the ohmic contacts of the bidirectional transistor. In other words, the position and / or orientation of the ohmic contacts of the bidirectional transistor no longer dictates the position and / or orientation of the ohmic contacts of the biasing transistors. For example, the ohmic contacts of the biasing transistors can be positioned on either side of the bidirectional transistor along a Y-direction perpendicular to an X-direction passing through the gates of the bidirectional transistor.For example, the ohmic contacts of the biasing transistors can also be oriented along the X direction, making the integrated circuit more compact in the X direction. This provides a method and an integrated circuit that allow the dimensions of the integrated circuit to be adapted to the dimensions of an electronic device in which it is integrated.

[0010] According to a particular aspect of the invention, in step (III), the first bias transistor and the second bias transistor are placed so that the bidirectional transistor is arranged between the first bias transistor on one side and the second bias transistor on the opposite side in a direction parallel to the plane of the substrate.

[0011] According to a particular aspect of the invention, the formation of the gates of the bidirectional transistor is carried out simultaneously with the formation of the gate of the first biasing transistor and the gate of the second biasing transistor.

[0012] According to a particular aspect of the invention, the formation of the sources of the bidirectional transistor is carried out simultaneously with the formation of the source and drain of the first biasing transistor and the source and drain of the second biasing transistor.

[0013] The invention relates to a monolithic integrated circuit fabricated on a substrate comprising: a bidirectional field-effect transistor comprising: a heterojunction formed by a barrier layer in a first type III-V semiconductor material disposed on a channel layer in a second type III-V semiconductor material having an energy gap lower than that of the first semiconductor material; o a first source and a second source; o two grids arranged between the first source on one side and the second source on the other side; - a first biasing transistor having a drain electrically connected to the first source of the bidirectional transistor and a source electrically connected to the substrate; a second biasing transistor having a drain electrically connected to the second source of the bidirectional transistor and a source electrically connected to the substrate; the bidirectional transistor, the first biasing transistor and the second biasing transistor being monolithic.

[0014] According to a particular aspect of the invention, an ohmic contact adjacent to the first gate forms the first source of the bidirectional transistor, an ohmic contact adjacent to the second gate forms the second source of the bidirectional transistor, an ohmic contact adjacent to the first source forms the drain of the first biasing transistor, and an ohmic contact adjacent to the second source forms the drain of the second biasing transistor.

[0015] According to a particular aspect of the invention, the bidirectional transistor is arranged between the first biasing transistor on one side and the second biasing transistor on the opposite side in a direction parallel to the plane of the substrate.

[0016] According to one particular aspect of the invention, the circuit further comprises control means configured to: - apply a first bias voltage on the first source and a second bias voltage on the second source greater than the first bias voltage; - and put the first bias transistor in a conducting state and the second bias transistor in a blocking state.

[0017] According to one particular aspect of the invention, the circuit further comprises control means configured to: - apply a first bias voltage on the first source and a second bias voltage on the second source lower than the first bias voltage; - and put the first bias transistor in a blocking state and the second bias transistor in a conducting state.

[0018] According to a particular aspect of the invention, the geometric width-to-length ratio of the first biasing transistor or the second biasing transistor is less than 5% of the geometric width-to-length ratio of the bidirectional transistor.

[0019] Other features and advantages of the present invention will become more apparent from the following description in relation to the following attached drawings.

[0020] Figure 1 illustrates a cross-sectional view of a state-of-the-art dual-gate power lateral transistor. This figure has already been described.

[0021] Figure 2 illustrates the flowchart of a manufacturing process according to the invention.

[0022] Figures 3a to 3f illustrate an example of the steps in the manufacturing process according to the invention.

[0023] Figure 4a illustrates a top view of the integrated circuit according to the invention.

[0024] Figure 4b illustrates an electrical diagram of the integrated circuit according to the invention.

[0025] In the figures illustrating the invention, the horizontal is represented by the X and Y directions of an orthogonal coordinate system (X, Y, Z). The Z direction of this orthogonal coordinate system represents the vertical direction. Hereafter, terms such as "upper," "lower," "above," "below," "top," and "bottom" are defined with respect to this Z direction. The terms "left" and "right" are defined with respect to the X direction. The terms "front" and "back" are defined with respect to the Y direction. Hereafter, the term "thickness" refers to the maximum thickness of an element along the Z direction, also known as the stacking direction. The term "width" refers to the dimension of a layer along the X direction.

[0026] Figure 2 illustrates the flowchart of a manufacturing process according to the invention.

[0027] The first step (I) consists of providing or fabricating a stack of EC layers deposited on a semiconductor substrate, advantageously silicon. The EC stack comprises a barrier layer C1 made of a first III-V type semiconductor material deposited on a channel layer C2 made of a second III-V type semiconductor material. The second semiconductor material has a smaller energy gap than the first semiconductor material such that the interface between the barrier layer C1 and the channel layer C2 forms a heterojunction. For example, the barrier layer C1 is made of AIGaN and the channel layer C2 of GaN. Advantageously, the EC stack further comprises a passivation layer C4 made of a dielectric material such as SiU2 deposited on the barrier layer C1 to electrically insulate and protect it during the fabrication process. Advantageously, the stack further includes a C3 buffer layer confined between the C2 channel layer and the SUB silicon substrate. The C3 buffer layer allows for adjustment of the crystal lattice during epitaxial growth of the C2 channel layer on a silicon substrate.

[0028] The second step (II) consists of manufacturing the bidirectional transistor T1 by implementing the following substeps without any chronological order requirement: forming at least two gates G1, G2 in the barrier layer C1; forming a first ohmic contact S1 in the barrier layer C1, which acts as a first source; and forming a second ohmic contact S2 in the barrier layer C1, which acts as a second source. The two gates G1, G2 are positioned between, on the one hand, the first ohmic contact S1 and, on the other hand, the second ohmic contact S2. The substeps of manufacturing the bidirectional transistor T1 are not necessarily performed consecutively during the execution of the various steps of the manufacturing process according to the invention. The conduction channel formation zone when the bidirectional transistor is in the on-state is located in the channel layer C2 below the heterojunction of said layer with the barrier layer C1.

[0029] The third step (III) consists of fabricating, on the same stack of EC layers, a first biasing transistor Ta and a second biasing transistor Tb configured to control the biasing of the SUB substrate according to the direction of the current in the bidirectional transistor T1. The third step is executed by implementing the following substeps: forming, for the first biasing transistor Ta, a gate Ga, next to the first source S1 of the bidirectional transistor T1; forming, for the second biasing transistor Tb, a gate Gb next to the second source S2 of the bidirectional transistor T1; fabricating the drain Da and the source Sa of the first biasing transistor Ta by placing the drain Da between the gate Ga and the first source S1; and fabricating the drain Db and the source Sb of the second biasing transistor Tb by placing the drain Db between the gate Gb and the second source S2.The fabrication of the Sa, Sb sources and the Da, Db drains is carried out by etching several cavities in the stack up to the C2 channel layer and filling them with an electrical conductor forming a plurality of ohmic contacts.

[0030] The fourth step (IV) consists of electrically connecting the source Sa of the first biasing transistor Ta to the SUB substrate; connecting the source Sb of the second biasing transistor Tb to the SUB substrate; connecting the drain Da of the first biasing transistor Ta to the first source S1; and finally, connecting the drain Db of the second biasing transistor Tb to the second source S2. The connections to sources S1 and S2 are made by depositing metallic traces. The connections of the biasing transistors Ta and Tb to the SUB substrate are made by connecting trenches that extend through the stack of EC layers to the SUB substrate.

[0031] The biasing transistors Ta, Tb allow the biasing of the SUB substrate to be adapted according to the direction of conduction in the bidirectional transistor T1, such that the SUB substrate is common to both gates G1 and G2. The method according to the invention thus enables a monolithic assembly of the bidirectional two-gate transistor T1 while overcoming the problems associated with the variable biasing of the SUB substrate depending on the direction of the current in the transistor. Monolithic integration reduces the size of the integrated circuit (IC) comprising a plurality of dual-gate transistors compared to state-of-the-art solutions. Furthermore, monolithic integration allows for faster transistor switching and thus enables high-frequency operation.The biasing transistors Ta,Tb allow for integrated control of the biasing of the SUB substrate: Indeed, when the electrons of the conduction channel move from the first source S1 to the second source S2, the first biasing transistor Ta is put into a conducting state and the second biasing transistor Tb into a blocking state so that the SUB substrate is connected to the first source S1. Conversely, the first biasing transistor Ta is switched on and the second biasing transistor Tb is switched on, so that the substrate SUB is connected to the second source S2. This configuration minimizes the on-state resistance after the bidirectional transistor T1 switches off compared to state-of-the-art solutions. For example, a 20% reduction in RON resistance is observed compared to a two-gate bidirectional transistor in which the substrate is simultaneously short-circuited to both the first and second sources S1 and S2.

[0032] The monolithic implementation of the Ta,Tb bias transistors allows them to be manufactured simultaneously with the fabrication of transistor T1. The use of the Ta,Tb bias transistors in the context of the invention avoids etching and doping operations on the SUB substrate, which offers several advantages: simplifying the manufacturing process by reducing the number of steps, improving the mechanical and electrical robustness of the integrated circuit by avoiding etching of the SUB substrate; and providing physical and electrical continuity of the SUB substrate, simplifying its biasing.

[0033] To better understand the invention, Figures 3a to 3f illustrate an example of the steps in the manufacturing process according to the invention. The chronological order of the substeps is for illustrative purposes only and is not limiting.

[0034] The first step (i), illustrated in Figure 3a, consists of providing or fabricating the stack of EC layers deposited on a semiconductor SUB substrate described in the first step (I) of Figure 2. The interface between the barrier layer C1 and the channel layer C2 creates a discontinuity in the energy bands, which leads to the formation of a two-dimensional (2DEG) electron gas in the channel layer C2 near the junction. This gas is a region where electrons can move with very high mobility because they do not undergo collisions with atoms, unlike in a conventional conductor. When the transistor T1 is in a conducting state, the two-dimensional electron gas forms a conduction channel under the C1 / C2 interface, through which electrons can move rapidly. The C1 and C2 layers, made of III-V type semiconductor materials, are fabricated by epitaxial growth on the silicon SUB substrate.

[0035] The second step (ii), illustrated in Figure 3b, consists of forming two gates G1 and G2 in the barrier layer C1. Simultaneously, during the second step (ii), the Ga gate of the first biasing transistor Ta and the Gb gate of the second biasing transistor are fabricated. The formation of the G1, G2, Ga, and Gb gates is achieved by etching the EC stack on the side of the passivation layer C4 to create four cavities extending to the channel layer C2. An oxidation process deposits a dielectric layer on the inner walls of these cavities. The remaining volume of each cavity is then filled with a metal, such as titanium nitride or a copper-aluminum alloy. This results in the two G1 and G2 gates of the bidirectional transistor T1, surrounded by the Ga gate on one side and the Gb gate on the other.This simultaneous realization of the four grids means that the second step (ii) is at the same time a sub-step of the step (III) of manufacturing the biasing transistors Ta,Tb and of the second step (II) of manufacturing the transistor T1 of the process according to the invention.

[0036] The third step (iii), illustrated in Figure 3c, consists of forming the drain / source pair for each biasing transistor Ta,Tb and simultaneously fabricating the first source S1 and the second source S2. Each of these fabricated electrodes is made by an ohmic contact with at least the heterojunction C1 / C2 and, more advantageously, up to the channel layer C3. The formation of each ohmic contact is achieved by etching the stack EC on the side of the passivation layer C4 to create six cavities extending at least to the channel layer C2. The depth of each cavity does not exceed 1000 nm relative to the heterojunction formed by the layers C1 and C2. The location of the cavities is chosen to obtain the following arrangement: the two gates G1,G2 are positioned between, on the one hand, a first pair of cavities and, on the other hand, a second pair of cavities along the (X,Y) plane of the substrate SUB.The Ga grid is positioned between the first pair of cavities and a cavity. The Gb grid is positioned between the second pair of cavities and a cavity. Each cavity is then filled with an electrically conductive material having an electron affinity lower than that of the first semiconductor material in the barrier layer C1 and lower than that of the second semiconductor material in the channel layer C2. More specifically, when the barrier layer C1 is made of AIGaN and the channel layer C2 is made of GaN, the second electrically conductive material in each ohmic contact has a work function of 4 eV or less. For example, the second electrically conductive material in each ohmic contact is chosen from titanium or a titanium-containing alloy such as a titanium-aluminum alloy.

[0037] Alternatively, each fabricated ohmic contact is formed by a stacking of a plurality of layers all made of conductive materials with an output work less than the electronic affinity of the first semiconductor material of the barrier layer C1 and less than the electronic affinity of the second semiconductor material of the channel layer C2.

[0038] As an example, the first electrically conductive material is deposited in the cavity by thermal evaporation or sputtering. The thickness of each ohmic contact is between 50 nm and 100 nm.

[0039] The ohmic contact adjacent to the first gate G1 forms the first source S1 of transistor T1. The ohmic contact adjacent to the second gate G2 forms the second source S2 of transistor T1. The ohmic contact adjacent to the first source S1 forms the drain Da of the first biasing transistor Ta. The ohmic contact adjacent to the second source S2 forms the drain Db of the second biasing transistor Tb. The ohmic contact adjacent to the gate Ga and opposite the drain Da forms the source Sa of the first biasing transistor Ta. The ohmic contact adjacent to the gate Gb and opposite the drain Db forms the source Sb of the second biasing transistor Ta. This simultaneous fabrication of the six electrodes means that the third step (iii) is also a substep of step (III) for manufacturing the biasing transistors Ta and Tb, and of the second step (II) for manufacturing transistor T1 of the process according to the invention.

[0040] For example, the ohmic contact forming the drain Da of the first biasing transistor Ta is distinct from the first ohmic contact forming the first source S1 of the bidirectional transistor T1. In other words, the drain Da of the first biasing transistor Ta is located at a non-zero distance from the first source S1 of the bidirectional transistor T1. As another example, the ohmic contact forming the drain Db of the second biasing transistor Tb is distinct from the second ohmic contact forming the second source S2 of the bidirectional transistor T1. In other words, the drain Db of the second biasing transistor Tb is located at a non-zero distance from the second source S2 of the bidirectional transistor T1. For example, by non-zero distance, we mean a distance between 10 microns and a few hundred microns, the distance being measured along the X direction.

[0041] The fourth step (iv), illustrated in figure 3d, consists of depositing a dielectric ENC encapsulation layer on the resulting structure to protect it mechanically and insulate it electrically.

[0042] The fifth step (v), illustrated in Figure 3e, consists of fabricating a V1,V2 connection trench for each associated biasing transistor. The first V1 connection trench is adjacent to the Sa source of the first biasing transistor Ta. The second V2 connection trench is adjacent to the Sb source of the second debiasing transistor Tb. The fabrication of each V1,V2 connection trench comprises the following substeps: a first substep (va) which consists of etching a cavity along the Z stacking direction and through the EC stacking layers until reaching the SUB substrate. The cavity has a width between 10 pm and 100 pm and a depth between 2 pm and 20 pm. The second substep (vb) consists of depositing a dielectric layer on the inner side walls of said cavity. The third substep (v.c) consists of etching the dielectric layer deposited on the surface of the cavity floor to create an opening that leads to the SUB substrate. The fourth substep (vd) consists of filling the cavity with an electrically conductive material, for example, a metallic deposit. In the fifth substep (ve), the excess metal deposited in the cavity is planarized by chemical-mechanical polishing to obtain a thickness equal to the thickness of the ENC encapsulation layer.

[0043] The sixth step (vi), illustrated in Figure 3f, consists of depositing a first electrically conductive track P1, for example made of copper or titanium, interconnecting the first connection trench V1 and the source Sa of the first biasing transistor Ta. Simultaneously, the sixth step further includes the depositing of a second electrically conductive track P2, for example made of copper or titanium, interconnecting the first source S1 and the drain Da of the first biasing transistor Ta. Simultaneously, the sixth step further includes the depositing of a third electrically conductive track P3, for example made of copper or titanium, interconnecting the second connection trench V2 and the source Sb of the second biasing transistor Tb.Simultaneously, the sixth step further comprises the deposition of a fourth electrically conductive track P4, for example made of copper or titanium, interconnecting the second source S2 and the drain Db of the second biasing transistor Tb. The fifth and sixth steps together constitute step (III) of the method according to the invention.

[0044] Optionally, the sixth step also includes the deposition of a metallic electrode, for example copper or titanium, on the first grid G1, on the second grid G2 and on the Ga,Gb grids of Ta,Tb biasing transistors.

[0045] The method according to the invention thus makes it possible to manufacture an integrated circuit comprising a monolithic dual-gate power transistor in which the biasing of the substrate with respect to the first source S1 or the second source S2 is better controlled. The manufacturing method according to the invention does not require etching operations on the back side of the substrate, which solves the substrate biasing problem while ensuring the mechanical and electronic robustness of the integrated circuit (IC) and without complicating the manufacturing process.

[0046] Figure 4a illustrates a top view of the integrated circuit (IC) according to the invention along the (X,Y) plane parallel to the substrate plane. The bidirectional transistor T1 and the biasing transistors Ta, Tb are implemented using a plurality of identical microstructures called "fingers." A finger corresponds to multiplying the effective channel width of a transistor by distributing the total width W across several smaller parallel "fingers" dg1, each having the same channel length. Thus, for each transistor, the geometric width-to-length ratio is proportional to the number of fingers used. The integrated circuit according to the invention allows for dynamic control of the substrate bias while maintaining a compact surface area compared to prior art solutions.Indeed, in the integrated circuit (IC) according to the invention, the number of fingers of any one of the biasing transistors Ta or Tb is less than 5% of the number of fingers of the bidirectional transistor T1, and more advantageously less than 2.5% of the number of fingers of the bidirectional transistor T1. This implies that the area occupied along the (X,Y) plane increases by only 5% compared to a solution in which the substrate bias is not controlled. In other words, the circuit according to the invention allows dynamic adjustment of the substrate bias according to the direction of the current with a width-to-length ratio Wi / Li of the first biasing transistor Ta that is less than 5% of the width-to-length ratio Wi / Li of the bidirectional transistor T1, and advantageously less than 2.5%.Similarly, the geometric width-to-length ratio Wïb / Lïb of the second biasing transistor Tb is less than 5% of the geometric width-to-length ratio WTI / LTI of the bidirectional transistor T1, and advantageously less than 2.5%.

[0047] Figure 4b illustrates an electrical diagram of the integrated circuit IC according to the invention. The integrated circuit IC comprises a bidirectional transistor T1 with dual gates G1, G2, the first bias transistor Ta, and the second bias transistor Tb, which are monolithic and connected as described in the invention. The integrated circuit IC further comprises control means CONT configured to bias the sources S1, S2 of the bidirectional transistor T1 and control the state of the bias transistors Ta, Tb according to the direction of the current in the conduction channel of the bidirectional transistor T1.

[0048] More specifically, when the bidirectional transistor T1 is intended to conduct current from the first source S1 to the second source S2, the control means CONT are configured to apply a first bias voltage Vsi to the first source S1 and a second bias voltage Vs2 to the second source S2 that is lower than the first bias voltage Vsi. The control means CONT are also configured to put the first bias transistor Ta in a blocking state and the second bias transistor Tb in a conducting state. This allows the substrate SUB to be connected to the second source S2, which has the lowest potential. This configuration results in a considerable reduction in the on-state resistance after the bidirectional transistor T1 is blocked, compared to state-of-the-art solutions.Conversely, when the bidirectional transistor T1 is intended to conduct current from the second source S2 to the first source S1, the control means CONT are configured to apply a first bias voltage Vsi to the first source S1 and a second bias voltage Vs2 to the second source S2 that is higher than the first bias voltage Vsi. The control means CONT are also configured to set the first bias transistor Ta to a conducting state and the second bias transistor Tb to a blocking state. This allows the substrate SUB to be connected to the first source S1, which has the lowest potential. This configuration results in a considerable reduction in the on-state resistance after the bidirectional transistor T1 is blocked, compared to state-of-the-art solutions.

Claims

DEMANDS 1. A method for manufacturing an integrated circuit (IC) comprising a bidirectional field-effect transistor (1) comprising the following steps: (I) provide a stack of layers (EC) deposited on a substrate (SUB) along a stacking direction (Z) orthogonal to the plane of the substrate (X,Y); the stack of layers (EC) comprising: a barrier layer (C1) made of a first type III-V semiconductor material disposed on a channel layer (C2) made of a second type III-V semiconductor material having an energy gap lower than that of the first semiconductor material; the interface between the barrier layer (C1) and the channel layer (C2) forming a heterojunction; (II) fabricate the bidirectional transistor (T1) by forming: o at least two grids (G1, G2) in the barrier layer (C1); o a first source (S1) and a second source (S2); o and a channel zone (CZ) formed in the channel layer (C2); the two grids (G1, G2) being arranged between on the one hand the first source (S1) and on the other hand the second source (S2); (III) fabricate, on the same stack of layers (EC), a first biasing transistor (Ta) having a gate (Ga), a source (Sa) and a drain (Da); and fabricate, on the same stack of layers (EC), a second biasing transistor (Tb) having a gate (Gb), a source (Sb) and a drain (Db) such that the bidirectional transistor, the first biasing transistor (Ta) and the second biasing transistor (Tb) are monolithic, in which an ohmic contact adjacent to the first gate (G1) forms the first source (S1) of the bidirectional transistor (T1), an ohmic contact adjacent to the second gate (G2) forms the second source (S2) of the bidirectional transistor (T1), an ohmic contact adjacent to the first source (S1) forms the drain (Da) of the first biasing transistor (Ta), and an ohmic contact adjacent to the second source (S2) forms the drain (Db) of the second biasing transistor (Tb); (IV) electrically connect: o the source (Sa) of the first biasing transistor (Ta) to the substrate; o the source (Sb) of the second biasing transistor (Tb) to the substrate (SUB); o the drain (Da) of the first biasing transistor (Ta) to the first source (51); o and the drain (Db) of the second biasing transistor (Tb) to the second source (52).

2. A manufacturing method according to claim 1 in which, during step (III), the first biasing transistor (Ta) and the second biasing transistor (Tb) are placed so that the bidirectional transistor (T1) is arranged between the first biasing transistor (Ta) on one side and the second biasing transistor (Tb) on the opposite side in a direction parallel (X) to the plane of the substrate (SUB).

3. A manufacturing method according to any one of claims 1 or 2 in which the formation of the gates (G1, G2) of the bidirectional transistor (T1) is carried out simultaneously with the formation of the gate (Ga) of the first biasing transistor (Ta) and the gate (Gb) of the second biasing transistor (Tb).

4. A manufacturing method according to any one of claims 1 to 3 in which the formation of the sources (S1, S2) of the bidirectional transistor (T1) is carried out simultaneously with the formation of the source (Sa) and the drain (Da) of the first biasing transistor (Ta) and with the source (Sb) and the drain (Db) of the second biasing transistor (Tb).

5. Monolithic integrated circuit (IC) fabricated on a substrate (SUB) comprising: - a bidirectional field-effect transistor (T1) comprising: o a heterojunction formed by a barrier layer (C1) in a first type III-V semiconductor material disposed on a channel layer (C2) in a second type III-V semiconductor material having an energy gap lower than that of the first semiconductor material; o a first source (S1) and a second source (S2); o two grids (G1, G2) arranged between on the one hand the first source (S1) and on the other hand the second source (S2); - a first biasing transistor (Ta) having a drain (Da) electrically connected to the first source (S1) of the bidirectional transistor (T1) and a source (Sa) electrically connected to the substrate (Sub); a second biasing transistor (Tb) having a drain (Db) electrically connected to the second source (S2) of the bidirectional transistor (T1) and a source (Sb) electrically connected to the substrate (Sub); the bidirectional transistor, the first biasing transistor (Ta) and the second biasing transistor (Tb) being monolithic, characterized in that: an ohmic contact adjacent to the first gate (G1) forms the first source (S1) of the bidirectional transistor (T1), an ohmic contact adjacent to the second gate (G2) forms the second source (S2) of the bidirectional transistor (T1), an ohmic contact adjacent to the first source (S1) forms the drain (Da) of the first biasing transistor (Ta), and an ohmic contact adjacent to the second source (S2) forms the drain (Db) of the second biasing transistor (Tb).

6. Integrated circuit (IC) according to claim 5 in which the bidirectional transistor (T1) is arranged between on one side the first biasing transistor (Ta) and on the opposite side the second biasing transistor (Tb) in a direction parallel (X) to the plane of the substrate (SUB).

7. Integrated circuit (IC) according to any one of claims 5 or 6 further comprising control means (CONT) configured to: - apply a first bias voltage (Vsi) on the first source (S1) and a second bias voltage (Vs2) on the second source (S2) greater than the first bias voltage (Vsi); - and put the first biasing transistor (Ta) in a conducting state and the second biasing transistor (Tb) in a blocking state.

8. Integrated circuit (IC) according to any one of claims 5 or 6 further comprising control means (CONT) configured to: - apply a first bias voltage (Vsi) on the first source (S1) and a second bias voltage (Vs2) on the second source (S2) lower than the first bias voltage (Vsi); - and put the first biasing transistor (Ta) in a blocking state and the second biasing transistor (Tb) in a conducting state.

9. Integrated circuit (IC) according to any one of claims 5 to 8 wherein the geometric width-to-length ratio (Wïa / Lïa; Wïb / LTb) of the first biasing transistor (Ta) or of the second biasing transistor (Ta) is less than 5% of the geometric width-to-length ratio (WTI / LTI) of the bidirectional transistor (T1).

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