Integrated circuit chip

Abstract

An integrated circuit chip (100) is disclosed that is formed on a substrate (102) and has connection regions (104b) for facilitating external electrical connections. A passivation layer (106) extends over an active surface of at least a portion of the integrated circuit. A plurality of projecting features (108) formed of a dielectric material extend from the passivation layer, in a direction away from the active surface. The surface density and arrangement of projecting features are configured for providing additional protection of the integrated circuit, for supporting the integrated circuit during assembly of the integrated circuit chip with external circuitry to form an electronic device, and for limiting wafer-level deformation during manufacture.

Description

Integrated Circuit Chip

[0001] The present invention relates to an integrated circuit (IC) chip, an electronic device comprising application circuitry and at least one IC chip, and to methods and / or apparatus for fabricating an IC chip and / or for assembling at least one IC chip with application circuitry to form an electronic device. The invention has particular, but not exclusive, relevance to the provision of a flexible IC chip having a layer for protecting and / or for supporting the IC chip, during assembly with corresponding application circuitry to form an electronic device such as, but not limited to, a radio-frequency identification (RFID) tag.

[0002] Historically, during the manufacture of IC chips, a wafer consisting of a thin layer of semiconductor material such as crystalline Silicon (c-Si) is provided which serves as a substrate for supporting microelectronics that form the IC chips. Such wafers typically have an extreme level of purity and are formed in a single crystal structure.

[0003] During the manufacturing process the IC chips may be built up on the wafer. For example, devices such as diodes, transistors, capacitors, and resistors, can be built up by forming p-type and n-type regions, at appropriate locations, in the semiconductor substrate (or other semiconducting layers) using appropriate doping, and by building up and patterning one or more layers of insulating and / or conducting material using appropriate fabrication processes. Layers of insulating, semiconducting and / or conducting material are typically formed using appropriate deposition, growth and / or crystallisation processes. The location of the n-type and p-type regions, the pattern of insulating, semiconducting and / or conducting material in each layer, and the interconnectivity between them, is typically defined using appropriate photolithographic processes.

[0004] Whilst fabrication on crystalline semiconductor substrates is widespread, fabrication of IC chips may be carried out on other substrate materials including flexible insulating substrates. For example, it is known to use a flexible substrate formed of, for example, a thin, heat-resistant material such as polymers to manufacture flexible IC chips. Where the substrate is flexible, a rigid carrier is typically used to support the flexible substrate during the subsequent manufacture of electronic devices on that flexible substrate to form the flexible IC chip, for example using manufacturing processes similar to those described above for a crystalline semiconductor wafer, albeit adapted to besuitable to the flexible substrate being used (e.g., using lower temperatures suitable for polymer substrates or the like).

[0005] Over the past decade there has been a large increase in the demand for flexible IC chip based electronic devices, especially for electronic devices such as RFID devices / tags that typically incorporate simple two terminal flexible IC chips. This increase in demand has been driven, in particular, by the increasing and varied applications of RFID tags in fields as diverse as medical devices, product packaging, asset tracking, security, logistics, etc.

[0006] IC chips, whether crystalline semiconductor-based IC chips or flexible IC chips, once fabricated, are typically separated / singulated (or diced) into individual dies for subsequent removal and integration with external application circuitry to form an end product in the form of an electronic device such as an RFID tag, or the like.

[0007] One method of assembly that is widely used includes the use of an anisotropic conductive medium such as an anisotropic conductive adhesive (ACA) I anisotropic conductive paste (ACP) I anisotropic conductive film (ACF) that is deposited onto a surface of a substrate carrying the application circuitry with exposed connection regions (referred to as ‘bond pads’ or ‘contact pads’) formed from a layer of metal (or other conductive material) for allowing electrical connection to the application circuitry. The ACA (or other anisotropic conductive medium) may be deposited as a blanket layer, or selectively deposited onto the contact regions (e.g., through a needle) as separate regions which form a blanket layer, with at least some adhesive spreading into the active region(s), when the assembly is compressed during a subsequent procedure to attach the application circuitry to the IC chip. The ACA typically comprises a spatial distribution of conductive particles (e.g., nickel particles), in a non-conductive polymer matrix (for example formed of an epoxy resin or acrylic), that is intrinsically random. A surface of the IC chip, carrying complementary connection regions, typically formed in a redistribution (or redistributive) layer (RDL) formed on the surface of the IC chip, is then appropriately aligned for required electrical connectivity with the application circuitry and then pressed into the ACA on the substrate. The pressure applied is sufficient to embed the conductive particles into the respective connection regions of the IC chip, and the application circuitry, and thus form corresponding electrical connections between them. Heat is also applied to the assemblyto cure the polymer matrix and secure the IC chip in place with the required electrical connectivity to the application circuitry.

[0008] The concentration and size of the conductive particles in the ACA, and the thickness of the ACA, is such that the adhesive will allow electrical conduction generally orthogonal to the bonded surfaces of the application circuitry substrate and IC chip substrate, through the thickness of the adhesive, without allowing transverse flow generally parallel to those opposing surfaces. Accordingly, when the IC chips are bonded to the application circuitry, an orthogonal electrical connection is formed between the complementary connection regions of the application circuitry and the IC chip without any transverse electrical connection being formed (parallel to the surfaces of the IC chip substrate I application circuitry substrate) between different laterally spaced connection regions.

[0009] It can be seen, therefore, that the use of ACA beneficially allows the assembly of IC chips and external application circuitry, without the need for localised placement of a conductive adhesive onto the relatively small complementary connection regions on the bonded surfaces of the application circuitry substrate and / or IC chip substrate. This helps to reduce the complexity of assembly processes, and hence the cost. Whilst this is particularly important in the context of flexible IC chips, it also provides benefits in the context of crystalline semiconductor-based IC chips.

[0010] It will be appreciated that, the pressure that needs to be applied to the IC chip during assembly is relatively high, to ensure that the ACA layer is squeezed to form a sufficiently thin film (i.e., slightly thinner than the average size of the conductive particles), and to ensure that the particles are sufficiently pressed into the respective electrical connection regions of both the IC chip and the application circuitry to form good electrical connections with those regions. However, as explained above the ACA will typically extend laterally beyond the connection regions and in-between the active circuitry of the IC chip and the application circuitry. Moreover, whilst the active circuitry is typically protected by a passivation layer such as an oxide, a nitride, or the like, the insulating layer can be relatively thin (typically < 1 m) and / or soft (especially in the case of flexible IC chips). Accordingly, when pressure is applied during assembly the conductive particles in the ACA (which may have a size that is several times the thickness of the protective passivation layer) can damage (or ‘punch through’) the passivation layer, and potentiallythe underlying active circuitry, causing unpredictable parasitic effects and even short I open circuits that result in the IC chip becoming unusable.

[0011] Moreover, as the electrical connection regions are typically formed from a relatively thick layer of a metal (or other conductive material), when the connection regions of the IC chip and the connection regions of the application circuitry are bonded together, a relatively large gap may arise between the surface of the IC chip substrate and the surface of the application circuitry substrate in areas where a connection region is not present. Whilst this gap may be at least partially filled with ACA, the pressures and temperatures used in the assembly process can result in stress induced distortion of, and or damage to, the IC, as the forces applied to the IC chip during assembly tend to urge the IC chip substrate into the gap in areas located laterally between the connection regions.

[0012] Due to the nature of the flexible substrate used these issues are of particular concern in the context of flexible IC chips. Specifically, by their nature, the flexible substrates tend to be thin, flexible, pieces of plastic or the like, which deform easily under pressure and are particularly prone to damage from high point / indentation forces. Accordingly, flexible IC chips are particularly susceptible both to distortion such as ‘sagging’ between adjacent connection regions or tracks of the application circuitry and to conductive particle induced damage. Nevertheless, it will be appreciated that during assembly other forms of IC chip, including IC chips with rigid substrates, may also experience distortion, pressure induced stress related damage, and / or conductive particle induced damage.

[0013] To protect against these issues, a number of proposals have been made including to use a thicker passivation layer, and / or to introduce a shield between the application circuitry and the IC formed from a portion of the RDL, to help protect against damage such as ‘punch-through’ caused by the hard metal particles in the ACA. It will be appreciated that the use of such an RDL shield can also help to provide a consistent flat structure as well, and thus has the potential to provide improved IC chip support, and to mitigate issues such as distortion or ‘sagging’ between adjacent connection regions or tracks of the application circuitry.

[0014] However, whilst using a thicker passivation layer can reduce the incidence of punch-through, doing so has been found to result in an increase in the electrical resistance associated with the bond joints between the connection regions of the IC chip and thecorresponding regions of the application circuitry (which may, for example, be at least partially associated with a lower pressure on the joint during bonding), which is generally undesirable and, for some use-cases, unacceptable. It has also been found that introduction of a shield formed from an RDL of a typical thickness, without increasing the thickness of the passivation layer, can still result in an undesirably high occurrence of punch-through. Whilst increasing the thickness of the RDL can reduce this occurrence of punch-through, the reduction is not as significant as that achieved by the increase in the passivation layer thickness.

[0015] Moreover, increasing the thicknesses of a passivation layer and / or providing an (thicker) RDL shield, were found to contribute to other, undesirable wafer-level physical effects such as, for example, stiffness / stress related wafer deformation. In the case of a flexible substrate, for example, the thicker passivation layer I RDL shield were found to increase the amount of post fabrication wafer curling undesirably.

[0016] The invention aims to provide an IC chip, an electronic device comprising application circuitry and at least one IC chip, and / or associated methods and / or apparatus that at least partially contributes to mitigating one or more of the above issues.

[0017] In one example described herein there is provided, an integrated circuit chip comprising: a substrate on which is formed an integrated circuit; at least one connection region for forming an external electrical connection to the integrated circuit; a passivation layer extending over an active surface of at least a portion of the integrated circuit for protecting that active surface; and a plurality of projecting features extending from the passivation layer, in a direction away from the active surface, each projecting feature being respectively formed of a dielectric material, wherein the surface density and arrangement of projecting features are configured for providing additional protection of the integrated circuit, for supporting the integrated circuit during assembly of the integrated circuit chip with external circuitry to form an electronic device, and / or for limiting wafer-level deformation during manufacture.

[0018] At least a subset of one or more of the projecting features may be formed of the same dielectric material as the passivation layer. At least a subset of one or more of the projecting features may be formed integrally with the passivation layer. At least a subset of one or more of the projecting features may be formed of a different dielectric material than that of the passivation layer. Each projecting feature formed of a different dielectricmaterial than that of the passivation layer may be formed of a polymer-based material. The polymer-based material may be a polyimide-based material. Each projecting feature formed of a different dielectric material than that of the passivation layer may be formed of a photo-definable material. The photo-definable material may be a negative tone photo-definable material. Each projecting feature formed of a different dielectric material than that of the passivation layer may be formed of a thermosetting plastic material. Each projecting feature formed of a different dielectric material than that of the passivation layer may be formed of SU-8. Each projecting feature formed of a different dielectric material than that of the passivation layer may be formed of a material that is more elastic than SU-8. The plurality of projecting features may include at least one columnar protection feature, at least one ridge shaped projection features, at least one grid shaped protection feature, and / or at least one projection feature defining a boundary around at least part of the integrated circuit.

[0019] A backfill material may be provided between at least a subset of the plurality of projecting features. The backfill material may be provided on a surface of at least part of the passivation layer extending between at least a subset of the plurality of projecting features.

[0020] At least one projecting feature, of the plurality of projecting features, may be respectively provided in each connection region. At least one projecting feature respectively provided in each connection region may comprise a continuous region of the dielectric material extending a substantial part of that connection region. At least one projecting feature respectively provided in each connection region may comprise a plurality of columnar protection features, ridge shaped projection features, and / or grid shaped protection features.

[0021] Each projecting feature, of at least a subset of one or more of the projecting features, may be respectively provided with a shielding element on a surface of that projecting feature. Each shielding element may be formed from a common layer of conductive material.

[0022] The substrate may be a flexible substrate, and the integrated circuit chip may be a flexible integrated circuit chip.

[0023] In one example described herein there is provided, a method of fabricating an integrated circuit chip, the method comprising: providing a substrate; forming, on the substrate, an integrated circuit; forming at least one connection region for forming an external electrical connection to the integrated circuit; and forming a passivation layer extending over an active surface of at least a portion of the integrated circuit for protecting that active surface; and forming a plurality of projecting features extending from the passivation layer, in a direction away from the active surface, each projecting feature being respectively formed of a dielectric material, wherein the surface density and arrangement of projecting features are configured for providing additional protection of the integrated circuit, for supporting the integrated circuit during assembly of the integrated circuit chip with external circuitry to form an electronic device, and / or for limiting wafer-level deformation during manufacture.

[0024] At least a subset of one or more of the projecting features may be formed of the same dielectric material as the passivation layer, and the passivation layer and each projecting feature formed of that dielectric material may be formed by depositing that dielectric material and by partially etching the deposited dielectric material back to leave each projecting feature formed of that dielectric material extending from the passivation layer.

[0025] At least a subset of one or more of the projecting features may be formed of a different dielectric material than that of the passivation layer, and each projecting feature formed of that different dielectric material may be formed by depositing that different dielectric material over at least part of the passivation layer and by patterning that different dielectric material to form each projecting feature formed of that different dielectric material.

[0026] Each projecting feature formed of a different dielectric material than that of the passivation layer may be formed of a photo-definable material, and the patterning of that different dielectric material may be achieved by photo-defining that different dielectric material to form each projecting feature formed of that different dielectric material.

[0027] In one example described herein there is provided, an electronic device comprising: electronic circuitry formed on an electronic device substrate; and an integrated circuit chip, as set out above, electrically connected to the electronic circuitry to form the electronic device.

[0028] At least one supporting element may be provided on the electronic substrate for providing mechanical support to the integrated circuit chip. The at least one supporting element may comprise at least one structure comprising: an active structure; an inactive structure; a functional part of the electronic circuitry; a non-functional part of the electronic circuitry; at least part of a conductive routing trace; an extension of a contact region or pad; and / or at least part of a dummy circuit.

[0029] The electronic circuitry may comprise at least one antenna. The electronic device may be a radio frequency identification (RFID) device. The electronic device substrate may be a flexible electronic device substrate.

[0030] In one example described herein there is provided, a method of assembling an electronic device, the method comprising: providing an electronic device substrate on which electronic circuitry of the electronic device is formed; providing integrated circuit chip as aet out above; and electrically connecting the integrated circuit chip to the electronic circuitry to form the electronic device.

[0031] The electrically connecting may comprise: depositing an anisotropic conducting medium on the electronic device substrate; positioning the integrated circuit chip relative to the electronic circuitry to align at least one connection region of the integrated circuit chip with at least one corresponding electrical connection region of the electronic circuitry; and pressing the integrated circuit chip, when in the aligned position, into the anisotropic conducting medium to form an electrical connection between the at least one connection region of the integrated circuit chip and the at least one corresponding electrical connection region of the electronic circuitry.

[0032] The method may further comprise curing the anisotropic conducting medium to secure the integrated circuit chip in position.

[0033] In one example described herein there is provided, an integrated circuit chip obtained by the method of fabricating an integrated circuit chip as set out above.

[0034] An electronic device obtained by the method of assembling an electronic device as set out above.

[0035] The electrically connecting may further comprise curing the anisotropic conducting medium to secure the integrated circuit chip in position.

[0036] Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings in which:Figures 1 (a) and 1 (b) are each a simplified cross-sectional view through a portion of a different respective variation of an integrated circuit (IC) chip;Figure 1(c) is a simplified partial plan view showing a possible arrangement of stand-off features, shielding elements, and contact region for an IC chip such as that shown in Figure 1(b);Figure 2 is simplified illustration showing initial steps of a first generalised procedure that may be used for fabricating an IC chip such as that shown in Figures 1(a) and 1(b);Figure 3 is simplified illustration showing further steps of the first generalised procedure to which Figure 2 relates;Figure 4 is simplified illustration showing initial steps of a second generalised procedure that may be used for fabricating an IC chip such as that shown in Figures 1(a) and 1(b);Figure 5 is simplified illustration showing further steps of the second generalised procedure to which Figure 4 relates;Figure 6 is simplified illustration showing the further steps of the second generalised procedure to which Figures 4 and 5 relate for an IC chip such as that shown in Figure 1 (b);Figure 7 is an illustration showing simplified illustrative cross-sections respectively through the IC chip of Figure 1(a), but without a backfill, and through a corresponding circuit component with which that IC chip is to be assembled;Figure 8 is an illustration showing simplified illustrative cross-sections respectively through the IC chip of Figure 1(a), but without a backfill, and through the corresponding circuit component with which that IC chip is to be assembled following the first stage of an assembly procedure;Figure 9 is an illustration showing simplified illustrative cross-sections respectively through the IC chip of Figure 1(a), but without a backfill, and through the corresponding circuit component with which that IC chip is being assembled during a second stage of an assembly procedure;Figure 10 illustrates a respective simplified plan view for each of a plurality of different possible regular patterns of stand-off features for an IC chip such as that shown in Figures 1(a) or 1(b);Figure 11 illustrates a respective simplified plan view for each of a plurality of different possible non-uniform patterns of stand-off features for an IC chip such as that shown in Figures 1(a) or 1(b); andFigure 12 illustrates a respective simplified plan view for each of a plurality of different possible patterns of stand-off features, for an IC chip such as that shown in Figures 1(a) or 1(b), where all or a subset of the stand-off features have a different configuration to those of Figures 10 and 11.OverviewFigures 1 (a) and 1 (b) are each a simplified cross-sectional view through a portion of a respective variation of an integrated circuit (IC) chip 100. Figure 1(c) is a simplified partial plan view showing a possible arrangement of stand-off features, shielding elements, and contact region for an IC chip such as that shown in Figure 1(b).

[0037] As seen in Figures 1(a) and 1(b), in each variation, the IC chip 100 comprises a substrate 102 having a surface on which an integrated circuit (IC) layer (or active layer) 104 is formed. The substrate 102 in this example is a flexible substrate. Nevertheless, it will be appreciated that the substrate 102 may be formed of any suitable rigid or flexible material depending on the application for which the IC is to be used.

[0038] An IC 104a is formed in the IC layer 104 of each variation. IC layer 104 may comprise one or more conducting, semiconducting or insulating materials in order to form devices, such as transistors, capacitors, resistors, etc., and conductive features to form connections between devices, in IC 104a. For example, devices such as diodes, transistors, capacitors, and resistors of the IC 104a, may be fabricated: by forming one or more semiconducting layers on the substrate 102 in which p-type and / or n-type regions are formed at appropriate locations; and by building up and patterning one or more layers of insulating and / or conducting material using appropriate fabrication processes. Layers of insulating, semiconducting and / or conducting material may, for example, be formed as thin films using appropriate deposition, growth and / or crystallisation processes. Thelocation of the n-type and / or p-type regions, the pattern of insulating, semiconducting and / or conducting material in each layer, and the interconnectivity between them, may, for example, be defined using appropriate photolithographic processes and etching techniques. As shown in the illustrated example, one or more conductive paths 104b may also be provided, if necessary, for connecting the IC 104a to an external connection region of the IC chip 100 (for subsequent connection with application circuitry of an electronic device).

[0039] A passivation layer 106 extends over the IC layer 104 (or an active surface of at least part of the IC 104a) and thus forms an interface between a first surface of the passivation layer 106 and the IC 104a. The passivation layer 106 may, for example, be formed of any appropriate electrically insulating / dielectric material. It will be appreciated that for some devices (e.g., some sensors or the like) part of the active surface of the IC may not be passivated and so may be exposed to the external environment.

[0040] A further insulating / dielectric layer, referred to as a ‘stand-off’ layer 108, is provided on the passivation layer 106 and a conductive layer 110, which may be referred to as a redistribution (or redistributive) layer (RDL), extends over the stand-off layer 108.

[0041] The stand-off layer 108 comprises a plurality of stand-off features 108a, 108b that extend from a second surface of the passivation layer 106, opposite the interface with the IC layer 104. As described in more detail later, during fabrication, the stand-off layer 108 and passivation layer 106 may be formed from different parts (or ‘sub-layers’) of the same starting layer of material. Nevertheless, the stand-off layer 108 and passivation layer 106 may be formed from different layers (or sub-layers) of the same material or of different materials (as illustrated in Figures 1(a) and 1(b)).

[0042] As described in more detail later, the plurality of stand-off features 108a, 108b includes a first set of one or more ‘main active area’ stand-off features 108a arranged in a pattern over the part of the IC 104a where the main circuitry I electronic components are located. It will, nevertheless, be appreciated that some ‘active’ circuitry I components may extend beyond the main active area - for example beneath one or more connection regions (as described in more detail later). These main active area stand-off features 108a are configured both to provide mechanical support for the IC 104a during (and following) assembly, and to contribute to mitigating against the occurrence of punch-through. Specifically, it has been found that by using an appropriate surface density of these ‘mainactive area’ (percentage of the passivation layer surface area covered by) stand-off features 108a (ensuring a sufficient, but not excessive, area of the passivation layer 106 that does not have a stand-off feature 108a extending from it), the incidence of punch-through can be reduced to acceptable levels, whilst minimising the stresses experienced by the IC 104a during assembly, and still maintaining a sufficiently low electrical resistance associated with the bond joints between the IC chip 104 and the application circuitry. Specifically, by tuning the number density (number of stand-off features 108a per unit area) and the size of those stand-off features to provide an appropriate surface density of the stand-off layer material, the balance between reducing incidence of punch-through and minimising stresses can be optimised. Using an appropriate surface density (or standoff feature to spacing ratio) for the set of main active area stand-off features 108a also mitigates the risk of significant wafer-level deformation (e.g., wafer curling in the case of flexible substrates). For example, having a surface density of stand-off features, depending on the use case, in the range of 10% to 90%, although a surface density below 50%, and more typically below 25%, has been found to be appropriate for many use cases. By way of example only, in one experimental scenario, a surface density of below approximately 15% ± 3% was found to produce acceptable results for typical substrates I substrate thicknesses.

[0043] It will be appreciated that the specific stand-off feature surface density I stand-off feature to spacing ratio used for a given device may be tailored based on several factors such as, for example: the type of anisotropic conductive medium (e.g., ACA. ACP, ACF, and / or the like) used (e.g., based on the maximum or average conductive particle size, conductive particle distribution characteristics, conductive particle fill factor, conductive particle material composition, binder resin viscosity, or the like); the design of the IC 104a; the thickness of and / or stress introduced by the passivation layer 106; the thickness of and / or stress introduced by the stand-off layer 108; the presence or absence, and thickness, of any RDL shielding; the thickness, stress introduced by and / or material of the substrate 102; the maximum acceptable wafer-level deformation (e.g., curl profile of a flexible substrate or the like); the design of the application circuitry with which the IC is assembled; and / or the like.

[0044] It will also be appreciated that the stand-off feature surface density I stand-off feature to spacing ratio need not be uniform across the IC 104a.

[0045] In the illustrated example these main active area stand-off features 108a comprise a plurality of pillar like, or columnar, structures. Nevertheless, as described in more detail later, the pattern of main active area stand-off features 108a may, additionally (or alternatively), comprise other shaped stand-off features depending on requirements (e.g., depending on the nature of the IC 104a that is being protected).

[0046] The conductive layer 110 comprises, in the illustrated example, a pattern of (RDL) shielding elements 110a that corresponds to the pattern of main active area stand-off features 108a in the first set. Specifically, each main active area stand-off feature 108a has a respective shielding element 110a provided on the surface of that stand-off feature 108a (opposite the surface of the stand-off feature 108a that interfaces with the passivation layer 106). Each shielding element 110a may have a shape and area that is substantially the same as that as the stand-off feature 108a below it (as seen in Figure 1 (a)). Nevertheless, all or a subset of the shielding elements 110a may have a shape that is greater in area than that of the stand-off feature 108a upon which it is positioned (as seen in Figure 1(b)).

[0047] It will be appreciated that, in the example of Figure 1(b), part of the shielding element 110a will extend onto the surface of the passivation layer 106 from the stand-off feature 108a upon which it is positioned. Referring to Figure 1(c), for example, each main active area stand-off feature 108a may comprises a column / pillar, having generally square cross-section, of a dielectric / insulating material. Each main active area stand-off feature 108a may be capped with a much larger area shielding element 110a, that is generally hexagonal in shape, and that forms part of a tessellating pattern of similar shielding elements 110a.

[0048] It will also be appreciated that whilst the presence of shielding elements 110a, such as those shown in Figures 1(a) and 1(b), can provide additional benefits in terms of reduced incidence of punch-through and / or reduced / minimised stress on the IC 104a, the presence of such shielding elements 110a may not be necessary in all scenarios and even where such shielding elements 110a are provided they may not be provided on every main active area stand-off feature 108a.

[0049] The conductive layer 110, in each of the illustrated examples of Figures 1(a) and 1(b), also comprises a plurality of connection regions 110b (which may be referred to as ‘bond pads’ or ‘contact pads’) which are configured for forming an electrical connectionwith corresponding application circuitry when the IC chip 100 is assembled with that application circuitry as part of a process to form an end product in the form of an electronic device such as an RFID tag, or the like. In the illustrated examples, the connection regions 110b are interconnected internally to the IC 104a (e.g. via one or more conductive paths 104b), whereas the shielding elements 110a are not interconnected internally to the IC 104a. It will, nevertheless, be appreciated that the shielding elements 110a may be provided as an active or inactive part of the IC 104a. For example, one or more of the shielding elements 110a may form part of a functional conductive path, an extension of a contact region, and / or the like. The shielding elements 110a may also be configured to provide enhanced thermal management of the IC 104a, for example as heat spreaders and / or heat sinks and / or heat bridges to the application circuitry of thermal energy generated within IC 104a.

[0050] The plurality of stand-off features 108a, 108b also includes a second set of one or more ‘connection region’ stand-off features 108b. Each ‘connection region’ stand-off feature is located between a connection region 110b of the RDL 110 and a corresponding portion of the passivation layer 106. In the example illustrated in Figure 1(a), other than one or more respective via like structures 112 through the stand-off layer 108 and passivation layer 106 to provide the required connectivity, each connection region standofffeature 108b is configured to extend as a substantially continuous area for a substantial majority of the corresponding connection region. In the example illustrated in Figure 1(b), on the other hand, the via like structures 112 for providing the required connectivity only extend through the passivation layer 106, and do not extend through the stand-off layer 108 as distinct vias. Specifically, in the example of Figure 1 (b), the connection region 110b extends beyond the connection region stand-off feature(s) 108b on which it is provided, onto the surface of the passivation layer 106, and into the via like structures 112. Whilst, in both the illustrated examples, each connection region stand-off feature 108b is configured to extend as a substantially continuous area for a substantial majority of the corresponding connection region (e.g., as seen in Figure 1(c)), it will be appreciated that connection region stand-off features 108a may be configured in any suitable manner. For example, the stand-off layer 108 may comprise a respective plurality of connection region stand-off features 108b beneath the material of each connection region 110b (e.g., in the form of columnar and / or other shaped structures, similar to the main active area stand-off features 108a).

[0051] It will be appreciated that, as seen in Figures 1(a) and 1(b), parts of the IC 104a forming the IC layer 104 may extend beneath the connection regions 110b. For example, insulating layers of the IC 104a (inter-layer dielectrics, for example) will typically extend beneath the passivation layer 106 to the outer edge of the IC chip 100. Moreover, whilst the conducting and semiconducting layers of the IC 104a will, typically, notextend beneath the connection regions, in some cases part of the active area of the IC 104a (e.g., certain types of device, such as capacitors or the like) may be located entirely or partially beneath a corresponding connection region 110b.

[0052] In the illustrated example, a layer of backfill 114 is provided that extends over the passivation layer 106 between the main active area stand-off features 108a. In this example the layer of backfill 114 also extends over the stand-off features 108a but this need not be the case. This layer of backfill 114 beneficially provides additional protection, support, and stress relief. Nevertheless, it will be appreciated that significant benefit is still achievable even without such backfill and hence the use of a backfill is optional.

[0053] By providing a stand-off layer 108 comprising main active area stand-off features 108a as described above, it has been found that a relatively low bond joint electrical resistance can be maintained compared with, for example, using a blanket stand-off layer 108, or a thicker passivation layer 106 (e.g., equivalent to a depth of the passivation layer 106 and main active area stand-off features 108a combined).

[0054] It will be appreciated that an IC chip 100, similar or the same as that illustrated in Figures 1(a) or 1(b), may be fabricated in a number of different ways. Different ways in which the IC chip 100 shown in Figure 1(a) can be fabricated will now be described, by way of example only, with reference to Figures 2 to 5. Nevertheless, it will be appreciated that similar procedures can be adapted for the fabrication of the IC chip 100 shown in Figure 1(b).IC Chip Fabrication - Passivation and Stand-off Layers Formed from Same Layer

[0055] One procedure for fabricating such an IC chip 100, will now be described, by way of example only, with reference to Figures 2 and 3. In this example procedure, the passivation and stand-off layers are formed from a single deposited layer of electrically insulating / dielectric material.

[0056] It will be appreciated that whilst Figures 2 and 3 illustrate formation of a single IC chip 100 for reasons of descriptive clarity, in a typical manufacturing scenario many (e.g., tens, hundreds, or even thousands of) such IC chips will be fabricated together on a single starting wafer of an appropriate material.

[0057] Figure 2 is a simplified illustration showing the initial steps of a generalised procedure that may be used for fabricating the IC chip 100. Specifically, Figure 2 illustrates, at (a) to (c), a series of simplified illustrative cross-sections through the (partially formed I completed) IC chip 100, each cross-section corresponding to a different stage of the fabrication procedure.

[0058] As seen in Figure 2(a), a substrate 102 of an appropriate starting material is initially provided upon which the IC can be formed. For a flexible IC chip, this starting material may, for example, comprise a flexible polymer such as polyimide, or some other suitable substrate material.

[0059] It will be appreciated that the substrate 102 may be formed on a rigid carrier (not shown) made of a rigid material (e.g., to facilitate manufacture of an IC on a flexible substrate to form a flexible IC chip). A rigid carrier may, for example, be formed from a transparent material such as glass although it will be appreciated that the rigid carrier may be formed of any other suitable material, for example, polycarbonate, quartz, silicon, or any other known materials suitable for supporting the flexible substrate. Where the substrate 102 is formed on such a carrier the material forming the substrate 102 may, for example, be deposited using thin-film processes such as, for example: physical vapour deposition (e.g. sputter), chemical vapour deposition (e.g. plasma-enhanced chemical vapour deposition (PECVD)), vacuum deposition (e.g. thermal or electron-beam evaporation); coating (e.g. spin, dip, blade, bar, spray, or slot-die), printing (e.g. jet, gravure, offset, screen, or flexographic), pulsed-laser deposition (PLD), atomic layer deposition (ALD), lamination and / or any other suitable processes.

[0060] As seen at (b) in Figure 2, the next stage of the fabrication procedure comprises forming an IC layer 104 comprising at least one IC 104a on the substrate 102. For example, as those skilled in the art will be familiar with, the material forming each of one or more layers (e.g., conducting, semiconducting, and / or insulating layers) forming the IC 104a may be respectively deposited onto the substrate 102. These IC layers may be patterned using conventional photoresist-based lithography (and / or other form oflithography such as X-ray lithography, electron beam lithography or the like), doped to form p-type and n-type regions where required, and / or etched using a suitable etchant, to form the required IC structure - for example an IC structure comprising: devices such as diodes, transistors, capacitors, and / or resistors, at appropriate locations; appropriate conductive paths interconnecting the devices; and insulating regions where necessary. It will be appreciated that other processes may alternatively (or additionally) be used for fabricating the IC 104a. For example, one or more imprint lithography processes and / or any other appropriate patterning technique, such as printing, may be used for patterning one or more IC layers. Moreover, where the substrate 102 is not formed of a crystalline semiconductor (e.g., in the case of a flexible substrate), a crystalline or polycrystalline semiconductor IC may be formed in a separate process and subsequently embedded into the substrate 102. Nevertheless, it will be appreciated that the use of stand-off features, shielding elements, and associated techniques described throughout this description are particularly relevant to thin film ICs - for example, but not limited to, ICs formed by the deposition (and possibly subsequent (partial) crystallisation) of thin layers of amorphous or partially crystalline semiconductor material (and associated dielectric / insulating materials where needed). Such thin film ICs may, for example, include one or more devices (e.g., thin-film transistors (TFTs)) formed from low temperature polycrystalline silicon (‘polysilicon’) and or one or more devices (e.g., thin-film transistors (TFTs)) formed from metal oxide semiconductor materials.

[0061] As part of this stage of the fabrication procedure conductive paths 104b may be formed, if necessary, for connecting the IC 104a to an external connection region of the IC chip 100 (for subsequent connection with application circuitry of an electronic device).

[0062] As seen at (c) in Figure 2, the next stage of the fabrication procedure comprises forming / depositing an appropriate insulating / dielectric layer 105 over the IC 104a (or at least active parts of the IC 104a). This insulating / dielectric layer 105 may, for example, be formed of any appropriate electrically insulating / dielectric material such as a polymer, a photo-patternable polymer, silicon dioxide (SiO2), hafnium dioxide (HfO2), silicon nitride (SiNx), aluminium oxide (AI2O3), or any suitable combination thereof. Nevertheless, these are only examples, the passivation layer could be formed from other insulating / dielectric materials.

[0063] In the example of Figure 2, the insulating / dielectric layer 105 is of sufficient thickness to ultimately form both a passivation layer 106 for protecting I passivating the IC 104a and a stand-off layer 108 (as described with reference to Figure 1 (a)). For example, the insulating / dielectric layer 105 may be formed to a thickness of 5.5pm (±2pm) for ultimately forming a passivation (sub-)layer 106 of 2.5pm (±1pm) thickness, and a standoff (sub-)layer 108 of 3.0pm (±1pm). Nevertheless, it will be appreciated that these thicknesses are purely exemplary, and any appropriate thicknesses could be applicable for a given device.

[0064] It will be appreciated that the specific thickness of the passivation layer 106 and / or the specific thickness of the stand-off layer 108 selected may be tuned based on several factors such as, for example: the type of anisotropic conductive medium used (e.g., based on the maximum or average conductive particle size, conductive particle distribution characteristics, conductive particle fill factor, conductive particle material composition, binder resin viscosity, or the like); the design of the IC 104a; the stand-off feature pattern used (e.g., surface density I feature to spacing ratio); the thickness of and / or stress introduced by the other of the stand-off layer 108 and the passivation layer 106; the presence or absence of any RDL shielding; the thickness, stress introduced by and / or material of the substrate 102; the maximum acceptable wafer-level deformation (e.g., curl profile of a flexible substrate or the like); the design of the application circuitry with which the IC is assembled; and / or the like.

[0065] Figure 3 is a simplified illustration showing further steps of the generalised procedure to which Figure 2 relates.

[0066] As seen in Figure 3(a), the next stage of the fabrication procedure comprises formation of the connection regions 110b and the shielding elements 110a. This stage also involves forming appropriate vias 112 in the insulating / dielectric layer 105 for allowing a connection to be made to the IC 104a (e.g., via the conductive paths 104b). These vias 112 are filled during subsequent formation of the conductive layer 110 to provide an electrically conductive external connection to the connection regions 110b. Nevertheless, it will be appreciated that where the vias 112 do not extend through the stand-off layer 108 (as in the example of Figure 1(b)), the stand-off layer 108 may be patterned to form the stand-off features 108a in a separate step to (e.g., before) formation of the vias 112 in the insulating / dielectric layer 105 for allowing a connection to be made to the IC 104a.

[0067] Beneficially, as seen in Figure 3(a), in the illustrated example, the connection regions 110b and the shielding elements 110a are formed from a common metallisation (or other conductive material) layer 110 that is deposited on the insulating / dielectric layer 105 and then patterned in a common patterning step, e.g., using a conventional photoresist-based lithography (or other form of lithography such as X-ray lithography, electron beam lithography or the like). Alternatively, a printing or other selective deposition technique may be used to form connection regions 110b and shielding elements 110a, for example using conductive ink. Thus, the provision of the shielding elements 110a does not add appreciably to the complexity of the fabrication process and can be integrated into existing processes relatively easily without the introduction of additional masking steps. For example, the conductive layer 110 may be formed to a thickness of 2pm (±1pm) or the like. Nevertheless, it will be appreciated that this thickness is purely exemplary, and any appropriate thicknesses could be applicable for a given device.

[0068] Referring to Figure 3(b), once the conductive layer 110 has been patterned, the stand-off (sub-)layer 108 and passivation (sub-)layer 106 can be defined by etching the original insulating / dielectric layer 105 back to form the stand-off features 108a, 108b. Beneficially, this etch back procedure can be facilitated by using the patterned conductive layer 110 as a hard mask when etching the electrically insulating / dielectric layer 105 thereby avoiding an additional masking step (hence simplifying the process, reducing the number of masks required, avoiding potential misalignment issues etc.). During this etch back step the resist material, used in the previous masking step for forming the conductive layer 110, may also be removed thus helping to keep the manufacturing process relatively simple.

[0069] Referring to Figure 3(c), once the stand-off (sub-)layer 108 and the passivation (sub-)layer 106 have been defined, the space between the stand-off features 108a, 108b may optionally be backfilled, using an appropriate material, to form the backfill layer 114 having an appropriate backfill thickness (after any cure related shrinkage) - e.g., in the region of 3pm to 5pm or the like.

[0070] Any suitable material may be used for the purposes of this backfill step, if present, in a manner that would be familiar to those skilled in the art. Typically, the backfill will be a relatively soft material (once cured), for example having a relatively low hardness and Young’s Modulus compared to the photoresist or the like used elsewhere in the fabricationprocess (e.g., significantly less than that of the photoresist / photo-definable polymer used elsewhere in the procedure of Figures 2 and 3 - e.g., to form, or pattern, the passivation layer). For example, the backfill will typically be sufficiently soft for the conductive particles of the anisotropic conductive medium to embed themselves in the backfill during the assembly. Similarly, the backfill material will typically be a relatively low stress material (e.g., significantly lower than that of the photoresist used elsewhere in the procedure of Figures 2 and 3 - e.g. , to form, or pattern, the passivation layer) and will have material characteristics (once cured) that will contribute minimally to the IC level and wafer-level stresses imparted during manufacture.

[0071] Moreover, the backfill material will typically be selected for compatibility with, and / or to avoid increasing the complexity of, the wider manufacturing process. Typically, for example, the backfill material: will have a relatively low cure temperature (e.g., less than or equal to approximately 165°C); will have low risk hazard statements associated with it; will have a reflow capability; will have a resist chemistry compatible with the wider manufacturing process; will use a developer solvent that is compatible with wider manufacturing process; will be thermally stable (e.g., during post-processing steps at around 175°C); and / or will be capable of surface planarisation following cure.

[0072] It will be appreciated that the specific (post cure) thickness of the backfill layer 114, and / or backfill material selection, may be tailored based on several factors such as, for example: the type of anisotropic conductive medium used (e.g., based on the maximum or average conductive particle size, conductive particle distribution characteristics, or the like); the design of the IC 104a; the stand-off feature pattern used (e.g., surface density I feature to spacing ratio); the thickness of the passivation layer 106; the thickness of the stand-off layer 108; the presence or absence of any RDL shielding; the thickness and / or material of the substrate 102; the maximum acceptable wafer-level deformation (e.g., curl profile of a flexible substrate or the like); the design of the application circuitry with which the IC is assembled; and / or the like.

[0073] Following formation of the IC 104a on the substrate 102 and subsequent passivation and metallisation steps, the wafer comprising the IC chip 100 may be removed from any carrier and transferred to a wafer frame. The IC chip 100 may be singulated from any other IC chips formed at the same time and removed from the wafer frame (or from any carrier that may be used if the wafer is not transferred to a wafer frame). For example,the IC chip 100 (or ‘die’) may be separated from other IC chips (possibly on a rigid carrier, wafer frame or the like) by dicing the substrate 102 upon which the respective IC of each IC chip is formed, along straight lines (known as scribe lines) between the ICs, typically using a laser, an abrasive waterjet, a saw, or some other appropriate dicing procedure.

[0074] Once singulated, the IC chip 100 may be individually picked (e.g., off a carrier or wafer frame on which it is located) for subsequent assembly with application circuitry (e.g., an antenna, other electronic circuitry, and / or the like) to form an electronic device (e.g., an RFID tag or the like).IC Chip Fabrication - Separate Passivation and Stand-off Layers

[0075] Another procedure for fabricating such an IC chip 100, will now be described, by way of example only, with reference to Figures 4 and 5. In this example procedure, the passivation and stand-off layers are formed from layers of electrically insulating / dielectric material that are fabricated separately.

[0076] It will be appreciated that, as with the fabrication procedure of Figures 2 and 3, whilst Figures 4 and 5 illustrate formation of a single IC chip 100 for reasons of descriptive clarity, in a typical manufacturing scenario many (e.g., tens, hundreds, or even thousands of) such IC chips will be fabricated together on a single starting wafer of an appropriate material.

[0077] Figure 4 is a simplified illustration showing the initial steps of a generalised procedure that may be used for fabricating the IC chip 100. Specifically, Figure 4 illustrates, at (a) to (d), a series of simplified illustrative cross-sections through the (partially formed I completed) IC chip 100, each cross-section corresponding to a different stage of the fabrication procedure.

[0078] As seen in Figure 4(a), a substrate 102 of an appropriate starting material is initially provided upon which the IC can be formed. For a flexible IC chip, this starting material may, for example, comprise a flexible polymer such as polyimide, or some other suitable substrate material.

[0079] It will be appreciated that the substrate 102 may be formed on a rigid carrier (not shown) made of a rigid material (e.g., to facilitate manufacture of an IC on a flexible substrate to form a flexible IC chip). A rigid carrier may, for example, be formed from atransparent material such as glass although it will be appreciated that the rigid carrier may be formed of any other suitable material, for example, polycarbonate, quartz, silicon, or any other known materials suitable for supporting the flexible substrate. Where the substrate 102 is formed on such a carrier the material forming the substrate 102 may, for example, be deposited using thin-film processes such as, for example: physical vapour deposition (e.g. sputter), chemical vapour deposition (e.g. plasma-enhanced chemical vapour deposition (PECVD)), vacuum deposition (e.g. thermal or electron-beam evaporation); coating (e.g. spin, dip, blade, bar, spray, or slot-die), printing (e.g. jet, gravure, offset, screen, or flexographic), pulsed-laser deposition (PLD), atomic layer deposition (ALD), lamination and / or any other suitable processes.

[0080] As seen at (b) in Figure 4, the next stage of the fabrication procedure comprises forming an IC layer 104 comprising at least one IC 104a on the substrate 102. For example, as those skilled in the art will be familiar with, the material forming each of one or more layers (e.g., conducting, semiconducting, and / or insulating layers) forming the IC 104a may be respectively deposited onto the substrate 102. These IC layers may be patterned using conventional photoresist-based lithography (and / or other form of lithography), doped to form p-type and n-type regions where required, and / or etched using a suitable etchant, to form the required IC structure - for example an IC structure comprising: devices such as diodes, transistors, capacitors, and / or resistors, at appropriate locations; appropriate conductive paths interconnecting the devices; and insulating regions where necessary. It will be appreciated that other processes may alternatively (or additionally) be used for fabricating the IC 104a. For example, one or more imprint lithography processes and / or any other appropriate patterning technique, such as printing, may be used for patterning one or more IC layers. Moreover, where the substrate 102 is not formed of a crystalline semiconductor (e.g., in the case of a flexible substrate), a crystalline orpolycrystalline semiconductor IC may be formed in a separate process and subsequently embedded into the substrate 102. Nevertheless, it will be appreciated that the use of stand-off features, shielding elements, and associated techniques described throughout this description are particularly relevant to thin film ICs - for example, but not limited to, ICs formed by the deposition (and possibly subsequent (partial) crystallisation) of thin layers of amorphous or partially crystalline semiconductor material (and associated dielectric / insulating materials where needed). Such thin film ICs may, for example, include one or more devices (e.g., thin-film transistors (TFTs)) formed from low temperaturepolycrystalline silicon (‘polysilicon’) and or one or more devices (e.g., thin-film transistors (TFTs)) formed from metal oxide semiconductor materials.

[0081] As part of this stage of the fabrication procedure conductive paths 104b may be formed, if necessary, for connecting the IC 104a to an external connection region of the IC chip 100 (for subsequent connection with application circuitry of an electronic device).

[0082] Referring to Figure 4(c), the next stage of the fabrication procedure comprises forming / depositing a passivation layer 106 over the IC 104a (or at least active parts of the IC 104a). This passivation layer 106 may, for example, be formed of any appropriate electrically insulating / dielectric material such as a polymer, a photo-patternable polymer, silicon dioxide (SiO2), hafnium dioxide (HfO2), silicon nitride (SiNx), aluminium oxide (AI2O3), or any suitable combination thereof. Nevertheless, these are only examples, the passivation layer could be formed from other insulating / dielectric materials including polymers or the like.

[0083] In the example of Figure 4, as the passivation layer 106 is formed separately to the stand-off layer 108 and so may be thinner than the insulating / dielectric layer 105 described with reference to Figure 2. For example, passivation layer 106 may be formed to a thickness of 2.5pm (±1 m) thickness. Nevertheless, it will be appreciated that this thickness is purely exemplary, and any appropriate thickness could be applicable for a given device.

[0084] Turning to Figure 4(d), following formation of the passivation layer 106, the passivation layer 106 may be patterned (e.g., to form vias 112 for subsequent connection to the conductive layer 108) and the material of the stand-off layer 108 deposited to an appropriate thickness. The stand-off layer 108 may, for example, be formed to a thickness of 3.0pm (±1pm).

[0085] As the stand-off layer 108 is formed separately to the passivation layer 106, it may be formed of a different material. In this example, the stand-off layer 108 is formed of an appropriate polymeric material that can be patterned directly (without etching) using, for example, an appropriate lithographic procedure. For example, the stand-off layer 108 may be formed of a photo-definable polymer material or the like, such as an epoxy or resin typically used as photoresist (e.g., SU-8, diazonaphthoquinone (DNQ)-Novolac, off-stoichiometry thiol-enes (OSTE), hydrogen silsesquioxane (HSQ),polydimethylsiloxane (PDMS), silicone, polyimide, cyclic olefin, polymethylmethacrylate (PMMA)), that can be subsequently patterned using photolithography.

[0086] It will be appreciated that the specific thickness of the passivation layer 106 and / or the specific thickness of the stand-off layer 108 selected may be tuned based on several factors such as, for example: the type of anisotropic conductive medium used (e.g., based on the maximum or average conductive particle size, conductive particle distribution characteristics, conductive particle fill factor, conductive particle material composition, binder resin viscosity or the like); the design of the IC 104a; the stand-off feature pattern used (e.g., surface density I feature to spacing ratio); the thickness of and / or stress introduced by the other of the stand-off layer 108 and the passivation layer 106; the presence or absence of any RDL shielding; the thickness, stress introduced by and / or material of the substrate 102; the maximum acceptable wafer-level deformation (e.g., curl profile of a flexible substrate or the like); the design of the application circuitry with which the IC is assembled; and / or the like.

[0087] Figure 5 is a simplified illustration showing further steps of the generalised procedure to which Figure 4 relates.

[0088] As seen in Figure 5(a), the next stage of the fabrication procedure comprises formation of the stand-off features 108a, 108b. Beneficially, as the stand-off layer 108 is formed of an appropriate polymeric material that can be patterned directly (without etching) this can be achieved using an appropriate lithographic procedure (e.g., photolithography or other form of lithography such as X-ray lithography, electron beam lithography or the like). It will be appreciated that the formation of the stand-off features 108a, 108b in this way has the potential to be faster than the etch back procedure described with reference to Figure 3, to provide greater uniformity in the stand-off layer 108 and / or passivation layer 106, and avoid possible other issues associated with the etch attacking the conductive layer 110 (e.g., clouding of the stand-off layer 108 and / or passivation layer 106). Nevertheless, the method of Figures 2 and 3 is still an efficient and beneficial way of forming the IC chip 100.

[0089] Once the stand-off features 108a, 108b have been formed, the conductive layer 110 may be deposited and the connection regions 110b and any (RDL) shielding elements 110a formed as seen in Figure 5(b). Specifically, in the illustrated example, the connection regions 110b and the shielding elements 110a are formed from a common metallisation(or other conductive material) layer 110 that is deposited on the patterned stand-off layer 108 and passivation layer 106 (in the spacing between stand-off features 108a, 108b) and then patterned in a common patterning step, e.g., using a conventional photoresist-based lithography (or other form of lithography such as X-ray lithography, electron beam lithography or the like). Thus, the provision of the shielding elements 110a does not add appreciably to the complexity of the fabrication process and can be integrated into existing processes relatively easily without the introduction of additional masking steps. For example, the conductive layer 110 may be formed to a thickness of 2pm (±1 ,5pm) or the like. Nevertheless, it will be appreciated that this thickness is purely exemplary, and any appropriate thicknesses could be applicable for a given device.

[0090] Referring to Figure 5(c), once the stand-off features 108a, 108b have been formed, the space between the stand-off features 108a, 108b may optionally be backfilled, using an appropriate material, to form the backfill layer 114 having an appropriate backfill thickness (after any cure related shrinkage) - e.g., in the region of 3pm to 5pm or the like.

[0091] Any suitable material may be used for the purposes of this backfill step, if present, in a manner that would be familiar to those skilled in the art. Typically, the backfill will be a relatively soft material (once cured), for example having a relatively low hardness and Young’s Modulus compared to the photoresist (or the like) used elsewhere in the fabrication process (e.g., significantly less than that of the photoresist / photo-definable polymer used elsewhere in the procedure of Figures 2 and 3 - e.g., to form, or pattern, the passivation layer). For example, the backfill will typically be sufficiently soft for the conductive particles of the anisotropic conductive medium to embed themselves in the backfill during the assembly. Similarly, the backfill material will typically be a relatively low stress material (e.g., significantly lower than that of the photoresist / photo-definable polymer used elsewhere in the procedure of Figures 2 and 3 - e.g., to form, or pattern, the passivation layer) and will have material characteristics (once cured) that will contribute minimally to the IC level and wafer-level stresses imparted during manufacture.

[0092] Moreover, the backfill material will typically be selected for compatibility with, and / or to avoid increasing the complexity of, the wider manufacturing process. Typically, for example, the backfill material: will have a relatively low cure temperature (e.g., less than or equal to approximately 165°C); will have low risk hazard statements associated with it; will have a reflow capability; will have a resist chemistry compatible with the widermanufacturing process; will use a developer solvent that is compatible with wider manufacturing process; will be thermally stable (e.g., during post-processing steps at around 175°C); and / or will be capable of surface planarisation following cure.

[0093] It will be appreciated that the specific (post cure) thickness of the backfill layer 114, and / or backfill material selection, may be tailored based on several factors such as, for example: the type of anisotropic conductive medium used (e.g., based on the maximum or average conductive particle size, conductive particle distribution characteristics, or the like); the design of the IC 104a; the stand-off feature pattern used (e.g., surface density I feature to spacing ratio); the thickness of the passivation layer 106; the thickness of the stand-off layer 108; the presence or absence of any RDL shielding; the thickness and / or material of the substrate 102; the maximum acceptable wafer-level deformation (e.g., curl profile of a flexible substrate or the like); the design of the application circuitry with which the IC is assembled; and / or the like.

[0094] Following formation of the IC 104a on the substrate 102 and subsequent passivation and metallisation steps, the wafer comprising the IC chip 100 may be removed from any carrier and transferred to a wafer frame. The IC chip 100 may be singulated from any other IC chips formed at the same time and removed from the wafer frame (or any carrier that may be used if the wafer is not transferred to a wafer frame). For example, the IC chip 100 (or ‘die’) may be separated from other IC chips (possibly on a rigid carrier, wafer frame or the like) by dicing the substrate 102 upon which the respective IC of each IC chip is formed, along straight lines (known as scribe lines) between the ICs, typically using a laser, an abrasive waterjet, a saw, or some other appropriate dicing procedure.

[0095] Once singulated, the IC chip 100 may be individually picked (e.g., off a carrier or wafer frame on which it is located) for subsequent assembly with application circuitry (e.g., an antenna, other electronic circuitry, and / or the like) to form an electronic device (e.g., an RFID tag or the like).

[0096] It will be appreciated that, in the procedure of Figures 4 and 5 where the vias 112 do not extend through the stand-off layer 108 (as in the example of Figure 1(b)), there is no need for a corresponding via to be provided through the stand-off layer 108 for allowing a connection to be made to the IC 104a because the patterning of the stand-off layer 108 to form the stand-off features 108a will naturally leave the vias 112 through the passivation layer 106 exposed for forming the required connections subsequently. This can be seenin Figure 6 which is a simplified illustration showing key steps from the generalised procedure of Figures 4 and 5, but for the connection region of the example of Figure 1 (b).

[0097] Specifically, the step illustrated in Figure 6(a) corresponds to the step shown and described with reference to Figure 4(b) and the corresponding description applies. The step illustrated in Figure 6(b) corresponds to the step shown and described with reference to Figure 4(c) and the corresponding description applies. The step illustrated in Figure 6(c) corresponds to the step shown and described with reference to Figure 4(d) and the corresponding description applies. The step illustrated in Figure 6(d) corresponds to the step shown and described with reference to Figure 5(a) and the corresponding description applies. The step illustrated in Figure 6(e) corresponds to the step shown and described with reference to Figure 5(b) and the corresponding description applies. The step illustrated in Figure 6(f) corresponds to the step shown and described with reference to Figure 5(c) and the corresponding description applies.

[0098]

[0099] As those skilled in the art will appreciate, the procedures described above with reference to Figures 2 and 3, Figures 4 and 5, and Figure 6 represent just a few different ways in which the IC 100, and in particular the stand-off features 108a, 108b, may be fabricated. It will also be appreciated that the illustrations in Figures 2 to 5 are simplified for illustrative purposes and not to scale. For example, in reality, in a practical IC chip 100 the IC 104a will have a semiconductor topography comprising a plurality of layers of different materials representing a particular design of circuit I semiconductor device. Moreover, in the illustrations of the example IC chips 100 referred to above there were a relatively few stand-off features 108a shown in the main active area for ease of description and illustration. Nevertheless, in a practical IC chip 100 there may be a relatively large number of stand-off features 108a in the main active area depending on the type of IC chip 100 and / or the application circuitry with which it is being assembled.Assembly

[0100] A procedure for assembling an IC chip 100, such as that illustrated in Figure 1 (a), but without a backfill layer, with application circuitry to form an electronic device will now be described, by way of example only, with reference to Figures to 7 to 9.

[0101] In the example of Figures 7 to 9 the illustrated IC chip 100 is similar to that fabricated in accordance with the procedure described with reference to Figures 4 and 5 (except that the optional backfill is omitted). Nevertheless, the assembly procedure is equally applicable to an IC chip 100 fabricated in accordance with the procedure described with reference to Figures 2 and 3 (or some other suitable procedure for fabricating such an IC chip 100).

[0102] Figure 7 is an illustration showing simplified illustrative cross-sections respectively through the IC chip 100 and through a corresponding circuit component 200 with which that IC chip 100 is to be assembled.

[0103] As seen in Figure 7, the circuit component 200 with which the IC chip 100 is to be assembled comprises an application circuit substrate 202 on which application circuitry 210 is provided. The application circuitry 210 comprises a plurality of application circuitry connection regions 210b configured for interconnection with the connection regions 110b of the IC chip 100. It will be appreciated that the application circuitry connection regions 210b may be in the form of dedicated connection regions 210b (e.g., dedicated contact pads, bond pads, or the like) or may simply form part of a circuit trace or track forming part of the application circuitry 210 (e.g., part of an antenna trace, a routing track, and / or the like).

[0104] In the illustrated example, the application circuitry 210 also comprises a plurality of additional conductive features 210a that may provide additional support for the IC chip 100. It will be appreciated that these conductive features 210a may be active or inactive, may be formed as a functional or as a non-functional, part of the application circuitry 210 on the application circuit substrate 202. For example, the conductive features 210a may comprise part of conductive routing traces, extensions of contact pads, dummy circuits and / or the like, and may be designed for the express purpose of providing additional mechanical support for the IC chip 100 during (and following) assembly. For example, the conductive features 210a may be in the form of additional turns (or part thereof) of the antenna tracks forming a coil loop type antenna. Alternatively (or additionally) the conductive features 210a may comprise conductive tracks (or part thereof) that are routed from outside the area of the IC chip 100 to a conductive feature 210a in the form of a pad or the like that is located within the perimeter of the IC chip 100 (as opposed to at the edges) for providing the additional mechanical support. Alternatively (or additionally) theconductive features 210a may comprise floating (unconnected) metal traces / structures located between the middle (and / or somewhere near the middle) of the IC chip 100 and the application circuit substrate 202. Such conductive features 210a may be configured to provide additional support to the IC chip 100 and hence beneficially allow (e.g., for a flexible IC chip) the IC chip 100 to sit “flat” on the surface of the conductive features 210a rather than “sag” between connection regions 210b of the application circuit, that are located (in this example) at positions corresponding to either end of the IC chip 100.

[0105] Figure 8 is an illustration showing simplified illustrative cross-sections respectively through the IC chip 100 and through a corresponding circuit component 200 with which that IC chip 100 is to be assembled following a first stage of an assembly procedure.

[0106] As seen in Figure 8, during the first stage of the assembly procedure, a layer of anisotropic conductive medium 300 (e.g., ACA, ACP, ACF, and / or the like) is deposited on the application circuit substrate 202 to cover the application circuitry 210. The anisotropic conductive medium may be deposited as a blanket layer (as illustrated), or selectively deposited onto the contact regions (e.g., through a needle) as separate regions which form a blanket layer, with at least some adhesive spreading into the active region(s), when the assembly is compressed during a subsequent procedure to attach the circuit component 200 to the IC chip 100.

[0107] Figure 9 is an illustration showing simplified illustrative cross-sections respectively through the IC chip 100 and through a corresponding circuit component 200 with which that IC chip 100 is to be assembled during a second stage of the assembly procedure.

[0108] As seen in Figure 9, during the second stage of the assembly procedure, the IC chip 100 is appropriately aligned with the application circuitry 210 of the circuit component 200 - e.g., an alignment in which the connection regions 110b of the IC chip 100 are aligned with the connection regions 210b of the application circuit 210 within acceptable tolerances. The surface of the IC chip 100 on which the metallisation layer 110 is formed is pressed into the anisotropic conductive medium layer 300 provided on that circuit component 200 to form an electrical connection between the connection regions 110b of the IC chip 100 and the corresponding connection regions 210b of the application circuit 210.

[0109] Appropriate pressure P-P’ is applied between the IC chip 100 and the circuit component 200 to ensure that conductive particles in the anisotropic conductive medium are sufficiently pressed into the connection regions 110b of the IC chip 100 and the corresponding connection regions 210b to form an electrical connection having the required electrical characteristics. Heat and / or electromagnetic radiation may also be applied to the assembly to cure the polymer matrix of the anisotropic conductive medium and hence secure the IC chip 100 in place with the required electrical connectivity to the application circuitry. It will be appreciated that an appropriate tool, such as a thermodes or the like, may be used to apply the pressure (while heating the IC chip 100).

[0110] Beneficially, during this process, in addition to the protection provided by the passivation layer 106, the main active area stand-off features 108a (together with any RDL shielding elements 110a) provide extra protection for the IC 104a from damage caused by the conductive particles in the anisotropic conductive medium 300. Moreover, the pattern of stand-off features 108a (together with any RDL shielding elements 110a) provides a generally flat, relatively thick, layer that mitigates the risk of pressure induced distortion of the IC chip 100 during assembly and / or wafer-level deformation (such as curling associated with a flexible substrate).

[0111] The risk of pressure induced distortion of the IC chip 100 may be further reduced by the presence of the additional conductive features 210a as part of the application circuitry that are configured for providing additional support for the IC chip 100. Nevertheless, even without such features, the area stand-off features 108a (together with any RDL shielding elements 110a) provides some additional structural benefits e.g., by spreading the forces arising from the applied pressure across the IC chip 100 as the IC chip 100 is pressed into the anisotropic conductive medium 300.Arrangement and Configuration of Stand-Off Features

[0112] As mentioned above, in a practical IC chip 100 there may be a relatively large number of stand-off features 108a in the main active area depending on the type of IC chip 100 and / or the application circuitry with which it is being assembled. Moreover, the arrangement of the main active area (and possibly other) stand-off features (including, for example, both the configuration of the pattern of the stand-off features 108a, 108b, and the respective shape, size and configuration of each stand-off feature 108a, 108b) maybe tailored to the requirements of the type of IC chip 100 and / or the application circuitry with which it is being assembled.

[0113] A number of different possible arrangements and configurations of the main active area stand-off features will now be described, by way of example only, with reference to Figures 10 to 12.Regular Patterns:

[0114] Figure 10 illustrates, at (a) to (c), a respective simplified plan view for each of a plurality of different possible regular patterns 908 of main active area stand-off features 108a for an IC chip 100.

[0115] In each of the examples of Figure 10 each main active area stand-off feature 108a respectively comprises a column / pillar, having generally square cross-section, of a dielectric / insulating material capped with a RDL shield (e.g., as described above). Nevertheless, it will be appreciated that all, or a subset of, the main active area stand-off features 108a may not be provided with an RDL shield. It will also be appreciated that whilst having a square cross-section provides some benefits in terms of simplicity of design and manufacture all or a subset of the main active area stand-off features 108a may have a different cross-sectional shape - for example, a rectangular shape (of appropriate aspect ratio), a hexagonal shape, and / or the like. Having a hexagonal crosssection, for example, increases the angles at the corners of each column which, as those skilled in the art will appreciate, can provide a structural advantage. Typically, for example, the width of each column / pillar (which may be either the minimum width or the maximum width for non-unity aspect ratios), may be in the range 15pm ± 10% to 40pm ± 10% (e.g., 15pm ± 10%, 20pm ± 10%, 25pm ± 10%, 30pm ± 10%, 35pm ± 10%, or 40pm ± 10%). Typical spacings between nearest neighbouring columns / pillars may, for example, be in the range 40pm ± 10% to 160pm ± 10% (e.g., 40pm ± 10%, 45pm ± 10%, 50pm ± 10%, 55pm ± 10%, 65pm ± 10%, 80pm ± 10%, 100pm ± 10%, 120pm ± 10%, 140pm ± 10%, 160pm ± 10%).

[0116] Moreover, in each of the examples of Figure 10 a plurality of connection regions 110b are shown. In this example, each connection region 110b has a corresponding connection region stand-off feature beneath it that is configured to extend as a substantially continuous area for a substantial majority of that connection region. It will,nevertheless, be appreciated that in a structure such as that shown in Figure 1(a), one or more respective via like structures may be provided beneath the connection region 110b through the stand-off layer and passivation layer to provide the required connectivity. Similarly, in a structure such as that shown in Figure 1 (b), the connection region 110b may extend beyond the connection region stand-off feature(s) beneath it onto the surface of the passivation layer (and possibly into one or more vias provided through the passivation layer). It will also be appreciated that connection region stand-off features may be configured in any suitable manner. For example, the connection region stand-off features may be patterned in a similar manner to the main active area stand-off features.

[0117] In each of the examples of Figure 10 the IC chip 100 comprises an IC formed of a number of distinct IC regions or blocks 104a’. The location of these IC blocks 104a’ are shown with dotted lines for illustrative purposes only.

[0118] Referring to Figure 10(a), in this example, the pattern 908 of main active area stand-off features 108a comprises a regular offset pattern (having a generally uniform surface density across the main active area of the IC chip 100). Specifically, in the pattern shown in Figure 10(a), other than at the edges of the pattern 908, each stand-off feature 108a is located at the centre of a (regular) hexagonal arrangement of other stand-off features 108a (as illustrated at 908a) - each other stand-off feature 108a being located at a vertex of the hexagonal arrangement.

[0119] Referring to Figure 10(b), in this example, the pattern 908 of main active area stand-off features 108a comprises a regular pattern (having a generally uniform surface density across the main active area of the IC chip 100) of columns and rows of main active area stand-off features 108a. Specifically, in the pattern shown in Figure 10(b), each stand-off feature 108a is located at the corner of at least one square arrangement of standoff features 108a (as illustrated at 908b) - each other stand-off feature 108a being located at the vertex of the square arrangement. In the example of Figure 10(b), the surface density is similar to (slightly lower than) that of Figure 10(a).

[0120] Referring to Figure 10(c), as in the example of Figure 10(b), the pattern 908 of main active area stand-off features 108a comprises a regular pattern (having a generally uniform surface density across the main active area of the IC chip 100) of columns and rows of main active area stand-off features 108a. Specifically, in the pattern shown in Figure 10(c), each stand-off feature 108a is located at the corner of at least one squarearrangement of stand-off features 108a (as illustrated at 908c) - each other stand-off feature 108a being located at the vertex of the square arrangement. In the example of Figure 10(c), however, the surface density is greater than (just over twice) that of Figure 10(b).

[0121] It will be appreciated that whilst each of the examples shown in Figure 10 comprises regular / uniform patterns 908 of main active area stand-off features 108a, the patterns 908 need not be uniform. For example, the pattern 908 could be non-uniform by design with different parts of the main active area having different densities specifically configured to compensate for and manage stresses in the IC chip 100. For example, a particular pattern having a higher-than-average surface density might be used for a section corresponding to a circuit element, or a circuit region or block 104a’, that is particularly sensitive to stress, or to anisotropic conductive medium particulate damage, so that the stress applied I risk of damage to that specific circuit component during assembly is minimised. Elsewhere, however, it may be preferable to provide a lower-than-average surface density to minimise the magnitude / risk of wafer-level deformation.

[0122] A number of different possible non-uniform arrangements of the main active area stand-off features will now be described, by way of example only, with reference to Figure 11.Non-uniform / Irregular Patterns:

[0123] Figure 11 illustrates, at (a) to (c), a respective simplified plan view for each of a plurality of different possible non-uniform patterns 1008 of main active area stand-off features 108a for an IC chip 100.

[0124] In each of the examples of Figure 11 each main active area stand-off feature 108a respectively comprises a column, having generally square cross-section, of a dielectric / insulating material capped with a RDL shield (e.g., as described above). Nevertheless, it will be appreciated that all, or a subset of, the main active area stand-off features 108a may not be provided with an RDL shield. It will also be appreciated that whilst having a square cross-section provides some benefits in terms of simplicity of design and manufacture all or a subset of the main active area stand-off features 108a may have a different cross-sectional shape - for example, a rectangular shape (of appropriate aspect ratio), a hexagonal shape, and / or the like. Having a hexagonal cross-section, for example, increases the angles at the corners of each column which, as those skilled in the art will appreciate, can provide a structural advantage.

[0125] Moreover, in each of the examples of Figure 11 a plurality of connection regions 110b are shown. In this example, each connection region 110b has a corresponding connection region stand-off feature beneath it that is configured to extend as a substantially continuous area for a substantial majority of that connection region. It will, nevertheless, be appreciated that in a structure such as that shown in Figure 1(a), one or more respective via like structures may be provided beneath the connection region 110b through the stand-off layer and passivation layer to provide the required connectivity. Similarly, in a structure such as that shown in Figure 1 (b), the connection region 110b may extend beyond the connection region stand-off feature(s) beneath it onto the surface of the passivation layer (and possibly into one or more vias provided through the passivation layer). It will also be appreciated that connection region stand-off features may be configured in any suitable manner. For example, the connection region stand-off features may be patterned in a similar manner to the main active area stand-off features.

[0126] In each of the examples of Figure 11 the IC chip 100 comprises an IC formed of a number of distinct IC regions or blocks 104a’. The location of these IC blocks 104a’ are shown with dotted lines for illustrative purposes only.

[0127] Referring to Figure 11(a), in this example, the underlying pattern 1008 of main active area stand-off features 108a is similar to that of Figure 10(b). However, in the example of Figure 11(a) the pattern is not completely uniform with one or more areas 1008a having a lower surface density of main active area stand-off features 108a than the rest of the IC. These lower surface density areas 1008a may, for example, be provided where the underlying circuitry is less prone to stress and / or particulate damage to allow the overall average surface density of the stand-off features to be tuned downwards as needed (e.g., to minimise risk / magnitude of associated wafer-level deformation. It will be appreciated that the use of an underlying pattern similar to that of Figure 10(b) is purely for illustrative purposes and, in reality, any appropriate pattern may be used (e.g., as described with reference to Figure 10(a), Figure 10(c) or some other pattern).

[0128] Referring to Figure 11(b), in this example, the underlying pattern 1008 of main active area stand-off features 108a is also similar to that of Figure 10(b) but, as with the example of Figure 11(a), the pattern is not completely uniform. In the example of Figure11 (b) one or more areas 1008b have a higher surface density of main active area standoff features 108a than the rest of the IC. A higher surface density area 1008b may, for example, be provided where the underlying circuitry is more prone to stress and / or particulate damage. It will be appreciated that the use of an underlying pattern similar to that of Figure 10(b) is purely for illustrative purposes and, in reality, any appropriate pattern may be used (e.g., as described with reference to Figure 10(a), Figure 10(c) or some other pattern).

[0129] Referring to Figure 11(c), in this example, the underlying pattern 1008 of main active area stand-off features 108a is also similar to that of Figure 10(b) but, as with the example of Figures 11(a) and 11(b), the pattern is not completely uniform. In the example of Figure 11 (c) one or more areas 1008c have a higher surface density of main active area stand-off features 108a, one or more areas 1008d having a lower surface density of main active area stand-off features 108a, than the rest of the IC. As with the example of Figure 11(b), one or more higher surface density areas 1008c may, for example, be provided where the underlying circuitry is more prone to stress and / or particulate damage. Similarly, as with the example of Figure 11(a) one or more lower surface density areas 1008d may be provided where the underlying circuitry is less prone to stress and / or particulate damage to allow the overall average surface density of the stand-off features to be tuned downwards as needed (e.g., to compensate for the increased surface density of the higher surface density areas). It will be appreciated that the use of an underlying pattern similar to that of Figure 10(b) is purely for illustrative purposes and, in reality, any appropriate pattern may be used (e.g., as described with reference to Figure 10(a), Figure 10(c) or some other pattern).

[0130] It will be appreciated that whilst each of the examples shown in Figures 10 and 11 comprise main active area stand-off features 108a in the form of columns, all or a subset of the main active area stand-off features 108a may have a different configuration.

[0131] A number of different possible configurations of the main active area stand-off features will now be described, by way of example only, with reference to Figure 12.Other Stand-Off Feature Configurations:

[0132] Figure 12 illustrates, at (a) to (c), a respective simplified plan view for each of a plurality of different possible patterns 1108 of main active area stand-off features 108a, foran IC chip 100, where all ora subset of the main active area stand-off features 108a have a different configuration to the columnar configuration described above.

[0133] In each of the examples of Figure 12 a plurality of connection regions 110b are shown. In this example, each connection region 110b has a corresponding connection region stand-off feature beneath it that is configured to extend as a substantially continuous area for a substantial majority of that connection region. It will, nevertheless, be appreciated that in a structure such as that shown in Figure 1(a), one or more respective via like structures may be provided beneath the connection region 110b through the stand-off layer and passivation layer to provide the required connectivity. Similarly, in a structure such as that shown in Figure 1(b), the connection region 110b may extend beyond the connection region stand-off feature(s) beneath it onto the surface of the passivation layer (and possibly into one or more vias provided through the passivation layer). It will also be appreciated that connection region stand-off features may be configured in any suitable manner. For example, the connection region stand-off features may be patterned in a similar manner to the main active area stand-off features.

[0134] In each of the examples of Figure 12 the IC chip 100 comprises an IC formed of a number of distinct IC regions or blocks 104a’. The location of these IC blocks 104a’ are shown with dotted lines for illustrative purposes only.

[0135] Referring to Figure 12(a), in this example, the pattern 1108 of main active area stand-off features 108a comprises a ‘mesh’, ‘matrix’, or ‘grid’ like structure comprising, in this example, a plurality of grid portions 1108a arranged across the main active area. Nevertheless, this arrangement is purely illustrative - any suitable arrangement is possible. For example, it will be appreciated that whilst, in the illustrated example, a plurality of grid portions 1108a are shown that form a non-continuous grid like structure, a single continuous grid like structure could be formed. Nevertheless, having breaks I spacing in the grid can help to mitigate against wafer-level deformation. As with the previous examples, the surface density of the main active area stand-off features 108a can also be tuned as required and need not be uniform across the main active area.

[0136] Referring to Figure 12(b), in this example, the pattern 1108 of main active area stand-off features 108a comprises a plurality of similar ridge portions 1108b. Each ridge portion extending transversely across part of the main active area generally parallel to a plurality of similar ridge portions 1108b. In the illustrated pattern 1108 the ridge portions1108b are arranged in a plurality of pairs of coaxially aligned ridge portions 1108b arranged generally symmetrically relative to a longitudinal axis of the IC chip 100. Nevertheless, this arrangement is purely illustrative - any suitable arrangement of ridge portions 1108b is possible. For example: the ridge portions 1108b need not all have the same length and / or width; the pattern 1108 could be arranged such that some or all of the ridge portions 1108b extend longitudinally rather than transversely (or at another angle); the ridge portions 1108b on either side of the main active area need not be aligned but may, instead, be offset from one another; at least some of the ridge portions 1108b may be arranged in an interleaved pattern; and / or the like. It will, nevertheless, be appreciated that having breaks I spacing between such ridges can help to mitigate against wafer-level deformation. Moreover, the ridge-like stand-off features could also be configured to direct flow of the anisotropic conductive medium during the compression (e.g., to facilitate control and distribution of an ACA paste). As with the previous examples, the surface density of the main active area stand-off features 108a can also be tuned as required and need not be uniformly arranged across the main active area. It will be appreciated that the pattern 1108 of main active area stand-off features 108a could include a combination of one or more grid like portions (similar to those illustrated in Figure 12(a)) and one or more ridges (similar to those illustrated in Figure 12(b)).

[0137] Referring to Figure 12(c), in this example, the pattern 1108 of main active area stand-off features 108a includes a pattern 1108c of columnar main active area stand-off features 108a similar to that of Figure 10(b) framed by a stand-off feature 1108d in the form of a thin perimeter of the same material(s) that extends around the edge of (at least) the main active area part of the stand-off layer. The presence of such a perimeter standoff feature 1108d can beneficially help to inhibit the backfill material (if used) and I or paste from exiting from the sides of at least the main active area of the IC 100. It will, nevertheless, be appreciated that the perimeter stand-off feature 1108d (or an additional such feature) could extend closer to the edges of the IC chip 100 (for example encompassing the connection regions 110b). Moreover, similar stand-off features could also be used to direct flow of the paste during the compression of the paste (e.g., to facilitate control and distribution of the paste). As with the previous examples, the surface density of the main active area stand-off features 108a can also be tuned as required and need not be uniformly arranged across the main active area. It will be appreciated that the pattern 1108 of main active area stand-off features 108a could include a combination ofone or more grid like portions (similar to those illustrated in Figure 12(a)), one or more ridges (similar to those illustrated in Figure 12(b)), and / or one or more perimeter stand-off features (similar to that illustrated in Figure 12(c)).Modifications and Alternatives

[0138] A detailed example has been described above. As those skilled in the art will appreciate, a number of modifications and alternatives can be made to the above example whilst still benefiting from the inventions embodied therein.

[0139] For example, referring to Figures 4, 5 and 6, whilst SU-8 may be used for forming the features of the stand-off layer because patterning of SU-8 is straight-forward and typically compatible with existing procedures, other materials may be used.

[0140] Moreover, the material for the optional backfilling of the stand-off layer could be any suitable material and could be specifically selected for its compatibility with the material used to define the features of the stand-off layer and / or because it can work together with the material of the stand-off features to achieve the required properties. Beneficially, the backfilling material is not a liquid (or is relatively viscous) to inhibit it from flowing out of the sides of the IC chip.

[0141] It will be appreciated that whilst one procedure is described in which the stand-off features are formed by etching back the material deposited for forming the passivation layer (e.g., with respect to Figures 2 and 3), and another procedure is described in which the stand-off features are formed from a material that is deposited separately from that forming the passivation layer (e.g., with respect to Figures 4 and 5), stand-off features of both types may be present. Specifically, one or more stand-off features could potentially be formed from a first material which is also used for the passivation layer and one or more other stand-off features could potentially be formed from a second material that is deposited separately from that forming the passivation layer. For example, a certain type of stand-off feature (e.g., the columnar stand-off features) may be formed from one of the first material or second material and another type of stand-off feature (e.g., a perimeter feature, ridge feature, grid feature, or the like as described earlier) may be formed from the other of the first material or second material.

[0142] The maximum dimensions of the stand-off features (parallel to the surface of the IC) may be subject to a design rule for minimising the risk / magnitude of wafer-leveldeformation (such as curl in the case of a flexible substrate). For example, in some scenarios, a maximum dimension (before a space between such stand-off features) of between 700pm and 1000pm, or 800pm and 900pm may be appropriate (e.g., 880pm ± 5% or the like). It will be appreciated that this design rule may be particularly applicable to near continuous ‘large area’ stand-off features such as those that may be provided beneath the connection regions.

[0143] It will be appreciated that the optimum dimensions and surface density of the stand-off features and / or the optimum thickness of the various layers may vary depending on the substrate thickness.

[0144] It will be appreciated that the use of stand-off structures as described above is particularly beneficial in the context of electrically connecting IC chips to near field communication (NFC) I radio frequency identification (RFID) antenna. Nevertheless, stand-off structures as described above may also be used with a commensurate benefit in the context of electrical connections for IC chips to other forms of application circuitry.

[0145] Moreover whilst, as described above, the substrate carrying the IC may be a flexible substrate formed of a flexible material such as an appropriate flexible polymer material, the flexible substrate may be formed from any other materials that provide suitable electrical, chemical, and / or structural properties. The flexible substrate may be formed from a single common material, may be formed from a plurality of different materials, or may be formed from a plurality of different types of the same material. A flexible substrate may, for example, comprise one or more materials selected from the following list of materials: flexible glass, polymer materials, metal oxide materials, resin materials, resist materials, foil materials, paper, insulator coated metals, or any other suitable material.

[0146] Where a polymer based material is used, the substrate may comprise one or more polymers selected from: polyethylene naphthalates, polyethylene terephthalates; polymethyl methacrylates; polycarbonates, polyvinyl alcohols, polyvinyl acetates, polyvinyl pyrrolidones, polyvinyl phenols, polyvinyl chlorides, polystyrenes, polyimides, polyamides (e.g. Nylon); poly(hydroxy ethers), polyurethanes, polycarbonates, polysulfones, parylenes, polyarylates, polyether ether ketones (PEEKs); acrylonitrile butadiene styrene (ABS), 1 Methoxy 2 propyl acetates, Benzocyclobutenes (BCB), polylactic acid (PLA), polyhydroxyalkanoates (PHAs), polybutylene succinate (PBS),polybutylene adipate terephthalate (PBAT), cellulose polymers, or any other suitable polymer material.

[0147] Where a metal oxide-based material is used, the substrate may comprise one or more metal oxides selected from: AI2O3, SiOxNy, SiO2, Si3N4, or any other suitable metal oxide. Where a resin-based material is used, the substrate may comprise one or more resins selected from: a UV-curable resin or any other suitable resin. Where a resist-based material is used, the substrate may comprise one or more resists selected from: nanoimprint resists, photoresists such as, for example, Bisphenol A novolac epoxy (SU-8) or polyhydroxybenzyl silsesquioxane, or any other suitable resist. Where a foil-based material is used the substrate may comprise one or more foils selected from: polymeric foils or any other suitable foil. Where an insulator-coated metal is used, the substrate may comprise one or more insulator-coated metals selected from: insulator coated stainless-steel or any other suitable insulator-coated metal.

[0148] Various other modifications will be apparent to those skilled in the art and will not be described in further detail here.

Claims

Claims1. An integrated circuit chip comprising:a substrate on which is formed an integrated circuit;at least one connection region for forming an external electrical connection to the integrated circuit;a passivation layer extending over an active surface of at least a portion of the integrated circuit for protecting that active surface; anda plurality of projecting features extending from the passivation layer, in a direction away from the active surface, each projecting feature being respectively formed of a dielectric material,wherein the surface density and arrangement of projecting features are configured for providing additional protection of the integrated circuit, for supporting the integrated circuit during assembly of the integrated circuit chip with external circuitry to form an electronic device, and / or for limiting wafer-level deformation during manufacture.

2. An integrated circuit chip as claimed in claim 1 , wherein at least a subset of one or more of the projecting features are formed of the same dielectric material as the passivation layer.

3. An integrated circuit chip as claimed in claim 2, wherein at least a subset of one or more of the projecting features are formed integrally with the passivation layer.

4. An integrated circuit chip as claimed in any preceding claim, wherein at least a subset of one or more of the projecting features are formed of a different dielectric material than that of the passivation layer.

5. An integrated circuit chip as claimed in claim 4, wherein each projecting feature formed of a different dielectric material than that of the passivation layer is formed of a polymer-based material.

6. An integrated circuit chip as claimed in claim 5, wherein the polymer-based material is a polyimide-based material.

7. An integrated circuit chip as claimed in any of claims 4 to 6, wherein each projecting feature formed of a different dielectric material than that of the passivation layer is formed of a photo-definable material.

8. An integrated circuit chip as claimed in claim 7, wherein the photo-definable material is a negative tone photo-definable material.

9. An integrated circuit chip as claimed in any of claims 4 to 8, wherein each projecting feature formed of a different dielectric material than that of the passivation layer is formed of a thermosetting plastic material.

10. An integrated circuit chip as claimed in any of claims 4 to 8, wherein each projecting feature formed of a different dielectric material than that of the passivation layer is formed of SU-8.

11. An integrated circuit chip as claimed in any of claims 4 to 9, wherein each projecting feature formed of a different dielectric material than that of the passivation layer is formed of a material that is more elastic than SU-8.

12. An integrated circuit chip as claimed in any preceding claim wherein the plurality of projecting features include at least one columnar protection feature, at least one ridge shaped projection features, at least one grid shaped protection feature, and / or at least one projection feature defining a boundary around at least part of the integrated circuit.

13. An integrated circuit chip as claimed in any preceding claim wherein a backfill material is provided between at least a subset of the plurality of projecting features.

14. An integrated circuit chip as claimed in claim 13, wherein the backfill material is provided on a surface of at least part of the passivation layer extending between at least a subset of the plurality of projecting features.

15. An integrated circuit chip as claimed in any preceding claim wherein at least one projecting feature, of the plurality of projecting features, is respectively provided in each connection region.

16. An integrated circuit chip as claimed in claim 15, wherein the at least one projecting feature respectively provided in each connection region comprises a continuous region of the dielectric material extending a substantial part of that connection region.

17. An integrated circuit chip as claimed in claim 15 or 16, wherein the at least one projecting feature respectively provided in each connection region comprises a plurality of columnar protection features, ridge shaped projection features, and / or grid shaped protection features.

18. An integrated circuit chip as claimed in any preceding claim wherein each projecting feature, of at least a subset of one or more of the projecting features, is respectively provided with a shielding element on a surface of that projecting feature.

19. An integrated circuit chip as claimed in claim 18, wherein each shielding element is formed from a common layer of conductive material.

20. An integrated circuit chip as claimed in any preceding claim, wherein the substrate is a flexible substrate, and the integrated circuit chip is a flexible integrated circuit chip.

21. A method of fabricating an integrated circuit chip, the method comprising:providing a substrate;forming, on the substrate, an integrated circuit;forming at least one connection region for forming an external electrical connection to the integrated circuit; andforming a passivation layer extending over an active surface of at least a portion of the integrated circuit for protecting that active surface; andforming a plurality of projecting features extending from the passivation layer, in a direction away from the active surface, each projecting feature being respectively formed of a dielectric material,wherein the surface density and arrangement of projecting features are configured for providing additional protection of the integrated circuit, for supporting the integrated circuit during assembly of the integrated circuit chip with external circuitry to form an electronic device, and / or for limiting wafer-level deformation during manufacture.

22. A method as claimed in claim 21 , wherein at least a subset of one or more of the projecting features are formed of the same dielectric material as the passivation layer, and wherein the passivation layer and each projecting feature formed of that dielectric materialis formed by depositing that dielectric material and by partially etching the deposited dielectric material back to leave each projecting feature formed of that dielectric material extending from the passivation layer.

23. A method as claimed in claim 21 or 22, wherein at least a subset of one or more of the projecting features are formed of a different dielectric material than that of the passivation layer, and wherein each projecting feature formed of that different dielectric material is formed by depositing that different dielectric material over at least part of the passivation layer and by patterning that different dielectric material to form each projecting feature formed of that different dielectric material.

24. A method as claimed in claim 23, wherein each projecting feature formed of a different dielectric material than that of the passivation layer is formed of a photo-definable material, and wherein the patterning of that different dielectric material is achieved by photo-defining that different dielectric material to form each projecting feature formed of that different dielectric material.

25. An electronic device comprising:electronic circuitry formed on an electronic device substrate; andan integrated circuit chip, as claimed in any of claims 1 to 20, electrically connected to the electronic circuitry to form the electronic device.

26. An electronic device as claimed in claim 25, wherein at least one supporting element is provided on the electronic substrate for providing mechanical support to the integrated circuit chip.

27. An electronic device as claimed in claim 26, wherein the at least one supporting element comprises at least one structure comprising: an active structure; an inactive structure; a functional part of the electronic circuitry; a non-functional part of the electronic circuitry; at least part of a conductive routing trace; an extension of a contact region or pad; and / or at least part of a dummy circuit.

28. An electronic device as claimed in any of claims 25 to 27, wherein the electronic circuitry comprises at least one antenna.

29. An electronic device as claimed in any of claims 25 to 28, wherein the electronic device is a radio frequency identification (RFID) device.

30. An electronic device as claimed in any of claims 25 to 29, wherein the electronic device substrate is a flexible electronic device substrate.

31. A method of assembling an electronic device, the method comprising:providing an electronic device substrate on which electronic circuitry of the electronic device is formed;providing integrated circuit chip as claimed in any of claims 1 to 20; andelectrically connecting the integrated circuit chip to the electronic circuitry to form the electronic device.

32. A method as claimed in claim 31, wherein the electrically connecting comprises: depositing an anisotropic conducting medium on the electronic device substrate; positioning the integrated circuit chip relative to the electronic circuitry to align at least one connection region of the integrated circuit chip with at least one corresponding electrical connection region of the electronic circuitry; and pressing the integrated circuit chip, when in the aligned position, into the anisotropic conducting medium to form an electrical connection between the at least one connection region of the integrated circuit chip and the at least one corresponding electrical connection region of the electronic circuitry.

33. A method as claimed in claim 32, further comprising curing the anisotropic conducting medium to secure the integrated circuit chip in position.

34. An integrated circuit chip obtained by the method as claimed in any of claims 21 to 24.

35. An electronic device obtained by the method as claimed in any of claims 31 to 33.

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